110 lines
4.1 KiB
C
110 lines
4.1 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------------------
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* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
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* | (external 8 MHz clock) | (internal 8 MHz)
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* | 2- PLL_HSE_XTAL |
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* | (external 8 MHz xtal) |
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* AHBCLK (MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* APB1CLK (MHz) | 36 | 32
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*-----------------------------------------------------------------------------
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* APB2CLK (MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* USB capable (48 MHz precise clock) | NO | NO
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*-----------------------------------------------------------------------------
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******************************************************************************
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*/
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#include "stm32f1xx.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= 0x00000001U;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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#if !defined(STM32F105xC) && !defined(STM32F107xC)
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RCC->CFGR &= 0xF8FF0000U;
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#else
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RCC->CFGR &= 0xF0FF0000U;
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#endif /* STM32F105xC */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= 0xFEF6FFFFU;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= 0xFF80FFFFU;
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#if defined(STM32F105xC) || defined(STM32F107xC)
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/* Reset PLL2ON and PLL3ON bits */
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RCC->CR &= 0xEBFFFFFFU;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x00FF0000U;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000U;
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#elif defined(STM32F100xB) || defined(STM32F100xE)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000U;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000U;
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#else
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000U;
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#endif /* STM32F105xC */
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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#endif
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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