commit 14fb2033c2c6e7aa221e5a5af9092d96782dc6df Author: Steins7 Date: Mon Dec 2 22:49:10 2019 +0100 blink ! Timers are working and so are GPIOs in output mode the program contain a basic blink cadenced on a timer IRQ diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..08c8fd6 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +bin +.gdb_history diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..de8facf --- /dev/null +++ b/Makefile @@ -0,0 +1,175 @@ +#----------------------------------------------------------------------------- +# this GNU-makefile relies on the GCC toolchain + +# --- control global project settings +# RELEASE=1 -> enable optimisation, then disable debug +# RELEASE=0 -> disbale optimisation, then enable debug +RELEASE=0 + +# --- project architecture +# program name +EXE_PREFIX=main +# project folders, This Makefile should be in the same folder as the SRC folder +SRC=src +BIN=bin +LIB=lib +OBJ=${BIN}/obj +DEP=${BIN}/dep +# code folders, in the SRC folder +SUBFOLDERS=drivers target +# Define linker script file here +LDSCRIPT=${SRC}/target/STM32F103XB.ld + +# --- advanced config +# List all user C define here +UDEFS= +# Define ASM defines here +UADEFS= +# List all user directories here +UINCDIR=. +# List the user directory to look for the libraries here +ULIBDIR= + +# --- toolchain configuration +TARGET=arm-none-eabi- +CC=$(TARGET)gcc +OBJCOPY=$(TARGET)objcopy +AS=$(TARGET)gcc -x assembler-with-cpp -c +SIZE=$(TARGET)size +OBJDUMP=$(TARGET)objdump + +# --- hardware settings +ARCH=armv7-m +FLOAT-ABI=soft +CPU=cortex-m3 +CPUFLAGS=-mthumb +FPU=fpv4-sp-d16 + +##----------------------------------------------------------------------------- +# --- makefile pre-incantation + +# List all default C defines here, like -D_DEBUG=1 +DDEFS=-march=$(ARCH) -mfloat-abi=$(FLOAT-ABI) -mcpu=$(CPU) -mfpu=$(FPU) $(CPUFLAGS) +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS=-D__ASSEMBLY__ +# List all default directories to look for include files here +DINCDIR= +# List the default directory to look for the libraries here +DLIBDIR= +# List all default libraries here +DLIBS= + +# --- deduce file names +MAIN_C_FILES=${wildcard ${SRC}/${strip ${EXE_PREFIX}}*.c} +COMMON_C_FILES=${filter-out ${MAIN_C_FILES},${wildcard *.c} \ + ${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.c}}} + #${wildcard ${TC}*.c}} +COMMON_ASM_FILES=${filter-out ${MAIN_CXX_FILES},${wildcard *.s} \ + ${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.s}}} + #${wildcard ${TC}*.s}} +MAIN_OBJECT_FILES=${sort ${patsubst ${SRC}/%.c,${OBJ}/%.o,${MAIN_C_FILES}}} +COMMON_OBJECT_FILES=${sort ${patsubst ${SRC}/%.c,${OBJ}/%.o,${COMMON_C_FILES}} \ + ${patsubst ${SRC}/%.s,${OBJ}/%.o,${COMMON_ASM_FILES}}} +LIBRARIES=${foreach dir,${wildcard ${LIB}/*},${wildcard ${LIB}/${dir}/*.a}} + +#----------------------------------------------------------------------------- +# --- makefile incantation +# down here is black magic, you probably don't want to modify anything + +DEFS =$(DDEFS) $(UDEFS) +ADEFS =$(DADEFS) $(UADEFS) +ASFLAGS=$(INCDIR) $(DEFS) -Wa,--gdwarf2 $(ADEFS) + +ifeq (${strip ${RELEASE}},0) + CFLAGS=-g3 -O0 +else + CFLAGS=-O3 +endif + +ASFLAGS = $(INCDIR) $(DEFS) -Wa,--gdwarf2 $(ADEFS) +CFLAGS+=-std=c17 -Wall $(DEFS) -Wextra -Warray-bounds -Wno-unused-parameter -fomit-frame-pointer +LDFLAGS= -T$(LDSCRIPT) -lc -lgcc -lgcov -lm -Wl,-Map=$@.map,--gc-sections --specs=nosys.specs +INC=-I${LIB} + +# --- Generate dependency information +#CFLAGS += -MD -MP -MF ${DEP}/$(@F0).d +#ASFLAGS += -MD -MP -MF ${DEP}/$(@F).d + +# --- folder tree +DIR_GUARD=@mkdir -p ${@D} +ifeq (${OS},Windows_NT) + DIR_GUARD=@md ${@D} +endif + +# --- make rules +all: ${BIN}/${EXE_PREFIX}.elf ${BIN}/${EXE_PREFIX}.hex ${BIN}/${EXE_PREFIX}.bin + +rebuild : clean all + +.SUFFIXES: +.SECONDARY: +.PHONY: all clean rebuild + +${BIN}/%.elf : ${MAIN_OBJECT_FILES} ${COMMON_OBJECT_FILES} + @echo + @echo ==== linking $@ ==== + @echo ${COMMON_OBJECT_FILES} + @echo + ${DIR_GUARD} + ${CC} --verbose -o $@ ${filter-out %ld, $^} ${LIBRARIES} ${LDFLAGS} + ${OBJDUMP} -h $@ + ${SIZE} $@ + @${SKIP_LINE} + +${BIN}/%.hex : ${BIN}/%.elf + @echo + @echo ==== traducing [opt=${opt}] $< ==== + @echo + ${OBJCOPY} -O ihex $< $@ + +${BIN}/%.bin : ${BIN}/%.elf + @echo + @echo ==== traducing [opt=${opt}] $< ==== + @echo + ${OBJCOPY} -O binary $< $@ + +${OBJ}/%.o : ${SRC}/%.c + @echo + @echo ==== compiling [opt=${opt}] $< ==== + @echo + ${DIR_GUARD} + ${CC} ${INC} -c ${CFLAGS} $< -o $@ ${LIBRARIES} + @${SKIP_LINE} + +${BIN}/%.o : ${SRC}/%.c + @echo + @echo ==== compiling [opt=${opt}] $< ==== + @echo + ${DIR_GUARD} + ${CC} ${INC} -c ${CFLAGS} $< -o $@ ${LIBRARIES} + @${SKIP_LINE} + +${OBJ}/%.o : ${SRC}/%.s + @echo + @echo ==== compiling [opt=${opt}] $^ $@ ${LIBRARIES}==== + @echo + ${DIR_GUARD} + ${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES} + @${SKIP_LINE} + +${BIN}/%.o : ${SRC}/%.s + @echo + @echo ==== compiling [opt=${opt}] $^ $@ ${LIBRARIES}==== + @echo + ${DIR_GUARD} + ${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES} + @${SKIP_LINE} + +# --- remove generated files +clean: + -rm -rf ${BIN}/* + +# Include the dependency files, should be the last of the makefile +# +#-include $(shell mkdir ${DEP}/ 2>/dev/null) $(wildcard ${DEP}/*) +-include ${DEPEND_FILES} diff --git a/docs/en.CD00171190.pdf b/docs/en.CD00171190.pdf new file mode 100644 index 0000000..d1b38ad Binary files /dev/null and b/docs/en.CD00171190.pdf differ diff --git a/docs/stm32f103c8.pdf b/docs/stm32f103c8.pdf new file mode 100644 index 0000000..cbe5419 Binary files /dev/null and b/docs/stm32f103c8.pdf differ diff --git a/lib/cmsis/arm_math.h b/lib/cmsis/arm_math.h new file mode 100644 index 0000000..f867d49 --- /dev/null +++ b/lib/cmsis/arm_math.h @@ -0,0 +1,7190 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_math.h + * Description: Public header file for CMSIS DSP Library + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library + * on ARMv8M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#if 0 + /* + * @brief C custom defined PKHBT for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( + uint32_t x, + uint32_t y, + uint32_t leftshift) + { + return ( ((x ) & 0x0000FFFFUL) | + ((y << leftshift) & 0xFFFF0000UL) ); + } + + /* + * @brief C custom defined PKHTB for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( + uint32_t x, + uint32_t y, + uint32_t rightshift) + { + return ( ((x ) & 0xFFFF0000UL) | + ((y >> rightshift) & 0x0000FFFFUL) ); + } +#endif + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/lib/cmsis/cmsis_armcc.h b/lib/cmsis/cmsis_armcc.h new file mode 100644 index 0000000..174d744 --- /dev/null +++ b/lib/cmsis/cmsis_armcc.h @@ -0,0 +1,869 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.5 + * @date 14. December 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/lib/cmsis/cmsis_armclang.h b/lib/cmsis/cmsis_armclang.h new file mode 100644 index 0000000..6a8867d --- /dev/null +++ b/lib/cmsis/cmsis_armclang.h @@ -0,0 +1,1420 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.1.0 + * @date 14. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/cmsis/cmsis_armclang_ltm.h b/lib/cmsis/cmsis_armclang_ltm.h new file mode 100644 index 0000000..e4002a3 --- /dev/null +++ b/lib/cmsis/cmsis_armclang_ltm.h @@ -0,0 +1,1866 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.0.1 + * @date 19. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/cmsis/cmsis_compiler.h b/lib/cmsis/cmsis_compiler.h new file mode 100644 index 0000000..fdb1a97 --- /dev/null +++ b/lib/cmsis/cmsis_compiler.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/lib/cmsis/cmsis_gcc.h b/lib/cmsis/cmsis_gcc.h new file mode 100644 index 0000000..d86b0a2 --- /dev/null +++ b/lib/cmsis/cmsis_gcc.h @@ -0,0 +1,2101 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.1.0 + * @date 20. December 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/lib/cmsis/cmsis_iccarm.h b/lib/cmsis/cmsis_iccarm.h new file mode 100644 index 0000000..20b50ce --- /dev/null +++ b/lib/cmsis/cmsis_iccarm.h @@ -0,0 +1,940 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.8 + * @date 04. September 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/lib/cmsis/cmsis_version.h b/lib/cmsis/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/lib/cmsis/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/lib/cmsis/core_armv81mml.h b/lib/cmsis/core_armv81mml.h new file mode 100644 index 0000000..db6d9f2 --- /dev/null +++ b/lib/cmsis/core_armv81mml.h @@ -0,0 +1,2967 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_armv8mbl.h b/lib/cmsis/core_armv8mbl.h new file mode 100644 index 0000000..57d9f66 --- /dev/null +++ b/lib/cmsis/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_armv8mml.h b/lib/cmsis/core_armv8mml.h new file mode 100644 index 0000000..30aab58 --- /dev/null +++ b/lib/cmsis/core_armv8mml.h @@ -0,0 +1,2832 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm0.h b/lib/cmsis/core_cm0.h new file mode 100644 index 0000000..fcf2757 --- /dev/null +++ b/lib/cmsis/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm0plus.h b/lib/cmsis/core_cm0plus.h new file mode 100644 index 0000000..65ea443 --- /dev/null +++ b/lib/cmsis/core_cm0plus.h @@ -0,0 +1,1082 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm1.h b/lib/cmsis/core_cm1.h new file mode 100644 index 0000000..72c515c --- /dev/null +++ b/lib/cmsis/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm23.h b/lib/cmsis/core_cm23.h new file mode 100644 index 0000000..26fe163 --- /dev/null +++ b/lib/cmsis/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm3.h b/lib/cmsis/core_cm3.h new file mode 100644 index 0000000..ea54050 --- /dev/null +++ b/lib/cmsis/core_cm3.h @@ -0,0 +1,1934 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm33.h b/lib/cmsis/core_cm33.h new file mode 100644 index 0000000..d5d97a9 --- /dev/null +++ b/lib/cmsis/core_cm33.h @@ -0,0 +1,2907 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm35p.h b/lib/cmsis/core_cm35p.h new file mode 100644 index 0000000..c00e54c --- /dev/null +++ b/lib/cmsis/core_cm35p.h @@ -0,0 +1,2907 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm4.h b/lib/cmsis/core_cm4.h new file mode 100644 index 0000000..f205b33 --- /dev/null +++ b/lib/cmsis/core_cm4.h @@ -0,0 +1,2121 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_cm7.h b/lib/cmsis/core_cm7.h new file mode 100644 index 0000000..41f9afb --- /dev/null +++ b/lib/cmsis/core_cm7.h @@ -0,0 +1,2691 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_sc000.h b/lib/cmsis/core_sc000.h new file mode 100644 index 0000000..389535a --- /dev/null +++ b/lib/cmsis/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/core_sc300.h b/lib/cmsis/core_sc300.h new file mode 100644 index 0000000..5478ea7 --- /dev/null +++ b/lib/cmsis/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis/mbed_tz_context.c b/lib/cmsis/mbed_tz_context.c new file mode 100644 index 0000000..17bf625 --- /dev/null +++ b/lib/cmsis/mbed_tz_context.c @@ -0,0 +1,207 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !TARGET_TFM + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} +#endif + +#endif // !TARGET_TFM diff --git a/lib/cmsis/mpu_armv7.h b/lib/cmsis/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/lib/cmsis/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/lib/cmsis/mpu_armv8.h b/lib/cmsis/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/lib/cmsis/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/lib/cmsis/tz_context.h b/lib/cmsis/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/lib/cmsis/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/openocd b/openocd new file mode 100755 index 0000000..d7055aa --- /dev/null +++ b/openocd @@ -0,0 +1,3 @@ +#!/bin/bash +openocd -f interface/stlink-v2.cfg -f target/cs32f1x.cfg + diff --git a/src/config.h b/src/config.h new file mode 100644 index 0000000..e8b1fd9 --- /dev/null +++ b/src/config.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * IRQ Priority + ****************************************************************************/ +#define EXTI0_IRQ_PRIORITY 8 +#define EXTI1_IRQ_PRIORITY 8 +#define EXTI2_IRQ_PRIORITY 8 +#define EXTI3_IRQ_PRIORITY 8 +#define EXTI4_IRQ_PRIORITY 8 +#define EXTI9_5_IRQ_PRIORITY 8 +#define EXTI15_10_IRQ_PRIORITY 8 + +#define TIM2_IRQ_PRIORITY 4 +#define TIM3_IRQ_PRIORITY 4 +#define TIM4_IRQ_PRIORITY 4 + +#define USART1_IRQ_PRIORITY 3 +#define USART2_IRQ_PRIORITY 3 +#define USART6_IRQ_PRIORITY 3 + +#define I2C1_IRQ_PRIORITY 2 +#define I2C1_IRQERR_PRIORITY 1 +#define I2C2_IRQ_PRIORITY 2 +#define I2C2_IRQERR_PRIORITY 1 +#define I2C3_IRQ_PRIORITY 2 +#define I2C3_IRQERR_PRIORITY 1 + +#define SPI1_IRQ_PRIORITY 4 +#define SPI2_IRQ_PRIORITY 4 +#define SPI3_IRQ_PRIORITY 4 +#define SPI4_IRQ_PRIORITY 4 +#define SPI5_IRQ_PRIORITY 4 + +#define ADC1_IRQ_PRIORITY 5 + +/**************************************************************************** + * USART Pin and use configuration + ****************************************************************************/ + +//#define USE_USART1 +//#define USART1_GPIO_PORT +//#define USART1_GPIO_PINS + +// USART2: Tx --> PA2, Rx --> PA3 +//#define USE_USART2 +//#define USART2_GPIO_PORT _GPIOA +//#define USART2_GPIO_PINS PIN_2|PIN_3 + +//#define USE_USART6 +//#define USART6_GPIO_PORT +//#define USART6_GPIO_PINS + +/**************************************************************************** + * I2C Pin and use configuration + ****************************************************************************/ + +// I2C1 : SCL --> PB8, SDA --> PB9 +//#define USE_I2C1 +//#define I2C1_GPIO_PORT _GPIOB +//#define I2C1_GPIO_PINS PIN_8|PIN_9 + +//#define USE_I2C2 +//#define I2C2_GPIO_PORT +//#define I2C2_GPIO_PINS + +//#define USE_I2C3 +//#define I2C3_GPIO_PORT +//#define I2C3_GPIO_PINS + +/**************************************************************************** + * SPI pin and use configuration + ****************************************************************************/ + +// SPI1 pins : LCD_SCK --> D13 --> PA5 : SPI1_SCK +// LCD_MOSI --> D11 --> PA7 : SPI1_MOSI +//#define USE_SPI1 +//#define SPI1_GPIO_PORT _GPIOA +//#define SPI1_GPIO_PINS PIN_5|PIN_7 + +//#define USE_SPI2 +//#define SPI2_GPIO_PORT +//#define SPI2_GPIO_PINS + +//#define USE_SPI3 +//#define SPI3_GPIO_PORT +//#define SPI3_GPIO_PINS + +//#define USE_SPI4 +//#define SPI4_GPIO_PORT +//#define SPI4_GPIO_PINS + +//#define USE_SPI5 +//#define SPI5_GPIO_PORT +//#define SPI5_GPIO_PINS + +/**************************************************************************** + * ADC pin and use configuration + ****************************************************************************/ + +// ADC1: ADC1_0 --> PA0, ADC1_1 -->PA1 +//#define USE_ADC1 +//#define ADC1_GPIO_PORT _GPIOA +//#define ADC1_GPIO_PINS PIN_0|PIN_1 + diff --git a/src/drivers/io.c b/src/drivers/io.c new file mode 100644 index 0000000..64eaf5f --- /dev/null +++ b/src/drivers/io.c @@ -0,0 +1,255 @@ +//target header +#include "../target/stm32f103xb.h" + +//custom header +#include "../config.h" + +//std headers +#include + +//driver header +#include "io.h" + +static OnIO io_cb[16]={ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL +}; + +void EXTI0_IRQHandler() { + if (io_cb[0]) (io_cb[0])(); + + EXTI->PR = 1<<0; +} + +void EXTI1_IRQHandler() { + if (io_cb[1]) (io_cb[1])(); + + EXTI->PR = 1<<1; +} + +void EXTI2_IRQHandler() { + if (io_cb[2]) (io_cb[2])(); + + EXTI->PR = 1<<2; +} + +void EXTI3_IRQHandler() { + if (io_cb[3]) (io_cb[3])(); + + EXTI->PR = 1<<3; +} + +void EXTI4_IRQHandler() { + if (io_cb[4]) (io_cb[4])(); + + EXTI->PR = 1<<4; +} + +void EXTI9_5_IRQHandler() { + if (EXTI->PR & (1<<5)) { + if (io_cb[5]) (io_cb[5])(); + EXTI->PR = 1<<5; + } else if (EXTI->PR & (1<<6)) { + if (io_cb[6]) (io_cb[6])(); + EXTI->PR = 1<<6; + } else if (EXTI->PR & (1<<7)) { + if (io_cb[7]) (io_cb[7])(); + EXTI->PR = 1<<7; + } else if (EXTI->PR & (1<<8)) { + if (io_cb[8]) (io_cb[8])(); + EXTI->PR = 1<<8; + } else if (EXTI->PR & (1<<9)) { + if (io_cb[9]) (io_cb[9])(); + EXTI->PR = 1<<9; + } +} + +void EXTI15_10_IRQHandler() { + if (EXTI->PR & (1<<10)) { + if (io_cb[10]) (io_cb[10])(); + EXTI->PR = 1<<10; + } else if (EXTI->PR & (1<<11)) { + if (io_cb[11]) (io_cb[11])(); + EXTI->PR = 1<<11; + } else if (EXTI->PR & (1<<12)) { + if (io_cb[12]) (io_cb[12])(); + EXTI->PR = 1<<12; + } else if (EXTI->PR & (1<<13)) { + if (io_cb[13]) (io_cb[13])(); + EXTI->PR = 1<<13; + } else if (EXTI->PR & (1<<14)) { + if (io_cb[14]) (io_cb[14])(); + EXTI->PR = 1<<14; + } else if (EXTI->PR & (1<<15)) { + if (io_cb[15]) (io_cb[15])(); + EXTI->PR = 1<<15; + } +} + +/* Definitions for EXTI configuration */ +#define SYSCFG_EXTI_PA_MASK 0 +#define SYSCFG_EXTI_PB_MASK 1 +#define SYSCFG_EXTI_PC_MASK 2 +#define SYSCFG_EXTI_PD_MASK 3 +#define SYSCFG_EXTI_PE_MASK 4 +#define SYSCFG_EXTI_PH_MASK 7 + + +int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint32_t pin_cfg, OnIO cb) { + + // enable GPIOx subsystem clocking + if (gpio == GPIOA) RCC->APB2ENR |= 1<<2; + else if (gpio == GPIOB) RCC->APB2ENR |= 1<<3; + else if (gpio == GPIOC) RCC->APB2ENR |= 1<<4; + else if (gpio == GPIOD) RCC->APB2ENR |= 1<<5; + else if (gpio == GPIOE) RCC->APB2ENR |= 1<<6; + + // ssetup the config bits + uint32_t crx = 0; + uint16_t odr = 0; + for(int i=0; i<8; i++) { + if(pin & (1 << i)) { + crx |= (pin_cfg & 0xF) << (4*i); + odr |= (pin_cfg & 0xF0) << i; + } + } + gpio->CRL |= crx; + + crx = 0; + for(int i=8; i<16; i++) { + if(pin & (1 << i)) { + crx |= (pin_cfg & 0xF) << (4*(i-8)); + odr |= (pin_cfg & 0xF0) << i; + } + } + gpio->CRH |= crx; + gpio->ODR |= odr; + + /* + if (!cb) return -1; //no callback attached + + //TODO manage alternate functions + if (pin_cfg & 0x3) return -1; //callback set, but not in input mode + + // ************* Input GPIO + External IRQ ************* + + uint32_t port_mask = 0; + uint32_t pin_mask = 0; + + if (gpio == GPIOA) port_mask = SYSCFG_EXTI_PA_MASK; + else if (gpio == GPIOB) port_mask = SYSCFG_EXTI_PB_MASK; + else if (gpio == GPIOC) port_mask = SYSCFG_EXTI_PC_MASK; + else if (gpio == GPIOD) port_mask = SYSCFG_EXTI_PD_MASK; + else if (gpio == GPIOE) port_mask = SYSCFG_EXTI_PE_MASK; + + uint32_t bit_mask = 0x1; + + for (int i=0; i<16; i++) { + if (pin_mask & bit_mask) { + // enable clock for SYSCFG, no need for EXTI (interface not clocked) + RCC->APB2ENR = RCC->APB2ENR | (1<<14); + + // configure pin Px_i (4 pin config per EXTICR[] register, 4 bits per pin) + // use port Px and bind Px_i --> EXTIi + // i>>2 = i/4 ; i & 0x3 = i%4 + gpio->EXTICR[i>>2] = (SYSCFG->EXTICR[i>>2] & + ~(0x0000000F << ((i & 3)<<2))) | + (port_mask << ((i & 3)<<2)); + + // allow pin EXTIi to send an IRQ + EXTI->IMR = EXTI->IMR | bit_mask; + // not a wakeup event + EXTI->EMR = EXTI->EMR & (~bit_mask); + + // Configure pin event IRQ on rising (RTSR)/falling (FTSR) edge (rising only here) + if (pin_cfg & PIN_OPT_IRQ_EDGE_RISE) { + EXTI->RTSR = EXTI->RTSR | bit_mask; + } else { + EXTI->RTSR = EXTI->RTSR & (~bit_mask); + } + + if (pin_cfg & PIN_OPT_IRQ_EDGE_FALL) { + EXTI->FTSR = EXTI->FTSR | bit_mask; + } else { + EXTI->FTSR = EXTI->FTSR & (~bit_mask); + } + + io_cb[i] = cb; + + // reset any pending IRQ on PC13 + EXTI->PR = bit_mask; + + // Setup NVIC + switch (i) { + case 0: + NVIC_SetPriority(EXTI0_IRQn, EXTI0_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI0_IRQn); + break; + case 1: + NVIC_SetPriority(EXTI1_IRQn, EXTI1_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI1_IRQn); + break; + case 2: + NVIC_SetPriority(EXTI2_IRQn, EXTI2_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI2_IRQn); + break; + case 3: + NVIC_SetPriority(EXTI3_IRQn, EXTI3_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI3_IRQn); + break; + case 4: + NVIC_SetPriority(EXTI4_IRQn, EXTI4_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI4_IRQn); + break; + case 5: + case 6: + case 7: + case 8: + case 9: + NVIC_SetPriority(EXTI9_5_IRQn, EXTI9_5_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI9_5_IRQn); + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + NVIC_SetPriority(EXTI15_10_IRQn, EXTI15_10_IRQ_PRIORITY); + NVIC_EnableIRQ(EXTI15_10_IRQn); + break; + default: + return 0; +} +} +bit_mask = bit_mask<<1; +} +*/ +return 0; +} + + +uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask) +{ + return gpio->IDR & mask; +} + +void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) +{ + gpio->BSRR = (uint32_t)(mask) << (val ? 0 : 16); +} + +void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) +{ + gpio->BSRR = (uint32_t)(mask) << (val ? 16 : 0); +} + +void io_set(GPIO_TypeDef *gpio, uint16_t mask) +{ + gpio->BSRR = mask; +} + +void io_clear(GPIO_TypeDef *gpio, uint16_t mask) +{ + gpio->BSRR = (uint32_t)(mask) << 16; +} diff --git a/src/drivers/io.h b/src/drivers/io.h new file mode 100644 index 0000000..533cff7 --- /dev/null +++ b/src/drivers/io.h @@ -0,0 +1,119 @@ +#ifndef _IO_H_ +#define _IO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* --- GPIO pin mask definitions ---------------------------------------- */ +#define PIN_0 (1 << 0) +#define PIN_1 (1 << 1) +#define PIN_2 (1 << 2) +#define PIN_3 (1 << 3) +#define PIN_4 (1 << 4) +#define PIN_5 (1 << 5) +#define PIN_6 (1 << 6) +#define PIN_7 (1 << 7) +#define PIN_8 (1 << 8) +#define PIN_9 (1 << 9) +#define PIN_10 (1 << 10) +#define PIN_11 (1 << 11) +#define PIN_12 (1 << 12) +#define PIN_13 (1 << 13) +#define PIN_14 (1 << 14) +#define PIN_15 (1 << 15) +#define PIN_ALL 0xFFFF + +/* --- GPIO pin mode definitions ---------------------------------------- */ +#define PIN_MODE_INPUT (0) +#define PIN_MODE_OUTPUT (1 << 0) +#define PIN_MODE_ALTFUNC (1 << 3 | 1 << 0) +#define PIN_MODE_ANALOG (0) + +/* --- GPIO pin option definitions -------------------------------------- */ +/* none for analog pin */ +#define PIN_OPT_NONE (0) + +/* pull up/pull down resistor option */ +#define PIN_OPT_RESISTOR_NONE (1 << 2) +#define PIN_OPT_RESISTOR_PULLUP (1 << 4 | 1 << 3) +#define PIN_OPT_RESISTOR_PULLDOWN (1 << 3) + +/* push-pull/open drain output option */ +#define PIN_OPT_OUTPUT_PUSHPULL (0) +#define PIN_OPT_OUTPUT_OPENDRAIN (1 << 2) + +/* output speed option + * - LOW ~ 2MHz max + * - MEDIUM ~ 10MHz max + * - FAST ~ 50MHz max + **/ +#define PIN_OPT_OUTPUT_SPEED_LOW (10 << 0) +#define PIN_OPT_OUTPUT_SPEED_MEDIUM (1 << 0) +#define PIN_OPT_OUTPUT_SPEED_FAST (11 << 0) + +/* alternate function selection option */ +#define PIN_OPT_AF0 0x0 +#define PIN_OPT_AF1 0x1 +#define PIN_OPT_AF2 0x2 +#define PIN_OPT_AF3 0x3 +#define PIN_OPT_AF4 0x4 +#define PIN_OPT_AF5 0x5 +#define PIN_OPT_AF6 0x6 +#define PIN_OPT_AF7 0x7 +#define PIN_OPT_AF8 0x8 +#define PIN_OPT_AF9 0x9 +#define PIN_OPT_AF10 0xA +#define PIN_OPT_AF11 0xB +#define PIN_OPT_AF12 0xC +#define PIN_OPT_AF13 0xD +#define PIN_OPT_AF14 0xE +#define PIN_OPT_AF15 0xF + +/* irq pin option */ +#define PIN_OPT_IRQ_EDGE_RISE (1 << 12) +#define PIN_OPT_IRQ_EDGE_FALL (2 << 12) +#define PIN_OPT_IRQ_EDGE_BOTH (3 << 12) + +typedef void (*OnIO)(); + +/* io_configure + * + * configure pins referenced in 'pin_mask' of specified port + * 'gpio' according to 'pin_cfg' and associate a callback + * function 'cb' if not NULL. + * returns 0 if success + */ +int io_configure(GPIO_TypeDef *gpio, uint16_t pin_mask, uint32_t pin_cfg, OnIO cb); + +/* io_read + * + * read 32 bit data from port 'gpio', filter the result with mask + */ +uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask); + +/* io_write + * + * write 16 bit data filtered by mask to port 'gpio' + * '1' in val are written as HIGH level on port pins + */ +void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask); + +/* io_write_n + * + * write 16 bit data filtered by mask to port 'gpio' + * '1' in val are written as LOW level on port pins + */ +void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask); + +/* io_set/clear + * + * set or clear outputs according to bit mask + */ +void io_set(GPIO_TypeDef *gpio, uint16_t mask); +void io_clear(GPIO_TypeDef *gpio, uint16_t mask); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/src/drivers/rcc.c b/src/drivers/rcc.c new file mode 100644 index 0000000..cfa9a04 --- /dev/null +++ b/src/drivers/rcc.c @@ -0,0 +1,252 @@ +/** + ============================================================================== +##### RCC specific features ##### +============================================================================== +[..] +After reset the device is running from Internal High Speed oscillator +(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache +and I-Cache are disabled, and all peripherals are off except internal +SRAM, Flash and JTAG. +(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; +all peripherals mapped on these busses are running at HSI speed. +(+) The clock for all peripherals is switched off, except the SRAM and FLASH. +(+) All GPIOs are in input floating state, except the JTAG pins which +are assigned to be used for debug purpose. + +[..] +Once the device started from reset, the user application has to: +(+) Configure the clock source to be used to drive the System clock +(if the application needs higher frequency/performance) +(+) Configure the System clock frequency and Flash settings +(+) Configure the AHB and APB busses prescalers +(+) Enable the clock for the peripheral(s) to be used +(+) Configure the clock source(s) for peripherals which clocks are not +derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + +##### RCC Limitations ##### +============================================================================== +[..] +A delay between an RCC peripheral clock enable and the effective peripheral +enabling should be taken into account in order to manage the peripheral read/write +from/to registers. +(+) This delay depends on the peripheral mapping. +(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle +after the clock enable bit is set on the hardware register +(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle +after the clock enable bit is set on the hardware register + +[..] +Possible Workarounds: +(#) Enable the peripheral clock sometimes before the peripheral read/write +register is required. +(#) For AHB peripheral, insert two dummy read to the peripheral register. +(#) For APB peripheral, insert a dummy read to the peripheral register. +*/ + +#include "rcc.h" + +/* HPRE: AHB high-speed prescaler */ +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) + +/* PPRE1/2: APB high-speed prescalers */ +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +/* PPLMUL: PPL multiplier */ +#define RCC_CFGR_PLLMUL(fac) (fac + 2) + +enum rcc_osc { + RCC_HSI, + RCC_HSE, + RCC_PLL, + RCC_LSI, + RCC_LSE +}; + +struct ClockConfig_t { + uint8_t type; + uint8_t pll_src; + uint8_t pllmul; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint32_t flash_cfg; + uint32_t ahb_freq; + uint32_t apb1_freq; + uint32_t apb2_freq; +}; + +static struct ClockConfig_t _clock_config[] = { + {/* Performance Mode */ + .type = RCC_PLL, + .pll_src = RCC_HSE, //8MHz + .pllmul = RCC_CFGR_PLLMUL(9), //freq should noot exceed 72MHz + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, //freq should not exceed 36MHz + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .flash_cfg = FLASH_ACR_LATENCY_2, + .ahb_freq = 72000000, + .apb1_freq = 36000000, + .apb2_freq = 72000000 + }, + + {/* Powersave Mode */ + .type = RCC_HSE, + .hpre = RCC_CFGR_HPRE_DIV_16, + .ppre1 = RCC_CFGR_PPRE_DIV_16, + .ppre2 = RCC_CFGR_PPRE_DIV_16, + .flash_cfg = FLASH_ACR_LATENCY_0, + .ahb_freq = 500000, + .apb1_freq = 500000, + .apb2_freq = 500000 + } +}; + +static void rcc_osc_on(enum rcc_osc osc) +{ + switch (osc) { + case RCC_HSI: + if (!(RCC->CR & RCC_CR_HSION)) { + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY)==0); + } + break; + case RCC_HSE: + if (!(RCC->CR & RCC_CR_HSEON)) { + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY)==0); + } + break; + case RCC_PLL: + if (!(RCC->CR & RCC_CR_PLLON)) { + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY)==0); + } + break; + case RCC_LSI: + if (!(RCC->CSR & RCC_CSR_LSION)) { + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY)==0); + } + break; + case RCC_LSE: + if (!(RCC->BDCR & RCC_BDCR_LSEON)) { + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY)==0); + } + break; + } +} + +static void rcc_osc_off(enum rcc_osc osc) +{ + switch (osc) { + case RCC_HSI: + RCC->CR &= ~RCC_CR_HSION; + break; + case RCC_HSE: + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + break; + case RCC_PLL: + RCC->CR &= ~RCC_CR_PLLON; + break; + case RCC_LSI: + RCC->CSR &= ~RCC_CSR_LSION; + break; + case RCC_LSE: + RCC->BDCR &= ~RCC_BDCR_LSEON; + break; + } +} + +static void rcc_set_sysclk(enum rcc_osc osc) +{ + RCC->CFGR = (RCC->CFGR & ~0x3) | (osc & 3); + while (((RCC->CFGR & 0xC)>>2) != osc); +} + +//void SystemInit(void) { +// Clock_t tmp_clk; +// rcc_config_clock(CLOCK_CONFIG_PERFORMANCE, &tmp_clk); +//} + +void rcc_config_clock(uint32_t config, Clock_t *sysclks) +{ + struct ClockConfig_t *clk; + + if (config < CLOCK_CONFIG_END) { + clk=&(_clock_config[config]); + } else { + clk=&(_clock_config[CLOCK_CONFIG_PERFORMANCE]); + } + + if (clk->type == RCC_HSE) { // HSE Clock + rcc_osc_on(RCC_HSE); + rcc_set_sysclk(RCC_HSE); + rcc_osc_off(RCC_PLL); + rcc_osc_off(RCC_HSI); + + } else if (clk->type == RCC_PLL) { + // enable PWR module clocking + RCC->APB1ENR |= 1<<28; + + if (clk->pll_src == RCC_HSE) { // HSE Clock src + rcc_osc_on(RCC_HSE); + } else { // Default: HSI Clock src + rcc_osc_on(RCC_HSI); + } + + // configure prescalers for + // AHB: AHBCLK > 25MHz + // APB1: APB1CLK <= 36MHz + // APB2: APB2CLK <= 72MHz + RCC->CFGR = ( RCC->CFGR & ~((0x3F<<8) | (0xF<<4)) ) | + ((clk->hpre & 0xF) << 4) | + ((clk->ppre1 & 0x7) << 8) | + ((clk->ppre2 & 0x7) << 11); + + // configure PLL + RCC->CFGR &= !(0xF<<18); + RCC->CFGR |= clk->pllmul<<18; + + // enable PLL oscillator + rcc_osc_on(RCC_PLL); + + // set Flash timings + FLASH->ACR &= !0x8; + FLASH->ACR |= clk->flash_cfg; + //TODO set buffer bits + + // connect to PLL + rcc_set_sysclk(RCC_PLL); + + // stop unused clock + if ((clk->pll_src == RCC_HSE) && (RCC->CR & RCC_CR_HSION)) + rcc_osc_off(RCC_HSI); + else + rcc_osc_off(RCC_HSE); + + } else { // Default: HSI Clock + rcc_osc_on(RCC_HSI); + rcc_set_sysclk(RCC_HSI); + rcc_osc_off(RCC_PLL); + rcc_osc_off(RCC_HSE); + } + sysclks->ahb_freq = clk->ahb_freq; + sysclks->apb1_freq = clk->apb1_freq; + //TODO check timer frequencies + sysclks->apb1_timer_freq = clk->ppre1==RCC_CFGR_PPRE_DIV_NONE ? clk->apb1_freq : 2*clk->apb1_freq; + sysclks->apb2_freq = clk->apb2_freq; + sysclks->apb2_timer_freq = clk->ppre2==RCC_CFGR_PPRE_DIV_NONE ? clk->apb2_freq : 2*clk->apb2_freq; +} diff --git a/src/drivers/rcc.h b/src/drivers/rcc.h new file mode 100644 index 0000000..8996c09 --- /dev/null +++ b/src/drivers/rcc.h @@ -0,0 +1,33 @@ +#ifndef _RCC_H_ +#define _RCC_H_ + +#include "../target/stm32f103xb.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _Clock_t { + uint32_t ahb_freq; + uint32_t apb1_freq; + uint32_t apb1_timer_freq; + uint32_t apb2_freq; + uint32_t apb2_timer_freq; +} Clock_t; + +enum Clock_config { + CLOCK_CONFIG_PERFORMANCE, + CLOCK_CONFIG_POWERSAVE, + CLOCK_CONFIG_END +}; + +//void SystemInit(void); + +void rcc_config_clock(uint32_t config, Clock_t *sysclks); + +# +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/drivers/timer.c b/src/drivers/timer.c new file mode 100644 index 0000000..277ae81 --- /dev/null +++ b/src/drivers/timer.c @@ -0,0 +1,128 @@ +#include "timer.h" + +extern Clock_t sysclks; + +/* + * timerX_isr + * timerX ISR (Interrupt Service Routine) + */ +static OnTick callback2 = 0; +static OnTick callback3 = 0; +static OnTick callback4 = 0; + +void TIM2_IRQHandler() { + if (callback2) callback2(); + TIM2->SR &= ~0x1F; +} + +void TIM3_IRQHandler() { + if (callback3) callback3(); + TIM3->SR &= ~0x1F; +} + +void TIM4_IRQHandler() { + if (callback4) callback4(); + TIM4->SR &= ~0x1F; +} + + +/* + * timer_tick_init + * setup timer to call cb function periodically, each tick_ms + */ +int timer_tick_init(TIM_TypeDef *tmr, uint32_t tick_ms, OnTick cb) { + IRQn_Type irqn; + uint32_t irq_priority, clk; + //get back the clock frequency + clk = sysclks.apb1_timer_freq; + + if (tmr == TIM2) { + // register callback function + callback2 = cb; + irqn = TIM2_IRQn; + irq_priority = TIM2_IRQ_PRIORITY; + + // enable timer clocking + RCC->APB1ENR |=1<<0; + + } else if (tmr == TIM3) { + // register callback function + callback3 = cb; + irqn = TIM3_IRQn; + irq_priority = TIM3_IRQ_PRIORITY; + + // enable timer clocking + RCC->APB1ENR |=1<<1; + + } else if (tmr == TIM4) { + // register callback function + callback4 = cb; + irqn = TIM4_IRQn; + irq_priority = TIM4_IRQ_PRIORITY; + + // enable timer clocking + RCC->APB1ENR |=1<<2; + + } else { + return -1; + } + + // clear pending interrupts + tmr->SR &= !1; + + // set mode + tmr->CR1 = (1<<7); //buffering + tmr->DIER = (1<<0); //Enable interrupts + + // set prescaler 100us + tmr->PSC = clk/(10000-1); //100µs = (PSC+1)*Tclk + + // set period + if(timer_tick_period(tmr,tick_ms)) return -1; + + //enable counter + tmr->CR1= (1<<0)| tmr->CR1; + + if (cb) { + NVIC_SetPriority(irqn,irq_priority); //enable interuptions + NVIC_EnableIRQ(irqn); + } + + return 0; +} + +/* + * timer_tick_period + * change the tick_ms period + */ +int timer_tick_period(TIM_TypeDef *tmr, uint32_t tick_ms) { + // set period + tmr->ARR = tick_ms*10-1; //tickms = (ARR+1)Tpsc + + // force update to reset counter and prescaler + tmr->EGR |= 1; + return 0; +} + +/* + * timer_start + * reset & enable counting + */ +void timer_start(TIM_TypeDef *tmr) { + // force update to reset counter and prescaler + tmr->EGR |= 1; + + // enable counting + tmr->CR1 |= 1; +} + +/* + * timer_stop + * stop counting + */ +void timer_stop(TIM_TypeDef *tmr) { + // disable counting + tmr->CR1 &= !1; + +} + diff --git a/src/drivers/timer.h b/src/drivers/timer.h new file mode 100644 index 0000000..0333ac7 --- /dev/null +++ b/src/drivers/timer.h @@ -0,0 +1,85 @@ +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include "../target/stm32f103xb.h" +#include "../config.h" +#include "rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*OnTick)(void); + +/***************************************************************************/ +/* timer_wait_ms + * wait for ms millisecoonds function + */ +int timer_wait_ms(TIM_TypeDef *tmr, uint32_t ms, OnTick cb); + +/* timer_wait_us + * wait for us microsecoonds function + */ +int timer_wait_us(TIM_TypeDef *tmr, uint32_t us, OnTick cb); + +/***************************************************************************/ +/* timer_tick_init + * setup timer to call cb function periodically, each tick_ms + */ +int timer_tick_init(TIM_TypeDef *tmr, uint32_t tick_ms, OnTick cb); + +/* timer_tick_period + * change the tick_ms period + */ +int timer_tick_period(TIM_TypeDef *tmr, uint32_t tick_ms); + +/* timer_start + * start counting to generate ticks + */ +void timer_start(TIM_TypeDef *tmr); + +/* timer_stop + * stop and reset counting + */ +void timer_stop(TIM_TypeDef *tmr); + +/***************************************************************************/ +#define PWM_CHANNEL_1 0 +#define PWM_CHANNEL_2 1 +#define PWM_CHANNEL_3 2 +#define PWM_CHANNEL_4 3 + +/* pwm_init + * setup pwm timer period, each tick_ms + */ +int pwm_init(TIM_TypeDef *pwm, uint32_t period_ms, OnTick cb); + +/* pwm_channel_enable + * set up pwm channel + */ +int pwm_channel_enable(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle, uint32_t oe); + +/* pwm_channel_disable + * disable pwm channel + */ +int pwm_channel_disable(TIM_TypeDef *pwm, uint32_t channel); + +/* pwm_channel_set + * set up dutycycle for pwm channel + */ +int pwm_channel_set(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle); + +/* pwm_start + * start counting + */ +#define pwm_start(pwm) timer_start(pwm) + +/* pwm_stop + * stop and reset counting + */ +#define pwm_stop(pwm) timer_stop(pwm) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..f248262 --- /dev/null +++ b/src/main.c @@ -0,0 +1,29 @@ +#include "drivers/rcc.h" +#include "drivers/io.h" + +Clock_t sysclks; + +#include "drivers/timer.h" + +int val = 0; + +static void timeout_cb(void) { + io_write(GPIOC, val, PIN_13); + val = !val; +} + +int main(void) { + + rcc_config_clock(CLOCK_CONFIG_PERFORMANCE, &sysclks); + + if(io_configure(GPIOC, PIN_13, PIN_MODE_OUTPUT | PIN_OPT_OUTPUT_PUSHPULL, 0)) return 0; + io_write(GPIOC, 1, PIN_13); + + timer_tick_init(TIM2, 1000, timeout_cb); + timer_start(TIM2); + + for(;;){ + } + + return 0; +} diff --git a/src/tags b/src/tags new file mode 100644 index 0000000..7705469 --- /dev/null +++ b/src/tags @@ -0,0 +1,9180 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_OUTPUT_MODE u-ctags /u-ctags or e-ctags/ +!_TAG_PROGRAM_AUTHOR Universal Ctags Team // +!_TAG_PROGRAM_NAME Universal Ctags /Derived from Exuberant Ctags/ +!_TAG_PROGRAM_URL https://ctags.io/ /official site/ +!_TAG_PROGRAM_VERSION 0.0.0 /3fdf28bc/ +ACR target/stm32f103xb.h /^ __IO uint32_t ACR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +ADC12_COMMON target/stm32f103xb.h /^#define ADC12_COMMON /;" d +ADC1_2_IRQn target/stm32f103xb.h /^ ADC1_2_IRQn = 18, \/*!< ADC1 and ADC2 global Interrupt /;" e enum:__anon72c4c37e0103 +ADC1_BASE target/stm32f103xb.h /^#define ADC1_BASE /;" d +ADC1_IRQHandler target/stm32f103xb.h /^#define ADC1_IRQHandler /;" d +ADC1_IRQ_PRIORITY Untitled Folder/config.h /^#define ADC1_IRQ_PRIORITY /;" d +ADC1_IRQ_PRIORITY config.h /^#define ADC1_IRQ_PRIORITY /;" d +ADC1_IRQn target/stm32f103xb.h /^#define ADC1_IRQn /;" d +ADC1 target/stm32f103xb.h /^#define ADC1 /;" d +ADC2_BASE target/stm32f103xb.h /^#define ADC2_BASE /;" d +ADC2 target/stm32f103xb.h /^#define ADC2 /;" d +ADC_CR1_AWDCH_0 target/stm32f103xb.h /^#define ADC_CR1_AWDCH_0 /;" d +ADC_CR1_AWDCH_1 target/stm32f103xb.h /^#define ADC_CR1_AWDCH_1 /;" d +ADC_CR1_AWDCH_2 target/stm32f103xb.h /^#define ADC_CR1_AWDCH_2 /;" d +ADC_CR1_AWDCH_3 target/stm32f103xb.h /^#define ADC_CR1_AWDCH_3 /;" d +ADC_CR1_AWDCH_4 target/stm32f103xb.h /^#define ADC_CR1_AWDCH_4 /;" d +ADC_CR1_AWDCH_Msk target/stm32f103xb.h /^#define ADC_CR1_AWDCH_Msk /;" d +ADC_CR1_AWDCH_Pos target/stm32f103xb.h /^#define ADC_CR1_AWDCH_Pos /;" d +ADC_CR1_AWDCH target/stm32f103xb.h /^#define ADC_CR1_AWDCH /;" d +ADC_CR1_AWDEN_Msk target/stm32f103xb.h /^#define ADC_CR1_AWDEN_Msk /;" d +ADC_CR1_AWDEN_Pos target/stm32f103xb.h /^#define ADC_CR1_AWDEN_Pos /;" d +ADC_CR1_AWDEN target/stm32f103xb.h /^#define ADC_CR1_AWDEN /;" d +ADC_CR1_AWDIE_Msk target/stm32f103xb.h /^#define ADC_CR1_AWDIE_Msk /;" d +ADC_CR1_AWDIE_Pos target/stm32f103xb.h /^#define ADC_CR1_AWDIE_Pos /;" d +ADC_CR1_AWDIE target/stm32f103xb.h /^#define ADC_CR1_AWDIE /;" d +ADC_CR1_AWDSGL_Msk target/stm32f103xb.h /^#define ADC_CR1_AWDSGL_Msk /;" d +ADC_CR1_AWDSGL_Pos target/stm32f103xb.h /^#define ADC_CR1_AWDSGL_Pos /;" d +ADC_CR1_AWDSGL target/stm32f103xb.h /^#define ADC_CR1_AWDSGL /;" d +ADC_CR1_DISCEN_Msk target/stm32f103xb.h /^#define ADC_CR1_DISCEN_Msk /;" d +ADC_CR1_DISCEN_Pos target/stm32f103xb.h /^#define ADC_CR1_DISCEN_Pos /;" d +ADC_CR1_DISCEN target/stm32f103xb.h /^#define ADC_CR1_DISCEN /;" d +ADC_CR1_DISCNUM_0 target/stm32f103xb.h /^#define ADC_CR1_DISCNUM_0 /;" d +ADC_CR1_DISCNUM_1 target/stm32f103xb.h /^#define ADC_CR1_DISCNUM_1 /;" d +ADC_CR1_DISCNUM_2 target/stm32f103xb.h /^#define ADC_CR1_DISCNUM_2 /;" d +ADC_CR1_DISCNUM_Msk target/stm32f103xb.h /^#define ADC_CR1_DISCNUM_Msk /;" d +ADC_CR1_DISCNUM_Pos target/stm32f103xb.h /^#define ADC_CR1_DISCNUM_Pos /;" d +ADC_CR1_DISCNUM target/stm32f103xb.h /^#define ADC_CR1_DISCNUM /;" d +ADC_CR1_DUALMOD_0 target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_0 /;" d +ADC_CR1_DUALMOD_1 target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_1 /;" d +ADC_CR1_DUALMOD_2 target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_2 /;" d +ADC_CR1_DUALMOD_3 target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_3 /;" d +ADC_CR1_DUALMOD_Msk target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_Msk /;" d +ADC_CR1_DUALMOD_Pos target/stm32f103xb.h /^#define ADC_CR1_DUALMOD_Pos /;" d +ADC_CR1_DUALMOD target/stm32f103xb.h /^#define ADC_CR1_DUALMOD /;" d +ADC_CR1_EOCIE target/stm32f103xb.h /^#define ADC_CR1_EOCIE /;" d +ADC_CR1_EOSIE_Msk target/stm32f103xb.h /^#define ADC_CR1_EOSIE_Msk /;" d +ADC_CR1_EOSIE_Pos target/stm32f103xb.h /^#define ADC_CR1_EOSIE_Pos /;" d +ADC_CR1_EOSIE target/stm32f103xb.h /^#define ADC_CR1_EOSIE /;" d +ADC_CR1_JAUTO_Msk target/stm32f103xb.h /^#define ADC_CR1_JAUTO_Msk /;" d +ADC_CR1_JAUTO_Pos target/stm32f103xb.h /^#define ADC_CR1_JAUTO_Pos /;" d +ADC_CR1_JAUTO target/stm32f103xb.h /^#define ADC_CR1_JAUTO /;" d +ADC_CR1_JAWDEN_Msk target/stm32f103xb.h /^#define ADC_CR1_JAWDEN_Msk /;" d +ADC_CR1_JAWDEN_Pos target/stm32f103xb.h /^#define ADC_CR1_JAWDEN_Pos /;" d +ADC_CR1_JAWDEN target/stm32f103xb.h /^#define ADC_CR1_JAWDEN /;" d +ADC_CR1_JDISCEN_Msk target/stm32f103xb.h /^#define ADC_CR1_JDISCEN_Msk /;" d +ADC_CR1_JDISCEN_Pos target/stm32f103xb.h /^#define ADC_CR1_JDISCEN_Pos /;" d +ADC_CR1_JDISCEN target/stm32f103xb.h /^#define ADC_CR1_JDISCEN /;" d +ADC_CR1_JEOCIE target/stm32f103xb.h /^#define ADC_CR1_JEOCIE /;" d +ADC_CR1_JEOSIE_Msk target/stm32f103xb.h /^#define ADC_CR1_JEOSIE_Msk /;" d +ADC_CR1_JEOSIE_Pos target/stm32f103xb.h /^#define ADC_CR1_JEOSIE_Pos /;" d +ADC_CR1_JEOSIE target/stm32f103xb.h /^#define ADC_CR1_JEOSIE /;" d +ADC_CR1_SCAN_Msk target/stm32f103xb.h /^#define ADC_CR1_SCAN_Msk /;" d +ADC_CR1_SCAN_Pos target/stm32f103xb.h /^#define ADC_CR1_SCAN_Pos /;" d +ADC_CR1_SCAN target/stm32f103xb.h /^#define ADC_CR1_SCAN /;" d +ADC_CR2_ADON_Msk target/stm32f103xb.h /^#define ADC_CR2_ADON_Msk /;" d +ADC_CR2_ADON_Pos target/stm32f103xb.h /^#define ADC_CR2_ADON_Pos /;" d +ADC_CR2_ADON target/stm32f103xb.h /^#define ADC_CR2_ADON /;" d +ADC_CR2_ALIGN_Msk target/stm32f103xb.h /^#define ADC_CR2_ALIGN_Msk /;" d +ADC_CR2_ALIGN_Pos target/stm32f103xb.h /^#define ADC_CR2_ALIGN_Pos /;" d +ADC_CR2_ALIGN target/stm32f103xb.h /^#define ADC_CR2_ALIGN /;" d +ADC_CR2_CAL_Msk target/stm32f103xb.h /^#define ADC_CR2_CAL_Msk /;" d +ADC_CR2_CAL_Pos target/stm32f103xb.h /^#define ADC_CR2_CAL_Pos /;" d +ADC_CR2_CAL target/stm32f103xb.h /^#define ADC_CR2_CAL /;" d +ADC_CR2_CONT_Msk target/stm32f103xb.h /^#define ADC_CR2_CONT_Msk /;" d +ADC_CR2_CONT_Pos target/stm32f103xb.h /^#define ADC_CR2_CONT_Pos /;" d +ADC_CR2_CONT target/stm32f103xb.h /^#define ADC_CR2_CONT /;" d +ADC_CR2_DMA_Msk target/stm32f103xb.h /^#define ADC_CR2_DMA_Msk /;" d +ADC_CR2_DMA_Pos target/stm32f103xb.h /^#define ADC_CR2_DMA_Pos /;" d +ADC_CR2_DMA target/stm32f103xb.h /^#define ADC_CR2_DMA /;" d +ADC_CR2_EXTSEL_0 target/stm32f103xb.h /^#define ADC_CR2_EXTSEL_0 /;" d +ADC_CR2_EXTSEL_1 target/stm32f103xb.h /^#define ADC_CR2_EXTSEL_1 /;" d +ADC_CR2_EXTSEL_2 target/stm32f103xb.h /^#define ADC_CR2_EXTSEL_2 /;" d +ADC_CR2_EXTSEL_Msk target/stm32f103xb.h /^#define ADC_CR2_EXTSEL_Msk /;" d +ADC_CR2_EXTSEL_Pos target/stm32f103xb.h /^#define ADC_CR2_EXTSEL_Pos /;" d +ADC_CR2_EXTSEL target/stm32f103xb.h /^#define ADC_CR2_EXTSEL /;" d +ADC_CR2_EXTTRIG_Msk target/stm32f103xb.h /^#define ADC_CR2_EXTTRIG_Msk /;" d +ADC_CR2_EXTTRIG_Pos target/stm32f103xb.h /^#define ADC_CR2_EXTTRIG_Pos /;" d +ADC_CR2_EXTTRIG target/stm32f103xb.h /^#define ADC_CR2_EXTTRIG /;" d +ADC_CR2_JEXTSEL_0 target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL_0 /;" d +ADC_CR2_JEXTSEL_1 target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL_1 /;" d +ADC_CR2_JEXTSEL_2 target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL_2 /;" d +ADC_CR2_JEXTSEL_Msk target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL_Msk /;" d +ADC_CR2_JEXTSEL_Pos target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL_Pos /;" d +ADC_CR2_JEXTSEL target/stm32f103xb.h /^#define ADC_CR2_JEXTSEL /;" d +ADC_CR2_JEXTTRIG_Msk target/stm32f103xb.h /^#define ADC_CR2_JEXTTRIG_Msk /;" d +ADC_CR2_JEXTTRIG_Pos target/stm32f103xb.h /^#define ADC_CR2_JEXTTRIG_Pos /;" d +ADC_CR2_JEXTTRIG target/stm32f103xb.h /^#define ADC_CR2_JEXTTRIG /;" d +ADC_CR2_JSWSTART_Msk target/stm32f103xb.h /^#define ADC_CR2_JSWSTART_Msk /;" d +ADC_CR2_JSWSTART_Pos target/stm32f103xb.h /^#define ADC_CR2_JSWSTART_Pos /;" d +ADC_CR2_JSWSTART target/stm32f103xb.h /^#define ADC_CR2_JSWSTART /;" d +ADC_CR2_RSTCAL_Msk target/stm32f103xb.h /^#define ADC_CR2_RSTCAL_Msk /;" d +ADC_CR2_RSTCAL_Pos target/stm32f103xb.h /^#define ADC_CR2_RSTCAL_Pos /;" d +ADC_CR2_RSTCAL target/stm32f103xb.h /^#define ADC_CR2_RSTCAL /;" d +ADC_CR2_SWSTART_Msk target/stm32f103xb.h /^#define ADC_CR2_SWSTART_Msk /;" d +ADC_CR2_SWSTART_Pos target/stm32f103xb.h /^#define ADC_CR2_SWSTART_Pos /;" d +ADC_CR2_SWSTART target/stm32f103xb.h /^#define ADC_CR2_SWSTART /;" d +ADC_CR2_TSVREFE_Msk target/stm32f103xb.h /^#define ADC_CR2_TSVREFE_Msk /;" d +ADC_CR2_TSVREFE_Pos target/stm32f103xb.h /^#define ADC_CR2_TSVREFE_Pos /;" d +ADC_CR2_TSVREFE target/stm32f103xb.h /^#define ADC_CR2_TSVREFE /;" d +ADC_Common_TypeDef target/stm32f103xb.h /^} ADC_Common_TypeDef;$/;" t typeref:struct:__anon72c4c37e0308 +ADC_DR_ADC2DATA_Msk target/stm32f103xb.h /^#define ADC_DR_ADC2DATA_Msk /;" d +ADC_DR_ADC2DATA_Pos target/stm32f103xb.h /^#define ADC_DR_ADC2DATA_Pos /;" d +ADC_DR_ADC2DATA target/stm32f103xb.h /^#define ADC_DR_ADC2DATA /;" d +ADC_DR_DATA_Msk target/stm32f103xb.h /^#define ADC_DR_DATA_Msk /;" d +ADC_DR_DATA_Pos target/stm32f103xb.h /^#define ADC_DR_DATA_Pos /;" d +ADC_DR_DATA target/stm32f103xb.h /^#define ADC_DR_DATA /;" d +ADC_HTR_HT_Msk target/stm32f103xb.h /^#define ADC_HTR_HT_Msk /;" d +ADC_HTR_HT_Pos target/stm32f103xb.h /^#define ADC_HTR_HT_Pos /;" d +ADC_HTR_HT target/stm32f103xb.h /^#define ADC_HTR_HT /;" d +ADC_JDR1_JDATA_Msk target/stm32f103xb.h /^#define ADC_JDR1_JDATA_Msk /;" d +ADC_JDR1_JDATA_Pos target/stm32f103xb.h /^#define ADC_JDR1_JDATA_Pos /;" d +ADC_JDR1_JDATA target/stm32f103xb.h /^#define ADC_JDR1_JDATA /;" d +ADC_JDR2_JDATA_Msk target/stm32f103xb.h /^#define ADC_JDR2_JDATA_Msk /;" d +ADC_JDR2_JDATA_Pos target/stm32f103xb.h /^#define ADC_JDR2_JDATA_Pos /;" d +ADC_JDR2_JDATA target/stm32f103xb.h /^#define ADC_JDR2_JDATA /;" d +ADC_JDR3_JDATA_Msk target/stm32f103xb.h /^#define ADC_JDR3_JDATA_Msk /;" d +ADC_JDR3_JDATA_Pos target/stm32f103xb.h /^#define ADC_JDR3_JDATA_Pos /;" d +ADC_JDR3_JDATA target/stm32f103xb.h /^#define ADC_JDR3_JDATA /;" d +ADC_JDR4_JDATA_Msk target/stm32f103xb.h /^#define ADC_JDR4_JDATA_Msk /;" d +ADC_JDR4_JDATA_Pos target/stm32f103xb.h /^#define ADC_JDR4_JDATA_Pos /;" d +ADC_JDR4_JDATA target/stm32f103xb.h /^#define ADC_JDR4_JDATA /;" d +ADC_JOFR1_JOFFSET1_Msk target/stm32f103xb.h /^#define ADC_JOFR1_JOFFSET1_Msk /;" d +ADC_JOFR1_JOFFSET1_Pos target/stm32f103xb.h /^#define ADC_JOFR1_JOFFSET1_Pos /;" d +ADC_JOFR1_JOFFSET1 target/stm32f103xb.h /^#define ADC_JOFR1_JOFFSET1 /;" d +ADC_JOFR2_JOFFSET2_Msk target/stm32f103xb.h /^#define ADC_JOFR2_JOFFSET2_Msk /;" d +ADC_JOFR2_JOFFSET2_Pos target/stm32f103xb.h /^#define ADC_JOFR2_JOFFSET2_Pos /;" d +ADC_JOFR2_JOFFSET2 target/stm32f103xb.h /^#define ADC_JOFR2_JOFFSET2 /;" d +ADC_JOFR3_JOFFSET3_Msk target/stm32f103xb.h /^#define ADC_JOFR3_JOFFSET3_Msk /;" d +ADC_JOFR3_JOFFSET3_Pos target/stm32f103xb.h /^#define ADC_JOFR3_JOFFSET3_Pos /;" d +ADC_JOFR3_JOFFSET3 target/stm32f103xb.h /^#define ADC_JOFR3_JOFFSET3 /;" d +ADC_JOFR4_JOFFSET4_Msk target/stm32f103xb.h /^#define ADC_JOFR4_JOFFSET4_Msk /;" d +ADC_JOFR4_JOFFSET4_Pos target/stm32f103xb.h /^#define ADC_JOFR4_JOFFSET4_Pos /;" d +ADC_JOFR4_JOFFSET4 target/stm32f103xb.h /^#define ADC_JOFR4_JOFFSET4 /;" d +ADC_JSQR_JL_0 target/stm32f103xb.h /^#define ADC_JSQR_JL_0 /;" d +ADC_JSQR_JL_1 target/stm32f103xb.h /^#define ADC_JSQR_JL_1 /;" d +ADC_JSQR_JL_Msk target/stm32f103xb.h /^#define ADC_JSQR_JL_Msk /;" d +ADC_JSQR_JL_Pos target/stm32f103xb.h /^#define ADC_JSQR_JL_Pos /;" d +ADC_JSQR_JL target/stm32f103xb.h /^#define ADC_JSQR_JL /;" d +ADC_JSQR_JSQ1_0 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_0 /;" d +ADC_JSQR_JSQ1_1 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_1 /;" d +ADC_JSQR_JSQ1_2 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_2 /;" d +ADC_JSQR_JSQ1_3 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_3 /;" d +ADC_JSQR_JSQ1_4 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_4 /;" d +ADC_JSQR_JSQ1_Msk target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_Msk /;" d +ADC_JSQR_JSQ1_Pos target/stm32f103xb.h /^#define ADC_JSQR_JSQ1_Pos /;" d +ADC_JSQR_JSQ1 target/stm32f103xb.h /^#define ADC_JSQR_JSQ1 /;" d +ADC_JSQR_JSQ2_0 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_0 /;" d +ADC_JSQR_JSQ2_1 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_1 /;" d +ADC_JSQR_JSQ2_2 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_2 /;" d +ADC_JSQR_JSQ2_3 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_3 /;" d +ADC_JSQR_JSQ2_4 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_4 /;" d +ADC_JSQR_JSQ2_Msk target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_Msk /;" d +ADC_JSQR_JSQ2_Pos target/stm32f103xb.h /^#define ADC_JSQR_JSQ2_Pos /;" d +ADC_JSQR_JSQ2 target/stm32f103xb.h /^#define ADC_JSQR_JSQ2 /;" d +ADC_JSQR_JSQ3_0 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_0 /;" d +ADC_JSQR_JSQ3_1 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_1 /;" d +ADC_JSQR_JSQ3_2 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_2 /;" d +ADC_JSQR_JSQ3_3 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_3 /;" d +ADC_JSQR_JSQ3_4 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_4 /;" d +ADC_JSQR_JSQ3_Msk target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_Msk /;" d +ADC_JSQR_JSQ3_Pos target/stm32f103xb.h /^#define ADC_JSQR_JSQ3_Pos /;" d +ADC_JSQR_JSQ3 target/stm32f103xb.h /^#define ADC_JSQR_JSQ3 /;" d +ADC_JSQR_JSQ4_0 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_0 /;" d +ADC_JSQR_JSQ4_1 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_1 /;" d +ADC_JSQR_JSQ4_2 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_2 /;" d +ADC_JSQR_JSQ4_3 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_3 /;" d +ADC_JSQR_JSQ4_4 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_4 /;" d +ADC_JSQR_JSQ4_Msk target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_Msk /;" d +ADC_JSQR_JSQ4_Pos target/stm32f103xb.h /^#define ADC_JSQR_JSQ4_Pos /;" d +ADC_JSQR_JSQ4 target/stm32f103xb.h /^#define ADC_JSQR_JSQ4 /;" d +ADC_LTR_LT_Msk target/stm32f103xb.h /^#define ADC_LTR_LT_Msk /;" d +ADC_LTR_LT_Pos target/stm32f103xb.h /^#define ADC_LTR_LT_Pos /;" d +ADC_LTR_LT target/stm32f103xb.h /^#define ADC_LTR_LT /;" d +ADC_MULTIMODE_SUPPORT target/stm32f103xb.h /^#define ADC_MULTIMODE_SUPPORT /;" d +ADC_SMPR1_SMP10_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP10_0 /;" d +ADC_SMPR1_SMP10_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP10_1 /;" d +ADC_SMPR1_SMP10_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP10_2 /;" d +ADC_SMPR1_SMP10_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP10_Msk /;" d +ADC_SMPR1_SMP10_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP10_Pos /;" d +ADC_SMPR1_SMP10 target/stm32f103xb.h /^#define ADC_SMPR1_SMP10 /;" d +ADC_SMPR1_SMP11_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP11_0 /;" d +ADC_SMPR1_SMP11_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP11_1 /;" d +ADC_SMPR1_SMP11_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP11_2 /;" d +ADC_SMPR1_SMP11_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP11_Msk /;" d +ADC_SMPR1_SMP11_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP11_Pos /;" d +ADC_SMPR1_SMP11 target/stm32f103xb.h /^#define ADC_SMPR1_SMP11 /;" d +ADC_SMPR1_SMP12_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP12_0 /;" d +ADC_SMPR1_SMP12_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP12_1 /;" d +ADC_SMPR1_SMP12_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP12_2 /;" d +ADC_SMPR1_SMP12_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP12_Msk /;" d +ADC_SMPR1_SMP12_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP12_Pos /;" d +ADC_SMPR1_SMP12 target/stm32f103xb.h /^#define ADC_SMPR1_SMP12 /;" d +ADC_SMPR1_SMP13_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP13_0 /;" d +ADC_SMPR1_SMP13_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP13_1 /;" d +ADC_SMPR1_SMP13_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP13_2 /;" d +ADC_SMPR1_SMP13_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP13_Msk /;" d +ADC_SMPR1_SMP13_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP13_Pos /;" d +ADC_SMPR1_SMP13 target/stm32f103xb.h /^#define ADC_SMPR1_SMP13 /;" d +ADC_SMPR1_SMP14_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP14_0 /;" d +ADC_SMPR1_SMP14_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP14_1 /;" d +ADC_SMPR1_SMP14_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP14_2 /;" d +ADC_SMPR1_SMP14_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP14_Msk /;" d +ADC_SMPR1_SMP14_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP14_Pos /;" d +ADC_SMPR1_SMP14 target/stm32f103xb.h /^#define ADC_SMPR1_SMP14 /;" d +ADC_SMPR1_SMP15_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP15_0 /;" d +ADC_SMPR1_SMP15_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP15_1 /;" d +ADC_SMPR1_SMP15_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP15_2 /;" d +ADC_SMPR1_SMP15_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP15_Msk /;" d +ADC_SMPR1_SMP15_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP15_Pos /;" d +ADC_SMPR1_SMP15 target/stm32f103xb.h /^#define ADC_SMPR1_SMP15 /;" d +ADC_SMPR1_SMP16_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP16_0 /;" d +ADC_SMPR1_SMP16_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP16_1 /;" d +ADC_SMPR1_SMP16_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP16_2 /;" d +ADC_SMPR1_SMP16_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP16_Msk /;" d +ADC_SMPR1_SMP16_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP16_Pos /;" d +ADC_SMPR1_SMP16 target/stm32f103xb.h /^#define ADC_SMPR1_SMP16 /;" d +ADC_SMPR1_SMP17_0 target/stm32f103xb.h /^#define ADC_SMPR1_SMP17_0 /;" d +ADC_SMPR1_SMP17_1 target/stm32f103xb.h /^#define ADC_SMPR1_SMP17_1 /;" d +ADC_SMPR1_SMP17_2 target/stm32f103xb.h /^#define ADC_SMPR1_SMP17_2 /;" d +ADC_SMPR1_SMP17_Msk target/stm32f103xb.h /^#define ADC_SMPR1_SMP17_Msk /;" d +ADC_SMPR1_SMP17_Pos target/stm32f103xb.h /^#define ADC_SMPR1_SMP17_Pos /;" d +ADC_SMPR1_SMP17 target/stm32f103xb.h /^#define ADC_SMPR1_SMP17 /;" d +ADC_SMPR2_SMP0_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP0_0 /;" d +ADC_SMPR2_SMP0_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP0_1 /;" d +ADC_SMPR2_SMP0_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP0_2 /;" d +ADC_SMPR2_SMP0_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP0_Msk /;" d +ADC_SMPR2_SMP0_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP0_Pos /;" d +ADC_SMPR2_SMP0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP0 /;" d +ADC_SMPR2_SMP1_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP1_0 /;" d +ADC_SMPR2_SMP1_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP1_1 /;" d +ADC_SMPR2_SMP1_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP1_2 /;" d +ADC_SMPR2_SMP1_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP1_Msk /;" d +ADC_SMPR2_SMP1_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP1_Pos /;" d +ADC_SMPR2_SMP1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP1 /;" d +ADC_SMPR2_SMP2_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP2_0 /;" d +ADC_SMPR2_SMP2_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP2_1 /;" d +ADC_SMPR2_SMP2_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP2_2 /;" d +ADC_SMPR2_SMP2_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP2_Msk /;" d +ADC_SMPR2_SMP2_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP2_Pos /;" d +ADC_SMPR2_SMP2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP2 /;" d +ADC_SMPR2_SMP3_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP3_0 /;" d +ADC_SMPR2_SMP3_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP3_1 /;" d +ADC_SMPR2_SMP3_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP3_2 /;" d +ADC_SMPR2_SMP3_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP3_Msk /;" d +ADC_SMPR2_SMP3_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP3_Pos /;" d +ADC_SMPR2_SMP3 target/stm32f103xb.h /^#define ADC_SMPR2_SMP3 /;" d +ADC_SMPR2_SMP4_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP4_0 /;" d +ADC_SMPR2_SMP4_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP4_1 /;" d +ADC_SMPR2_SMP4_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP4_2 /;" d +ADC_SMPR2_SMP4_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP4_Msk /;" d +ADC_SMPR2_SMP4_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP4_Pos /;" d +ADC_SMPR2_SMP4 target/stm32f103xb.h /^#define ADC_SMPR2_SMP4 /;" d +ADC_SMPR2_SMP5_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP5_0 /;" d +ADC_SMPR2_SMP5_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP5_1 /;" d +ADC_SMPR2_SMP5_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP5_2 /;" d +ADC_SMPR2_SMP5_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP5_Msk /;" d +ADC_SMPR2_SMP5_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP5_Pos /;" d +ADC_SMPR2_SMP5 target/stm32f103xb.h /^#define ADC_SMPR2_SMP5 /;" d +ADC_SMPR2_SMP6_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP6_0 /;" d +ADC_SMPR2_SMP6_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP6_1 /;" d +ADC_SMPR2_SMP6_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP6_2 /;" d +ADC_SMPR2_SMP6_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP6_Msk /;" d +ADC_SMPR2_SMP6_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP6_Pos /;" d +ADC_SMPR2_SMP6 target/stm32f103xb.h /^#define ADC_SMPR2_SMP6 /;" d +ADC_SMPR2_SMP7_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP7_0 /;" d +ADC_SMPR2_SMP7_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP7_1 /;" d +ADC_SMPR2_SMP7_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP7_2 /;" d +ADC_SMPR2_SMP7_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP7_Msk /;" d +ADC_SMPR2_SMP7_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP7_Pos /;" d +ADC_SMPR2_SMP7 target/stm32f103xb.h /^#define ADC_SMPR2_SMP7 /;" d +ADC_SMPR2_SMP8_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP8_0 /;" d +ADC_SMPR2_SMP8_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP8_1 /;" d +ADC_SMPR2_SMP8_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP8_2 /;" d +ADC_SMPR2_SMP8_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP8_Msk /;" d +ADC_SMPR2_SMP8_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP8_Pos /;" d +ADC_SMPR2_SMP8 target/stm32f103xb.h /^#define ADC_SMPR2_SMP8 /;" d +ADC_SMPR2_SMP9_0 target/stm32f103xb.h /^#define ADC_SMPR2_SMP9_0 /;" d +ADC_SMPR2_SMP9_1 target/stm32f103xb.h /^#define ADC_SMPR2_SMP9_1 /;" d +ADC_SMPR2_SMP9_2 target/stm32f103xb.h /^#define ADC_SMPR2_SMP9_2 /;" d +ADC_SMPR2_SMP9_Msk target/stm32f103xb.h /^#define ADC_SMPR2_SMP9_Msk /;" d +ADC_SMPR2_SMP9_Pos target/stm32f103xb.h /^#define ADC_SMPR2_SMP9_Pos /;" d +ADC_SMPR2_SMP9 target/stm32f103xb.h /^#define ADC_SMPR2_SMP9 /;" d +ADC_SQR1_L_0 target/stm32f103xb.h /^#define ADC_SQR1_L_0 /;" d +ADC_SQR1_L_1 target/stm32f103xb.h /^#define ADC_SQR1_L_1 /;" d +ADC_SQR1_L_2 target/stm32f103xb.h /^#define ADC_SQR1_L_2 /;" d +ADC_SQR1_L_3 target/stm32f103xb.h /^#define ADC_SQR1_L_3 /;" d +ADC_SQR1_L_Msk target/stm32f103xb.h /^#define ADC_SQR1_L_Msk /;" d +ADC_SQR1_L_Pos target/stm32f103xb.h /^#define ADC_SQR1_L_Pos /;" d +ADC_SQR1_L target/stm32f103xb.h /^#define ADC_SQR1_L /;" d +ADC_SQR1_SQ13_0 target/stm32f103xb.h /^#define ADC_SQR1_SQ13_0 /;" d +ADC_SQR1_SQ13_1 target/stm32f103xb.h /^#define ADC_SQR1_SQ13_1 /;" d +ADC_SQR1_SQ13_2 target/stm32f103xb.h /^#define ADC_SQR1_SQ13_2 /;" d +ADC_SQR1_SQ13_3 target/stm32f103xb.h /^#define ADC_SQR1_SQ13_3 /;" d +ADC_SQR1_SQ13_4 target/stm32f103xb.h /^#define ADC_SQR1_SQ13_4 /;" d +ADC_SQR1_SQ13_Msk target/stm32f103xb.h /^#define ADC_SQR1_SQ13_Msk /;" d +ADC_SQR1_SQ13_Pos target/stm32f103xb.h /^#define ADC_SQR1_SQ13_Pos /;" d +ADC_SQR1_SQ13 target/stm32f103xb.h /^#define ADC_SQR1_SQ13 /;" d +ADC_SQR1_SQ14_0 target/stm32f103xb.h /^#define ADC_SQR1_SQ14_0 /;" d +ADC_SQR1_SQ14_1 target/stm32f103xb.h /^#define ADC_SQR1_SQ14_1 /;" d +ADC_SQR1_SQ14_2 target/stm32f103xb.h /^#define ADC_SQR1_SQ14_2 /;" d +ADC_SQR1_SQ14_3 target/stm32f103xb.h /^#define ADC_SQR1_SQ14_3 /;" d +ADC_SQR1_SQ14_4 target/stm32f103xb.h /^#define ADC_SQR1_SQ14_4 /;" d +ADC_SQR1_SQ14_Msk target/stm32f103xb.h /^#define ADC_SQR1_SQ14_Msk /;" d +ADC_SQR1_SQ14_Pos target/stm32f103xb.h /^#define ADC_SQR1_SQ14_Pos /;" d +ADC_SQR1_SQ14 target/stm32f103xb.h /^#define ADC_SQR1_SQ14 /;" d +ADC_SQR1_SQ15_0 target/stm32f103xb.h /^#define ADC_SQR1_SQ15_0 /;" d +ADC_SQR1_SQ15_1 target/stm32f103xb.h /^#define ADC_SQR1_SQ15_1 /;" d +ADC_SQR1_SQ15_2 target/stm32f103xb.h /^#define ADC_SQR1_SQ15_2 /;" d +ADC_SQR1_SQ15_3 target/stm32f103xb.h /^#define ADC_SQR1_SQ15_3 /;" d +ADC_SQR1_SQ15_4 target/stm32f103xb.h /^#define ADC_SQR1_SQ15_4 /;" d +ADC_SQR1_SQ15_Msk target/stm32f103xb.h /^#define ADC_SQR1_SQ15_Msk /;" d +ADC_SQR1_SQ15_Pos target/stm32f103xb.h /^#define ADC_SQR1_SQ15_Pos /;" d +ADC_SQR1_SQ15 target/stm32f103xb.h /^#define ADC_SQR1_SQ15 /;" d +ADC_SQR1_SQ16_0 target/stm32f103xb.h /^#define ADC_SQR1_SQ16_0 /;" d +ADC_SQR1_SQ16_1 target/stm32f103xb.h /^#define ADC_SQR1_SQ16_1 /;" d +ADC_SQR1_SQ16_2 target/stm32f103xb.h /^#define ADC_SQR1_SQ16_2 /;" d +ADC_SQR1_SQ16_3 target/stm32f103xb.h /^#define ADC_SQR1_SQ16_3 /;" d +ADC_SQR1_SQ16_4 target/stm32f103xb.h /^#define ADC_SQR1_SQ16_4 /;" d +ADC_SQR1_SQ16_Msk target/stm32f103xb.h /^#define ADC_SQR1_SQ16_Msk /;" d +ADC_SQR1_SQ16_Pos target/stm32f103xb.h /^#define ADC_SQR1_SQ16_Pos /;" d +ADC_SQR1_SQ16 target/stm32f103xb.h /^#define ADC_SQR1_SQ16 /;" d +ADC_SQR2_SQ10_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ10_0 /;" d +ADC_SQR2_SQ10_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ10_1 /;" d +ADC_SQR2_SQ10_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ10_2 /;" d +ADC_SQR2_SQ10_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ10_3 /;" d +ADC_SQR2_SQ10_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ10_4 /;" d +ADC_SQR2_SQ10_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ10_Msk /;" d +ADC_SQR2_SQ10_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ10_Pos /;" d +ADC_SQR2_SQ10 target/stm32f103xb.h /^#define ADC_SQR2_SQ10 /;" d +ADC_SQR2_SQ11_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ11_0 /;" d +ADC_SQR2_SQ11_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ11_1 /;" d +ADC_SQR2_SQ11_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ11_2 /;" d +ADC_SQR2_SQ11_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ11_3 /;" d +ADC_SQR2_SQ11_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ11_4 /;" d +ADC_SQR2_SQ11_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ11_Msk /;" d +ADC_SQR2_SQ11_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ11_Pos /;" d +ADC_SQR2_SQ11 target/stm32f103xb.h /^#define ADC_SQR2_SQ11 /;" d +ADC_SQR2_SQ12_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ12_0 /;" d +ADC_SQR2_SQ12_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ12_1 /;" d +ADC_SQR2_SQ12_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ12_2 /;" d +ADC_SQR2_SQ12_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ12_3 /;" d +ADC_SQR2_SQ12_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ12_4 /;" d +ADC_SQR2_SQ12_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ12_Msk /;" d +ADC_SQR2_SQ12_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ12_Pos /;" d +ADC_SQR2_SQ12 target/stm32f103xb.h /^#define ADC_SQR2_SQ12 /;" d +ADC_SQR2_SQ7_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ7_0 /;" d +ADC_SQR2_SQ7_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ7_1 /;" d +ADC_SQR2_SQ7_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ7_2 /;" d +ADC_SQR2_SQ7_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ7_3 /;" d +ADC_SQR2_SQ7_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ7_4 /;" d +ADC_SQR2_SQ7_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ7_Msk /;" d +ADC_SQR2_SQ7_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ7_Pos /;" d +ADC_SQR2_SQ7 target/stm32f103xb.h /^#define ADC_SQR2_SQ7 /;" d +ADC_SQR2_SQ8_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ8_0 /;" d +ADC_SQR2_SQ8_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ8_1 /;" d +ADC_SQR2_SQ8_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ8_2 /;" d +ADC_SQR2_SQ8_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ8_3 /;" d +ADC_SQR2_SQ8_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ8_4 /;" d +ADC_SQR2_SQ8_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ8_Msk /;" d +ADC_SQR2_SQ8_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ8_Pos /;" d +ADC_SQR2_SQ8 target/stm32f103xb.h /^#define ADC_SQR2_SQ8 /;" d +ADC_SQR2_SQ9_0 target/stm32f103xb.h /^#define ADC_SQR2_SQ9_0 /;" d +ADC_SQR2_SQ9_1 target/stm32f103xb.h /^#define ADC_SQR2_SQ9_1 /;" d +ADC_SQR2_SQ9_2 target/stm32f103xb.h /^#define ADC_SQR2_SQ9_2 /;" d +ADC_SQR2_SQ9_3 target/stm32f103xb.h /^#define ADC_SQR2_SQ9_3 /;" d +ADC_SQR2_SQ9_4 target/stm32f103xb.h /^#define ADC_SQR2_SQ9_4 /;" d +ADC_SQR2_SQ9_Msk target/stm32f103xb.h /^#define ADC_SQR2_SQ9_Msk /;" d +ADC_SQR2_SQ9_Pos target/stm32f103xb.h /^#define ADC_SQR2_SQ9_Pos /;" d +ADC_SQR2_SQ9 target/stm32f103xb.h /^#define ADC_SQR2_SQ9 /;" d +ADC_SQR3_SQ1_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ1_0 /;" d +ADC_SQR3_SQ1_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ1_1 /;" d +ADC_SQR3_SQ1_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ1_2 /;" d +ADC_SQR3_SQ1_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ1_3 /;" d +ADC_SQR3_SQ1_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ1_4 /;" d +ADC_SQR3_SQ1_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ1_Msk /;" d +ADC_SQR3_SQ1_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ1_Pos /;" d +ADC_SQR3_SQ1 target/stm32f103xb.h /^#define ADC_SQR3_SQ1 /;" d +ADC_SQR3_SQ2_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ2_0 /;" d +ADC_SQR3_SQ2_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ2_1 /;" d +ADC_SQR3_SQ2_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ2_2 /;" d +ADC_SQR3_SQ2_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ2_3 /;" d +ADC_SQR3_SQ2_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ2_4 /;" d +ADC_SQR3_SQ2_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ2_Msk /;" d +ADC_SQR3_SQ2_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ2_Pos /;" d +ADC_SQR3_SQ2 target/stm32f103xb.h /^#define ADC_SQR3_SQ2 /;" d +ADC_SQR3_SQ3_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ3_0 /;" d +ADC_SQR3_SQ3_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ3_1 /;" d +ADC_SQR3_SQ3_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ3_2 /;" d +ADC_SQR3_SQ3_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ3_3 /;" d +ADC_SQR3_SQ3_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ3_4 /;" d +ADC_SQR3_SQ3_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ3_Msk /;" d +ADC_SQR3_SQ3_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ3_Pos /;" d +ADC_SQR3_SQ3 target/stm32f103xb.h /^#define ADC_SQR3_SQ3 /;" d +ADC_SQR3_SQ4_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ4_0 /;" d +ADC_SQR3_SQ4_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ4_1 /;" d +ADC_SQR3_SQ4_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ4_2 /;" d +ADC_SQR3_SQ4_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ4_3 /;" d +ADC_SQR3_SQ4_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ4_4 /;" d +ADC_SQR3_SQ4_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ4_Msk /;" d +ADC_SQR3_SQ4_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ4_Pos /;" d +ADC_SQR3_SQ4 target/stm32f103xb.h /^#define ADC_SQR3_SQ4 /;" d +ADC_SQR3_SQ5_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ5_0 /;" d +ADC_SQR3_SQ5_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ5_1 /;" d +ADC_SQR3_SQ5_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ5_2 /;" d +ADC_SQR3_SQ5_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ5_3 /;" d +ADC_SQR3_SQ5_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ5_4 /;" d +ADC_SQR3_SQ5_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ5_Msk /;" d +ADC_SQR3_SQ5_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ5_Pos /;" d +ADC_SQR3_SQ5 target/stm32f103xb.h /^#define ADC_SQR3_SQ5 /;" d +ADC_SQR3_SQ6_0 target/stm32f103xb.h /^#define ADC_SQR3_SQ6_0 /;" d +ADC_SQR3_SQ6_1 target/stm32f103xb.h /^#define ADC_SQR3_SQ6_1 /;" d +ADC_SQR3_SQ6_2 target/stm32f103xb.h /^#define ADC_SQR3_SQ6_2 /;" d +ADC_SQR3_SQ6_3 target/stm32f103xb.h /^#define ADC_SQR3_SQ6_3 /;" d +ADC_SQR3_SQ6_4 target/stm32f103xb.h /^#define ADC_SQR3_SQ6_4 /;" d +ADC_SQR3_SQ6_Msk target/stm32f103xb.h /^#define ADC_SQR3_SQ6_Msk /;" d +ADC_SQR3_SQ6_Pos target/stm32f103xb.h /^#define ADC_SQR3_SQ6_Pos /;" d +ADC_SQR3_SQ6 target/stm32f103xb.h /^#define ADC_SQR3_SQ6 /;" d +ADC_SR_AWD_Msk target/stm32f103xb.h /^#define ADC_SR_AWD_Msk /;" d +ADC_SR_AWD_Pos target/stm32f103xb.h /^#define ADC_SR_AWD_Pos /;" d +ADC_SR_AWD target/stm32f103xb.h /^#define ADC_SR_AWD /;" d +ADC_SR_EOC target/stm32f103xb.h /^#define ADC_SR_EOC /;" d +ADC_SR_EOS_Msk target/stm32f103xb.h /^#define ADC_SR_EOS_Msk /;" d +ADC_SR_EOS_Pos target/stm32f103xb.h /^#define ADC_SR_EOS_Pos /;" d +ADC_SR_EOS target/stm32f103xb.h /^#define ADC_SR_EOS /;" d +ADC_SR_JEOC target/stm32f103xb.h /^#define ADC_SR_JEOC /;" d +ADC_SR_JEOS_Msk target/stm32f103xb.h /^#define ADC_SR_JEOS_Msk /;" d +ADC_SR_JEOS_Pos target/stm32f103xb.h /^#define ADC_SR_JEOS_Pos /;" d +ADC_SR_JEOS target/stm32f103xb.h /^#define ADC_SR_JEOS /;" d +ADC_SR_JSTRT_Msk target/stm32f103xb.h /^#define ADC_SR_JSTRT_Msk /;" d +ADC_SR_JSTRT_Pos target/stm32f103xb.h /^#define ADC_SR_JSTRT_Pos /;" d +ADC_SR_JSTRT target/stm32f103xb.h /^#define ADC_SR_JSTRT /;" d +ADC_SR_STRT_Msk target/stm32f103xb.h /^#define ADC_SR_STRT_Msk /;" d +ADC_SR_STRT_Pos target/stm32f103xb.h /^#define ADC_SR_STRT_Pos /;" d +ADC_SR_STRT target/stm32f103xb.h /^#define ADC_SR_STRT /;" d +ADC_TypeDef target/stm32f103xb.h /^} ADC_TypeDef;$/;" t typeref:struct:__anon72c4c37e0208 +AFIO_BASE target/stm32f103xb.h /^#define AFIO_BASE /;" d +AFIO_EVCR_EVOE_Msk target/stm32f103xb.h /^#define AFIO_EVCR_EVOE_Msk /;" d +AFIO_EVCR_EVOE_Pos target/stm32f103xb.h /^#define AFIO_EVCR_EVOE_Pos /;" d +AFIO_EVCR_EVOE target/stm32f103xb.h /^#define AFIO_EVCR_EVOE /;" d +AFIO_EVCR_PIN_0 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_0 /;" d +AFIO_EVCR_PIN_1 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_1 /;" d +AFIO_EVCR_PIN_2 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_2 /;" d +AFIO_EVCR_PIN_3 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_3 /;" d +AFIO_EVCR_PIN_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_Msk /;" d +AFIO_EVCR_PIN_PX0 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX0 /;" d +AFIO_EVCR_PIN_PX10_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX10_Msk /;" d +AFIO_EVCR_PIN_PX10_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX10_Pos /;" d +AFIO_EVCR_PIN_PX10 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX10 /;" d +AFIO_EVCR_PIN_PX11_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX11_Msk /;" d +AFIO_EVCR_PIN_PX11_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX11_Pos /;" d +AFIO_EVCR_PIN_PX11 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX11 /;" d +AFIO_EVCR_PIN_PX12_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX12_Msk /;" d +AFIO_EVCR_PIN_PX12_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX12_Pos /;" d +AFIO_EVCR_PIN_PX12 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX12 /;" d +AFIO_EVCR_PIN_PX13_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX13_Msk /;" d +AFIO_EVCR_PIN_PX13_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX13_Pos /;" d +AFIO_EVCR_PIN_PX13 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX13 /;" d +AFIO_EVCR_PIN_PX14_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX14_Msk /;" d +AFIO_EVCR_PIN_PX14_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX14_Pos /;" d +AFIO_EVCR_PIN_PX14 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX14 /;" d +AFIO_EVCR_PIN_PX15_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX15_Msk /;" d +AFIO_EVCR_PIN_PX15_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX15_Pos /;" d +AFIO_EVCR_PIN_PX15 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX15 /;" d +AFIO_EVCR_PIN_PX1_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX1_Msk /;" d +AFIO_EVCR_PIN_PX1_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX1_Pos /;" d +AFIO_EVCR_PIN_PX1 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX1 /;" d +AFIO_EVCR_PIN_PX2_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX2_Msk /;" d +AFIO_EVCR_PIN_PX2_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX2_Pos /;" d +AFIO_EVCR_PIN_PX2 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX2 /;" d +AFIO_EVCR_PIN_PX3_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX3_Msk /;" d +AFIO_EVCR_PIN_PX3_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX3_Pos /;" d +AFIO_EVCR_PIN_PX3 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX3 /;" d +AFIO_EVCR_PIN_PX4_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX4_Msk /;" d +AFIO_EVCR_PIN_PX4_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX4_Pos /;" d +AFIO_EVCR_PIN_PX4 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX4 /;" d +AFIO_EVCR_PIN_PX5_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX5_Msk /;" d +AFIO_EVCR_PIN_PX5_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX5_Pos /;" d +AFIO_EVCR_PIN_PX5 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX5 /;" d +AFIO_EVCR_PIN_PX6_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX6_Msk /;" d +AFIO_EVCR_PIN_PX6_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX6_Pos /;" d +AFIO_EVCR_PIN_PX6 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX6 /;" d +AFIO_EVCR_PIN_PX7_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX7_Msk /;" d +AFIO_EVCR_PIN_PX7_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX7_Pos /;" d +AFIO_EVCR_PIN_PX7 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX7 /;" d +AFIO_EVCR_PIN_PX8_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX8_Msk /;" d +AFIO_EVCR_PIN_PX8_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX8_Pos /;" d +AFIO_EVCR_PIN_PX8 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX8 /;" d +AFIO_EVCR_PIN_PX9_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX9_Msk /;" d +AFIO_EVCR_PIN_PX9_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX9_Pos /;" d +AFIO_EVCR_PIN_PX9 target/stm32f103xb.h /^#define AFIO_EVCR_PIN_PX9 /;" d +AFIO_EVCR_PIN_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PIN_Pos /;" d +AFIO_EVCR_PIN target/stm32f103xb.h /^#define AFIO_EVCR_PIN /;" d +AFIO_EVCR_PORT_0 target/stm32f103xb.h /^#define AFIO_EVCR_PORT_0 /;" d +AFIO_EVCR_PORT_1 target/stm32f103xb.h /^#define AFIO_EVCR_PORT_1 /;" d +AFIO_EVCR_PORT_2 target/stm32f103xb.h /^#define AFIO_EVCR_PORT_2 /;" d +AFIO_EVCR_PORT_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PORT_Msk /;" d +AFIO_EVCR_PORT_PA target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PA /;" d +AFIO_EVCR_PORT_PB_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PB_Msk /;" d +AFIO_EVCR_PORT_PB_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PB_Pos /;" d +AFIO_EVCR_PORT_PB target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PB /;" d +AFIO_EVCR_PORT_PC_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PC_Msk /;" d +AFIO_EVCR_PORT_PC_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PC_Pos /;" d +AFIO_EVCR_PORT_PC target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PC /;" d +AFIO_EVCR_PORT_PD_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PD_Msk /;" d +AFIO_EVCR_PORT_PD_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PD_Pos /;" d +AFIO_EVCR_PORT_PD target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PD /;" d +AFIO_EVCR_PORT_PE_Msk target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PE_Msk /;" d +AFIO_EVCR_PORT_PE_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PE_Pos /;" d +AFIO_EVCR_PORT_PE target/stm32f103xb.h /^#define AFIO_EVCR_PORT_PE /;" d +AFIO_EVCR_PORT_Pos target/stm32f103xb.h /^#define AFIO_EVCR_PORT_Pos /;" d +AFIO_EVCR_PORT target/stm32f103xb.h /^#define AFIO_EVCR_PORT /;" d +AFIO_EXTICR1_EXTI0_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_Msk /;" d +AFIO_EXTICR1_EXTI0_PA target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PA /;" d +AFIO_EXTICR1_EXTI0_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PB_Msk /;" d +AFIO_EXTICR1_EXTI0_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PB_Pos /;" d +AFIO_EXTICR1_EXTI0_PB target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PB /;" d +AFIO_EXTICR1_EXTI0_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PC_Msk /;" d +AFIO_EXTICR1_EXTI0_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PC_Pos /;" d +AFIO_EXTICR1_EXTI0_PC target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PC /;" d +AFIO_EXTICR1_EXTI0_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PD_Msk /;" d +AFIO_EXTICR1_EXTI0_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PD_Pos /;" d +AFIO_EXTICR1_EXTI0_PD target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PD /;" d +AFIO_EXTICR1_EXTI0_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PE_Msk /;" d +AFIO_EXTICR1_EXTI0_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PE_Pos /;" d +AFIO_EXTICR1_EXTI0_PE target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PE /;" d +AFIO_EXTICR1_EXTI0_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PF_Msk /;" d +AFIO_EXTICR1_EXTI0_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PF_Pos /;" d +AFIO_EXTICR1_EXTI0_PF target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PF /;" d +AFIO_EXTICR1_EXTI0_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PG_Msk /;" d +AFIO_EXTICR1_EXTI0_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PG_Pos /;" d +AFIO_EXTICR1_EXTI0_PG target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_PG /;" d +AFIO_EXTICR1_EXTI0_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0_Pos /;" d +AFIO_EXTICR1_EXTI0 target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI0 /;" d +AFIO_EXTICR1_EXTI1_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_Msk /;" d +AFIO_EXTICR1_EXTI1_PA target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PA /;" d +AFIO_EXTICR1_EXTI1_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PB_Msk /;" d +AFIO_EXTICR1_EXTI1_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PB_Pos /;" d +AFIO_EXTICR1_EXTI1_PB target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PB /;" d +AFIO_EXTICR1_EXTI1_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PC_Msk /;" d +AFIO_EXTICR1_EXTI1_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PC_Pos /;" d +AFIO_EXTICR1_EXTI1_PC target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PC /;" d +AFIO_EXTICR1_EXTI1_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PD_Msk /;" d +AFIO_EXTICR1_EXTI1_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PD_Pos /;" d +AFIO_EXTICR1_EXTI1_PD target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PD /;" d +AFIO_EXTICR1_EXTI1_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PE_Msk /;" d +AFIO_EXTICR1_EXTI1_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PE_Pos /;" d +AFIO_EXTICR1_EXTI1_PE target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PE /;" d +AFIO_EXTICR1_EXTI1_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PF_Msk /;" d +AFIO_EXTICR1_EXTI1_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PF_Pos /;" d +AFIO_EXTICR1_EXTI1_PF target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PF /;" d +AFIO_EXTICR1_EXTI1_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PG_Msk /;" d +AFIO_EXTICR1_EXTI1_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PG_Pos /;" d +AFIO_EXTICR1_EXTI1_PG target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_PG /;" d +AFIO_EXTICR1_EXTI1_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1_Pos /;" d +AFIO_EXTICR1_EXTI1 target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI1 /;" d +AFIO_EXTICR1_EXTI2_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_Msk /;" d +AFIO_EXTICR1_EXTI2_PA target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PA /;" d +AFIO_EXTICR1_EXTI2_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PB_Msk /;" d +AFIO_EXTICR1_EXTI2_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PB_Pos /;" d +AFIO_EXTICR1_EXTI2_PB target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PB /;" d +AFIO_EXTICR1_EXTI2_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PC_Msk /;" d +AFIO_EXTICR1_EXTI2_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PC_Pos /;" d +AFIO_EXTICR1_EXTI2_PC target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PC /;" d +AFIO_EXTICR1_EXTI2_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PD_Msk /;" d +AFIO_EXTICR1_EXTI2_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PD_Pos /;" d +AFIO_EXTICR1_EXTI2_PD target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PD /;" d +AFIO_EXTICR1_EXTI2_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PE_Msk /;" d +AFIO_EXTICR1_EXTI2_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PE_Pos /;" d +AFIO_EXTICR1_EXTI2_PE target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PE /;" d +AFIO_EXTICR1_EXTI2_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PF_Msk /;" d +AFIO_EXTICR1_EXTI2_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PF_Pos /;" d +AFIO_EXTICR1_EXTI2_PF target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PF /;" d +AFIO_EXTICR1_EXTI2_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PG_Msk /;" d +AFIO_EXTICR1_EXTI2_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PG_Pos /;" d +AFIO_EXTICR1_EXTI2_PG target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_PG /;" d +AFIO_EXTICR1_EXTI2_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2_Pos /;" d +AFIO_EXTICR1_EXTI2 target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI2 /;" d +AFIO_EXTICR1_EXTI3_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_Msk /;" d +AFIO_EXTICR1_EXTI3_PA target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PA /;" d +AFIO_EXTICR1_EXTI3_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PB_Msk /;" d +AFIO_EXTICR1_EXTI3_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PB_Pos /;" d +AFIO_EXTICR1_EXTI3_PB target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PB /;" d +AFIO_EXTICR1_EXTI3_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PC_Msk /;" d +AFIO_EXTICR1_EXTI3_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PC_Pos /;" d +AFIO_EXTICR1_EXTI3_PC target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PC /;" d +AFIO_EXTICR1_EXTI3_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PD_Msk /;" d +AFIO_EXTICR1_EXTI3_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PD_Pos /;" d +AFIO_EXTICR1_EXTI3_PD target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PD /;" d +AFIO_EXTICR1_EXTI3_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PE_Msk /;" d +AFIO_EXTICR1_EXTI3_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PE_Pos /;" d +AFIO_EXTICR1_EXTI3_PE target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PE /;" d +AFIO_EXTICR1_EXTI3_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PF_Msk /;" d +AFIO_EXTICR1_EXTI3_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PF_Pos /;" d +AFIO_EXTICR1_EXTI3_PF target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PF /;" d +AFIO_EXTICR1_EXTI3_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PG_Msk /;" d +AFIO_EXTICR1_EXTI3_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PG_Pos /;" d +AFIO_EXTICR1_EXTI3_PG target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_PG /;" d +AFIO_EXTICR1_EXTI3_Pos target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3_Pos /;" d +AFIO_EXTICR1_EXTI3 target/stm32f103xb.h /^#define AFIO_EXTICR1_EXTI3 /;" d +AFIO_EXTICR2_EXTI4_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_Msk /;" d +AFIO_EXTICR2_EXTI4_PA target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PA /;" d +AFIO_EXTICR2_EXTI4_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PB_Msk /;" d +AFIO_EXTICR2_EXTI4_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PB_Pos /;" d +AFIO_EXTICR2_EXTI4_PB target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PB /;" d +AFIO_EXTICR2_EXTI4_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PC_Msk /;" d +AFIO_EXTICR2_EXTI4_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PC_Pos /;" d +AFIO_EXTICR2_EXTI4_PC target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PC /;" d +AFIO_EXTICR2_EXTI4_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PD_Msk /;" d +AFIO_EXTICR2_EXTI4_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PD_Pos /;" d +AFIO_EXTICR2_EXTI4_PD target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PD /;" d +AFIO_EXTICR2_EXTI4_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PE_Msk /;" d +AFIO_EXTICR2_EXTI4_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PE_Pos /;" d +AFIO_EXTICR2_EXTI4_PE target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PE /;" d +AFIO_EXTICR2_EXTI4_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PF_Msk /;" d +AFIO_EXTICR2_EXTI4_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PF_Pos /;" d +AFIO_EXTICR2_EXTI4_PF target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PF /;" d +AFIO_EXTICR2_EXTI4_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PG_Msk /;" d +AFIO_EXTICR2_EXTI4_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PG_Pos /;" d +AFIO_EXTICR2_EXTI4_PG target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_PG /;" d +AFIO_EXTICR2_EXTI4_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4_Pos /;" d +AFIO_EXTICR2_EXTI4 target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI4 /;" d +AFIO_EXTICR2_EXTI5_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_Msk /;" d +AFIO_EXTICR2_EXTI5_PA target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PA /;" d +AFIO_EXTICR2_EXTI5_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PB_Msk /;" d +AFIO_EXTICR2_EXTI5_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PB_Pos /;" d +AFIO_EXTICR2_EXTI5_PB target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PB /;" d +AFIO_EXTICR2_EXTI5_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PC_Msk /;" d +AFIO_EXTICR2_EXTI5_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PC_Pos /;" d +AFIO_EXTICR2_EXTI5_PC target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PC /;" d +AFIO_EXTICR2_EXTI5_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PD_Msk /;" d +AFIO_EXTICR2_EXTI5_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PD_Pos /;" d +AFIO_EXTICR2_EXTI5_PD target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PD /;" d +AFIO_EXTICR2_EXTI5_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PE_Msk /;" d +AFIO_EXTICR2_EXTI5_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PE_Pos /;" d +AFIO_EXTICR2_EXTI5_PE target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PE /;" d +AFIO_EXTICR2_EXTI5_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PF_Msk /;" d +AFIO_EXTICR2_EXTI5_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PF_Pos /;" d +AFIO_EXTICR2_EXTI5_PF target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PF /;" d +AFIO_EXTICR2_EXTI5_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PG_Msk /;" d +AFIO_EXTICR2_EXTI5_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PG_Pos /;" d +AFIO_EXTICR2_EXTI5_PG target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_PG /;" d +AFIO_EXTICR2_EXTI5_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5_Pos /;" d +AFIO_EXTICR2_EXTI5 target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI5 /;" d +AFIO_EXTICR2_EXTI6_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_Msk /;" d +AFIO_EXTICR2_EXTI6_PA target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PA /;" d +AFIO_EXTICR2_EXTI6_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PB_Msk /;" d +AFIO_EXTICR2_EXTI6_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PB_Pos /;" d +AFIO_EXTICR2_EXTI6_PB target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PB /;" d +AFIO_EXTICR2_EXTI6_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PC_Msk /;" d +AFIO_EXTICR2_EXTI6_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PC_Pos /;" d +AFIO_EXTICR2_EXTI6_PC target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PC /;" d +AFIO_EXTICR2_EXTI6_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PD_Msk /;" d +AFIO_EXTICR2_EXTI6_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PD_Pos /;" d +AFIO_EXTICR2_EXTI6_PD target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PD /;" d +AFIO_EXTICR2_EXTI6_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PE_Msk /;" d +AFIO_EXTICR2_EXTI6_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PE_Pos /;" d +AFIO_EXTICR2_EXTI6_PE target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PE /;" d +AFIO_EXTICR2_EXTI6_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PF_Msk /;" d +AFIO_EXTICR2_EXTI6_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PF_Pos /;" d +AFIO_EXTICR2_EXTI6_PF target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PF /;" d +AFIO_EXTICR2_EXTI6_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PG_Msk /;" d +AFIO_EXTICR2_EXTI6_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PG_Pos /;" d +AFIO_EXTICR2_EXTI6_PG target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_PG /;" d +AFIO_EXTICR2_EXTI6_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6_Pos /;" d +AFIO_EXTICR2_EXTI6 target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI6 /;" d +AFIO_EXTICR2_EXTI7_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_Msk /;" d +AFIO_EXTICR2_EXTI7_PA target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PA /;" d +AFIO_EXTICR2_EXTI7_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PB_Msk /;" d +AFIO_EXTICR2_EXTI7_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PB_Pos /;" d +AFIO_EXTICR2_EXTI7_PB target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PB /;" d +AFIO_EXTICR2_EXTI7_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PC_Msk /;" d +AFIO_EXTICR2_EXTI7_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PC_Pos /;" d +AFIO_EXTICR2_EXTI7_PC target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PC /;" d +AFIO_EXTICR2_EXTI7_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PD_Msk /;" d +AFIO_EXTICR2_EXTI7_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PD_Pos /;" d +AFIO_EXTICR2_EXTI7_PD target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PD /;" d +AFIO_EXTICR2_EXTI7_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PE_Msk /;" d +AFIO_EXTICR2_EXTI7_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PE_Pos /;" d +AFIO_EXTICR2_EXTI7_PE target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PE /;" d +AFIO_EXTICR2_EXTI7_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PF_Msk /;" d +AFIO_EXTICR2_EXTI7_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PF_Pos /;" d +AFIO_EXTICR2_EXTI7_PF target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PF /;" d +AFIO_EXTICR2_EXTI7_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PG_Msk /;" d +AFIO_EXTICR2_EXTI7_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PG_Pos /;" d +AFIO_EXTICR2_EXTI7_PG target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_PG /;" d +AFIO_EXTICR2_EXTI7_Pos target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7_Pos /;" d +AFIO_EXTICR2_EXTI7 target/stm32f103xb.h /^#define AFIO_EXTICR2_EXTI7 /;" d +AFIO_EXTICR3_EXTI10_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_Msk /;" d +AFIO_EXTICR3_EXTI10_PA target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PA /;" d +AFIO_EXTICR3_EXTI10_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PB_Msk /;" d +AFIO_EXTICR3_EXTI10_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PB_Pos /;" d +AFIO_EXTICR3_EXTI10_PB target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PB /;" d +AFIO_EXTICR3_EXTI10_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PC_Msk /;" d +AFIO_EXTICR3_EXTI10_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PC_Pos /;" d +AFIO_EXTICR3_EXTI10_PC target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PC /;" d +AFIO_EXTICR3_EXTI10_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PD_Msk /;" d +AFIO_EXTICR3_EXTI10_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PD_Pos /;" d +AFIO_EXTICR3_EXTI10_PD target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PD /;" d +AFIO_EXTICR3_EXTI10_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PE_Msk /;" d +AFIO_EXTICR3_EXTI10_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PE_Pos /;" d +AFIO_EXTICR3_EXTI10_PE target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PE /;" d +AFIO_EXTICR3_EXTI10_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PF_Msk /;" d +AFIO_EXTICR3_EXTI10_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PF_Pos /;" d +AFIO_EXTICR3_EXTI10_PF target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PF /;" d +AFIO_EXTICR3_EXTI10_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PG_Msk /;" d +AFIO_EXTICR3_EXTI10_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PG_Pos /;" d +AFIO_EXTICR3_EXTI10_PG target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_PG /;" d +AFIO_EXTICR3_EXTI10_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10_Pos /;" d +AFIO_EXTICR3_EXTI10 target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI10 /;" d +AFIO_EXTICR3_EXTI11_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_Msk /;" d +AFIO_EXTICR3_EXTI11_PA target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PA /;" d +AFIO_EXTICR3_EXTI11_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PB_Msk /;" d +AFIO_EXTICR3_EXTI11_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PB_Pos /;" d +AFIO_EXTICR3_EXTI11_PB target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PB /;" d +AFIO_EXTICR3_EXTI11_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PC_Msk /;" d +AFIO_EXTICR3_EXTI11_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PC_Pos /;" d +AFIO_EXTICR3_EXTI11_PC target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PC /;" d +AFIO_EXTICR3_EXTI11_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PD_Msk /;" d +AFIO_EXTICR3_EXTI11_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PD_Pos /;" d +AFIO_EXTICR3_EXTI11_PD target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PD /;" d +AFIO_EXTICR3_EXTI11_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PE_Msk /;" d +AFIO_EXTICR3_EXTI11_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PE_Pos /;" d +AFIO_EXTICR3_EXTI11_PE target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PE /;" d +AFIO_EXTICR3_EXTI11_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PF_Msk /;" d +AFIO_EXTICR3_EXTI11_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PF_Pos /;" d +AFIO_EXTICR3_EXTI11_PF target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PF /;" d +AFIO_EXTICR3_EXTI11_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PG_Msk /;" d +AFIO_EXTICR3_EXTI11_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PG_Pos /;" d +AFIO_EXTICR3_EXTI11_PG target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_PG /;" d +AFIO_EXTICR3_EXTI11_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11_Pos /;" d +AFIO_EXTICR3_EXTI11 target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI11 /;" d +AFIO_EXTICR3_EXTI8_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_Msk /;" d +AFIO_EXTICR3_EXTI8_PA target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PA /;" d +AFIO_EXTICR3_EXTI8_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PB_Msk /;" d +AFIO_EXTICR3_EXTI8_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PB_Pos /;" d +AFIO_EXTICR3_EXTI8_PB target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PB /;" d +AFIO_EXTICR3_EXTI8_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PC_Msk /;" d +AFIO_EXTICR3_EXTI8_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PC_Pos /;" d +AFIO_EXTICR3_EXTI8_PC target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PC /;" d +AFIO_EXTICR3_EXTI8_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PD_Msk /;" d +AFIO_EXTICR3_EXTI8_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PD_Pos /;" d +AFIO_EXTICR3_EXTI8_PD target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PD /;" d +AFIO_EXTICR3_EXTI8_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PE_Msk /;" d +AFIO_EXTICR3_EXTI8_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PE_Pos /;" d +AFIO_EXTICR3_EXTI8_PE target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PE /;" d +AFIO_EXTICR3_EXTI8_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PF_Msk /;" d +AFIO_EXTICR3_EXTI8_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PF_Pos /;" d +AFIO_EXTICR3_EXTI8_PF target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PF /;" d +AFIO_EXTICR3_EXTI8_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PG_Msk /;" d +AFIO_EXTICR3_EXTI8_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PG_Pos /;" d +AFIO_EXTICR3_EXTI8_PG target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_PG /;" d +AFIO_EXTICR3_EXTI8_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8_Pos /;" d +AFIO_EXTICR3_EXTI8 target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI8 /;" d +AFIO_EXTICR3_EXTI9_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_Msk /;" d +AFIO_EXTICR3_EXTI9_PA target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PA /;" d +AFIO_EXTICR3_EXTI9_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PB_Msk /;" d +AFIO_EXTICR3_EXTI9_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PB_Pos /;" d +AFIO_EXTICR3_EXTI9_PB target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PB /;" d +AFIO_EXTICR3_EXTI9_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PC_Msk /;" d +AFIO_EXTICR3_EXTI9_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PC_Pos /;" d +AFIO_EXTICR3_EXTI9_PC target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PC /;" d +AFIO_EXTICR3_EXTI9_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PD_Msk /;" d +AFIO_EXTICR3_EXTI9_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PD_Pos /;" d +AFIO_EXTICR3_EXTI9_PD target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PD /;" d +AFIO_EXTICR3_EXTI9_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PE_Msk /;" d +AFIO_EXTICR3_EXTI9_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PE_Pos /;" d +AFIO_EXTICR3_EXTI9_PE target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PE /;" d +AFIO_EXTICR3_EXTI9_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PF_Msk /;" d +AFIO_EXTICR3_EXTI9_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PF_Pos /;" d +AFIO_EXTICR3_EXTI9_PF target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PF /;" d +AFIO_EXTICR3_EXTI9_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PG_Msk /;" d +AFIO_EXTICR3_EXTI9_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PG_Pos /;" d +AFIO_EXTICR3_EXTI9_PG target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_PG /;" d +AFIO_EXTICR3_EXTI9_Pos target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9_Pos /;" d +AFIO_EXTICR3_EXTI9 target/stm32f103xb.h /^#define AFIO_EXTICR3_EXTI9 /;" d +AFIO_EXTICR4_EXTI12_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_Msk /;" d +AFIO_EXTICR4_EXTI12_PA target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PA /;" d +AFIO_EXTICR4_EXTI12_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PB_Msk /;" d +AFIO_EXTICR4_EXTI12_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PB_Pos /;" d +AFIO_EXTICR4_EXTI12_PB target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PB /;" d +AFIO_EXTICR4_EXTI12_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PC_Msk /;" d +AFIO_EXTICR4_EXTI12_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PC_Pos /;" d +AFIO_EXTICR4_EXTI12_PC target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PC /;" d +AFIO_EXTICR4_EXTI12_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PD_Msk /;" d +AFIO_EXTICR4_EXTI12_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PD_Pos /;" d +AFIO_EXTICR4_EXTI12_PD target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PD /;" d +AFIO_EXTICR4_EXTI12_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PE_Msk /;" d +AFIO_EXTICR4_EXTI12_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PE_Pos /;" d +AFIO_EXTICR4_EXTI12_PE target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PE /;" d +AFIO_EXTICR4_EXTI12_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PF_Msk /;" d +AFIO_EXTICR4_EXTI12_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PF_Pos /;" d +AFIO_EXTICR4_EXTI12_PF target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PF /;" d +AFIO_EXTICR4_EXTI12_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PG_Msk /;" d +AFIO_EXTICR4_EXTI12_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PG_Pos /;" d +AFIO_EXTICR4_EXTI12_PG target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_PG /;" d +AFIO_EXTICR4_EXTI12_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12_Pos /;" d +AFIO_EXTICR4_EXTI12 target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI12 /;" d +AFIO_EXTICR4_EXTI13_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_Msk /;" d +AFIO_EXTICR4_EXTI13_PA target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PA /;" d +AFIO_EXTICR4_EXTI13_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PB_Msk /;" d +AFIO_EXTICR4_EXTI13_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PB_Pos /;" d +AFIO_EXTICR4_EXTI13_PB target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PB /;" d +AFIO_EXTICR4_EXTI13_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PC_Msk /;" d +AFIO_EXTICR4_EXTI13_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PC_Pos /;" d +AFIO_EXTICR4_EXTI13_PC target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PC /;" d +AFIO_EXTICR4_EXTI13_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PD_Msk /;" d +AFIO_EXTICR4_EXTI13_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PD_Pos /;" d +AFIO_EXTICR4_EXTI13_PD target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PD /;" d +AFIO_EXTICR4_EXTI13_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PE_Msk /;" d +AFIO_EXTICR4_EXTI13_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PE_Pos /;" d +AFIO_EXTICR4_EXTI13_PE target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PE /;" d +AFIO_EXTICR4_EXTI13_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PF_Msk /;" d +AFIO_EXTICR4_EXTI13_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PF_Pos /;" d +AFIO_EXTICR4_EXTI13_PF target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PF /;" d +AFIO_EXTICR4_EXTI13_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PG_Msk /;" d +AFIO_EXTICR4_EXTI13_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PG_Pos /;" d +AFIO_EXTICR4_EXTI13_PG target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_PG /;" d +AFIO_EXTICR4_EXTI13_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13_Pos /;" d +AFIO_EXTICR4_EXTI13 target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI13 /;" d +AFIO_EXTICR4_EXTI14_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_Msk /;" d +AFIO_EXTICR4_EXTI14_PA target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PA /;" d +AFIO_EXTICR4_EXTI14_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PB_Msk /;" d +AFIO_EXTICR4_EXTI14_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PB_Pos /;" d +AFIO_EXTICR4_EXTI14_PB target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PB /;" d +AFIO_EXTICR4_EXTI14_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PC_Msk /;" d +AFIO_EXTICR4_EXTI14_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PC_Pos /;" d +AFIO_EXTICR4_EXTI14_PC target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PC /;" d +AFIO_EXTICR4_EXTI14_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PD_Msk /;" d +AFIO_EXTICR4_EXTI14_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PD_Pos /;" d +AFIO_EXTICR4_EXTI14_PD target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PD /;" d +AFIO_EXTICR4_EXTI14_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PE_Msk /;" d +AFIO_EXTICR4_EXTI14_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PE_Pos /;" d +AFIO_EXTICR4_EXTI14_PE target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PE /;" d +AFIO_EXTICR4_EXTI14_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PF_Msk /;" d +AFIO_EXTICR4_EXTI14_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PF_Pos /;" d +AFIO_EXTICR4_EXTI14_PF target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PF /;" d +AFIO_EXTICR4_EXTI14_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PG_Msk /;" d +AFIO_EXTICR4_EXTI14_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PG_Pos /;" d +AFIO_EXTICR4_EXTI14_PG target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_PG /;" d +AFIO_EXTICR4_EXTI14_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14_Pos /;" d +AFIO_EXTICR4_EXTI14 target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI14 /;" d +AFIO_EXTICR4_EXTI15_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_Msk /;" d +AFIO_EXTICR4_EXTI15_PA target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PA /;" d +AFIO_EXTICR4_EXTI15_PB_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PB_Msk /;" d +AFIO_EXTICR4_EXTI15_PB_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PB_Pos /;" d +AFIO_EXTICR4_EXTI15_PB target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PB /;" d +AFIO_EXTICR4_EXTI15_PC_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PC_Msk /;" d +AFIO_EXTICR4_EXTI15_PC_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PC_Pos /;" d +AFIO_EXTICR4_EXTI15_PC target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PC /;" d +AFIO_EXTICR4_EXTI15_PD_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PD_Msk /;" d +AFIO_EXTICR4_EXTI15_PD_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PD_Pos /;" d +AFIO_EXTICR4_EXTI15_PD target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PD /;" d +AFIO_EXTICR4_EXTI15_PE_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PE_Msk /;" d +AFIO_EXTICR4_EXTI15_PE_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PE_Pos /;" d +AFIO_EXTICR4_EXTI15_PE target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PE /;" d +AFIO_EXTICR4_EXTI15_PF_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PF_Msk /;" d +AFIO_EXTICR4_EXTI15_PF_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PF_Pos /;" d +AFIO_EXTICR4_EXTI15_PF target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PF /;" d +AFIO_EXTICR4_EXTI15_PG_Msk target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PG_Msk /;" d +AFIO_EXTICR4_EXTI15_PG_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PG_Pos /;" d +AFIO_EXTICR4_EXTI15_PG target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_PG /;" d +AFIO_EXTICR4_EXTI15_Pos target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15_Pos /;" d +AFIO_EXTICR4_EXTI15 target/stm32f103xb.h /^#define AFIO_EXTICR4_EXTI15 /;" d +AFIO_MAPR_CAN_REMAP_0 target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_0 /;" d +AFIO_MAPR_CAN_REMAP_1 target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_1 /;" d +AFIO_MAPR_CAN_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_Msk /;" d +AFIO_MAPR_CAN_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_Pos /;" d +AFIO_MAPR_CAN_REMAP_REMAP1 target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP1 /;" d +AFIO_MAPR_CAN_REMAP_REMAP2_Msk target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk /;" d +AFIO_MAPR_CAN_REMAP_REMAP2_Pos target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos /;" d +AFIO_MAPR_CAN_REMAP_REMAP2 target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP2 /;" d +AFIO_MAPR_CAN_REMAP_REMAP3_Msk target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk /;" d +AFIO_MAPR_CAN_REMAP_REMAP3_Pos target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos /;" d +AFIO_MAPR_CAN_REMAP_REMAP3 target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP_REMAP3 /;" d +AFIO_MAPR_CAN_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_CAN_REMAP /;" d +AFIO_MAPR_I2C1_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_I2C1_REMAP_Msk /;" d +AFIO_MAPR_I2C1_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_I2C1_REMAP_Pos /;" d +AFIO_MAPR_I2C1_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_I2C1_REMAP /;" d +AFIO_MAPR_PD01_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_PD01_REMAP_Msk /;" d +AFIO_MAPR_PD01_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_PD01_REMAP_Pos /;" d +AFIO_MAPR_PD01_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_PD01_REMAP /;" d +AFIO_MAPR_SPI1_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_SPI1_REMAP_Msk /;" d +AFIO_MAPR_SPI1_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_SPI1_REMAP_Pos /;" d +AFIO_MAPR_SPI1_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_SPI1_REMAP /;" d +AFIO_MAPR_SWJ_CFG_0 target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_0 /;" d +AFIO_MAPR_SWJ_CFG_1 target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_1 /;" d +AFIO_MAPR_SWJ_CFG_2 target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_2 /;" d +AFIO_MAPR_SWJ_CFG_DISABLE_Msk target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk /;" d +AFIO_MAPR_SWJ_CFG_DISABLE_Pos target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos /;" d +AFIO_MAPR_SWJ_CFG_DISABLE target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_DISABLE /;" d +AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /;" d +AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos /;" d +AFIO_MAPR_SWJ_CFG_JTAGDISABLE target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE /;" d +AFIO_MAPR_SWJ_CFG_Msk target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_Msk /;" d +AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /;" d +AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos /;" d +AFIO_MAPR_SWJ_CFG_NOJNTRST target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_NOJNTRST /;" d +AFIO_MAPR_SWJ_CFG_Pos target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_Pos /;" d +AFIO_MAPR_SWJ_CFG_RESET target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG_RESET /;" d +AFIO_MAPR_SWJ_CFG target/stm32f103xb.h /^#define AFIO_MAPR_SWJ_CFG /;" d +AFIO_MAPR_TIM1_REMAP_0 target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_0 /;" d +AFIO_MAPR_TIM1_REMAP_1 target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_1 /;" d +AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /;" d +AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos /;" d +AFIO_MAPR_TIM1_REMAP_FULLREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_FULLREMAP /;" d +AFIO_MAPR_TIM1_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_Msk /;" d +AFIO_MAPR_TIM1_REMAP_NOREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_NOREMAP /;" d +AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /;" d +AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos /;" d +AFIO_MAPR_TIM1_REMAP_PARTIALREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP /;" d +AFIO_MAPR_TIM1_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP_Pos /;" d +AFIO_MAPR_TIM1_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM1_REMAP /;" d +AFIO_MAPR_TIM2_REMAP_0 target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_0 /;" d +AFIO_MAPR_TIM2_REMAP_1 target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_1 /;" d +AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /;" d +AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos /;" d +AFIO_MAPR_TIM2_REMAP_FULLREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_FULLREMAP /;" d +AFIO_MAPR_TIM2_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_Msk /;" d +AFIO_MAPR_TIM2_REMAP_NOREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_NOREMAP /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos /;" d +AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 /;" d +AFIO_MAPR_TIM2_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP_Pos /;" d +AFIO_MAPR_TIM2_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM2_REMAP /;" d +AFIO_MAPR_TIM3_REMAP_0 target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_0 /;" d +AFIO_MAPR_TIM3_REMAP_1 target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_1 /;" d +AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /;" d +AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos /;" d +AFIO_MAPR_TIM3_REMAP_FULLREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_FULLREMAP /;" d +AFIO_MAPR_TIM3_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_Msk /;" d +AFIO_MAPR_TIM3_REMAP_NOREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_NOREMAP /;" d +AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /;" d +AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos /;" d +AFIO_MAPR_TIM3_REMAP_PARTIALREMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP /;" d +AFIO_MAPR_TIM3_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP_Pos /;" d +AFIO_MAPR_TIM3_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM3_REMAP /;" d +AFIO_MAPR_TIM4_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_TIM4_REMAP_Msk /;" d +AFIO_MAPR_TIM4_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_TIM4_REMAP_Pos /;" d +AFIO_MAPR_TIM4_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_TIM4_REMAP /;" d +AFIO_MAPR_USART1_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_USART1_REMAP_Msk /;" d +AFIO_MAPR_USART1_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_USART1_REMAP_Pos /;" d +AFIO_MAPR_USART1_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART1_REMAP /;" d +AFIO_MAPR_USART2_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_USART2_REMAP_Msk /;" d +AFIO_MAPR_USART2_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_USART2_REMAP_Pos /;" d +AFIO_MAPR_USART2_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART2_REMAP /;" d +AFIO_MAPR_USART3_REMAP_0 target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_0 /;" d +AFIO_MAPR_USART3_REMAP_1 target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_1 /;" d +AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /;" d +AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos /;" d +AFIO_MAPR_USART3_REMAP_FULLREMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_FULLREMAP /;" d +AFIO_MAPR_USART3_REMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_Msk /;" d +AFIO_MAPR_USART3_REMAP_NOREMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_NOREMAP /;" d +AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /;" d +AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos /;" d +AFIO_MAPR_USART3_REMAP_PARTIALREMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP /;" d +AFIO_MAPR_USART3_REMAP_Pos target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP_Pos /;" d +AFIO_MAPR_USART3_REMAP target/stm32f103xb.h /^#define AFIO_MAPR_USART3_REMAP /;" d +AFIO_TypeDef target/stm32f103xb.h /^} AFIO_TypeDef;$/;" t typeref:struct:__anon72c4c37e1108 +AFIO target/stm32f103xb.h /^#define AFIO /;" d +AHBENR target/stm32f103xb.h /^ __IO uint32_t AHBENR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +AHBPERIPH_BASE target/stm32f103xb.h /^#define AHBPERIPH_BASE /;" d +ALRH target/stm32f103xb.h /^ __IO uint32_t ALRH;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +ALRL target/stm32f103xb.h /^ __IO uint32_t ALRL;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +APB1ENR target/stm32f103xb.h /^ __IO uint32_t APB1ENR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +APB1PERIPH_BASE target/stm32f103xb.h /^#define APB1PERIPH_BASE /;" d +APB1RSTR target/stm32f103xb.h /^ __IO uint32_t APB1RSTR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +APB2ENR target/stm32f103xb.h /^ __IO uint32_t APB2ENR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +APB2PERIPH_BASE target/stm32f103xb.h /^#define APB2PERIPH_BASE /;" d +APB2RSTR target/stm32f103xb.h /^ __IO uint32_t APB2RSTR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +ARG target/stm32f103xb.h /^ __IO uint32_t ARG;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +ARR target/stm32f103xb.h /^ __IO uint32_t ARR; \/*!< TIM auto-reload register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +AR target/stm32f103xb.h /^ __IO uint32_t AR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +BDCR target/stm32f103xb.h /^ __IO uint32_t BDCR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +BDTR target/stm32f103xb.h /^ __IO uint32_t BDTR; \/*!< TIM break and dead-time register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +BKP_BASE target/stm32f103xb.h /^#define BKP_BASE /;" d +BKP_CR_TPAL_Msk target/stm32f103xb.h /^#define BKP_CR_TPAL_Msk /;" d +BKP_CR_TPAL_Pos target/stm32f103xb.h /^#define BKP_CR_TPAL_Pos /;" d +BKP_CR_TPAL target/stm32f103xb.h /^#define BKP_CR_TPAL /;" d +BKP_CR_TPE_Msk target/stm32f103xb.h /^#define BKP_CR_TPE_Msk /;" d +BKP_CR_TPE_Pos target/stm32f103xb.h /^#define BKP_CR_TPE_Pos /;" d +BKP_CR_TPE target/stm32f103xb.h /^#define BKP_CR_TPE /;" d +BKP_CSR_CTE_Msk target/stm32f103xb.h /^#define BKP_CSR_CTE_Msk /;" d +BKP_CSR_CTE_Pos target/stm32f103xb.h /^#define BKP_CSR_CTE_Pos /;" d +BKP_CSR_CTE target/stm32f103xb.h /^#define BKP_CSR_CTE /;" d +BKP_CSR_CTI_Msk target/stm32f103xb.h /^#define BKP_CSR_CTI_Msk /;" d +BKP_CSR_CTI_Pos target/stm32f103xb.h /^#define BKP_CSR_CTI_Pos /;" d +BKP_CSR_CTI target/stm32f103xb.h /^#define BKP_CSR_CTI /;" d +BKP_CSR_TEF_Msk target/stm32f103xb.h /^#define BKP_CSR_TEF_Msk /;" d +BKP_CSR_TEF_Pos target/stm32f103xb.h /^#define BKP_CSR_TEF_Pos /;" d +BKP_CSR_TEF target/stm32f103xb.h /^#define BKP_CSR_TEF /;" d +BKP_CSR_TIF_Msk target/stm32f103xb.h /^#define BKP_CSR_TIF_Msk /;" d +BKP_CSR_TIF_Pos target/stm32f103xb.h /^#define BKP_CSR_TIF_Pos /;" d +BKP_CSR_TIF target/stm32f103xb.h /^#define BKP_CSR_TIF /;" d +BKP_CSR_TPIE_Msk target/stm32f103xb.h /^#define BKP_CSR_TPIE_Msk /;" d +BKP_CSR_TPIE_Pos target/stm32f103xb.h /^#define BKP_CSR_TPIE_Pos /;" d +BKP_CSR_TPIE target/stm32f103xb.h /^#define BKP_CSR_TPIE /;" d +BKP_DR10_D_Msk target/stm32f103xb.h /^#define BKP_DR10_D_Msk /;" d +BKP_DR10_D_Pos target/stm32f103xb.h /^#define BKP_DR10_D_Pos /;" d +BKP_DR10_D target/stm32f103xb.h /^#define BKP_DR10_D /;" d +BKP_DR1_D_Msk target/stm32f103xb.h /^#define BKP_DR1_D_Msk /;" d +BKP_DR1_D_Pos target/stm32f103xb.h /^#define BKP_DR1_D_Pos /;" d +BKP_DR1_D target/stm32f103xb.h /^#define BKP_DR1_D /;" d +BKP_DR2_D_Msk target/stm32f103xb.h /^#define BKP_DR2_D_Msk /;" d +BKP_DR2_D_Pos target/stm32f103xb.h /^#define BKP_DR2_D_Pos /;" d +BKP_DR2_D target/stm32f103xb.h /^#define BKP_DR2_D /;" d +BKP_DR3_D_Msk target/stm32f103xb.h /^#define BKP_DR3_D_Msk /;" d +BKP_DR3_D_Pos target/stm32f103xb.h /^#define BKP_DR3_D_Pos /;" d +BKP_DR3_D target/stm32f103xb.h /^#define BKP_DR3_D /;" d +BKP_DR4_D_Msk target/stm32f103xb.h /^#define BKP_DR4_D_Msk /;" d +BKP_DR4_D_Pos target/stm32f103xb.h /^#define BKP_DR4_D_Pos /;" d +BKP_DR4_D target/stm32f103xb.h /^#define BKP_DR4_D /;" d +BKP_DR5_D_Msk target/stm32f103xb.h /^#define BKP_DR5_D_Msk /;" d +BKP_DR5_D_Pos target/stm32f103xb.h /^#define BKP_DR5_D_Pos /;" d +BKP_DR5_D target/stm32f103xb.h /^#define BKP_DR5_D /;" d +BKP_DR6_D_Msk target/stm32f103xb.h /^#define BKP_DR6_D_Msk /;" d +BKP_DR6_D_Pos target/stm32f103xb.h /^#define BKP_DR6_D_Pos /;" d +BKP_DR6_D target/stm32f103xb.h /^#define BKP_DR6_D /;" d +BKP_DR7_D_Msk target/stm32f103xb.h /^#define BKP_DR7_D_Msk /;" d +BKP_DR7_D_Pos target/stm32f103xb.h /^#define BKP_DR7_D_Pos /;" d +BKP_DR7_D target/stm32f103xb.h /^#define BKP_DR7_D /;" d +BKP_DR8_D_Msk target/stm32f103xb.h /^#define BKP_DR8_D_Msk /;" d +BKP_DR8_D_Pos target/stm32f103xb.h /^#define BKP_DR8_D_Pos /;" d +BKP_DR8_D target/stm32f103xb.h /^#define BKP_DR8_D /;" d +BKP_DR9_D_Msk target/stm32f103xb.h /^#define BKP_DR9_D_Msk /;" d +BKP_DR9_D_Pos target/stm32f103xb.h /^#define BKP_DR9_D_Pos /;" d +BKP_DR9_D target/stm32f103xb.h /^#define BKP_DR9_D /;" d +BKP_RTCCR_ASOE_Msk target/stm32f103xb.h /^#define BKP_RTCCR_ASOE_Msk /;" d +BKP_RTCCR_ASOE_Pos target/stm32f103xb.h /^#define BKP_RTCCR_ASOE_Pos /;" d +BKP_RTCCR_ASOE target/stm32f103xb.h /^#define BKP_RTCCR_ASOE /;" d +BKP_RTCCR_ASOS_Msk target/stm32f103xb.h /^#define BKP_RTCCR_ASOS_Msk /;" d +BKP_RTCCR_ASOS_Pos target/stm32f103xb.h /^#define BKP_RTCCR_ASOS_Pos /;" d +BKP_RTCCR_ASOS target/stm32f103xb.h /^#define BKP_RTCCR_ASOS /;" d +BKP_RTCCR_CAL_Msk target/stm32f103xb.h /^#define BKP_RTCCR_CAL_Msk /;" d +BKP_RTCCR_CAL_Pos target/stm32f103xb.h /^#define BKP_RTCCR_CAL_Pos /;" d +BKP_RTCCR_CAL target/stm32f103xb.h /^#define BKP_RTCCR_CAL /;" d +BKP_RTCCR_CCO_Msk target/stm32f103xb.h /^#define BKP_RTCCR_CCO_Msk /;" d +BKP_RTCCR_CCO_Pos target/stm32f103xb.h /^#define BKP_RTCCR_CCO_Pos /;" d +BKP_RTCCR_CCO target/stm32f103xb.h /^#define BKP_RTCCR_CCO /;" d +BKP_TypeDef target/stm32f103xb.h /^} BKP_TypeDef;$/;" t typeref:struct:__anon72c4c37e0408 +BKP target/stm32f103xb.h /^#define BKP /;" d +BRR target/stm32f103xb.h /^ __IO uint32_t BRR; \/*!< USART Baud rate register, Address offset: 0x08 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +BRR target/stm32f103xb.h /^ __IO uint32_t BRR;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +BSRR target/stm32f103xb.h /^ __IO uint32_t BSRR;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +BTABLE target/stm32f103xb.h /^ __IO uint16_t BTABLE; \/*!< Buffer Table address register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +BTR target/stm32f103xb.h /^ __IO uint32_t BTR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +BusFault_Handler Untitled Folder/sys_handlers.c /^void BusFault_Handler(void)$/;" f typeref:typename:void +BusFault_IRQn target/stm32f103xb.h /^ BusFault_IRQn = -11, \/*!< 5 Cortex-M3 Bus Fault Interrupt /;" e enum:__anon72c4c37e0103 +CAN1_BASE target/stm32f103xb.h /^#define CAN1_BASE /;" d +CAN1_RX0_IRQHandler target/stm32f103xb.h /^#define CAN1_RX0_IRQHandler /;" d +CAN1_RX0_IRQn target/stm32f103xb.h /^#define CAN1_RX0_IRQn /;" d +CAN1_RX1_IRQn target/stm32f103xb.h /^ CAN1_RX1_IRQn = 21, \/*!< CAN1 RX1 Interrupt /;" e enum:__anon72c4c37e0103 +CAN1_SCE_IRQn target/stm32f103xb.h /^ CAN1_SCE_IRQn = 22, \/*!< CAN1 SCE Interrupt /;" e enum:__anon72c4c37e0103 +CAN1_TX_IRQHandler target/stm32f103xb.h /^#define CAN1_TX_IRQHandler /;" d +CAN1_TX_IRQn target/stm32f103xb.h /^#define CAN1_TX_IRQn /;" d +CAN1 target/stm32f103xb.h /^#define CAN1 /;" d +CAN_BTR_BRP_Msk target/stm32f103xb.h /^#define CAN_BTR_BRP_Msk /;" d +CAN_BTR_BRP_Pos target/stm32f103xb.h /^#define CAN_BTR_BRP_Pos /;" d +CAN_BTR_BRP target/stm32f103xb.h /^#define CAN_BTR_BRP /;" d +CAN_BTR_LBKM_Msk target/stm32f103xb.h /^#define CAN_BTR_LBKM_Msk /;" d +CAN_BTR_LBKM_Pos target/stm32f103xb.h /^#define CAN_BTR_LBKM_Pos /;" d +CAN_BTR_LBKM target/stm32f103xb.h /^#define CAN_BTR_LBKM /;" d +CAN_BTR_SILM_Msk target/stm32f103xb.h /^#define CAN_BTR_SILM_Msk /;" d +CAN_BTR_SILM_Pos target/stm32f103xb.h /^#define CAN_BTR_SILM_Pos /;" d +CAN_BTR_SILM target/stm32f103xb.h /^#define CAN_BTR_SILM /;" d +CAN_BTR_SJW_0 target/stm32f103xb.h /^#define CAN_BTR_SJW_0 /;" d +CAN_BTR_SJW_1 target/stm32f103xb.h /^#define CAN_BTR_SJW_1 /;" d +CAN_BTR_SJW_Msk target/stm32f103xb.h /^#define CAN_BTR_SJW_Msk /;" d +CAN_BTR_SJW_Pos target/stm32f103xb.h /^#define CAN_BTR_SJW_Pos /;" d +CAN_BTR_SJW target/stm32f103xb.h /^#define CAN_BTR_SJW /;" d +CAN_BTR_TS1_0 target/stm32f103xb.h /^#define CAN_BTR_TS1_0 /;" d +CAN_BTR_TS1_1 target/stm32f103xb.h /^#define CAN_BTR_TS1_1 /;" d +CAN_BTR_TS1_2 target/stm32f103xb.h /^#define CAN_BTR_TS1_2 /;" d +CAN_BTR_TS1_3 target/stm32f103xb.h /^#define CAN_BTR_TS1_3 /;" d +CAN_BTR_TS1_Msk target/stm32f103xb.h /^#define CAN_BTR_TS1_Msk /;" d +CAN_BTR_TS1_Pos target/stm32f103xb.h /^#define CAN_BTR_TS1_Pos /;" d +CAN_BTR_TS1 target/stm32f103xb.h /^#define CAN_BTR_TS1 /;" d +CAN_BTR_TS2_0 target/stm32f103xb.h /^#define CAN_BTR_TS2_0 /;" d +CAN_BTR_TS2_1 target/stm32f103xb.h /^#define CAN_BTR_TS2_1 /;" d +CAN_BTR_TS2_2 target/stm32f103xb.h /^#define CAN_BTR_TS2_2 /;" d +CAN_BTR_TS2_Msk target/stm32f103xb.h /^#define CAN_BTR_TS2_Msk /;" d +CAN_BTR_TS2_Pos target/stm32f103xb.h /^#define CAN_BTR_TS2_Pos /;" d +CAN_BTR_TS2 target/stm32f103xb.h /^#define CAN_BTR_TS2 /;" d +CAN_ESR_BOFF_Msk target/stm32f103xb.h /^#define CAN_ESR_BOFF_Msk /;" d +CAN_ESR_BOFF_Pos target/stm32f103xb.h /^#define CAN_ESR_BOFF_Pos /;" d +CAN_ESR_BOFF target/stm32f103xb.h /^#define CAN_ESR_BOFF /;" d +CAN_ESR_EPVF_Msk target/stm32f103xb.h /^#define CAN_ESR_EPVF_Msk /;" d +CAN_ESR_EPVF_Pos target/stm32f103xb.h /^#define CAN_ESR_EPVF_Pos /;" d +CAN_ESR_EPVF target/stm32f103xb.h /^#define CAN_ESR_EPVF /;" d +CAN_ESR_EWGF_Msk target/stm32f103xb.h /^#define CAN_ESR_EWGF_Msk /;" d +CAN_ESR_EWGF_Pos target/stm32f103xb.h /^#define CAN_ESR_EWGF_Pos /;" d +CAN_ESR_EWGF target/stm32f103xb.h /^#define CAN_ESR_EWGF /;" d +CAN_ESR_LEC_0 target/stm32f103xb.h /^#define CAN_ESR_LEC_0 /;" d +CAN_ESR_LEC_1 target/stm32f103xb.h /^#define CAN_ESR_LEC_1 /;" d +CAN_ESR_LEC_2 target/stm32f103xb.h /^#define CAN_ESR_LEC_2 /;" d +CAN_ESR_LEC_Msk target/stm32f103xb.h /^#define CAN_ESR_LEC_Msk /;" d +CAN_ESR_LEC_Pos target/stm32f103xb.h /^#define CAN_ESR_LEC_Pos /;" d +CAN_ESR_LEC target/stm32f103xb.h /^#define CAN_ESR_LEC /;" d +CAN_ESR_REC_Msk target/stm32f103xb.h /^#define CAN_ESR_REC_Msk /;" d +CAN_ESR_REC_Pos target/stm32f103xb.h /^#define CAN_ESR_REC_Pos /;" d +CAN_ESR_REC target/stm32f103xb.h /^#define CAN_ESR_REC /;" d +CAN_ESR_TEC_Msk target/stm32f103xb.h /^#define CAN_ESR_TEC_Msk /;" d +CAN_ESR_TEC_Pos target/stm32f103xb.h /^#define CAN_ESR_TEC_Pos /;" d +CAN_ESR_TEC target/stm32f103xb.h /^#define CAN_ESR_TEC /;" d +CAN_F0R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB0_Msk /;" d +CAN_F0R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB0_Pos /;" d +CAN_F0R1_FB0 target/stm32f103xb.h /^#define CAN_F0R1_FB0 /;" d +CAN_F0R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB10_Msk /;" d +CAN_F0R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB10_Pos /;" d +CAN_F0R1_FB10 target/stm32f103xb.h /^#define CAN_F0R1_FB10 /;" d +CAN_F0R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB11_Msk /;" d +CAN_F0R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB11_Pos /;" d +CAN_F0R1_FB11 target/stm32f103xb.h /^#define CAN_F0R1_FB11 /;" d +CAN_F0R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB12_Msk /;" d +CAN_F0R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB12_Pos /;" d +CAN_F0R1_FB12 target/stm32f103xb.h /^#define CAN_F0R1_FB12 /;" d +CAN_F0R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB13_Msk /;" d +CAN_F0R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB13_Pos /;" d +CAN_F0R1_FB13 target/stm32f103xb.h /^#define CAN_F0R1_FB13 /;" d +CAN_F0R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB14_Msk /;" d +CAN_F0R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB14_Pos /;" d +CAN_F0R1_FB14 target/stm32f103xb.h /^#define CAN_F0R1_FB14 /;" d +CAN_F0R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB15_Msk /;" d +CAN_F0R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB15_Pos /;" d +CAN_F0R1_FB15 target/stm32f103xb.h /^#define CAN_F0R1_FB15 /;" d +CAN_F0R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB16_Msk /;" d +CAN_F0R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB16_Pos /;" d +CAN_F0R1_FB16 target/stm32f103xb.h /^#define CAN_F0R1_FB16 /;" d +CAN_F0R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB17_Msk /;" d +CAN_F0R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB17_Pos /;" d +CAN_F0R1_FB17 target/stm32f103xb.h /^#define CAN_F0R1_FB17 /;" d +CAN_F0R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB18_Msk /;" d +CAN_F0R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB18_Pos /;" d +CAN_F0R1_FB18 target/stm32f103xb.h /^#define CAN_F0R1_FB18 /;" d +CAN_F0R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB19_Msk /;" d +CAN_F0R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB19_Pos /;" d +CAN_F0R1_FB19 target/stm32f103xb.h /^#define CAN_F0R1_FB19 /;" d +CAN_F0R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB1_Msk /;" d +CAN_F0R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB1_Pos /;" d +CAN_F0R1_FB1 target/stm32f103xb.h /^#define CAN_F0R1_FB1 /;" d +CAN_F0R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB20_Msk /;" d +CAN_F0R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB20_Pos /;" d +CAN_F0R1_FB20 target/stm32f103xb.h /^#define CAN_F0R1_FB20 /;" d +CAN_F0R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB21_Msk /;" d +CAN_F0R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB21_Pos /;" d +CAN_F0R1_FB21 target/stm32f103xb.h /^#define CAN_F0R1_FB21 /;" d +CAN_F0R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB22_Msk /;" d +CAN_F0R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB22_Pos /;" d +CAN_F0R1_FB22 target/stm32f103xb.h /^#define CAN_F0R1_FB22 /;" d +CAN_F0R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB23_Msk /;" d +CAN_F0R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB23_Pos /;" d +CAN_F0R1_FB23 target/stm32f103xb.h /^#define CAN_F0R1_FB23 /;" d +CAN_F0R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB24_Msk /;" d +CAN_F0R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB24_Pos /;" d +CAN_F0R1_FB24 target/stm32f103xb.h /^#define CAN_F0R1_FB24 /;" d +CAN_F0R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB25_Msk /;" d +CAN_F0R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB25_Pos /;" d +CAN_F0R1_FB25 target/stm32f103xb.h /^#define CAN_F0R1_FB25 /;" d +CAN_F0R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB26_Msk /;" d +CAN_F0R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB26_Pos /;" d +CAN_F0R1_FB26 target/stm32f103xb.h /^#define CAN_F0R1_FB26 /;" d +CAN_F0R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB27_Msk /;" d +CAN_F0R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB27_Pos /;" d +CAN_F0R1_FB27 target/stm32f103xb.h /^#define CAN_F0R1_FB27 /;" d +CAN_F0R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB28_Msk /;" d +CAN_F0R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB28_Pos /;" d +CAN_F0R1_FB28 target/stm32f103xb.h /^#define CAN_F0R1_FB28 /;" d +CAN_F0R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB29_Msk /;" d +CAN_F0R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB29_Pos /;" d +CAN_F0R1_FB29 target/stm32f103xb.h /^#define CAN_F0R1_FB29 /;" d +CAN_F0R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB2_Msk /;" d +CAN_F0R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB2_Pos /;" d +CAN_F0R1_FB2 target/stm32f103xb.h /^#define CAN_F0R1_FB2 /;" d +CAN_F0R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB30_Msk /;" d +CAN_F0R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB30_Pos /;" d +CAN_F0R1_FB30 target/stm32f103xb.h /^#define CAN_F0R1_FB30 /;" d +CAN_F0R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB31_Msk /;" d +CAN_F0R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB31_Pos /;" d +CAN_F0R1_FB31 target/stm32f103xb.h /^#define CAN_F0R1_FB31 /;" d +CAN_F0R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB3_Msk /;" d +CAN_F0R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB3_Pos /;" d +CAN_F0R1_FB3 target/stm32f103xb.h /^#define CAN_F0R1_FB3 /;" d +CAN_F0R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB4_Msk /;" d +CAN_F0R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB4_Pos /;" d +CAN_F0R1_FB4 target/stm32f103xb.h /^#define CAN_F0R1_FB4 /;" d +CAN_F0R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB5_Msk /;" d +CAN_F0R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB5_Pos /;" d +CAN_F0R1_FB5 target/stm32f103xb.h /^#define CAN_F0R1_FB5 /;" d +CAN_F0R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB6_Msk /;" d +CAN_F0R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB6_Pos /;" d +CAN_F0R1_FB6 target/stm32f103xb.h /^#define CAN_F0R1_FB6 /;" d +CAN_F0R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB7_Msk /;" d +CAN_F0R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB7_Pos /;" d +CAN_F0R1_FB7 target/stm32f103xb.h /^#define CAN_F0R1_FB7 /;" d +CAN_F0R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB8_Msk /;" d +CAN_F0R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB8_Pos /;" d +CAN_F0R1_FB8 target/stm32f103xb.h /^#define CAN_F0R1_FB8 /;" d +CAN_F0R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F0R1_FB9_Msk /;" d +CAN_F0R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F0R1_FB9_Pos /;" d +CAN_F0R1_FB9 target/stm32f103xb.h /^#define CAN_F0R1_FB9 /;" d +CAN_F0R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB0_Msk /;" d +CAN_F0R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB0_Pos /;" d +CAN_F0R2_FB0 target/stm32f103xb.h /^#define CAN_F0R2_FB0 /;" d +CAN_F0R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB10_Msk /;" d +CAN_F0R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB10_Pos /;" d +CAN_F0R2_FB10 target/stm32f103xb.h /^#define CAN_F0R2_FB10 /;" d +CAN_F0R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB11_Msk /;" d +CAN_F0R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB11_Pos /;" d +CAN_F0R2_FB11 target/stm32f103xb.h /^#define CAN_F0R2_FB11 /;" d +CAN_F0R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB12_Msk /;" d +CAN_F0R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB12_Pos /;" d +CAN_F0R2_FB12 target/stm32f103xb.h /^#define CAN_F0R2_FB12 /;" d +CAN_F0R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB13_Msk /;" d +CAN_F0R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB13_Pos /;" d +CAN_F0R2_FB13 target/stm32f103xb.h /^#define CAN_F0R2_FB13 /;" d +CAN_F0R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB14_Msk /;" d +CAN_F0R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB14_Pos /;" d +CAN_F0R2_FB14 target/stm32f103xb.h /^#define CAN_F0R2_FB14 /;" d +CAN_F0R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB15_Msk /;" d +CAN_F0R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB15_Pos /;" d +CAN_F0R2_FB15 target/stm32f103xb.h /^#define CAN_F0R2_FB15 /;" d +CAN_F0R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB16_Msk /;" d +CAN_F0R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB16_Pos /;" d +CAN_F0R2_FB16 target/stm32f103xb.h /^#define CAN_F0R2_FB16 /;" d +CAN_F0R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB17_Msk /;" d +CAN_F0R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB17_Pos /;" d +CAN_F0R2_FB17 target/stm32f103xb.h /^#define CAN_F0R2_FB17 /;" d +CAN_F0R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB18_Msk /;" d +CAN_F0R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB18_Pos /;" d +CAN_F0R2_FB18 target/stm32f103xb.h /^#define CAN_F0R2_FB18 /;" d +CAN_F0R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB19_Msk /;" d +CAN_F0R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB19_Pos /;" d +CAN_F0R2_FB19 target/stm32f103xb.h /^#define CAN_F0R2_FB19 /;" d +CAN_F0R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB1_Msk /;" d +CAN_F0R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB1_Pos /;" d +CAN_F0R2_FB1 target/stm32f103xb.h /^#define CAN_F0R2_FB1 /;" d +CAN_F0R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB20_Msk /;" d +CAN_F0R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB20_Pos /;" d +CAN_F0R2_FB20 target/stm32f103xb.h /^#define CAN_F0R2_FB20 /;" d +CAN_F0R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB21_Msk /;" d +CAN_F0R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB21_Pos /;" d +CAN_F0R2_FB21 target/stm32f103xb.h /^#define CAN_F0R2_FB21 /;" d +CAN_F0R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB22_Msk /;" d +CAN_F0R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB22_Pos /;" d +CAN_F0R2_FB22 target/stm32f103xb.h /^#define CAN_F0R2_FB22 /;" d +CAN_F0R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB23_Msk /;" d +CAN_F0R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB23_Pos /;" d +CAN_F0R2_FB23 target/stm32f103xb.h /^#define CAN_F0R2_FB23 /;" d +CAN_F0R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB24_Msk /;" d +CAN_F0R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB24_Pos /;" d +CAN_F0R2_FB24 target/stm32f103xb.h /^#define CAN_F0R2_FB24 /;" d +CAN_F0R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB25_Msk /;" d +CAN_F0R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB25_Pos /;" d +CAN_F0R2_FB25 target/stm32f103xb.h /^#define CAN_F0R2_FB25 /;" d +CAN_F0R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB26_Msk /;" d +CAN_F0R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB26_Pos /;" d +CAN_F0R2_FB26 target/stm32f103xb.h /^#define CAN_F0R2_FB26 /;" d +CAN_F0R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB27_Msk /;" d +CAN_F0R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB27_Pos /;" d +CAN_F0R2_FB27 target/stm32f103xb.h /^#define CAN_F0R2_FB27 /;" d +CAN_F0R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB28_Msk /;" d +CAN_F0R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB28_Pos /;" d +CAN_F0R2_FB28 target/stm32f103xb.h /^#define CAN_F0R2_FB28 /;" d +CAN_F0R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB29_Msk /;" d +CAN_F0R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB29_Pos /;" d +CAN_F0R2_FB29 target/stm32f103xb.h /^#define CAN_F0R2_FB29 /;" d +CAN_F0R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB2_Msk /;" d +CAN_F0R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB2_Pos /;" d +CAN_F0R2_FB2 target/stm32f103xb.h /^#define CAN_F0R2_FB2 /;" d +CAN_F0R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB30_Msk /;" d +CAN_F0R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB30_Pos /;" d +CAN_F0R2_FB30 target/stm32f103xb.h /^#define CAN_F0R2_FB30 /;" d +CAN_F0R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB31_Msk /;" d +CAN_F0R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB31_Pos /;" d +CAN_F0R2_FB31 target/stm32f103xb.h /^#define CAN_F0R2_FB31 /;" d +CAN_F0R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB3_Msk /;" d +CAN_F0R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB3_Pos /;" d +CAN_F0R2_FB3 target/stm32f103xb.h /^#define CAN_F0R2_FB3 /;" d +CAN_F0R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB4_Msk /;" d +CAN_F0R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB4_Pos /;" d +CAN_F0R2_FB4 target/stm32f103xb.h /^#define CAN_F0R2_FB4 /;" d +CAN_F0R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB5_Msk /;" d +CAN_F0R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB5_Pos /;" d +CAN_F0R2_FB5 target/stm32f103xb.h /^#define CAN_F0R2_FB5 /;" d +CAN_F0R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB6_Msk /;" d +CAN_F0R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB6_Pos /;" d +CAN_F0R2_FB6 target/stm32f103xb.h /^#define CAN_F0R2_FB6 /;" d +CAN_F0R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB7_Msk /;" d +CAN_F0R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB7_Pos /;" d +CAN_F0R2_FB7 target/stm32f103xb.h /^#define CAN_F0R2_FB7 /;" d +CAN_F0R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB8_Msk /;" d +CAN_F0R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB8_Pos /;" d +CAN_F0R2_FB8 target/stm32f103xb.h /^#define CAN_F0R2_FB8 /;" d +CAN_F0R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F0R2_FB9_Msk /;" d +CAN_F0R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F0R2_FB9_Pos /;" d +CAN_F0R2_FB9 target/stm32f103xb.h /^#define CAN_F0R2_FB9 /;" d +CAN_F10R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB0_Msk /;" d +CAN_F10R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB0_Pos /;" d +CAN_F10R1_FB0 target/stm32f103xb.h /^#define CAN_F10R1_FB0 /;" d +CAN_F10R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB10_Msk /;" d +CAN_F10R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB10_Pos /;" d +CAN_F10R1_FB10 target/stm32f103xb.h /^#define CAN_F10R1_FB10 /;" d +CAN_F10R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB11_Msk /;" d +CAN_F10R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB11_Pos /;" d +CAN_F10R1_FB11 target/stm32f103xb.h /^#define CAN_F10R1_FB11 /;" d +CAN_F10R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB12_Msk /;" d +CAN_F10R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB12_Pos /;" d +CAN_F10R1_FB12 target/stm32f103xb.h /^#define CAN_F10R1_FB12 /;" d +CAN_F10R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB13_Msk /;" d +CAN_F10R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB13_Pos /;" d +CAN_F10R1_FB13 target/stm32f103xb.h /^#define CAN_F10R1_FB13 /;" d +CAN_F10R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB14_Msk /;" d +CAN_F10R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB14_Pos /;" d +CAN_F10R1_FB14 target/stm32f103xb.h /^#define CAN_F10R1_FB14 /;" d +CAN_F10R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB15_Msk /;" d +CAN_F10R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB15_Pos /;" d +CAN_F10R1_FB15 target/stm32f103xb.h /^#define CAN_F10R1_FB15 /;" d +CAN_F10R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB16_Msk /;" d +CAN_F10R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB16_Pos /;" d +CAN_F10R1_FB16 target/stm32f103xb.h /^#define CAN_F10R1_FB16 /;" d +CAN_F10R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB17_Msk /;" d +CAN_F10R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB17_Pos /;" d +CAN_F10R1_FB17 target/stm32f103xb.h /^#define CAN_F10R1_FB17 /;" d +CAN_F10R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB18_Msk /;" d +CAN_F10R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB18_Pos /;" d +CAN_F10R1_FB18 target/stm32f103xb.h /^#define CAN_F10R1_FB18 /;" d +CAN_F10R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB19_Msk /;" d +CAN_F10R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB19_Pos /;" d +CAN_F10R1_FB19 target/stm32f103xb.h /^#define CAN_F10R1_FB19 /;" d +CAN_F10R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB1_Msk /;" d +CAN_F10R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB1_Pos /;" d +CAN_F10R1_FB1 target/stm32f103xb.h /^#define CAN_F10R1_FB1 /;" d +CAN_F10R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB20_Msk /;" d +CAN_F10R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB20_Pos /;" d +CAN_F10R1_FB20 target/stm32f103xb.h /^#define CAN_F10R1_FB20 /;" d +CAN_F10R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB21_Msk /;" d +CAN_F10R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB21_Pos /;" d +CAN_F10R1_FB21 target/stm32f103xb.h /^#define CAN_F10R1_FB21 /;" d +CAN_F10R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB22_Msk /;" d +CAN_F10R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB22_Pos /;" d +CAN_F10R1_FB22 target/stm32f103xb.h /^#define CAN_F10R1_FB22 /;" d +CAN_F10R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB23_Msk /;" d +CAN_F10R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB23_Pos /;" d +CAN_F10R1_FB23 target/stm32f103xb.h /^#define CAN_F10R1_FB23 /;" d +CAN_F10R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB24_Msk /;" d +CAN_F10R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB24_Pos /;" d +CAN_F10R1_FB24 target/stm32f103xb.h /^#define CAN_F10R1_FB24 /;" d +CAN_F10R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB25_Msk /;" d +CAN_F10R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB25_Pos /;" d +CAN_F10R1_FB25 target/stm32f103xb.h /^#define CAN_F10R1_FB25 /;" d +CAN_F10R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB26_Msk /;" d +CAN_F10R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB26_Pos /;" d +CAN_F10R1_FB26 target/stm32f103xb.h /^#define CAN_F10R1_FB26 /;" d +CAN_F10R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB27_Msk /;" d +CAN_F10R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB27_Pos /;" d +CAN_F10R1_FB27 target/stm32f103xb.h /^#define CAN_F10R1_FB27 /;" d +CAN_F10R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB28_Msk /;" d +CAN_F10R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB28_Pos /;" d +CAN_F10R1_FB28 target/stm32f103xb.h /^#define CAN_F10R1_FB28 /;" d +CAN_F10R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB29_Msk /;" d +CAN_F10R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB29_Pos /;" d +CAN_F10R1_FB29 target/stm32f103xb.h /^#define CAN_F10R1_FB29 /;" d +CAN_F10R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB2_Msk /;" d +CAN_F10R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB2_Pos /;" d +CAN_F10R1_FB2 target/stm32f103xb.h /^#define CAN_F10R1_FB2 /;" d +CAN_F10R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB30_Msk /;" d +CAN_F10R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB30_Pos /;" d +CAN_F10R1_FB30 target/stm32f103xb.h /^#define CAN_F10R1_FB30 /;" d +CAN_F10R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB31_Msk /;" d +CAN_F10R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB31_Pos /;" d +CAN_F10R1_FB31 target/stm32f103xb.h /^#define CAN_F10R1_FB31 /;" d +CAN_F10R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB3_Msk /;" d +CAN_F10R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB3_Pos /;" d +CAN_F10R1_FB3 target/stm32f103xb.h /^#define CAN_F10R1_FB3 /;" d +CAN_F10R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB4_Msk /;" d +CAN_F10R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB4_Pos /;" d +CAN_F10R1_FB4 target/stm32f103xb.h /^#define CAN_F10R1_FB4 /;" d +CAN_F10R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB5_Msk /;" d +CAN_F10R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB5_Pos /;" d +CAN_F10R1_FB5 target/stm32f103xb.h /^#define CAN_F10R1_FB5 /;" d +CAN_F10R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB6_Msk /;" d +CAN_F10R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB6_Pos /;" d +CAN_F10R1_FB6 target/stm32f103xb.h /^#define CAN_F10R1_FB6 /;" d +CAN_F10R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB7_Msk /;" d +CAN_F10R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB7_Pos /;" d +CAN_F10R1_FB7 target/stm32f103xb.h /^#define CAN_F10R1_FB7 /;" d +CAN_F10R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB8_Msk /;" d +CAN_F10R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB8_Pos /;" d +CAN_F10R1_FB8 target/stm32f103xb.h /^#define CAN_F10R1_FB8 /;" d +CAN_F10R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F10R1_FB9_Msk /;" d +CAN_F10R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F10R1_FB9_Pos /;" d +CAN_F10R1_FB9 target/stm32f103xb.h /^#define CAN_F10R1_FB9 /;" d +CAN_F10R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB0_Msk /;" d +CAN_F10R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB0_Pos /;" d +CAN_F10R2_FB0 target/stm32f103xb.h /^#define CAN_F10R2_FB0 /;" d +CAN_F10R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB10_Msk /;" d +CAN_F10R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB10_Pos /;" d +CAN_F10R2_FB10 target/stm32f103xb.h /^#define CAN_F10R2_FB10 /;" d +CAN_F10R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB11_Msk /;" d +CAN_F10R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB11_Pos /;" d +CAN_F10R2_FB11 target/stm32f103xb.h /^#define CAN_F10R2_FB11 /;" d +CAN_F10R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB12_Msk /;" d +CAN_F10R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB12_Pos /;" d +CAN_F10R2_FB12 target/stm32f103xb.h /^#define CAN_F10R2_FB12 /;" d +CAN_F10R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB13_Msk /;" d +CAN_F10R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB13_Pos /;" d +CAN_F10R2_FB13 target/stm32f103xb.h /^#define CAN_F10R2_FB13 /;" d +CAN_F10R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB14_Msk /;" d +CAN_F10R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB14_Pos /;" d +CAN_F10R2_FB14 target/stm32f103xb.h /^#define CAN_F10R2_FB14 /;" d +CAN_F10R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB15_Msk /;" d +CAN_F10R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB15_Pos /;" d +CAN_F10R2_FB15 target/stm32f103xb.h /^#define CAN_F10R2_FB15 /;" d +CAN_F10R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB16_Msk /;" d +CAN_F10R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB16_Pos /;" d +CAN_F10R2_FB16 target/stm32f103xb.h /^#define CAN_F10R2_FB16 /;" d +CAN_F10R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB17_Msk /;" d +CAN_F10R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB17_Pos /;" d +CAN_F10R2_FB17 target/stm32f103xb.h /^#define CAN_F10R2_FB17 /;" d +CAN_F10R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB18_Msk /;" d +CAN_F10R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB18_Pos /;" d +CAN_F10R2_FB18 target/stm32f103xb.h /^#define CAN_F10R2_FB18 /;" d +CAN_F10R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB19_Msk /;" d +CAN_F10R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB19_Pos /;" d +CAN_F10R2_FB19 target/stm32f103xb.h /^#define CAN_F10R2_FB19 /;" d +CAN_F10R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB1_Msk /;" d +CAN_F10R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB1_Pos /;" d +CAN_F10R2_FB1 target/stm32f103xb.h /^#define CAN_F10R2_FB1 /;" d +CAN_F10R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB20_Msk /;" d +CAN_F10R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB20_Pos /;" d +CAN_F10R2_FB20 target/stm32f103xb.h /^#define CAN_F10R2_FB20 /;" d +CAN_F10R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB21_Msk /;" d +CAN_F10R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB21_Pos /;" d +CAN_F10R2_FB21 target/stm32f103xb.h /^#define CAN_F10R2_FB21 /;" d +CAN_F10R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB22_Msk /;" d +CAN_F10R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB22_Pos /;" d +CAN_F10R2_FB22 target/stm32f103xb.h /^#define CAN_F10R2_FB22 /;" d +CAN_F10R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB23_Msk /;" d +CAN_F10R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB23_Pos /;" d +CAN_F10R2_FB23 target/stm32f103xb.h /^#define CAN_F10R2_FB23 /;" d +CAN_F10R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB24_Msk /;" d +CAN_F10R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB24_Pos /;" d +CAN_F10R2_FB24 target/stm32f103xb.h /^#define CAN_F10R2_FB24 /;" d +CAN_F10R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB25_Msk /;" d +CAN_F10R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB25_Pos /;" d +CAN_F10R2_FB25 target/stm32f103xb.h /^#define CAN_F10R2_FB25 /;" d +CAN_F10R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB26_Msk /;" d +CAN_F10R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB26_Pos /;" d +CAN_F10R2_FB26 target/stm32f103xb.h /^#define CAN_F10R2_FB26 /;" d +CAN_F10R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB27_Msk /;" d +CAN_F10R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB27_Pos /;" d +CAN_F10R2_FB27 target/stm32f103xb.h /^#define CAN_F10R2_FB27 /;" d +CAN_F10R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB28_Msk /;" d +CAN_F10R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB28_Pos /;" d +CAN_F10R2_FB28 target/stm32f103xb.h /^#define CAN_F10R2_FB28 /;" d +CAN_F10R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB29_Msk /;" d +CAN_F10R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB29_Pos /;" d +CAN_F10R2_FB29 target/stm32f103xb.h /^#define CAN_F10R2_FB29 /;" d +CAN_F10R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB2_Msk /;" d +CAN_F10R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB2_Pos /;" d +CAN_F10R2_FB2 target/stm32f103xb.h /^#define CAN_F10R2_FB2 /;" d +CAN_F10R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB30_Msk /;" d +CAN_F10R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB30_Pos /;" d +CAN_F10R2_FB30 target/stm32f103xb.h /^#define CAN_F10R2_FB30 /;" d +CAN_F10R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB31_Msk /;" d +CAN_F10R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB31_Pos /;" d +CAN_F10R2_FB31 target/stm32f103xb.h /^#define CAN_F10R2_FB31 /;" d +CAN_F10R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB3_Msk /;" d +CAN_F10R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB3_Pos /;" d +CAN_F10R2_FB3 target/stm32f103xb.h /^#define CAN_F10R2_FB3 /;" d +CAN_F10R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB4_Msk /;" d +CAN_F10R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB4_Pos /;" d +CAN_F10R2_FB4 target/stm32f103xb.h /^#define CAN_F10R2_FB4 /;" d +CAN_F10R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB5_Msk /;" d +CAN_F10R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB5_Pos /;" d +CAN_F10R2_FB5 target/stm32f103xb.h /^#define CAN_F10R2_FB5 /;" d +CAN_F10R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB6_Msk /;" d +CAN_F10R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB6_Pos /;" d +CAN_F10R2_FB6 target/stm32f103xb.h /^#define CAN_F10R2_FB6 /;" d +CAN_F10R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB7_Msk /;" d +CAN_F10R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB7_Pos /;" d +CAN_F10R2_FB7 target/stm32f103xb.h /^#define CAN_F10R2_FB7 /;" d +CAN_F10R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB8_Msk /;" d +CAN_F10R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB8_Pos /;" d +CAN_F10R2_FB8 target/stm32f103xb.h /^#define CAN_F10R2_FB8 /;" d +CAN_F10R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F10R2_FB9_Msk /;" d +CAN_F10R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F10R2_FB9_Pos /;" d +CAN_F10R2_FB9 target/stm32f103xb.h /^#define CAN_F10R2_FB9 /;" d +CAN_F11R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB0_Msk /;" d +CAN_F11R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB0_Pos /;" d +CAN_F11R1_FB0 target/stm32f103xb.h /^#define CAN_F11R1_FB0 /;" d +CAN_F11R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB10_Msk /;" d +CAN_F11R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB10_Pos /;" d +CAN_F11R1_FB10 target/stm32f103xb.h /^#define CAN_F11R1_FB10 /;" d +CAN_F11R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB11_Msk /;" d +CAN_F11R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB11_Pos /;" d +CAN_F11R1_FB11 target/stm32f103xb.h /^#define CAN_F11R1_FB11 /;" d +CAN_F11R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB12_Msk /;" d +CAN_F11R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB12_Pos /;" d +CAN_F11R1_FB12 target/stm32f103xb.h /^#define CAN_F11R1_FB12 /;" d +CAN_F11R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB13_Msk /;" d +CAN_F11R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB13_Pos /;" d +CAN_F11R1_FB13 target/stm32f103xb.h /^#define CAN_F11R1_FB13 /;" d +CAN_F11R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB14_Msk /;" d +CAN_F11R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB14_Pos /;" d +CAN_F11R1_FB14 target/stm32f103xb.h /^#define CAN_F11R1_FB14 /;" d +CAN_F11R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB15_Msk /;" d +CAN_F11R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB15_Pos /;" d +CAN_F11R1_FB15 target/stm32f103xb.h /^#define CAN_F11R1_FB15 /;" d +CAN_F11R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB16_Msk /;" d +CAN_F11R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB16_Pos /;" d +CAN_F11R1_FB16 target/stm32f103xb.h /^#define CAN_F11R1_FB16 /;" d +CAN_F11R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB17_Msk /;" d +CAN_F11R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB17_Pos /;" d +CAN_F11R1_FB17 target/stm32f103xb.h /^#define CAN_F11R1_FB17 /;" d +CAN_F11R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB18_Msk /;" d +CAN_F11R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB18_Pos /;" d +CAN_F11R1_FB18 target/stm32f103xb.h /^#define CAN_F11R1_FB18 /;" d +CAN_F11R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB19_Msk /;" d +CAN_F11R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB19_Pos /;" d +CAN_F11R1_FB19 target/stm32f103xb.h /^#define CAN_F11R1_FB19 /;" d +CAN_F11R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB1_Msk /;" d +CAN_F11R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB1_Pos /;" d +CAN_F11R1_FB1 target/stm32f103xb.h /^#define CAN_F11R1_FB1 /;" d +CAN_F11R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB20_Msk /;" d +CAN_F11R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB20_Pos /;" d +CAN_F11R1_FB20 target/stm32f103xb.h /^#define CAN_F11R1_FB20 /;" d +CAN_F11R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB21_Msk /;" d +CAN_F11R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB21_Pos /;" d +CAN_F11R1_FB21 target/stm32f103xb.h /^#define CAN_F11R1_FB21 /;" d +CAN_F11R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB22_Msk /;" d +CAN_F11R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB22_Pos /;" d +CAN_F11R1_FB22 target/stm32f103xb.h /^#define CAN_F11R1_FB22 /;" d +CAN_F11R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB23_Msk /;" d +CAN_F11R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB23_Pos /;" d +CAN_F11R1_FB23 target/stm32f103xb.h /^#define CAN_F11R1_FB23 /;" d +CAN_F11R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB24_Msk /;" d +CAN_F11R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB24_Pos /;" d +CAN_F11R1_FB24 target/stm32f103xb.h /^#define CAN_F11R1_FB24 /;" d +CAN_F11R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB25_Msk /;" d +CAN_F11R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB25_Pos /;" d +CAN_F11R1_FB25 target/stm32f103xb.h /^#define CAN_F11R1_FB25 /;" d +CAN_F11R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB26_Msk /;" d +CAN_F11R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB26_Pos /;" d +CAN_F11R1_FB26 target/stm32f103xb.h /^#define CAN_F11R1_FB26 /;" d +CAN_F11R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB27_Msk /;" d +CAN_F11R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB27_Pos /;" d +CAN_F11R1_FB27 target/stm32f103xb.h /^#define CAN_F11R1_FB27 /;" d +CAN_F11R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB28_Msk /;" d +CAN_F11R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB28_Pos /;" d +CAN_F11R1_FB28 target/stm32f103xb.h /^#define CAN_F11R1_FB28 /;" d +CAN_F11R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB29_Msk /;" d +CAN_F11R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB29_Pos /;" d +CAN_F11R1_FB29 target/stm32f103xb.h /^#define CAN_F11R1_FB29 /;" d +CAN_F11R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB2_Msk /;" d +CAN_F11R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB2_Pos /;" d +CAN_F11R1_FB2 target/stm32f103xb.h /^#define CAN_F11R1_FB2 /;" d +CAN_F11R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB30_Msk /;" d +CAN_F11R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB30_Pos /;" d +CAN_F11R1_FB30 target/stm32f103xb.h /^#define CAN_F11R1_FB30 /;" d +CAN_F11R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB31_Msk /;" d +CAN_F11R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB31_Pos /;" d +CAN_F11R1_FB31 target/stm32f103xb.h /^#define CAN_F11R1_FB31 /;" d +CAN_F11R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB3_Msk /;" d +CAN_F11R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB3_Pos /;" d +CAN_F11R1_FB3 target/stm32f103xb.h /^#define CAN_F11R1_FB3 /;" d +CAN_F11R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB4_Msk /;" d +CAN_F11R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB4_Pos /;" d +CAN_F11R1_FB4 target/stm32f103xb.h /^#define CAN_F11R1_FB4 /;" d +CAN_F11R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB5_Msk /;" d +CAN_F11R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB5_Pos /;" d +CAN_F11R1_FB5 target/stm32f103xb.h /^#define CAN_F11R1_FB5 /;" d +CAN_F11R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB6_Msk /;" d +CAN_F11R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB6_Pos /;" d +CAN_F11R1_FB6 target/stm32f103xb.h /^#define CAN_F11R1_FB6 /;" d +CAN_F11R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB7_Msk /;" d +CAN_F11R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB7_Pos /;" d +CAN_F11R1_FB7 target/stm32f103xb.h /^#define CAN_F11R1_FB7 /;" d +CAN_F11R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB8_Msk /;" d +CAN_F11R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB8_Pos /;" d +CAN_F11R1_FB8 target/stm32f103xb.h /^#define CAN_F11R1_FB8 /;" d +CAN_F11R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F11R1_FB9_Msk /;" d +CAN_F11R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F11R1_FB9_Pos /;" d +CAN_F11R1_FB9 target/stm32f103xb.h /^#define CAN_F11R1_FB9 /;" d +CAN_F11R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB0_Msk /;" d +CAN_F11R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB0_Pos /;" d +CAN_F11R2_FB0 target/stm32f103xb.h /^#define CAN_F11R2_FB0 /;" d +CAN_F11R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB10_Msk /;" d +CAN_F11R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB10_Pos /;" d +CAN_F11R2_FB10 target/stm32f103xb.h /^#define CAN_F11R2_FB10 /;" d +CAN_F11R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB11_Msk /;" d +CAN_F11R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB11_Pos /;" d +CAN_F11R2_FB11 target/stm32f103xb.h /^#define CAN_F11R2_FB11 /;" d +CAN_F11R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB12_Msk /;" d +CAN_F11R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB12_Pos /;" d +CAN_F11R2_FB12 target/stm32f103xb.h /^#define CAN_F11R2_FB12 /;" d +CAN_F11R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB13_Msk /;" d +CAN_F11R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB13_Pos /;" d +CAN_F11R2_FB13 target/stm32f103xb.h /^#define CAN_F11R2_FB13 /;" d +CAN_F11R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB14_Msk /;" d +CAN_F11R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB14_Pos /;" d +CAN_F11R2_FB14 target/stm32f103xb.h /^#define CAN_F11R2_FB14 /;" d +CAN_F11R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB15_Msk /;" d +CAN_F11R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB15_Pos /;" d +CAN_F11R2_FB15 target/stm32f103xb.h /^#define CAN_F11R2_FB15 /;" d +CAN_F11R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB16_Msk /;" d +CAN_F11R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB16_Pos /;" d +CAN_F11R2_FB16 target/stm32f103xb.h /^#define CAN_F11R2_FB16 /;" d +CAN_F11R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB17_Msk /;" d +CAN_F11R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB17_Pos /;" d +CAN_F11R2_FB17 target/stm32f103xb.h /^#define CAN_F11R2_FB17 /;" d +CAN_F11R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB18_Msk /;" d +CAN_F11R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB18_Pos /;" d +CAN_F11R2_FB18 target/stm32f103xb.h /^#define CAN_F11R2_FB18 /;" d +CAN_F11R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB19_Msk /;" d +CAN_F11R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB19_Pos /;" d +CAN_F11R2_FB19 target/stm32f103xb.h /^#define CAN_F11R2_FB19 /;" d +CAN_F11R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB1_Msk /;" d +CAN_F11R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB1_Pos /;" d +CAN_F11R2_FB1 target/stm32f103xb.h /^#define CAN_F11R2_FB1 /;" d +CAN_F11R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB20_Msk /;" d +CAN_F11R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB20_Pos /;" d +CAN_F11R2_FB20 target/stm32f103xb.h /^#define CAN_F11R2_FB20 /;" d +CAN_F11R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB21_Msk /;" d +CAN_F11R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB21_Pos /;" d +CAN_F11R2_FB21 target/stm32f103xb.h /^#define CAN_F11R2_FB21 /;" d +CAN_F11R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB22_Msk /;" d +CAN_F11R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB22_Pos /;" d +CAN_F11R2_FB22 target/stm32f103xb.h /^#define CAN_F11R2_FB22 /;" d +CAN_F11R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB23_Msk /;" d +CAN_F11R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB23_Pos /;" d +CAN_F11R2_FB23 target/stm32f103xb.h /^#define CAN_F11R2_FB23 /;" d +CAN_F11R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB24_Msk /;" d +CAN_F11R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB24_Pos /;" d +CAN_F11R2_FB24 target/stm32f103xb.h /^#define CAN_F11R2_FB24 /;" d +CAN_F11R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB25_Msk /;" d +CAN_F11R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB25_Pos /;" d +CAN_F11R2_FB25 target/stm32f103xb.h /^#define CAN_F11R2_FB25 /;" d +CAN_F11R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB26_Msk /;" d +CAN_F11R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB26_Pos /;" d +CAN_F11R2_FB26 target/stm32f103xb.h /^#define CAN_F11R2_FB26 /;" d +CAN_F11R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB27_Msk /;" d +CAN_F11R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB27_Pos /;" d +CAN_F11R2_FB27 target/stm32f103xb.h /^#define CAN_F11R2_FB27 /;" d +CAN_F11R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB28_Msk /;" d +CAN_F11R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB28_Pos /;" d +CAN_F11R2_FB28 target/stm32f103xb.h /^#define CAN_F11R2_FB28 /;" d +CAN_F11R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB29_Msk /;" d +CAN_F11R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB29_Pos /;" d +CAN_F11R2_FB29 target/stm32f103xb.h /^#define CAN_F11R2_FB29 /;" d +CAN_F11R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB2_Msk /;" d +CAN_F11R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB2_Pos /;" d +CAN_F11R2_FB2 target/stm32f103xb.h /^#define CAN_F11R2_FB2 /;" d +CAN_F11R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB30_Msk /;" d +CAN_F11R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB30_Pos /;" d +CAN_F11R2_FB30 target/stm32f103xb.h /^#define CAN_F11R2_FB30 /;" d +CAN_F11R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB31_Msk /;" d +CAN_F11R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB31_Pos /;" d +CAN_F11R2_FB31 target/stm32f103xb.h /^#define CAN_F11R2_FB31 /;" d +CAN_F11R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB3_Msk /;" d +CAN_F11R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB3_Pos /;" d +CAN_F11R2_FB3 target/stm32f103xb.h /^#define CAN_F11R2_FB3 /;" d +CAN_F11R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB4_Msk /;" d +CAN_F11R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB4_Pos /;" d +CAN_F11R2_FB4 target/stm32f103xb.h /^#define CAN_F11R2_FB4 /;" d +CAN_F11R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB5_Msk /;" d +CAN_F11R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB5_Pos /;" d +CAN_F11R2_FB5 target/stm32f103xb.h /^#define CAN_F11R2_FB5 /;" d +CAN_F11R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB6_Msk /;" d +CAN_F11R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB6_Pos /;" d +CAN_F11R2_FB6 target/stm32f103xb.h /^#define CAN_F11R2_FB6 /;" d +CAN_F11R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB7_Msk /;" d +CAN_F11R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB7_Pos /;" d +CAN_F11R2_FB7 target/stm32f103xb.h /^#define CAN_F11R2_FB7 /;" d +CAN_F11R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB8_Msk /;" d +CAN_F11R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB8_Pos /;" d +CAN_F11R2_FB8 target/stm32f103xb.h /^#define CAN_F11R2_FB8 /;" d +CAN_F11R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F11R2_FB9_Msk /;" d +CAN_F11R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F11R2_FB9_Pos /;" d +CAN_F11R2_FB9 target/stm32f103xb.h /^#define CAN_F11R2_FB9 /;" d +CAN_F12R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB0_Msk /;" d +CAN_F12R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB0_Pos /;" d +CAN_F12R1_FB0 target/stm32f103xb.h /^#define CAN_F12R1_FB0 /;" d +CAN_F12R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB10_Msk /;" d +CAN_F12R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB10_Pos /;" d +CAN_F12R1_FB10 target/stm32f103xb.h /^#define CAN_F12R1_FB10 /;" d +CAN_F12R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB11_Msk /;" d +CAN_F12R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB11_Pos /;" d +CAN_F12R1_FB11 target/stm32f103xb.h /^#define CAN_F12R1_FB11 /;" d +CAN_F12R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB12_Msk /;" d +CAN_F12R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB12_Pos /;" d +CAN_F12R1_FB12 target/stm32f103xb.h /^#define CAN_F12R1_FB12 /;" d +CAN_F12R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB13_Msk /;" d +CAN_F12R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB13_Pos /;" d +CAN_F12R1_FB13 target/stm32f103xb.h /^#define CAN_F12R1_FB13 /;" d +CAN_F12R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB14_Msk /;" d +CAN_F12R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB14_Pos /;" d +CAN_F12R1_FB14 target/stm32f103xb.h /^#define CAN_F12R1_FB14 /;" d +CAN_F12R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB15_Msk /;" d +CAN_F12R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB15_Pos /;" d +CAN_F12R1_FB15 target/stm32f103xb.h /^#define CAN_F12R1_FB15 /;" d +CAN_F12R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB16_Msk /;" d +CAN_F12R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB16_Pos /;" d +CAN_F12R1_FB16 target/stm32f103xb.h /^#define CAN_F12R1_FB16 /;" d +CAN_F12R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB17_Msk /;" d +CAN_F12R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB17_Pos /;" d +CAN_F12R1_FB17 target/stm32f103xb.h /^#define CAN_F12R1_FB17 /;" d +CAN_F12R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB18_Msk /;" d +CAN_F12R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB18_Pos /;" d +CAN_F12R1_FB18 target/stm32f103xb.h /^#define CAN_F12R1_FB18 /;" d +CAN_F12R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB19_Msk /;" d +CAN_F12R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB19_Pos /;" d +CAN_F12R1_FB19 target/stm32f103xb.h /^#define CAN_F12R1_FB19 /;" d +CAN_F12R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB1_Msk /;" d +CAN_F12R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB1_Pos /;" d +CAN_F12R1_FB1 target/stm32f103xb.h /^#define CAN_F12R1_FB1 /;" d +CAN_F12R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB20_Msk /;" d +CAN_F12R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB20_Pos /;" d +CAN_F12R1_FB20 target/stm32f103xb.h /^#define CAN_F12R1_FB20 /;" d +CAN_F12R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB21_Msk /;" d +CAN_F12R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB21_Pos /;" d +CAN_F12R1_FB21 target/stm32f103xb.h /^#define CAN_F12R1_FB21 /;" d +CAN_F12R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB22_Msk /;" d +CAN_F12R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB22_Pos /;" d +CAN_F12R1_FB22 target/stm32f103xb.h /^#define CAN_F12R1_FB22 /;" d +CAN_F12R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB23_Msk /;" d +CAN_F12R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB23_Pos /;" d +CAN_F12R1_FB23 target/stm32f103xb.h /^#define CAN_F12R1_FB23 /;" d +CAN_F12R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB24_Msk /;" d +CAN_F12R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB24_Pos /;" d +CAN_F12R1_FB24 target/stm32f103xb.h /^#define CAN_F12R1_FB24 /;" d +CAN_F12R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB25_Msk /;" d +CAN_F12R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB25_Pos /;" d +CAN_F12R1_FB25 target/stm32f103xb.h /^#define CAN_F12R1_FB25 /;" d +CAN_F12R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB26_Msk /;" d +CAN_F12R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB26_Pos /;" d +CAN_F12R1_FB26 target/stm32f103xb.h /^#define CAN_F12R1_FB26 /;" d +CAN_F12R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB27_Msk /;" d +CAN_F12R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB27_Pos /;" d +CAN_F12R1_FB27 target/stm32f103xb.h /^#define CAN_F12R1_FB27 /;" d +CAN_F12R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB28_Msk /;" d +CAN_F12R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB28_Pos /;" d +CAN_F12R1_FB28 target/stm32f103xb.h /^#define CAN_F12R1_FB28 /;" d +CAN_F12R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB29_Msk /;" d +CAN_F12R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB29_Pos /;" d +CAN_F12R1_FB29 target/stm32f103xb.h /^#define CAN_F12R1_FB29 /;" d +CAN_F12R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB2_Msk /;" d +CAN_F12R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB2_Pos /;" d +CAN_F12R1_FB2 target/stm32f103xb.h /^#define CAN_F12R1_FB2 /;" d +CAN_F12R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB30_Msk /;" d +CAN_F12R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB30_Pos /;" d +CAN_F12R1_FB30 target/stm32f103xb.h /^#define CAN_F12R1_FB30 /;" d +CAN_F12R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB31_Msk /;" d +CAN_F12R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB31_Pos /;" d +CAN_F12R1_FB31 target/stm32f103xb.h /^#define CAN_F12R1_FB31 /;" d +CAN_F12R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB3_Msk /;" d +CAN_F12R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB3_Pos /;" d +CAN_F12R1_FB3 target/stm32f103xb.h /^#define CAN_F12R1_FB3 /;" d +CAN_F12R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB4_Msk /;" d +CAN_F12R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB4_Pos /;" d +CAN_F12R1_FB4 target/stm32f103xb.h /^#define CAN_F12R1_FB4 /;" d +CAN_F12R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB5_Msk /;" d +CAN_F12R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB5_Pos /;" d +CAN_F12R1_FB5 target/stm32f103xb.h /^#define CAN_F12R1_FB5 /;" d +CAN_F12R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB6_Msk /;" d +CAN_F12R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB6_Pos /;" d +CAN_F12R1_FB6 target/stm32f103xb.h /^#define CAN_F12R1_FB6 /;" d +CAN_F12R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB7_Msk /;" d +CAN_F12R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB7_Pos /;" d +CAN_F12R1_FB7 target/stm32f103xb.h /^#define CAN_F12R1_FB7 /;" d +CAN_F12R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB8_Msk /;" d +CAN_F12R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB8_Pos /;" d +CAN_F12R1_FB8 target/stm32f103xb.h /^#define CAN_F12R1_FB8 /;" d +CAN_F12R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F12R1_FB9_Msk /;" d +CAN_F12R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F12R1_FB9_Pos /;" d +CAN_F12R1_FB9 target/stm32f103xb.h /^#define CAN_F12R1_FB9 /;" d +CAN_F12R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB0_Msk /;" d +CAN_F12R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB0_Pos /;" d +CAN_F12R2_FB0 target/stm32f103xb.h /^#define CAN_F12R2_FB0 /;" d +CAN_F12R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB10_Msk /;" d +CAN_F12R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB10_Pos /;" d +CAN_F12R2_FB10 target/stm32f103xb.h /^#define CAN_F12R2_FB10 /;" d +CAN_F12R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB11_Msk /;" d +CAN_F12R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB11_Pos /;" d +CAN_F12R2_FB11 target/stm32f103xb.h /^#define CAN_F12R2_FB11 /;" d +CAN_F12R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB12_Msk /;" d +CAN_F12R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB12_Pos /;" d +CAN_F12R2_FB12 target/stm32f103xb.h /^#define CAN_F12R2_FB12 /;" d +CAN_F12R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB13_Msk /;" d +CAN_F12R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB13_Pos /;" d +CAN_F12R2_FB13 target/stm32f103xb.h /^#define CAN_F12R2_FB13 /;" d +CAN_F12R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB14_Msk /;" d +CAN_F12R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB14_Pos /;" d +CAN_F12R2_FB14 target/stm32f103xb.h /^#define CAN_F12R2_FB14 /;" d +CAN_F12R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB15_Msk /;" d +CAN_F12R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB15_Pos /;" d +CAN_F12R2_FB15 target/stm32f103xb.h /^#define CAN_F12R2_FB15 /;" d +CAN_F12R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB16_Msk /;" d +CAN_F12R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB16_Pos /;" d +CAN_F12R2_FB16 target/stm32f103xb.h /^#define CAN_F12R2_FB16 /;" d +CAN_F12R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB17_Msk /;" d +CAN_F12R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB17_Pos /;" d +CAN_F12R2_FB17 target/stm32f103xb.h /^#define CAN_F12R2_FB17 /;" d +CAN_F12R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB18_Msk /;" d +CAN_F12R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB18_Pos /;" d +CAN_F12R2_FB18 target/stm32f103xb.h /^#define CAN_F12R2_FB18 /;" d +CAN_F12R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB19_Msk /;" d +CAN_F12R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB19_Pos /;" d +CAN_F12R2_FB19 target/stm32f103xb.h /^#define CAN_F12R2_FB19 /;" d +CAN_F12R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB1_Msk /;" d +CAN_F12R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB1_Pos /;" d +CAN_F12R2_FB1 target/stm32f103xb.h /^#define CAN_F12R2_FB1 /;" d +CAN_F12R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB20_Msk /;" d +CAN_F12R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB20_Pos /;" d +CAN_F12R2_FB20 target/stm32f103xb.h /^#define CAN_F12R2_FB20 /;" d +CAN_F12R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB21_Msk /;" d +CAN_F12R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB21_Pos /;" d +CAN_F12R2_FB21 target/stm32f103xb.h /^#define CAN_F12R2_FB21 /;" d +CAN_F12R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB22_Msk /;" d +CAN_F12R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB22_Pos /;" d +CAN_F12R2_FB22 target/stm32f103xb.h /^#define CAN_F12R2_FB22 /;" d +CAN_F12R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB23_Msk /;" d +CAN_F12R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB23_Pos /;" d +CAN_F12R2_FB23 target/stm32f103xb.h /^#define CAN_F12R2_FB23 /;" d +CAN_F12R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB24_Msk /;" d +CAN_F12R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB24_Pos /;" d +CAN_F12R2_FB24 target/stm32f103xb.h /^#define CAN_F12R2_FB24 /;" d +CAN_F12R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB25_Msk /;" d +CAN_F12R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB25_Pos /;" d +CAN_F12R2_FB25 target/stm32f103xb.h /^#define CAN_F12R2_FB25 /;" d +CAN_F12R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB26_Msk /;" d +CAN_F12R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB26_Pos /;" d +CAN_F12R2_FB26 target/stm32f103xb.h /^#define CAN_F12R2_FB26 /;" d +CAN_F12R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB27_Msk /;" d +CAN_F12R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB27_Pos /;" d +CAN_F12R2_FB27 target/stm32f103xb.h /^#define CAN_F12R2_FB27 /;" d +CAN_F12R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB28_Msk /;" d +CAN_F12R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB28_Pos /;" d +CAN_F12R2_FB28 target/stm32f103xb.h /^#define CAN_F12R2_FB28 /;" d +CAN_F12R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB29_Msk /;" d +CAN_F12R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB29_Pos /;" d +CAN_F12R2_FB29 target/stm32f103xb.h /^#define CAN_F12R2_FB29 /;" d +CAN_F12R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB2_Msk /;" d +CAN_F12R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB2_Pos /;" d +CAN_F12R2_FB2 target/stm32f103xb.h /^#define CAN_F12R2_FB2 /;" d +CAN_F12R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB30_Msk /;" d +CAN_F12R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB30_Pos /;" d +CAN_F12R2_FB30 target/stm32f103xb.h /^#define CAN_F12R2_FB30 /;" d +CAN_F12R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB31_Msk /;" d +CAN_F12R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB31_Pos /;" d +CAN_F12R2_FB31 target/stm32f103xb.h /^#define CAN_F12R2_FB31 /;" d +CAN_F12R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB3_Msk /;" d +CAN_F12R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB3_Pos /;" d +CAN_F12R2_FB3 target/stm32f103xb.h /^#define CAN_F12R2_FB3 /;" d +CAN_F12R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB4_Msk /;" d +CAN_F12R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB4_Pos /;" d +CAN_F12R2_FB4 target/stm32f103xb.h /^#define CAN_F12R2_FB4 /;" d +CAN_F12R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB5_Msk /;" d +CAN_F12R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB5_Pos /;" d +CAN_F12R2_FB5 target/stm32f103xb.h /^#define CAN_F12R2_FB5 /;" d +CAN_F12R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB6_Msk /;" d +CAN_F12R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB6_Pos /;" d +CAN_F12R2_FB6 target/stm32f103xb.h /^#define CAN_F12R2_FB6 /;" d +CAN_F12R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB7_Msk /;" d +CAN_F12R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB7_Pos /;" d +CAN_F12R2_FB7 target/stm32f103xb.h /^#define CAN_F12R2_FB7 /;" d +CAN_F12R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB8_Msk /;" d +CAN_F12R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB8_Pos /;" d +CAN_F12R2_FB8 target/stm32f103xb.h /^#define CAN_F12R2_FB8 /;" d +CAN_F12R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F12R2_FB9_Msk /;" d +CAN_F12R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F12R2_FB9_Pos /;" d +CAN_F12R2_FB9 target/stm32f103xb.h /^#define CAN_F12R2_FB9 /;" d +CAN_F13R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB0_Msk /;" d +CAN_F13R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB0_Pos /;" d +CAN_F13R1_FB0 target/stm32f103xb.h /^#define CAN_F13R1_FB0 /;" d +CAN_F13R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB10_Msk /;" d +CAN_F13R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB10_Pos /;" d +CAN_F13R1_FB10 target/stm32f103xb.h /^#define CAN_F13R1_FB10 /;" d +CAN_F13R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB11_Msk /;" d +CAN_F13R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB11_Pos /;" d +CAN_F13R1_FB11 target/stm32f103xb.h /^#define CAN_F13R1_FB11 /;" d +CAN_F13R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB12_Msk /;" d +CAN_F13R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB12_Pos /;" d +CAN_F13R1_FB12 target/stm32f103xb.h /^#define CAN_F13R1_FB12 /;" d +CAN_F13R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB13_Msk /;" d +CAN_F13R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB13_Pos /;" d +CAN_F13R1_FB13 target/stm32f103xb.h /^#define CAN_F13R1_FB13 /;" d +CAN_F13R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB14_Msk /;" d +CAN_F13R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB14_Pos /;" d +CAN_F13R1_FB14 target/stm32f103xb.h /^#define CAN_F13R1_FB14 /;" d +CAN_F13R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB15_Msk /;" d +CAN_F13R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB15_Pos /;" d +CAN_F13R1_FB15 target/stm32f103xb.h /^#define CAN_F13R1_FB15 /;" d +CAN_F13R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB16_Msk /;" d +CAN_F13R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB16_Pos /;" d +CAN_F13R1_FB16 target/stm32f103xb.h /^#define CAN_F13R1_FB16 /;" d +CAN_F13R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB17_Msk /;" d +CAN_F13R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB17_Pos /;" d +CAN_F13R1_FB17 target/stm32f103xb.h /^#define CAN_F13R1_FB17 /;" d +CAN_F13R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB18_Msk /;" d +CAN_F13R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB18_Pos /;" d +CAN_F13R1_FB18 target/stm32f103xb.h /^#define CAN_F13R1_FB18 /;" d +CAN_F13R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB19_Msk /;" d +CAN_F13R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB19_Pos /;" d +CAN_F13R1_FB19 target/stm32f103xb.h /^#define CAN_F13R1_FB19 /;" d +CAN_F13R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB1_Msk /;" d +CAN_F13R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB1_Pos /;" d +CAN_F13R1_FB1 target/stm32f103xb.h /^#define CAN_F13R1_FB1 /;" d +CAN_F13R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB20_Msk /;" d +CAN_F13R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB20_Pos /;" d +CAN_F13R1_FB20 target/stm32f103xb.h /^#define CAN_F13R1_FB20 /;" d +CAN_F13R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB21_Msk /;" d +CAN_F13R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB21_Pos /;" d +CAN_F13R1_FB21 target/stm32f103xb.h /^#define CAN_F13R1_FB21 /;" d +CAN_F13R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB22_Msk /;" d +CAN_F13R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB22_Pos /;" d +CAN_F13R1_FB22 target/stm32f103xb.h /^#define CAN_F13R1_FB22 /;" d +CAN_F13R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB23_Msk /;" d +CAN_F13R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB23_Pos /;" d +CAN_F13R1_FB23 target/stm32f103xb.h /^#define CAN_F13R1_FB23 /;" d +CAN_F13R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB24_Msk /;" d +CAN_F13R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB24_Pos /;" d +CAN_F13R1_FB24 target/stm32f103xb.h /^#define CAN_F13R1_FB24 /;" d +CAN_F13R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB25_Msk /;" d +CAN_F13R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB25_Pos /;" d +CAN_F13R1_FB25 target/stm32f103xb.h /^#define CAN_F13R1_FB25 /;" d +CAN_F13R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB26_Msk /;" d +CAN_F13R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB26_Pos /;" d +CAN_F13R1_FB26 target/stm32f103xb.h /^#define CAN_F13R1_FB26 /;" d +CAN_F13R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB27_Msk /;" d +CAN_F13R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB27_Pos /;" d +CAN_F13R1_FB27 target/stm32f103xb.h /^#define CAN_F13R1_FB27 /;" d +CAN_F13R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB28_Msk /;" d +CAN_F13R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB28_Pos /;" d +CAN_F13R1_FB28 target/stm32f103xb.h /^#define CAN_F13R1_FB28 /;" d +CAN_F13R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB29_Msk /;" d +CAN_F13R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB29_Pos /;" d +CAN_F13R1_FB29 target/stm32f103xb.h /^#define CAN_F13R1_FB29 /;" d +CAN_F13R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB2_Msk /;" d +CAN_F13R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB2_Pos /;" d +CAN_F13R1_FB2 target/stm32f103xb.h /^#define CAN_F13R1_FB2 /;" d +CAN_F13R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB30_Msk /;" d +CAN_F13R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB30_Pos /;" d +CAN_F13R1_FB30 target/stm32f103xb.h /^#define CAN_F13R1_FB30 /;" d +CAN_F13R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB31_Msk /;" d +CAN_F13R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB31_Pos /;" d +CAN_F13R1_FB31 target/stm32f103xb.h /^#define CAN_F13R1_FB31 /;" d +CAN_F13R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB3_Msk /;" d +CAN_F13R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB3_Pos /;" d +CAN_F13R1_FB3 target/stm32f103xb.h /^#define CAN_F13R1_FB3 /;" d +CAN_F13R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB4_Msk /;" d +CAN_F13R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB4_Pos /;" d +CAN_F13R1_FB4 target/stm32f103xb.h /^#define CAN_F13R1_FB4 /;" d +CAN_F13R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB5_Msk /;" d +CAN_F13R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB5_Pos /;" d +CAN_F13R1_FB5 target/stm32f103xb.h /^#define CAN_F13R1_FB5 /;" d +CAN_F13R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB6_Msk /;" d +CAN_F13R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB6_Pos /;" d +CAN_F13R1_FB6 target/stm32f103xb.h /^#define CAN_F13R1_FB6 /;" d +CAN_F13R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB7_Msk /;" d +CAN_F13R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB7_Pos /;" d +CAN_F13R1_FB7 target/stm32f103xb.h /^#define CAN_F13R1_FB7 /;" d +CAN_F13R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB8_Msk /;" d +CAN_F13R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB8_Pos /;" d +CAN_F13R1_FB8 target/stm32f103xb.h /^#define CAN_F13R1_FB8 /;" d +CAN_F13R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F13R1_FB9_Msk /;" d +CAN_F13R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F13R1_FB9_Pos /;" d +CAN_F13R1_FB9 target/stm32f103xb.h /^#define CAN_F13R1_FB9 /;" d +CAN_F13R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB0_Msk /;" d +CAN_F13R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB0_Pos /;" d +CAN_F13R2_FB0 target/stm32f103xb.h /^#define CAN_F13R2_FB0 /;" d +CAN_F13R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB10_Msk /;" d +CAN_F13R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB10_Pos /;" d +CAN_F13R2_FB10 target/stm32f103xb.h /^#define CAN_F13R2_FB10 /;" d +CAN_F13R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB11_Msk /;" d +CAN_F13R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB11_Pos /;" d +CAN_F13R2_FB11 target/stm32f103xb.h /^#define CAN_F13R2_FB11 /;" d +CAN_F13R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB12_Msk /;" d +CAN_F13R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB12_Pos /;" d +CAN_F13R2_FB12 target/stm32f103xb.h /^#define CAN_F13R2_FB12 /;" d +CAN_F13R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB13_Msk /;" d +CAN_F13R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB13_Pos /;" d +CAN_F13R2_FB13 target/stm32f103xb.h /^#define CAN_F13R2_FB13 /;" d +CAN_F13R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB14_Msk /;" d +CAN_F13R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB14_Pos /;" d +CAN_F13R2_FB14 target/stm32f103xb.h /^#define CAN_F13R2_FB14 /;" d +CAN_F13R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB15_Msk /;" d +CAN_F13R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB15_Pos /;" d +CAN_F13R2_FB15 target/stm32f103xb.h /^#define CAN_F13R2_FB15 /;" d +CAN_F13R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB16_Msk /;" d +CAN_F13R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB16_Pos /;" d +CAN_F13R2_FB16 target/stm32f103xb.h /^#define CAN_F13R2_FB16 /;" d +CAN_F13R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB17_Msk /;" d +CAN_F13R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB17_Pos /;" d +CAN_F13R2_FB17 target/stm32f103xb.h /^#define CAN_F13R2_FB17 /;" d +CAN_F13R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB18_Msk /;" d +CAN_F13R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB18_Pos /;" d +CAN_F13R2_FB18 target/stm32f103xb.h /^#define CAN_F13R2_FB18 /;" d +CAN_F13R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB19_Msk /;" d +CAN_F13R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB19_Pos /;" d +CAN_F13R2_FB19 target/stm32f103xb.h /^#define CAN_F13R2_FB19 /;" d +CAN_F13R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB1_Msk /;" d +CAN_F13R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB1_Pos /;" d +CAN_F13R2_FB1 target/stm32f103xb.h /^#define CAN_F13R2_FB1 /;" d +CAN_F13R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB20_Msk /;" d +CAN_F13R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB20_Pos /;" d +CAN_F13R2_FB20 target/stm32f103xb.h /^#define CAN_F13R2_FB20 /;" d +CAN_F13R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB21_Msk /;" d +CAN_F13R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB21_Pos /;" d +CAN_F13R2_FB21 target/stm32f103xb.h /^#define CAN_F13R2_FB21 /;" d +CAN_F13R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB22_Msk /;" d +CAN_F13R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB22_Pos /;" d +CAN_F13R2_FB22 target/stm32f103xb.h /^#define CAN_F13R2_FB22 /;" d +CAN_F13R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB23_Msk /;" d +CAN_F13R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB23_Pos /;" d +CAN_F13R2_FB23 target/stm32f103xb.h /^#define CAN_F13R2_FB23 /;" d +CAN_F13R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB24_Msk /;" d +CAN_F13R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB24_Pos /;" d +CAN_F13R2_FB24 target/stm32f103xb.h /^#define CAN_F13R2_FB24 /;" d +CAN_F13R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB25_Msk /;" d +CAN_F13R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB25_Pos /;" d +CAN_F13R2_FB25 target/stm32f103xb.h /^#define CAN_F13R2_FB25 /;" d +CAN_F13R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB26_Msk /;" d +CAN_F13R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB26_Pos /;" d +CAN_F13R2_FB26 target/stm32f103xb.h /^#define CAN_F13R2_FB26 /;" d +CAN_F13R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB27_Msk /;" d +CAN_F13R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB27_Pos /;" d +CAN_F13R2_FB27 target/stm32f103xb.h /^#define CAN_F13R2_FB27 /;" d +CAN_F13R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB28_Msk /;" d +CAN_F13R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB28_Pos /;" d +CAN_F13R2_FB28 target/stm32f103xb.h /^#define CAN_F13R2_FB28 /;" d +CAN_F13R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB29_Msk /;" d +CAN_F13R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB29_Pos /;" d +CAN_F13R2_FB29 target/stm32f103xb.h /^#define CAN_F13R2_FB29 /;" d +CAN_F13R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB2_Msk /;" d +CAN_F13R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB2_Pos /;" d +CAN_F13R2_FB2 target/stm32f103xb.h /^#define CAN_F13R2_FB2 /;" d +CAN_F13R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB30_Msk /;" d +CAN_F13R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB30_Pos /;" d +CAN_F13R2_FB30 target/stm32f103xb.h /^#define CAN_F13R2_FB30 /;" d +CAN_F13R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB31_Msk /;" d +CAN_F13R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB31_Pos /;" d +CAN_F13R2_FB31 target/stm32f103xb.h /^#define CAN_F13R2_FB31 /;" d +CAN_F13R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB3_Msk /;" d +CAN_F13R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB3_Pos /;" d +CAN_F13R2_FB3 target/stm32f103xb.h /^#define CAN_F13R2_FB3 /;" d +CAN_F13R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB4_Msk /;" d +CAN_F13R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB4_Pos /;" d +CAN_F13R2_FB4 target/stm32f103xb.h /^#define CAN_F13R2_FB4 /;" d +CAN_F13R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB5_Msk /;" d +CAN_F13R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB5_Pos /;" d +CAN_F13R2_FB5 target/stm32f103xb.h /^#define CAN_F13R2_FB5 /;" d +CAN_F13R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB6_Msk /;" d +CAN_F13R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB6_Pos /;" d +CAN_F13R2_FB6 target/stm32f103xb.h /^#define CAN_F13R2_FB6 /;" d +CAN_F13R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB7_Msk /;" d +CAN_F13R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB7_Pos /;" d +CAN_F13R2_FB7 target/stm32f103xb.h /^#define CAN_F13R2_FB7 /;" d +CAN_F13R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB8_Msk /;" d +CAN_F13R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB8_Pos /;" d +CAN_F13R2_FB8 target/stm32f103xb.h /^#define CAN_F13R2_FB8 /;" d +CAN_F13R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F13R2_FB9_Msk /;" d +CAN_F13R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F13R2_FB9_Pos /;" d +CAN_F13R2_FB9 target/stm32f103xb.h /^#define CAN_F13R2_FB9 /;" d +CAN_F1R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB0_Msk /;" d +CAN_F1R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB0_Pos /;" d +CAN_F1R1_FB0 target/stm32f103xb.h /^#define CAN_F1R1_FB0 /;" d +CAN_F1R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB10_Msk /;" d +CAN_F1R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB10_Pos /;" d +CAN_F1R1_FB10 target/stm32f103xb.h /^#define CAN_F1R1_FB10 /;" d +CAN_F1R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB11_Msk /;" d +CAN_F1R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB11_Pos /;" d +CAN_F1R1_FB11 target/stm32f103xb.h /^#define CAN_F1R1_FB11 /;" d +CAN_F1R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB12_Msk /;" d +CAN_F1R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB12_Pos /;" d +CAN_F1R1_FB12 target/stm32f103xb.h /^#define CAN_F1R1_FB12 /;" d +CAN_F1R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB13_Msk /;" d +CAN_F1R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB13_Pos /;" d +CAN_F1R1_FB13 target/stm32f103xb.h /^#define CAN_F1R1_FB13 /;" d +CAN_F1R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB14_Msk /;" d +CAN_F1R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB14_Pos /;" d +CAN_F1R1_FB14 target/stm32f103xb.h /^#define CAN_F1R1_FB14 /;" d +CAN_F1R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB15_Msk /;" d +CAN_F1R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB15_Pos /;" d +CAN_F1R1_FB15 target/stm32f103xb.h /^#define CAN_F1R1_FB15 /;" d +CAN_F1R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB16_Msk /;" d +CAN_F1R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB16_Pos /;" d +CAN_F1R1_FB16 target/stm32f103xb.h /^#define CAN_F1R1_FB16 /;" d +CAN_F1R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB17_Msk /;" d +CAN_F1R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB17_Pos /;" d +CAN_F1R1_FB17 target/stm32f103xb.h /^#define CAN_F1R1_FB17 /;" d +CAN_F1R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB18_Msk /;" d +CAN_F1R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB18_Pos /;" d +CAN_F1R1_FB18 target/stm32f103xb.h /^#define CAN_F1R1_FB18 /;" d +CAN_F1R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB19_Msk /;" d +CAN_F1R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB19_Pos /;" d +CAN_F1R1_FB19 target/stm32f103xb.h /^#define CAN_F1R1_FB19 /;" d +CAN_F1R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB1_Msk /;" d +CAN_F1R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB1_Pos /;" d +CAN_F1R1_FB1 target/stm32f103xb.h /^#define CAN_F1R1_FB1 /;" d +CAN_F1R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB20_Msk /;" d +CAN_F1R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB20_Pos /;" d +CAN_F1R1_FB20 target/stm32f103xb.h /^#define CAN_F1R1_FB20 /;" d +CAN_F1R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB21_Msk /;" d +CAN_F1R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB21_Pos /;" d +CAN_F1R1_FB21 target/stm32f103xb.h /^#define CAN_F1R1_FB21 /;" d +CAN_F1R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB22_Msk /;" d +CAN_F1R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB22_Pos /;" d +CAN_F1R1_FB22 target/stm32f103xb.h /^#define CAN_F1R1_FB22 /;" d +CAN_F1R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB23_Msk /;" d +CAN_F1R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB23_Pos /;" d +CAN_F1R1_FB23 target/stm32f103xb.h /^#define CAN_F1R1_FB23 /;" d +CAN_F1R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB24_Msk /;" d +CAN_F1R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB24_Pos /;" d +CAN_F1R1_FB24 target/stm32f103xb.h /^#define CAN_F1R1_FB24 /;" d +CAN_F1R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB25_Msk /;" d +CAN_F1R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB25_Pos /;" d +CAN_F1R1_FB25 target/stm32f103xb.h /^#define CAN_F1R1_FB25 /;" d +CAN_F1R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB26_Msk /;" d +CAN_F1R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB26_Pos /;" d +CAN_F1R1_FB26 target/stm32f103xb.h /^#define CAN_F1R1_FB26 /;" d +CAN_F1R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB27_Msk /;" d +CAN_F1R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB27_Pos /;" d +CAN_F1R1_FB27 target/stm32f103xb.h /^#define CAN_F1R1_FB27 /;" d +CAN_F1R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB28_Msk /;" d +CAN_F1R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB28_Pos /;" d +CAN_F1R1_FB28 target/stm32f103xb.h /^#define CAN_F1R1_FB28 /;" d +CAN_F1R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB29_Msk /;" d +CAN_F1R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB29_Pos /;" d +CAN_F1R1_FB29 target/stm32f103xb.h /^#define CAN_F1R1_FB29 /;" d +CAN_F1R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB2_Msk /;" d +CAN_F1R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB2_Pos /;" d +CAN_F1R1_FB2 target/stm32f103xb.h /^#define CAN_F1R1_FB2 /;" d +CAN_F1R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB30_Msk /;" d +CAN_F1R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB30_Pos /;" d +CAN_F1R1_FB30 target/stm32f103xb.h /^#define CAN_F1R1_FB30 /;" d +CAN_F1R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB31_Msk /;" d +CAN_F1R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB31_Pos /;" d +CAN_F1R1_FB31 target/stm32f103xb.h /^#define CAN_F1R1_FB31 /;" d +CAN_F1R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB3_Msk /;" d +CAN_F1R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB3_Pos /;" d +CAN_F1R1_FB3 target/stm32f103xb.h /^#define CAN_F1R1_FB3 /;" d +CAN_F1R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB4_Msk /;" d +CAN_F1R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB4_Pos /;" d +CAN_F1R1_FB4 target/stm32f103xb.h /^#define CAN_F1R1_FB4 /;" d +CAN_F1R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB5_Msk /;" d +CAN_F1R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB5_Pos /;" d +CAN_F1R1_FB5 target/stm32f103xb.h /^#define CAN_F1R1_FB5 /;" d +CAN_F1R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB6_Msk /;" d +CAN_F1R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB6_Pos /;" d +CAN_F1R1_FB6 target/stm32f103xb.h /^#define CAN_F1R1_FB6 /;" d +CAN_F1R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB7_Msk /;" d +CAN_F1R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB7_Pos /;" d +CAN_F1R1_FB7 target/stm32f103xb.h /^#define CAN_F1R1_FB7 /;" d +CAN_F1R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB8_Msk /;" d +CAN_F1R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB8_Pos /;" d +CAN_F1R1_FB8 target/stm32f103xb.h /^#define CAN_F1R1_FB8 /;" d +CAN_F1R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F1R1_FB9_Msk /;" d +CAN_F1R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F1R1_FB9_Pos /;" d +CAN_F1R1_FB9 target/stm32f103xb.h /^#define CAN_F1R1_FB9 /;" d +CAN_F1R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB0_Msk /;" d +CAN_F1R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB0_Pos /;" d +CAN_F1R2_FB0 target/stm32f103xb.h /^#define CAN_F1R2_FB0 /;" d +CAN_F1R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB10_Msk /;" d +CAN_F1R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB10_Pos /;" d +CAN_F1R2_FB10 target/stm32f103xb.h /^#define CAN_F1R2_FB10 /;" d +CAN_F1R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB11_Msk /;" d +CAN_F1R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB11_Pos /;" d +CAN_F1R2_FB11 target/stm32f103xb.h /^#define CAN_F1R2_FB11 /;" d +CAN_F1R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB12_Msk /;" d +CAN_F1R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB12_Pos /;" d +CAN_F1R2_FB12 target/stm32f103xb.h /^#define CAN_F1R2_FB12 /;" d +CAN_F1R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB13_Msk /;" d +CAN_F1R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB13_Pos /;" d +CAN_F1R2_FB13 target/stm32f103xb.h /^#define CAN_F1R2_FB13 /;" d +CAN_F1R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB14_Msk /;" d +CAN_F1R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB14_Pos /;" d +CAN_F1R2_FB14 target/stm32f103xb.h /^#define CAN_F1R2_FB14 /;" d +CAN_F1R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB15_Msk /;" d +CAN_F1R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB15_Pos /;" d +CAN_F1R2_FB15 target/stm32f103xb.h /^#define CAN_F1R2_FB15 /;" d +CAN_F1R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB16_Msk /;" d +CAN_F1R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB16_Pos /;" d +CAN_F1R2_FB16 target/stm32f103xb.h /^#define CAN_F1R2_FB16 /;" d +CAN_F1R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB17_Msk /;" d +CAN_F1R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB17_Pos /;" d +CAN_F1R2_FB17 target/stm32f103xb.h /^#define CAN_F1R2_FB17 /;" d +CAN_F1R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB18_Msk /;" d +CAN_F1R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB18_Pos /;" d +CAN_F1R2_FB18 target/stm32f103xb.h /^#define CAN_F1R2_FB18 /;" d +CAN_F1R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB19_Msk /;" d +CAN_F1R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB19_Pos /;" d +CAN_F1R2_FB19 target/stm32f103xb.h /^#define CAN_F1R2_FB19 /;" d +CAN_F1R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB1_Msk /;" d +CAN_F1R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB1_Pos /;" d +CAN_F1R2_FB1 target/stm32f103xb.h /^#define CAN_F1R2_FB1 /;" d +CAN_F1R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB20_Msk /;" d +CAN_F1R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB20_Pos /;" d +CAN_F1R2_FB20 target/stm32f103xb.h /^#define CAN_F1R2_FB20 /;" d +CAN_F1R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB21_Msk /;" d +CAN_F1R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB21_Pos /;" d +CAN_F1R2_FB21 target/stm32f103xb.h /^#define CAN_F1R2_FB21 /;" d +CAN_F1R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB22_Msk /;" d +CAN_F1R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB22_Pos /;" d +CAN_F1R2_FB22 target/stm32f103xb.h /^#define CAN_F1R2_FB22 /;" d +CAN_F1R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB23_Msk /;" d +CAN_F1R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB23_Pos /;" d +CAN_F1R2_FB23 target/stm32f103xb.h /^#define CAN_F1R2_FB23 /;" d +CAN_F1R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB24_Msk /;" d +CAN_F1R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB24_Pos /;" d +CAN_F1R2_FB24 target/stm32f103xb.h /^#define CAN_F1R2_FB24 /;" d +CAN_F1R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB25_Msk /;" d +CAN_F1R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB25_Pos /;" d +CAN_F1R2_FB25 target/stm32f103xb.h /^#define CAN_F1R2_FB25 /;" d +CAN_F1R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB26_Msk /;" d +CAN_F1R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB26_Pos /;" d +CAN_F1R2_FB26 target/stm32f103xb.h /^#define CAN_F1R2_FB26 /;" d +CAN_F1R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB27_Msk /;" d +CAN_F1R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB27_Pos /;" d +CAN_F1R2_FB27 target/stm32f103xb.h /^#define CAN_F1R2_FB27 /;" d +CAN_F1R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB28_Msk /;" d +CAN_F1R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB28_Pos /;" d +CAN_F1R2_FB28 target/stm32f103xb.h /^#define CAN_F1R2_FB28 /;" d +CAN_F1R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB29_Msk /;" d +CAN_F1R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB29_Pos /;" d +CAN_F1R2_FB29 target/stm32f103xb.h /^#define CAN_F1R2_FB29 /;" d +CAN_F1R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB2_Msk /;" d +CAN_F1R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB2_Pos /;" d +CAN_F1R2_FB2 target/stm32f103xb.h /^#define CAN_F1R2_FB2 /;" d +CAN_F1R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB30_Msk /;" d +CAN_F1R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB30_Pos /;" d +CAN_F1R2_FB30 target/stm32f103xb.h /^#define CAN_F1R2_FB30 /;" d +CAN_F1R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB31_Msk /;" d +CAN_F1R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB31_Pos /;" d +CAN_F1R2_FB31 target/stm32f103xb.h /^#define CAN_F1R2_FB31 /;" d +CAN_F1R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB3_Msk /;" d +CAN_F1R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB3_Pos /;" d +CAN_F1R2_FB3 target/stm32f103xb.h /^#define CAN_F1R2_FB3 /;" d +CAN_F1R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB4_Msk /;" d +CAN_F1R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB4_Pos /;" d +CAN_F1R2_FB4 target/stm32f103xb.h /^#define CAN_F1R2_FB4 /;" d +CAN_F1R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB5_Msk /;" d +CAN_F1R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB5_Pos /;" d +CAN_F1R2_FB5 target/stm32f103xb.h /^#define CAN_F1R2_FB5 /;" d +CAN_F1R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB6_Msk /;" d +CAN_F1R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB6_Pos /;" d +CAN_F1R2_FB6 target/stm32f103xb.h /^#define CAN_F1R2_FB6 /;" d +CAN_F1R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB7_Msk /;" d +CAN_F1R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB7_Pos /;" d +CAN_F1R2_FB7 target/stm32f103xb.h /^#define CAN_F1R2_FB7 /;" d +CAN_F1R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB8_Msk /;" d +CAN_F1R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB8_Pos /;" d +CAN_F1R2_FB8 target/stm32f103xb.h /^#define CAN_F1R2_FB8 /;" d +CAN_F1R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F1R2_FB9_Msk /;" d +CAN_F1R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F1R2_FB9_Pos /;" d +CAN_F1R2_FB9 target/stm32f103xb.h /^#define CAN_F1R2_FB9 /;" d +CAN_F2R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB0_Msk /;" d +CAN_F2R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB0_Pos /;" d +CAN_F2R1_FB0 target/stm32f103xb.h /^#define CAN_F2R1_FB0 /;" d +CAN_F2R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB10_Msk /;" d +CAN_F2R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB10_Pos /;" d +CAN_F2R1_FB10 target/stm32f103xb.h /^#define CAN_F2R1_FB10 /;" d +CAN_F2R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB11_Msk /;" d +CAN_F2R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB11_Pos /;" d +CAN_F2R1_FB11 target/stm32f103xb.h /^#define CAN_F2R1_FB11 /;" d +CAN_F2R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB12_Msk /;" d +CAN_F2R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB12_Pos /;" d +CAN_F2R1_FB12 target/stm32f103xb.h /^#define CAN_F2R1_FB12 /;" d +CAN_F2R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB13_Msk /;" d +CAN_F2R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB13_Pos /;" d +CAN_F2R1_FB13 target/stm32f103xb.h /^#define CAN_F2R1_FB13 /;" d +CAN_F2R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB14_Msk /;" d +CAN_F2R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB14_Pos /;" d +CAN_F2R1_FB14 target/stm32f103xb.h /^#define CAN_F2R1_FB14 /;" d +CAN_F2R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB15_Msk /;" d +CAN_F2R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB15_Pos /;" d +CAN_F2R1_FB15 target/stm32f103xb.h /^#define CAN_F2R1_FB15 /;" d +CAN_F2R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB16_Msk /;" d +CAN_F2R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB16_Pos /;" d +CAN_F2R1_FB16 target/stm32f103xb.h /^#define CAN_F2R1_FB16 /;" d +CAN_F2R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB17_Msk /;" d +CAN_F2R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB17_Pos /;" d +CAN_F2R1_FB17 target/stm32f103xb.h /^#define CAN_F2R1_FB17 /;" d +CAN_F2R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB18_Msk /;" d +CAN_F2R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB18_Pos /;" d +CAN_F2R1_FB18 target/stm32f103xb.h /^#define CAN_F2R1_FB18 /;" d +CAN_F2R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB19_Msk /;" d +CAN_F2R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB19_Pos /;" d +CAN_F2R1_FB19 target/stm32f103xb.h /^#define CAN_F2R1_FB19 /;" d +CAN_F2R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB1_Msk /;" d +CAN_F2R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB1_Pos /;" d +CAN_F2R1_FB1 target/stm32f103xb.h /^#define CAN_F2R1_FB1 /;" d +CAN_F2R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB20_Msk /;" d +CAN_F2R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB20_Pos /;" d +CAN_F2R1_FB20 target/stm32f103xb.h /^#define CAN_F2R1_FB20 /;" d +CAN_F2R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB21_Msk /;" d +CAN_F2R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB21_Pos /;" d +CAN_F2R1_FB21 target/stm32f103xb.h /^#define CAN_F2R1_FB21 /;" d +CAN_F2R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB22_Msk /;" d +CAN_F2R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB22_Pos /;" d +CAN_F2R1_FB22 target/stm32f103xb.h /^#define CAN_F2R1_FB22 /;" d +CAN_F2R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB23_Msk /;" d +CAN_F2R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB23_Pos /;" d +CAN_F2R1_FB23 target/stm32f103xb.h /^#define CAN_F2R1_FB23 /;" d +CAN_F2R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB24_Msk /;" d +CAN_F2R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB24_Pos /;" d +CAN_F2R1_FB24 target/stm32f103xb.h /^#define CAN_F2R1_FB24 /;" d +CAN_F2R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB25_Msk /;" d +CAN_F2R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB25_Pos /;" d +CAN_F2R1_FB25 target/stm32f103xb.h /^#define CAN_F2R1_FB25 /;" d +CAN_F2R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB26_Msk /;" d +CAN_F2R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB26_Pos /;" d +CAN_F2R1_FB26 target/stm32f103xb.h /^#define CAN_F2R1_FB26 /;" d +CAN_F2R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB27_Msk /;" d +CAN_F2R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB27_Pos /;" d +CAN_F2R1_FB27 target/stm32f103xb.h /^#define CAN_F2R1_FB27 /;" d +CAN_F2R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB28_Msk /;" d +CAN_F2R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB28_Pos /;" d +CAN_F2R1_FB28 target/stm32f103xb.h /^#define CAN_F2R1_FB28 /;" d +CAN_F2R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB29_Msk /;" d +CAN_F2R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB29_Pos /;" d +CAN_F2R1_FB29 target/stm32f103xb.h /^#define CAN_F2R1_FB29 /;" d +CAN_F2R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB2_Msk /;" d +CAN_F2R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB2_Pos /;" d +CAN_F2R1_FB2 target/stm32f103xb.h /^#define CAN_F2R1_FB2 /;" d +CAN_F2R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB30_Msk /;" d +CAN_F2R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB30_Pos /;" d +CAN_F2R1_FB30 target/stm32f103xb.h /^#define CAN_F2R1_FB30 /;" d +CAN_F2R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB31_Msk /;" d +CAN_F2R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB31_Pos /;" d +CAN_F2R1_FB31 target/stm32f103xb.h /^#define CAN_F2R1_FB31 /;" d +CAN_F2R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB3_Msk /;" d +CAN_F2R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB3_Pos /;" d +CAN_F2R1_FB3 target/stm32f103xb.h /^#define CAN_F2R1_FB3 /;" d +CAN_F2R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB4_Msk /;" d +CAN_F2R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB4_Pos /;" d +CAN_F2R1_FB4 target/stm32f103xb.h /^#define CAN_F2R1_FB4 /;" d +CAN_F2R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB5_Msk /;" d +CAN_F2R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB5_Pos /;" d +CAN_F2R1_FB5 target/stm32f103xb.h /^#define CAN_F2R1_FB5 /;" d +CAN_F2R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB6_Msk /;" d +CAN_F2R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB6_Pos /;" d +CAN_F2R1_FB6 target/stm32f103xb.h /^#define CAN_F2R1_FB6 /;" d +CAN_F2R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB7_Msk /;" d +CAN_F2R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB7_Pos /;" d +CAN_F2R1_FB7 target/stm32f103xb.h /^#define CAN_F2R1_FB7 /;" d +CAN_F2R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB8_Msk /;" d +CAN_F2R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB8_Pos /;" d +CAN_F2R1_FB8 target/stm32f103xb.h /^#define CAN_F2R1_FB8 /;" d +CAN_F2R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F2R1_FB9_Msk /;" d +CAN_F2R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F2R1_FB9_Pos /;" d +CAN_F2R1_FB9 target/stm32f103xb.h /^#define CAN_F2R1_FB9 /;" d +CAN_F2R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB0_Msk /;" d +CAN_F2R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB0_Pos /;" d +CAN_F2R2_FB0 target/stm32f103xb.h /^#define CAN_F2R2_FB0 /;" d +CAN_F2R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB10_Msk /;" d +CAN_F2R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB10_Pos /;" d +CAN_F2R2_FB10 target/stm32f103xb.h /^#define CAN_F2R2_FB10 /;" d +CAN_F2R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB11_Msk /;" d +CAN_F2R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB11_Pos /;" d +CAN_F2R2_FB11 target/stm32f103xb.h /^#define CAN_F2R2_FB11 /;" d +CAN_F2R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB12_Msk /;" d +CAN_F2R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB12_Pos /;" d +CAN_F2R2_FB12 target/stm32f103xb.h /^#define CAN_F2R2_FB12 /;" d +CAN_F2R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB13_Msk /;" d +CAN_F2R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB13_Pos /;" d +CAN_F2R2_FB13 target/stm32f103xb.h /^#define CAN_F2R2_FB13 /;" d +CAN_F2R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB14_Msk /;" d +CAN_F2R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB14_Pos /;" d +CAN_F2R2_FB14 target/stm32f103xb.h /^#define CAN_F2R2_FB14 /;" d +CAN_F2R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB15_Msk /;" d +CAN_F2R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB15_Pos /;" d +CAN_F2R2_FB15 target/stm32f103xb.h /^#define CAN_F2R2_FB15 /;" d +CAN_F2R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB16_Msk /;" d +CAN_F2R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB16_Pos /;" d +CAN_F2R2_FB16 target/stm32f103xb.h /^#define CAN_F2R2_FB16 /;" d +CAN_F2R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB17_Msk /;" d +CAN_F2R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB17_Pos /;" d +CAN_F2R2_FB17 target/stm32f103xb.h /^#define CAN_F2R2_FB17 /;" d +CAN_F2R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB18_Msk /;" d +CAN_F2R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB18_Pos /;" d +CAN_F2R2_FB18 target/stm32f103xb.h /^#define CAN_F2R2_FB18 /;" d +CAN_F2R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB19_Msk /;" d +CAN_F2R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB19_Pos /;" d +CAN_F2R2_FB19 target/stm32f103xb.h /^#define CAN_F2R2_FB19 /;" d +CAN_F2R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB1_Msk /;" d +CAN_F2R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB1_Pos /;" d +CAN_F2R2_FB1 target/stm32f103xb.h /^#define CAN_F2R2_FB1 /;" d +CAN_F2R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB20_Msk /;" d +CAN_F2R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB20_Pos /;" d +CAN_F2R2_FB20 target/stm32f103xb.h /^#define CAN_F2R2_FB20 /;" d +CAN_F2R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB21_Msk /;" d +CAN_F2R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB21_Pos /;" d +CAN_F2R2_FB21 target/stm32f103xb.h /^#define CAN_F2R2_FB21 /;" d +CAN_F2R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB22_Msk /;" d +CAN_F2R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB22_Pos /;" d +CAN_F2R2_FB22 target/stm32f103xb.h /^#define CAN_F2R2_FB22 /;" d +CAN_F2R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB23_Msk /;" d +CAN_F2R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB23_Pos /;" d +CAN_F2R2_FB23 target/stm32f103xb.h /^#define CAN_F2R2_FB23 /;" d +CAN_F2R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB24_Msk /;" d +CAN_F2R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB24_Pos /;" d +CAN_F2R2_FB24 target/stm32f103xb.h /^#define CAN_F2R2_FB24 /;" d +CAN_F2R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB25_Msk /;" d +CAN_F2R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB25_Pos /;" d +CAN_F2R2_FB25 target/stm32f103xb.h /^#define CAN_F2R2_FB25 /;" d +CAN_F2R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB26_Msk /;" d +CAN_F2R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB26_Pos /;" d +CAN_F2R2_FB26 target/stm32f103xb.h /^#define CAN_F2R2_FB26 /;" d +CAN_F2R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB27_Msk /;" d +CAN_F2R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB27_Pos /;" d +CAN_F2R2_FB27 target/stm32f103xb.h /^#define CAN_F2R2_FB27 /;" d +CAN_F2R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB28_Msk /;" d +CAN_F2R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB28_Pos /;" d +CAN_F2R2_FB28 target/stm32f103xb.h /^#define CAN_F2R2_FB28 /;" d +CAN_F2R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB29_Msk /;" d +CAN_F2R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB29_Pos /;" d +CAN_F2R2_FB29 target/stm32f103xb.h /^#define CAN_F2R2_FB29 /;" d +CAN_F2R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB2_Msk /;" d +CAN_F2R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB2_Pos /;" d +CAN_F2R2_FB2 target/stm32f103xb.h /^#define CAN_F2R2_FB2 /;" d +CAN_F2R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB30_Msk /;" d +CAN_F2R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB30_Pos /;" d +CAN_F2R2_FB30 target/stm32f103xb.h /^#define CAN_F2R2_FB30 /;" d +CAN_F2R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB31_Msk /;" d +CAN_F2R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB31_Pos /;" d +CAN_F2R2_FB31 target/stm32f103xb.h /^#define CAN_F2R2_FB31 /;" d +CAN_F2R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB3_Msk /;" d +CAN_F2R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB3_Pos /;" d +CAN_F2R2_FB3 target/stm32f103xb.h /^#define CAN_F2R2_FB3 /;" d +CAN_F2R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB4_Msk /;" d +CAN_F2R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB4_Pos /;" d +CAN_F2R2_FB4 target/stm32f103xb.h /^#define CAN_F2R2_FB4 /;" d +CAN_F2R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB5_Msk /;" d +CAN_F2R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB5_Pos /;" d +CAN_F2R2_FB5 target/stm32f103xb.h /^#define CAN_F2R2_FB5 /;" d +CAN_F2R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB6_Msk /;" d +CAN_F2R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB6_Pos /;" d +CAN_F2R2_FB6 target/stm32f103xb.h /^#define CAN_F2R2_FB6 /;" d +CAN_F2R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB7_Msk /;" d +CAN_F2R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB7_Pos /;" d +CAN_F2R2_FB7 target/stm32f103xb.h /^#define CAN_F2R2_FB7 /;" d +CAN_F2R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB8_Msk /;" d +CAN_F2R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB8_Pos /;" d +CAN_F2R2_FB8 target/stm32f103xb.h /^#define CAN_F2R2_FB8 /;" d +CAN_F2R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F2R2_FB9_Msk /;" d +CAN_F2R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F2R2_FB9_Pos /;" d +CAN_F2R2_FB9 target/stm32f103xb.h /^#define CAN_F2R2_FB9 /;" d +CAN_F3R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB0_Msk /;" d +CAN_F3R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB0_Pos /;" d +CAN_F3R1_FB0 target/stm32f103xb.h /^#define CAN_F3R1_FB0 /;" d +CAN_F3R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB10_Msk /;" d +CAN_F3R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB10_Pos /;" d +CAN_F3R1_FB10 target/stm32f103xb.h /^#define CAN_F3R1_FB10 /;" d +CAN_F3R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB11_Msk /;" d +CAN_F3R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB11_Pos /;" d +CAN_F3R1_FB11 target/stm32f103xb.h /^#define CAN_F3R1_FB11 /;" d +CAN_F3R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB12_Msk /;" d +CAN_F3R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB12_Pos /;" d +CAN_F3R1_FB12 target/stm32f103xb.h /^#define CAN_F3R1_FB12 /;" d +CAN_F3R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB13_Msk /;" d +CAN_F3R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB13_Pos /;" d +CAN_F3R1_FB13 target/stm32f103xb.h /^#define CAN_F3R1_FB13 /;" d +CAN_F3R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB14_Msk /;" d +CAN_F3R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB14_Pos /;" d +CAN_F3R1_FB14 target/stm32f103xb.h /^#define CAN_F3R1_FB14 /;" d +CAN_F3R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB15_Msk /;" d +CAN_F3R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB15_Pos /;" d +CAN_F3R1_FB15 target/stm32f103xb.h /^#define CAN_F3R1_FB15 /;" d +CAN_F3R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB16_Msk /;" d +CAN_F3R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB16_Pos /;" d +CAN_F3R1_FB16 target/stm32f103xb.h /^#define CAN_F3R1_FB16 /;" d +CAN_F3R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB17_Msk /;" d +CAN_F3R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB17_Pos /;" d +CAN_F3R1_FB17 target/stm32f103xb.h /^#define CAN_F3R1_FB17 /;" d +CAN_F3R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB18_Msk /;" d +CAN_F3R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB18_Pos /;" d +CAN_F3R1_FB18 target/stm32f103xb.h /^#define CAN_F3R1_FB18 /;" d +CAN_F3R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB19_Msk /;" d +CAN_F3R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB19_Pos /;" d +CAN_F3R1_FB19 target/stm32f103xb.h /^#define CAN_F3R1_FB19 /;" d +CAN_F3R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB1_Msk /;" d +CAN_F3R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB1_Pos /;" d +CAN_F3R1_FB1 target/stm32f103xb.h /^#define CAN_F3R1_FB1 /;" d +CAN_F3R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB20_Msk /;" d +CAN_F3R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB20_Pos /;" d +CAN_F3R1_FB20 target/stm32f103xb.h /^#define CAN_F3R1_FB20 /;" d +CAN_F3R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB21_Msk /;" d +CAN_F3R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB21_Pos /;" d +CAN_F3R1_FB21 target/stm32f103xb.h /^#define CAN_F3R1_FB21 /;" d +CAN_F3R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB22_Msk /;" d +CAN_F3R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB22_Pos /;" d +CAN_F3R1_FB22 target/stm32f103xb.h /^#define CAN_F3R1_FB22 /;" d +CAN_F3R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB23_Msk /;" d +CAN_F3R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB23_Pos /;" d +CAN_F3R1_FB23 target/stm32f103xb.h /^#define CAN_F3R1_FB23 /;" d +CAN_F3R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB24_Msk /;" d +CAN_F3R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB24_Pos /;" d +CAN_F3R1_FB24 target/stm32f103xb.h /^#define CAN_F3R1_FB24 /;" d +CAN_F3R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB25_Msk /;" d +CAN_F3R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB25_Pos /;" d +CAN_F3R1_FB25 target/stm32f103xb.h /^#define CAN_F3R1_FB25 /;" d +CAN_F3R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB26_Msk /;" d +CAN_F3R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB26_Pos /;" d +CAN_F3R1_FB26 target/stm32f103xb.h /^#define CAN_F3R1_FB26 /;" d +CAN_F3R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB27_Msk /;" d +CAN_F3R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB27_Pos /;" d +CAN_F3R1_FB27 target/stm32f103xb.h /^#define CAN_F3R1_FB27 /;" d +CAN_F3R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB28_Msk /;" d +CAN_F3R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB28_Pos /;" d +CAN_F3R1_FB28 target/stm32f103xb.h /^#define CAN_F3R1_FB28 /;" d +CAN_F3R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB29_Msk /;" d +CAN_F3R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB29_Pos /;" d +CAN_F3R1_FB29 target/stm32f103xb.h /^#define CAN_F3R1_FB29 /;" d +CAN_F3R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB2_Msk /;" d +CAN_F3R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB2_Pos /;" d +CAN_F3R1_FB2 target/stm32f103xb.h /^#define CAN_F3R1_FB2 /;" d +CAN_F3R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB30_Msk /;" d +CAN_F3R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB30_Pos /;" d +CAN_F3R1_FB30 target/stm32f103xb.h /^#define CAN_F3R1_FB30 /;" d +CAN_F3R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB31_Msk /;" d +CAN_F3R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB31_Pos /;" d +CAN_F3R1_FB31 target/stm32f103xb.h /^#define CAN_F3R1_FB31 /;" d +CAN_F3R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB3_Msk /;" d +CAN_F3R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB3_Pos /;" d +CAN_F3R1_FB3 target/stm32f103xb.h /^#define CAN_F3R1_FB3 /;" d +CAN_F3R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB4_Msk /;" d +CAN_F3R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB4_Pos /;" d +CAN_F3R1_FB4 target/stm32f103xb.h /^#define CAN_F3R1_FB4 /;" d +CAN_F3R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB5_Msk /;" d +CAN_F3R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB5_Pos /;" d +CAN_F3R1_FB5 target/stm32f103xb.h /^#define CAN_F3R1_FB5 /;" d +CAN_F3R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB6_Msk /;" d +CAN_F3R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB6_Pos /;" d +CAN_F3R1_FB6 target/stm32f103xb.h /^#define CAN_F3R1_FB6 /;" d +CAN_F3R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB7_Msk /;" d +CAN_F3R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB7_Pos /;" d +CAN_F3R1_FB7 target/stm32f103xb.h /^#define CAN_F3R1_FB7 /;" d +CAN_F3R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB8_Msk /;" d +CAN_F3R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB8_Pos /;" d +CAN_F3R1_FB8 target/stm32f103xb.h /^#define CAN_F3R1_FB8 /;" d +CAN_F3R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F3R1_FB9_Msk /;" d +CAN_F3R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F3R1_FB9_Pos /;" d +CAN_F3R1_FB9 target/stm32f103xb.h /^#define CAN_F3R1_FB9 /;" d +CAN_F3R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB0_Msk /;" d +CAN_F3R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB0_Pos /;" d +CAN_F3R2_FB0 target/stm32f103xb.h /^#define CAN_F3R2_FB0 /;" d +CAN_F3R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB10_Msk /;" d +CAN_F3R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB10_Pos /;" d +CAN_F3R2_FB10 target/stm32f103xb.h /^#define CAN_F3R2_FB10 /;" d +CAN_F3R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB11_Msk /;" d +CAN_F3R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB11_Pos /;" d +CAN_F3R2_FB11 target/stm32f103xb.h /^#define CAN_F3R2_FB11 /;" d +CAN_F3R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB12_Msk /;" d +CAN_F3R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB12_Pos /;" d +CAN_F3R2_FB12 target/stm32f103xb.h /^#define CAN_F3R2_FB12 /;" d +CAN_F3R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB13_Msk /;" d +CAN_F3R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB13_Pos /;" d +CAN_F3R2_FB13 target/stm32f103xb.h /^#define CAN_F3R2_FB13 /;" d +CAN_F3R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB14_Msk /;" d +CAN_F3R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB14_Pos /;" d +CAN_F3R2_FB14 target/stm32f103xb.h /^#define CAN_F3R2_FB14 /;" d +CAN_F3R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB15_Msk /;" d +CAN_F3R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB15_Pos /;" d +CAN_F3R2_FB15 target/stm32f103xb.h /^#define CAN_F3R2_FB15 /;" d +CAN_F3R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB16_Msk /;" d +CAN_F3R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB16_Pos /;" d +CAN_F3R2_FB16 target/stm32f103xb.h /^#define CAN_F3R2_FB16 /;" d +CAN_F3R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB17_Msk /;" d +CAN_F3R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB17_Pos /;" d +CAN_F3R2_FB17 target/stm32f103xb.h /^#define CAN_F3R2_FB17 /;" d +CAN_F3R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB18_Msk /;" d +CAN_F3R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB18_Pos /;" d +CAN_F3R2_FB18 target/stm32f103xb.h /^#define CAN_F3R2_FB18 /;" d +CAN_F3R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB19_Msk /;" d +CAN_F3R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB19_Pos /;" d +CAN_F3R2_FB19 target/stm32f103xb.h /^#define CAN_F3R2_FB19 /;" d +CAN_F3R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB1_Msk /;" d +CAN_F3R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB1_Pos /;" d +CAN_F3R2_FB1 target/stm32f103xb.h /^#define CAN_F3R2_FB1 /;" d +CAN_F3R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB20_Msk /;" d +CAN_F3R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB20_Pos /;" d +CAN_F3R2_FB20 target/stm32f103xb.h /^#define CAN_F3R2_FB20 /;" d +CAN_F3R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB21_Msk /;" d +CAN_F3R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB21_Pos /;" d +CAN_F3R2_FB21 target/stm32f103xb.h /^#define CAN_F3R2_FB21 /;" d +CAN_F3R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB22_Msk /;" d +CAN_F3R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB22_Pos /;" d +CAN_F3R2_FB22 target/stm32f103xb.h /^#define CAN_F3R2_FB22 /;" d +CAN_F3R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB23_Msk /;" d +CAN_F3R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB23_Pos /;" d +CAN_F3R2_FB23 target/stm32f103xb.h /^#define CAN_F3R2_FB23 /;" d +CAN_F3R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB24_Msk /;" d +CAN_F3R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB24_Pos /;" d +CAN_F3R2_FB24 target/stm32f103xb.h /^#define CAN_F3R2_FB24 /;" d +CAN_F3R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB25_Msk /;" d +CAN_F3R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB25_Pos /;" d +CAN_F3R2_FB25 target/stm32f103xb.h /^#define CAN_F3R2_FB25 /;" d +CAN_F3R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB26_Msk /;" d +CAN_F3R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB26_Pos /;" d +CAN_F3R2_FB26 target/stm32f103xb.h /^#define CAN_F3R2_FB26 /;" d +CAN_F3R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB27_Msk /;" d +CAN_F3R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB27_Pos /;" d +CAN_F3R2_FB27 target/stm32f103xb.h /^#define CAN_F3R2_FB27 /;" d +CAN_F3R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB28_Msk /;" d +CAN_F3R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB28_Pos /;" d +CAN_F3R2_FB28 target/stm32f103xb.h /^#define CAN_F3R2_FB28 /;" d +CAN_F3R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB29_Msk /;" d +CAN_F3R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB29_Pos /;" d +CAN_F3R2_FB29 target/stm32f103xb.h /^#define CAN_F3R2_FB29 /;" d +CAN_F3R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB2_Msk /;" d +CAN_F3R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB2_Pos /;" d +CAN_F3R2_FB2 target/stm32f103xb.h /^#define CAN_F3R2_FB2 /;" d +CAN_F3R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB30_Msk /;" d +CAN_F3R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB30_Pos /;" d +CAN_F3R2_FB30 target/stm32f103xb.h /^#define CAN_F3R2_FB30 /;" d +CAN_F3R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB31_Msk /;" d +CAN_F3R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB31_Pos /;" d +CAN_F3R2_FB31 target/stm32f103xb.h /^#define CAN_F3R2_FB31 /;" d +CAN_F3R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB3_Msk /;" d +CAN_F3R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB3_Pos /;" d +CAN_F3R2_FB3 target/stm32f103xb.h /^#define CAN_F3R2_FB3 /;" d +CAN_F3R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB4_Msk /;" d +CAN_F3R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB4_Pos /;" d +CAN_F3R2_FB4 target/stm32f103xb.h /^#define CAN_F3R2_FB4 /;" d +CAN_F3R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB5_Msk /;" d +CAN_F3R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB5_Pos /;" d +CAN_F3R2_FB5 target/stm32f103xb.h /^#define CAN_F3R2_FB5 /;" d +CAN_F3R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB6_Msk /;" d +CAN_F3R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB6_Pos /;" d +CAN_F3R2_FB6 target/stm32f103xb.h /^#define CAN_F3R2_FB6 /;" d +CAN_F3R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB7_Msk /;" d +CAN_F3R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB7_Pos /;" d +CAN_F3R2_FB7 target/stm32f103xb.h /^#define CAN_F3R2_FB7 /;" d +CAN_F3R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB8_Msk /;" d +CAN_F3R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB8_Pos /;" d +CAN_F3R2_FB8 target/stm32f103xb.h /^#define CAN_F3R2_FB8 /;" d +CAN_F3R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F3R2_FB9_Msk /;" d +CAN_F3R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F3R2_FB9_Pos /;" d +CAN_F3R2_FB9 target/stm32f103xb.h /^#define CAN_F3R2_FB9 /;" d +CAN_F4R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB0_Msk /;" d +CAN_F4R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB0_Pos /;" d +CAN_F4R1_FB0 target/stm32f103xb.h /^#define CAN_F4R1_FB0 /;" d +CAN_F4R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB10_Msk /;" d +CAN_F4R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB10_Pos /;" d +CAN_F4R1_FB10 target/stm32f103xb.h /^#define CAN_F4R1_FB10 /;" d +CAN_F4R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB11_Msk /;" d +CAN_F4R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB11_Pos /;" d +CAN_F4R1_FB11 target/stm32f103xb.h /^#define CAN_F4R1_FB11 /;" d +CAN_F4R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB12_Msk /;" d +CAN_F4R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB12_Pos /;" d +CAN_F4R1_FB12 target/stm32f103xb.h /^#define CAN_F4R1_FB12 /;" d +CAN_F4R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB13_Msk /;" d +CAN_F4R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB13_Pos /;" d +CAN_F4R1_FB13 target/stm32f103xb.h /^#define CAN_F4R1_FB13 /;" d +CAN_F4R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB14_Msk /;" d +CAN_F4R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB14_Pos /;" d +CAN_F4R1_FB14 target/stm32f103xb.h /^#define CAN_F4R1_FB14 /;" d +CAN_F4R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB15_Msk /;" d +CAN_F4R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB15_Pos /;" d +CAN_F4R1_FB15 target/stm32f103xb.h /^#define CAN_F4R1_FB15 /;" d +CAN_F4R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB16_Msk /;" d +CAN_F4R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB16_Pos /;" d +CAN_F4R1_FB16 target/stm32f103xb.h /^#define CAN_F4R1_FB16 /;" d +CAN_F4R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB17_Msk /;" d +CAN_F4R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB17_Pos /;" d +CAN_F4R1_FB17 target/stm32f103xb.h /^#define CAN_F4R1_FB17 /;" d +CAN_F4R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB18_Msk /;" d +CAN_F4R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB18_Pos /;" d +CAN_F4R1_FB18 target/stm32f103xb.h /^#define CAN_F4R1_FB18 /;" d +CAN_F4R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB19_Msk /;" d +CAN_F4R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB19_Pos /;" d +CAN_F4R1_FB19 target/stm32f103xb.h /^#define CAN_F4R1_FB19 /;" d +CAN_F4R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB1_Msk /;" d +CAN_F4R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB1_Pos /;" d +CAN_F4R1_FB1 target/stm32f103xb.h /^#define CAN_F4R1_FB1 /;" d +CAN_F4R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB20_Msk /;" d +CAN_F4R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB20_Pos /;" d +CAN_F4R1_FB20 target/stm32f103xb.h /^#define CAN_F4R1_FB20 /;" d +CAN_F4R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB21_Msk /;" d +CAN_F4R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB21_Pos /;" d +CAN_F4R1_FB21 target/stm32f103xb.h /^#define CAN_F4R1_FB21 /;" d +CAN_F4R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB22_Msk /;" d +CAN_F4R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB22_Pos /;" d +CAN_F4R1_FB22 target/stm32f103xb.h /^#define CAN_F4R1_FB22 /;" d +CAN_F4R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB23_Msk /;" d +CAN_F4R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB23_Pos /;" d +CAN_F4R1_FB23 target/stm32f103xb.h /^#define CAN_F4R1_FB23 /;" d +CAN_F4R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB24_Msk /;" d +CAN_F4R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB24_Pos /;" d +CAN_F4R1_FB24 target/stm32f103xb.h /^#define CAN_F4R1_FB24 /;" d +CAN_F4R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB25_Msk /;" d +CAN_F4R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB25_Pos /;" d +CAN_F4R1_FB25 target/stm32f103xb.h /^#define CAN_F4R1_FB25 /;" d +CAN_F4R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB26_Msk /;" d +CAN_F4R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB26_Pos /;" d +CAN_F4R1_FB26 target/stm32f103xb.h /^#define CAN_F4R1_FB26 /;" d +CAN_F4R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB27_Msk /;" d +CAN_F4R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB27_Pos /;" d +CAN_F4R1_FB27 target/stm32f103xb.h /^#define CAN_F4R1_FB27 /;" d +CAN_F4R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB28_Msk /;" d +CAN_F4R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB28_Pos /;" d +CAN_F4R1_FB28 target/stm32f103xb.h /^#define CAN_F4R1_FB28 /;" d +CAN_F4R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB29_Msk /;" d +CAN_F4R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB29_Pos /;" d +CAN_F4R1_FB29 target/stm32f103xb.h /^#define CAN_F4R1_FB29 /;" d +CAN_F4R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB2_Msk /;" d +CAN_F4R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB2_Pos /;" d +CAN_F4R1_FB2 target/stm32f103xb.h /^#define CAN_F4R1_FB2 /;" d +CAN_F4R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB30_Msk /;" d +CAN_F4R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB30_Pos /;" d +CAN_F4R1_FB30 target/stm32f103xb.h /^#define CAN_F4R1_FB30 /;" d +CAN_F4R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB31_Msk /;" d +CAN_F4R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB31_Pos /;" d +CAN_F4R1_FB31 target/stm32f103xb.h /^#define CAN_F4R1_FB31 /;" d +CAN_F4R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB3_Msk /;" d +CAN_F4R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB3_Pos /;" d +CAN_F4R1_FB3 target/stm32f103xb.h /^#define CAN_F4R1_FB3 /;" d +CAN_F4R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB4_Msk /;" d +CAN_F4R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB4_Pos /;" d +CAN_F4R1_FB4 target/stm32f103xb.h /^#define CAN_F4R1_FB4 /;" d +CAN_F4R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB5_Msk /;" d +CAN_F4R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB5_Pos /;" d +CAN_F4R1_FB5 target/stm32f103xb.h /^#define CAN_F4R1_FB5 /;" d +CAN_F4R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB6_Msk /;" d +CAN_F4R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB6_Pos /;" d +CAN_F4R1_FB6 target/stm32f103xb.h /^#define CAN_F4R1_FB6 /;" d +CAN_F4R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB7_Msk /;" d +CAN_F4R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB7_Pos /;" d +CAN_F4R1_FB7 target/stm32f103xb.h /^#define CAN_F4R1_FB7 /;" d +CAN_F4R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB8_Msk /;" d +CAN_F4R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB8_Pos /;" d +CAN_F4R1_FB8 target/stm32f103xb.h /^#define CAN_F4R1_FB8 /;" d +CAN_F4R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F4R1_FB9_Msk /;" d +CAN_F4R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F4R1_FB9_Pos /;" d +CAN_F4R1_FB9 target/stm32f103xb.h /^#define CAN_F4R1_FB9 /;" d +CAN_F4R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB0_Msk /;" d +CAN_F4R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB0_Pos /;" d +CAN_F4R2_FB0 target/stm32f103xb.h /^#define CAN_F4R2_FB0 /;" d +CAN_F4R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB10_Msk /;" d +CAN_F4R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB10_Pos /;" d +CAN_F4R2_FB10 target/stm32f103xb.h /^#define CAN_F4R2_FB10 /;" d +CAN_F4R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB11_Msk /;" d +CAN_F4R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB11_Pos /;" d +CAN_F4R2_FB11 target/stm32f103xb.h /^#define CAN_F4R2_FB11 /;" d +CAN_F4R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB12_Msk /;" d +CAN_F4R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB12_Pos /;" d +CAN_F4R2_FB12 target/stm32f103xb.h /^#define CAN_F4R2_FB12 /;" d +CAN_F4R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB13_Msk /;" d +CAN_F4R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB13_Pos /;" d +CAN_F4R2_FB13 target/stm32f103xb.h /^#define CAN_F4R2_FB13 /;" d +CAN_F4R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB14_Msk /;" d +CAN_F4R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB14_Pos /;" d +CAN_F4R2_FB14 target/stm32f103xb.h /^#define CAN_F4R2_FB14 /;" d +CAN_F4R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB15_Msk /;" d +CAN_F4R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB15_Pos /;" d +CAN_F4R2_FB15 target/stm32f103xb.h /^#define CAN_F4R2_FB15 /;" d +CAN_F4R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB16_Msk /;" d +CAN_F4R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB16_Pos /;" d +CAN_F4R2_FB16 target/stm32f103xb.h /^#define CAN_F4R2_FB16 /;" d +CAN_F4R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB17_Msk /;" d +CAN_F4R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB17_Pos /;" d +CAN_F4R2_FB17 target/stm32f103xb.h /^#define CAN_F4R2_FB17 /;" d +CAN_F4R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB18_Msk /;" d +CAN_F4R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB18_Pos /;" d +CAN_F4R2_FB18 target/stm32f103xb.h /^#define CAN_F4R2_FB18 /;" d +CAN_F4R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB19_Msk /;" d +CAN_F4R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB19_Pos /;" d +CAN_F4R2_FB19 target/stm32f103xb.h /^#define CAN_F4R2_FB19 /;" d +CAN_F4R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB1_Msk /;" d +CAN_F4R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB1_Pos /;" d +CAN_F4R2_FB1 target/stm32f103xb.h /^#define CAN_F4R2_FB1 /;" d +CAN_F4R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB20_Msk /;" d +CAN_F4R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB20_Pos /;" d +CAN_F4R2_FB20 target/stm32f103xb.h /^#define CAN_F4R2_FB20 /;" d +CAN_F4R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB21_Msk /;" d +CAN_F4R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB21_Pos /;" d +CAN_F4R2_FB21 target/stm32f103xb.h /^#define CAN_F4R2_FB21 /;" d +CAN_F4R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB22_Msk /;" d +CAN_F4R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB22_Pos /;" d +CAN_F4R2_FB22 target/stm32f103xb.h /^#define CAN_F4R2_FB22 /;" d +CAN_F4R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB23_Msk /;" d +CAN_F4R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB23_Pos /;" d +CAN_F4R2_FB23 target/stm32f103xb.h /^#define CAN_F4R2_FB23 /;" d +CAN_F4R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB24_Msk /;" d +CAN_F4R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB24_Pos /;" d +CAN_F4R2_FB24 target/stm32f103xb.h /^#define CAN_F4R2_FB24 /;" d +CAN_F4R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB25_Msk /;" d +CAN_F4R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB25_Pos /;" d +CAN_F4R2_FB25 target/stm32f103xb.h /^#define CAN_F4R2_FB25 /;" d +CAN_F4R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB26_Msk /;" d +CAN_F4R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB26_Pos /;" d +CAN_F4R2_FB26 target/stm32f103xb.h /^#define CAN_F4R2_FB26 /;" d +CAN_F4R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB27_Msk /;" d +CAN_F4R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB27_Pos /;" d +CAN_F4R2_FB27 target/stm32f103xb.h /^#define CAN_F4R2_FB27 /;" d +CAN_F4R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB28_Msk /;" d +CAN_F4R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB28_Pos /;" d +CAN_F4R2_FB28 target/stm32f103xb.h /^#define CAN_F4R2_FB28 /;" d +CAN_F4R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB29_Msk /;" d +CAN_F4R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB29_Pos /;" d +CAN_F4R2_FB29 target/stm32f103xb.h /^#define CAN_F4R2_FB29 /;" d +CAN_F4R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB2_Msk /;" d +CAN_F4R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB2_Pos /;" d +CAN_F4R2_FB2 target/stm32f103xb.h /^#define CAN_F4R2_FB2 /;" d +CAN_F4R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB30_Msk /;" d +CAN_F4R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB30_Pos /;" d +CAN_F4R2_FB30 target/stm32f103xb.h /^#define CAN_F4R2_FB30 /;" d +CAN_F4R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB31_Msk /;" d +CAN_F4R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB31_Pos /;" d +CAN_F4R2_FB31 target/stm32f103xb.h /^#define CAN_F4R2_FB31 /;" d +CAN_F4R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB3_Msk /;" d +CAN_F4R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB3_Pos /;" d +CAN_F4R2_FB3 target/stm32f103xb.h /^#define CAN_F4R2_FB3 /;" d +CAN_F4R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB4_Msk /;" d +CAN_F4R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB4_Pos /;" d +CAN_F4R2_FB4 target/stm32f103xb.h /^#define CAN_F4R2_FB4 /;" d +CAN_F4R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB5_Msk /;" d +CAN_F4R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB5_Pos /;" d +CAN_F4R2_FB5 target/stm32f103xb.h /^#define CAN_F4R2_FB5 /;" d +CAN_F4R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB6_Msk /;" d +CAN_F4R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB6_Pos /;" d +CAN_F4R2_FB6 target/stm32f103xb.h /^#define CAN_F4R2_FB6 /;" d +CAN_F4R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB7_Msk /;" d +CAN_F4R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB7_Pos /;" d +CAN_F4R2_FB7 target/stm32f103xb.h /^#define CAN_F4R2_FB7 /;" d +CAN_F4R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB8_Msk /;" d +CAN_F4R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB8_Pos /;" d +CAN_F4R2_FB8 target/stm32f103xb.h /^#define CAN_F4R2_FB8 /;" d +CAN_F4R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F4R2_FB9_Msk /;" d +CAN_F4R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F4R2_FB9_Pos /;" d +CAN_F4R2_FB9 target/stm32f103xb.h /^#define CAN_F4R2_FB9 /;" d +CAN_F5R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB0_Msk /;" d +CAN_F5R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB0_Pos /;" d +CAN_F5R1_FB0 target/stm32f103xb.h /^#define CAN_F5R1_FB0 /;" d +CAN_F5R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB10_Msk /;" d +CAN_F5R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB10_Pos /;" d +CAN_F5R1_FB10 target/stm32f103xb.h /^#define CAN_F5R1_FB10 /;" d +CAN_F5R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB11_Msk /;" d +CAN_F5R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB11_Pos /;" d +CAN_F5R1_FB11 target/stm32f103xb.h /^#define CAN_F5R1_FB11 /;" d +CAN_F5R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB12_Msk /;" d +CAN_F5R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB12_Pos /;" d +CAN_F5R1_FB12 target/stm32f103xb.h /^#define CAN_F5R1_FB12 /;" d +CAN_F5R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB13_Msk /;" d +CAN_F5R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB13_Pos /;" d +CAN_F5R1_FB13 target/stm32f103xb.h /^#define CAN_F5R1_FB13 /;" d +CAN_F5R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB14_Msk /;" d +CAN_F5R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB14_Pos /;" d +CAN_F5R1_FB14 target/stm32f103xb.h /^#define CAN_F5R1_FB14 /;" d +CAN_F5R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB15_Msk /;" d +CAN_F5R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB15_Pos /;" d +CAN_F5R1_FB15 target/stm32f103xb.h /^#define CAN_F5R1_FB15 /;" d +CAN_F5R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB16_Msk /;" d +CAN_F5R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB16_Pos /;" d +CAN_F5R1_FB16 target/stm32f103xb.h /^#define CAN_F5R1_FB16 /;" d +CAN_F5R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB17_Msk /;" d +CAN_F5R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB17_Pos /;" d +CAN_F5R1_FB17 target/stm32f103xb.h /^#define CAN_F5R1_FB17 /;" d +CAN_F5R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB18_Msk /;" d +CAN_F5R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB18_Pos /;" d +CAN_F5R1_FB18 target/stm32f103xb.h /^#define CAN_F5R1_FB18 /;" d +CAN_F5R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB19_Msk /;" d +CAN_F5R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB19_Pos /;" d +CAN_F5R1_FB19 target/stm32f103xb.h /^#define CAN_F5R1_FB19 /;" d +CAN_F5R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB1_Msk /;" d +CAN_F5R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB1_Pos /;" d +CAN_F5R1_FB1 target/stm32f103xb.h /^#define CAN_F5R1_FB1 /;" d +CAN_F5R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB20_Msk /;" d +CAN_F5R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB20_Pos /;" d +CAN_F5R1_FB20 target/stm32f103xb.h /^#define CAN_F5R1_FB20 /;" d +CAN_F5R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB21_Msk /;" d +CAN_F5R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB21_Pos /;" d +CAN_F5R1_FB21 target/stm32f103xb.h /^#define CAN_F5R1_FB21 /;" d +CAN_F5R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB22_Msk /;" d +CAN_F5R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB22_Pos /;" d +CAN_F5R1_FB22 target/stm32f103xb.h /^#define CAN_F5R1_FB22 /;" d +CAN_F5R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB23_Msk /;" d +CAN_F5R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB23_Pos /;" d +CAN_F5R1_FB23 target/stm32f103xb.h /^#define CAN_F5R1_FB23 /;" d +CAN_F5R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB24_Msk /;" d +CAN_F5R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB24_Pos /;" d +CAN_F5R1_FB24 target/stm32f103xb.h /^#define CAN_F5R1_FB24 /;" d +CAN_F5R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB25_Msk /;" d +CAN_F5R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB25_Pos /;" d +CAN_F5R1_FB25 target/stm32f103xb.h /^#define CAN_F5R1_FB25 /;" d +CAN_F5R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB26_Msk /;" d +CAN_F5R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB26_Pos /;" d +CAN_F5R1_FB26 target/stm32f103xb.h /^#define CAN_F5R1_FB26 /;" d +CAN_F5R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB27_Msk /;" d +CAN_F5R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB27_Pos /;" d +CAN_F5R1_FB27 target/stm32f103xb.h /^#define CAN_F5R1_FB27 /;" d +CAN_F5R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB28_Msk /;" d +CAN_F5R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB28_Pos /;" d +CAN_F5R1_FB28 target/stm32f103xb.h /^#define CAN_F5R1_FB28 /;" d +CAN_F5R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB29_Msk /;" d +CAN_F5R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB29_Pos /;" d +CAN_F5R1_FB29 target/stm32f103xb.h /^#define CAN_F5R1_FB29 /;" d +CAN_F5R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB2_Msk /;" d +CAN_F5R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB2_Pos /;" d +CAN_F5R1_FB2 target/stm32f103xb.h /^#define CAN_F5R1_FB2 /;" d +CAN_F5R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB30_Msk /;" d +CAN_F5R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB30_Pos /;" d +CAN_F5R1_FB30 target/stm32f103xb.h /^#define CAN_F5R1_FB30 /;" d +CAN_F5R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB31_Msk /;" d +CAN_F5R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB31_Pos /;" d +CAN_F5R1_FB31 target/stm32f103xb.h /^#define CAN_F5R1_FB31 /;" d +CAN_F5R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB3_Msk /;" d +CAN_F5R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB3_Pos /;" d +CAN_F5R1_FB3 target/stm32f103xb.h /^#define CAN_F5R1_FB3 /;" d +CAN_F5R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB4_Msk /;" d +CAN_F5R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB4_Pos /;" d +CAN_F5R1_FB4 target/stm32f103xb.h /^#define CAN_F5R1_FB4 /;" d +CAN_F5R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB5_Msk /;" d +CAN_F5R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB5_Pos /;" d +CAN_F5R1_FB5 target/stm32f103xb.h /^#define CAN_F5R1_FB5 /;" d +CAN_F5R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB6_Msk /;" d +CAN_F5R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB6_Pos /;" d +CAN_F5R1_FB6 target/stm32f103xb.h /^#define CAN_F5R1_FB6 /;" d +CAN_F5R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB7_Msk /;" d +CAN_F5R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB7_Pos /;" d +CAN_F5R1_FB7 target/stm32f103xb.h /^#define CAN_F5R1_FB7 /;" d +CAN_F5R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB8_Msk /;" d +CAN_F5R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB8_Pos /;" d +CAN_F5R1_FB8 target/stm32f103xb.h /^#define CAN_F5R1_FB8 /;" d +CAN_F5R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F5R1_FB9_Msk /;" d +CAN_F5R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F5R1_FB9_Pos /;" d +CAN_F5R1_FB9 target/stm32f103xb.h /^#define CAN_F5R1_FB9 /;" d +CAN_F5R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB0_Msk /;" d +CAN_F5R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB0_Pos /;" d +CAN_F5R2_FB0 target/stm32f103xb.h /^#define CAN_F5R2_FB0 /;" d +CAN_F5R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB10_Msk /;" d +CAN_F5R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB10_Pos /;" d +CAN_F5R2_FB10 target/stm32f103xb.h /^#define CAN_F5R2_FB10 /;" d +CAN_F5R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB11_Msk /;" d +CAN_F5R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB11_Pos /;" d +CAN_F5R2_FB11 target/stm32f103xb.h /^#define CAN_F5R2_FB11 /;" d +CAN_F5R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB12_Msk /;" d +CAN_F5R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB12_Pos /;" d +CAN_F5R2_FB12 target/stm32f103xb.h /^#define CAN_F5R2_FB12 /;" d +CAN_F5R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB13_Msk /;" d +CAN_F5R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB13_Pos /;" d +CAN_F5R2_FB13 target/stm32f103xb.h /^#define CAN_F5R2_FB13 /;" d +CAN_F5R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB14_Msk /;" d +CAN_F5R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB14_Pos /;" d +CAN_F5R2_FB14 target/stm32f103xb.h /^#define CAN_F5R2_FB14 /;" d +CAN_F5R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB15_Msk /;" d +CAN_F5R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB15_Pos /;" d +CAN_F5R2_FB15 target/stm32f103xb.h /^#define CAN_F5R2_FB15 /;" d +CAN_F5R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB16_Msk /;" d +CAN_F5R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB16_Pos /;" d +CAN_F5R2_FB16 target/stm32f103xb.h /^#define CAN_F5R2_FB16 /;" d +CAN_F5R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB17_Msk /;" d +CAN_F5R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB17_Pos /;" d +CAN_F5R2_FB17 target/stm32f103xb.h /^#define CAN_F5R2_FB17 /;" d +CAN_F5R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB18_Msk /;" d +CAN_F5R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB18_Pos /;" d +CAN_F5R2_FB18 target/stm32f103xb.h /^#define CAN_F5R2_FB18 /;" d +CAN_F5R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB19_Msk /;" d +CAN_F5R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB19_Pos /;" d +CAN_F5R2_FB19 target/stm32f103xb.h /^#define CAN_F5R2_FB19 /;" d +CAN_F5R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB1_Msk /;" d +CAN_F5R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB1_Pos /;" d +CAN_F5R2_FB1 target/stm32f103xb.h /^#define CAN_F5R2_FB1 /;" d +CAN_F5R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB20_Msk /;" d +CAN_F5R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB20_Pos /;" d +CAN_F5R2_FB20 target/stm32f103xb.h /^#define CAN_F5R2_FB20 /;" d +CAN_F5R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB21_Msk /;" d +CAN_F5R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB21_Pos /;" d +CAN_F5R2_FB21 target/stm32f103xb.h /^#define CAN_F5R2_FB21 /;" d +CAN_F5R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB22_Msk /;" d +CAN_F5R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB22_Pos /;" d +CAN_F5R2_FB22 target/stm32f103xb.h /^#define CAN_F5R2_FB22 /;" d +CAN_F5R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB23_Msk /;" d +CAN_F5R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB23_Pos /;" d +CAN_F5R2_FB23 target/stm32f103xb.h /^#define CAN_F5R2_FB23 /;" d +CAN_F5R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB24_Msk /;" d +CAN_F5R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB24_Pos /;" d +CAN_F5R2_FB24 target/stm32f103xb.h /^#define CAN_F5R2_FB24 /;" d +CAN_F5R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB25_Msk /;" d +CAN_F5R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB25_Pos /;" d +CAN_F5R2_FB25 target/stm32f103xb.h /^#define CAN_F5R2_FB25 /;" d +CAN_F5R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB26_Msk /;" d +CAN_F5R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB26_Pos /;" d +CAN_F5R2_FB26 target/stm32f103xb.h /^#define CAN_F5R2_FB26 /;" d +CAN_F5R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB27_Msk /;" d +CAN_F5R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB27_Pos /;" d +CAN_F5R2_FB27 target/stm32f103xb.h /^#define CAN_F5R2_FB27 /;" d +CAN_F5R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB28_Msk /;" d +CAN_F5R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB28_Pos /;" d +CAN_F5R2_FB28 target/stm32f103xb.h /^#define CAN_F5R2_FB28 /;" d +CAN_F5R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB29_Msk /;" d +CAN_F5R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB29_Pos /;" d +CAN_F5R2_FB29 target/stm32f103xb.h /^#define CAN_F5R2_FB29 /;" d +CAN_F5R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB2_Msk /;" d +CAN_F5R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB2_Pos /;" d +CAN_F5R2_FB2 target/stm32f103xb.h /^#define CAN_F5R2_FB2 /;" d +CAN_F5R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB30_Msk /;" d +CAN_F5R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB30_Pos /;" d +CAN_F5R2_FB30 target/stm32f103xb.h /^#define CAN_F5R2_FB30 /;" d +CAN_F5R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB31_Msk /;" d +CAN_F5R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB31_Pos /;" d +CAN_F5R2_FB31 target/stm32f103xb.h /^#define CAN_F5R2_FB31 /;" d +CAN_F5R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB3_Msk /;" d +CAN_F5R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB3_Pos /;" d +CAN_F5R2_FB3 target/stm32f103xb.h /^#define CAN_F5R2_FB3 /;" d +CAN_F5R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB4_Msk /;" d +CAN_F5R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB4_Pos /;" d +CAN_F5R2_FB4 target/stm32f103xb.h /^#define CAN_F5R2_FB4 /;" d +CAN_F5R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB5_Msk /;" d +CAN_F5R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB5_Pos /;" d +CAN_F5R2_FB5 target/stm32f103xb.h /^#define CAN_F5R2_FB5 /;" d +CAN_F5R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB6_Msk /;" d +CAN_F5R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB6_Pos /;" d +CAN_F5R2_FB6 target/stm32f103xb.h /^#define CAN_F5R2_FB6 /;" d +CAN_F5R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB7_Msk /;" d +CAN_F5R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB7_Pos /;" d +CAN_F5R2_FB7 target/stm32f103xb.h /^#define CAN_F5R2_FB7 /;" d +CAN_F5R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB8_Msk /;" d +CAN_F5R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB8_Pos /;" d +CAN_F5R2_FB8 target/stm32f103xb.h /^#define CAN_F5R2_FB8 /;" d +CAN_F5R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F5R2_FB9_Msk /;" d +CAN_F5R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F5R2_FB9_Pos /;" d +CAN_F5R2_FB9 target/stm32f103xb.h /^#define CAN_F5R2_FB9 /;" d +CAN_F6R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB0_Msk /;" d +CAN_F6R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB0_Pos /;" d +CAN_F6R1_FB0 target/stm32f103xb.h /^#define CAN_F6R1_FB0 /;" d +CAN_F6R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB10_Msk /;" d +CAN_F6R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB10_Pos /;" d +CAN_F6R1_FB10 target/stm32f103xb.h /^#define CAN_F6R1_FB10 /;" d +CAN_F6R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB11_Msk /;" d +CAN_F6R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB11_Pos /;" d +CAN_F6R1_FB11 target/stm32f103xb.h /^#define CAN_F6R1_FB11 /;" d +CAN_F6R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB12_Msk /;" d +CAN_F6R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB12_Pos /;" d +CAN_F6R1_FB12 target/stm32f103xb.h /^#define CAN_F6R1_FB12 /;" d +CAN_F6R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB13_Msk /;" d +CAN_F6R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB13_Pos /;" d +CAN_F6R1_FB13 target/stm32f103xb.h /^#define CAN_F6R1_FB13 /;" d +CAN_F6R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB14_Msk /;" d +CAN_F6R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB14_Pos /;" d +CAN_F6R1_FB14 target/stm32f103xb.h /^#define CAN_F6R1_FB14 /;" d +CAN_F6R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB15_Msk /;" d +CAN_F6R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB15_Pos /;" d +CAN_F6R1_FB15 target/stm32f103xb.h /^#define CAN_F6R1_FB15 /;" d +CAN_F6R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB16_Msk /;" d +CAN_F6R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB16_Pos /;" d +CAN_F6R1_FB16 target/stm32f103xb.h /^#define CAN_F6R1_FB16 /;" d +CAN_F6R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB17_Msk /;" d +CAN_F6R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB17_Pos /;" d +CAN_F6R1_FB17 target/stm32f103xb.h /^#define CAN_F6R1_FB17 /;" d +CAN_F6R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB18_Msk /;" d +CAN_F6R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB18_Pos /;" d +CAN_F6R1_FB18 target/stm32f103xb.h /^#define CAN_F6R1_FB18 /;" d +CAN_F6R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB19_Msk /;" d +CAN_F6R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB19_Pos /;" d +CAN_F6R1_FB19 target/stm32f103xb.h /^#define CAN_F6R1_FB19 /;" d +CAN_F6R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB1_Msk /;" d +CAN_F6R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB1_Pos /;" d +CAN_F6R1_FB1 target/stm32f103xb.h /^#define CAN_F6R1_FB1 /;" d +CAN_F6R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB20_Msk /;" d +CAN_F6R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB20_Pos /;" d +CAN_F6R1_FB20 target/stm32f103xb.h /^#define CAN_F6R1_FB20 /;" d +CAN_F6R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB21_Msk /;" d +CAN_F6R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB21_Pos /;" d +CAN_F6R1_FB21 target/stm32f103xb.h /^#define CAN_F6R1_FB21 /;" d +CAN_F6R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB22_Msk /;" d +CAN_F6R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB22_Pos /;" d +CAN_F6R1_FB22 target/stm32f103xb.h /^#define CAN_F6R1_FB22 /;" d +CAN_F6R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB23_Msk /;" d +CAN_F6R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB23_Pos /;" d +CAN_F6R1_FB23 target/stm32f103xb.h /^#define CAN_F6R1_FB23 /;" d +CAN_F6R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB24_Msk /;" d +CAN_F6R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB24_Pos /;" d +CAN_F6R1_FB24 target/stm32f103xb.h /^#define CAN_F6R1_FB24 /;" d +CAN_F6R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB25_Msk /;" d +CAN_F6R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB25_Pos /;" d +CAN_F6R1_FB25 target/stm32f103xb.h /^#define CAN_F6R1_FB25 /;" d +CAN_F6R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB26_Msk /;" d +CAN_F6R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB26_Pos /;" d +CAN_F6R1_FB26 target/stm32f103xb.h /^#define CAN_F6R1_FB26 /;" d +CAN_F6R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB27_Msk /;" d +CAN_F6R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB27_Pos /;" d +CAN_F6R1_FB27 target/stm32f103xb.h /^#define CAN_F6R1_FB27 /;" d +CAN_F6R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB28_Msk /;" d +CAN_F6R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB28_Pos /;" d +CAN_F6R1_FB28 target/stm32f103xb.h /^#define CAN_F6R1_FB28 /;" d +CAN_F6R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB29_Msk /;" d +CAN_F6R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB29_Pos /;" d +CAN_F6R1_FB29 target/stm32f103xb.h /^#define CAN_F6R1_FB29 /;" d +CAN_F6R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB2_Msk /;" d +CAN_F6R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB2_Pos /;" d +CAN_F6R1_FB2 target/stm32f103xb.h /^#define CAN_F6R1_FB2 /;" d +CAN_F6R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB30_Msk /;" d +CAN_F6R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB30_Pos /;" d +CAN_F6R1_FB30 target/stm32f103xb.h /^#define CAN_F6R1_FB30 /;" d +CAN_F6R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB31_Msk /;" d +CAN_F6R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB31_Pos /;" d +CAN_F6R1_FB31 target/stm32f103xb.h /^#define CAN_F6R1_FB31 /;" d +CAN_F6R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB3_Msk /;" d +CAN_F6R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB3_Pos /;" d +CAN_F6R1_FB3 target/stm32f103xb.h /^#define CAN_F6R1_FB3 /;" d +CAN_F6R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB4_Msk /;" d +CAN_F6R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB4_Pos /;" d +CAN_F6R1_FB4 target/stm32f103xb.h /^#define CAN_F6R1_FB4 /;" d +CAN_F6R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB5_Msk /;" d +CAN_F6R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB5_Pos /;" d +CAN_F6R1_FB5 target/stm32f103xb.h /^#define CAN_F6R1_FB5 /;" d +CAN_F6R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB6_Msk /;" d +CAN_F6R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB6_Pos /;" d +CAN_F6R1_FB6 target/stm32f103xb.h /^#define CAN_F6R1_FB6 /;" d +CAN_F6R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB7_Msk /;" d +CAN_F6R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB7_Pos /;" d +CAN_F6R1_FB7 target/stm32f103xb.h /^#define CAN_F6R1_FB7 /;" d +CAN_F6R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB8_Msk /;" d +CAN_F6R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB8_Pos /;" d +CAN_F6R1_FB8 target/stm32f103xb.h /^#define CAN_F6R1_FB8 /;" d +CAN_F6R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F6R1_FB9_Msk /;" d +CAN_F6R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F6R1_FB9_Pos /;" d +CAN_F6R1_FB9 target/stm32f103xb.h /^#define CAN_F6R1_FB9 /;" d +CAN_F6R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB0_Msk /;" d +CAN_F6R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB0_Pos /;" d +CAN_F6R2_FB0 target/stm32f103xb.h /^#define CAN_F6R2_FB0 /;" d +CAN_F6R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB10_Msk /;" d +CAN_F6R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB10_Pos /;" d +CAN_F6R2_FB10 target/stm32f103xb.h /^#define CAN_F6R2_FB10 /;" d +CAN_F6R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB11_Msk /;" d +CAN_F6R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB11_Pos /;" d +CAN_F6R2_FB11 target/stm32f103xb.h /^#define CAN_F6R2_FB11 /;" d +CAN_F6R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB12_Msk /;" d +CAN_F6R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB12_Pos /;" d +CAN_F6R2_FB12 target/stm32f103xb.h /^#define CAN_F6R2_FB12 /;" d +CAN_F6R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB13_Msk /;" d +CAN_F6R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB13_Pos /;" d +CAN_F6R2_FB13 target/stm32f103xb.h /^#define CAN_F6R2_FB13 /;" d +CAN_F6R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB14_Msk /;" d +CAN_F6R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB14_Pos /;" d +CAN_F6R2_FB14 target/stm32f103xb.h /^#define CAN_F6R2_FB14 /;" d +CAN_F6R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB15_Msk /;" d +CAN_F6R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB15_Pos /;" d +CAN_F6R2_FB15 target/stm32f103xb.h /^#define CAN_F6R2_FB15 /;" d +CAN_F6R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB16_Msk /;" d +CAN_F6R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB16_Pos /;" d +CAN_F6R2_FB16 target/stm32f103xb.h /^#define CAN_F6R2_FB16 /;" d +CAN_F6R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB17_Msk /;" d +CAN_F6R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB17_Pos /;" d +CAN_F6R2_FB17 target/stm32f103xb.h /^#define CAN_F6R2_FB17 /;" d +CAN_F6R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB18_Msk /;" d +CAN_F6R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB18_Pos /;" d +CAN_F6R2_FB18 target/stm32f103xb.h /^#define CAN_F6R2_FB18 /;" d +CAN_F6R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB19_Msk /;" d +CAN_F6R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB19_Pos /;" d +CAN_F6R2_FB19 target/stm32f103xb.h /^#define CAN_F6R2_FB19 /;" d +CAN_F6R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB1_Msk /;" d +CAN_F6R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB1_Pos /;" d +CAN_F6R2_FB1 target/stm32f103xb.h /^#define CAN_F6R2_FB1 /;" d +CAN_F6R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB20_Msk /;" d +CAN_F6R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB20_Pos /;" d +CAN_F6R2_FB20 target/stm32f103xb.h /^#define CAN_F6R2_FB20 /;" d +CAN_F6R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB21_Msk /;" d +CAN_F6R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB21_Pos /;" d +CAN_F6R2_FB21 target/stm32f103xb.h /^#define CAN_F6R2_FB21 /;" d +CAN_F6R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB22_Msk /;" d +CAN_F6R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB22_Pos /;" d +CAN_F6R2_FB22 target/stm32f103xb.h /^#define CAN_F6R2_FB22 /;" d +CAN_F6R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB23_Msk /;" d +CAN_F6R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB23_Pos /;" d +CAN_F6R2_FB23 target/stm32f103xb.h /^#define CAN_F6R2_FB23 /;" d +CAN_F6R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB24_Msk /;" d +CAN_F6R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB24_Pos /;" d +CAN_F6R2_FB24 target/stm32f103xb.h /^#define CAN_F6R2_FB24 /;" d +CAN_F6R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB25_Msk /;" d +CAN_F6R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB25_Pos /;" d +CAN_F6R2_FB25 target/stm32f103xb.h /^#define CAN_F6R2_FB25 /;" d +CAN_F6R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB26_Msk /;" d +CAN_F6R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB26_Pos /;" d +CAN_F6R2_FB26 target/stm32f103xb.h /^#define CAN_F6R2_FB26 /;" d +CAN_F6R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB27_Msk /;" d +CAN_F6R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB27_Pos /;" d +CAN_F6R2_FB27 target/stm32f103xb.h /^#define CAN_F6R2_FB27 /;" d +CAN_F6R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB28_Msk /;" d +CAN_F6R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB28_Pos /;" d +CAN_F6R2_FB28 target/stm32f103xb.h /^#define CAN_F6R2_FB28 /;" d +CAN_F6R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB29_Msk /;" d +CAN_F6R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB29_Pos /;" d +CAN_F6R2_FB29 target/stm32f103xb.h /^#define CAN_F6R2_FB29 /;" d +CAN_F6R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB2_Msk /;" d +CAN_F6R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB2_Pos /;" d +CAN_F6R2_FB2 target/stm32f103xb.h /^#define CAN_F6R2_FB2 /;" d +CAN_F6R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB30_Msk /;" d +CAN_F6R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB30_Pos /;" d +CAN_F6R2_FB30 target/stm32f103xb.h /^#define CAN_F6R2_FB30 /;" d +CAN_F6R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB31_Msk /;" d +CAN_F6R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB31_Pos /;" d +CAN_F6R2_FB31 target/stm32f103xb.h /^#define CAN_F6R2_FB31 /;" d +CAN_F6R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB3_Msk /;" d +CAN_F6R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB3_Pos /;" d +CAN_F6R2_FB3 target/stm32f103xb.h /^#define CAN_F6R2_FB3 /;" d +CAN_F6R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB4_Msk /;" d +CAN_F6R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB4_Pos /;" d +CAN_F6R2_FB4 target/stm32f103xb.h /^#define CAN_F6R2_FB4 /;" d +CAN_F6R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB5_Msk /;" d +CAN_F6R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB5_Pos /;" d +CAN_F6R2_FB5 target/stm32f103xb.h /^#define CAN_F6R2_FB5 /;" d +CAN_F6R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB6_Msk /;" d +CAN_F6R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB6_Pos /;" d +CAN_F6R2_FB6 target/stm32f103xb.h /^#define CAN_F6R2_FB6 /;" d +CAN_F6R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB7_Msk /;" d +CAN_F6R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB7_Pos /;" d +CAN_F6R2_FB7 target/stm32f103xb.h /^#define CAN_F6R2_FB7 /;" d +CAN_F6R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB8_Msk /;" d +CAN_F6R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB8_Pos /;" d +CAN_F6R2_FB8 target/stm32f103xb.h /^#define CAN_F6R2_FB8 /;" d +CAN_F6R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F6R2_FB9_Msk /;" d +CAN_F6R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F6R2_FB9_Pos /;" d +CAN_F6R2_FB9 target/stm32f103xb.h /^#define CAN_F6R2_FB9 /;" d +CAN_F7R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB0_Msk /;" d +CAN_F7R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB0_Pos /;" d +CAN_F7R1_FB0 target/stm32f103xb.h /^#define CAN_F7R1_FB0 /;" d +CAN_F7R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB10_Msk /;" d +CAN_F7R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB10_Pos /;" d +CAN_F7R1_FB10 target/stm32f103xb.h /^#define CAN_F7R1_FB10 /;" d +CAN_F7R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB11_Msk /;" d +CAN_F7R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB11_Pos /;" d +CAN_F7R1_FB11 target/stm32f103xb.h /^#define CAN_F7R1_FB11 /;" d +CAN_F7R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB12_Msk /;" d +CAN_F7R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB12_Pos /;" d +CAN_F7R1_FB12 target/stm32f103xb.h /^#define CAN_F7R1_FB12 /;" d +CAN_F7R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB13_Msk /;" d +CAN_F7R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB13_Pos /;" d +CAN_F7R1_FB13 target/stm32f103xb.h /^#define CAN_F7R1_FB13 /;" d +CAN_F7R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB14_Msk /;" d +CAN_F7R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB14_Pos /;" d +CAN_F7R1_FB14 target/stm32f103xb.h /^#define CAN_F7R1_FB14 /;" d +CAN_F7R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB15_Msk /;" d +CAN_F7R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB15_Pos /;" d +CAN_F7R1_FB15 target/stm32f103xb.h /^#define CAN_F7R1_FB15 /;" d +CAN_F7R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB16_Msk /;" d +CAN_F7R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB16_Pos /;" d +CAN_F7R1_FB16 target/stm32f103xb.h /^#define CAN_F7R1_FB16 /;" d +CAN_F7R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB17_Msk /;" d +CAN_F7R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB17_Pos /;" d +CAN_F7R1_FB17 target/stm32f103xb.h /^#define CAN_F7R1_FB17 /;" d +CAN_F7R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB18_Msk /;" d +CAN_F7R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB18_Pos /;" d +CAN_F7R1_FB18 target/stm32f103xb.h /^#define CAN_F7R1_FB18 /;" d +CAN_F7R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB19_Msk /;" d +CAN_F7R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB19_Pos /;" d +CAN_F7R1_FB19 target/stm32f103xb.h /^#define CAN_F7R1_FB19 /;" d +CAN_F7R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB1_Msk /;" d +CAN_F7R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB1_Pos /;" d +CAN_F7R1_FB1 target/stm32f103xb.h /^#define CAN_F7R1_FB1 /;" d +CAN_F7R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB20_Msk /;" d +CAN_F7R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB20_Pos /;" d +CAN_F7R1_FB20 target/stm32f103xb.h /^#define CAN_F7R1_FB20 /;" d +CAN_F7R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB21_Msk /;" d +CAN_F7R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB21_Pos /;" d +CAN_F7R1_FB21 target/stm32f103xb.h /^#define CAN_F7R1_FB21 /;" d +CAN_F7R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB22_Msk /;" d +CAN_F7R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB22_Pos /;" d +CAN_F7R1_FB22 target/stm32f103xb.h /^#define CAN_F7R1_FB22 /;" d +CAN_F7R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB23_Msk /;" d +CAN_F7R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB23_Pos /;" d +CAN_F7R1_FB23 target/stm32f103xb.h /^#define CAN_F7R1_FB23 /;" d +CAN_F7R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB24_Msk /;" d +CAN_F7R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB24_Pos /;" d +CAN_F7R1_FB24 target/stm32f103xb.h /^#define CAN_F7R1_FB24 /;" d +CAN_F7R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB25_Msk /;" d +CAN_F7R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB25_Pos /;" d +CAN_F7R1_FB25 target/stm32f103xb.h /^#define CAN_F7R1_FB25 /;" d +CAN_F7R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB26_Msk /;" d +CAN_F7R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB26_Pos /;" d +CAN_F7R1_FB26 target/stm32f103xb.h /^#define CAN_F7R1_FB26 /;" d +CAN_F7R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB27_Msk /;" d +CAN_F7R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB27_Pos /;" d +CAN_F7R1_FB27 target/stm32f103xb.h /^#define CAN_F7R1_FB27 /;" d +CAN_F7R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB28_Msk /;" d +CAN_F7R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB28_Pos /;" d +CAN_F7R1_FB28 target/stm32f103xb.h /^#define CAN_F7R1_FB28 /;" d +CAN_F7R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB29_Msk /;" d +CAN_F7R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB29_Pos /;" d +CAN_F7R1_FB29 target/stm32f103xb.h /^#define CAN_F7R1_FB29 /;" d +CAN_F7R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB2_Msk /;" d +CAN_F7R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB2_Pos /;" d +CAN_F7R1_FB2 target/stm32f103xb.h /^#define CAN_F7R1_FB2 /;" d +CAN_F7R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB30_Msk /;" d +CAN_F7R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB30_Pos /;" d +CAN_F7R1_FB30 target/stm32f103xb.h /^#define CAN_F7R1_FB30 /;" d +CAN_F7R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB31_Msk /;" d +CAN_F7R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB31_Pos /;" d +CAN_F7R1_FB31 target/stm32f103xb.h /^#define CAN_F7R1_FB31 /;" d +CAN_F7R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB3_Msk /;" d +CAN_F7R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB3_Pos /;" d +CAN_F7R1_FB3 target/stm32f103xb.h /^#define CAN_F7R1_FB3 /;" d +CAN_F7R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB4_Msk /;" d +CAN_F7R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB4_Pos /;" d +CAN_F7R1_FB4 target/stm32f103xb.h /^#define CAN_F7R1_FB4 /;" d +CAN_F7R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB5_Msk /;" d +CAN_F7R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB5_Pos /;" d +CAN_F7R1_FB5 target/stm32f103xb.h /^#define CAN_F7R1_FB5 /;" d +CAN_F7R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB6_Msk /;" d +CAN_F7R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB6_Pos /;" d +CAN_F7R1_FB6 target/stm32f103xb.h /^#define CAN_F7R1_FB6 /;" d +CAN_F7R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB7_Msk /;" d +CAN_F7R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB7_Pos /;" d +CAN_F7R1_FB7 target/stm32f103xb.h /^#define CAN_F7R1_FB7 /;" d +CAN_F7R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB8_Msk /;" d +CAN_F7R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB8_Pos /;" d +CAN_F7R1_FB8 target/stm32f103xb.h /^#define CAN_F7R1_FB8 /;" d +CAN_F7R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F7R1_FB9_Msk /;" d +CAN_F7R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F7R1_FB9_Pos /;" d +CAN_F7R1_FB9 target/stm32f103xb.h /^#define CAN_F7R1_FB9 /;" d +CAN_F7R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB0_Msk /;" d +CAN_F7R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB0_Pos /;" d +CAN_F7R2_FB0 target/stm32f103xb.h /^#define CAN_F7R2_FB0 /;" d +CAN_F7R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB10_Msk /;" d +CAN_F7R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB10_Pos /;" d +CAN_F7R2_FB10 target/stm32f103xb.h /^#define CAN_F7R2_FB10 /;" d +CAN_F7R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB11_Msk /;" d +CAN_F7R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB11_Pos /;" d +CAN_F7R2_FB11 target/stm32f103xb.h /^#define CAN_F7R2_FB11 /;" d +CAN_F7R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB12_Msk /;" d +CAN_F7R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB12_Pos /;" d +CAN_F7R2_FB12 target/stm32f103xb.h /^#define CAN_F7R2_FB12 /;" d +CAN_F7R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB13_Msk /;" d +CAN_F7R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB13_Pos /;" d +CAN_F7R2_FB13 target/stm32f103xb.h /^#define CAN_F7R2_FB13 /;" d +CAN_F7R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB14_Msk /;" d +CAN_F7R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB14_Pos /;" d +CAN_F7R2_FB14 target/stm32f103xb.h /^#define CAN_F7R2_FB14 /;" d +CAN_F7R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB15_Msk /;" d +CAN_F7R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB15_Pos /;" d +CAN_F7R2_FB15 target/stm32f103xb.h /^#define CAN_F7R2_FB15 /;" d +CAN_F7R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB16_Msk /;" d +CAN_F7R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB16_Pos /;" d +CAN_F7R2_FB16 target/stm32f103xb.h /^#define CAN_F7R2_FB16 /;" d +CAN_F7R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB17_Msk /;" d +CAN_F7R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB17_Pos /;" d +CAN_F7R2_FB17 target/stm32f103xb.h /^#define CAN_F7R2_FB17 /;" d +CAN_F7R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB18_Msk /;" d +CAN_F7R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB18_Pos /;" d +CAN_F7R2_FB18 target/stm32f103xb.h /^#define CAN_F7R2_FB18 /;" d +CAN_F7R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB19_Msk /;" d +CAN_F7R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB19_Pos /;" d +CAN_F7R2_FB19 target/stm32f103xb.h /^#define CAN_F7R2_FB19 /;" d +CAN_F7R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB1_Msk /;" d +CAN_F7R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB1_Pos /;" d +CAN_F7R2_FB1 target/stm32f103xb.h /^#define CAN_F7R2_FB1 /;" d +CAN_F7R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB20_Msk /;" d +CAN_F7R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB20_Pos /;" d +CAN_F7R2_FB20 target/stm32f103xb.h /^#define CAN_F7R2_FB20 /;" d +CAN_F7R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB21_Msk /;" d +CAN_F7R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB21_Pos /;" d +CAN_F7R2_FB21 target/stm32f103xb.h /^#define CAN_F7R2_FB21 /;" d +CAN_F7R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB22_Msk /;" d +CAN_F7R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB22_Pos /;" d +CAN_F7R2_FB22 target/stm32f103xb.h /^#define CAN_F7R2_FB22 /;" d +CAN_F7R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB23_Msk /;" d +CAN_F7R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB23_Pos /;" d +CAN_F7R2_FB23 target/stm32f103xb.h /^#define CAN_F7R2_FB23 /;" d +CAN_F7R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB24_Msk /;" d +CAN_F7R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB24_Pos /;" d +CAN_F7R2_FB24 target/stm32f103xb.h /^#define CAN_F7R2_FB24 /;" d +CAN_F7R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB25_Msk /;" d +CAN_F7R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB25_Pos /;" d +CAN_F7R2_FB25 target/stm32f103xb.h /^#define CAN_F7R2_FB25 /;" d +CAN_F7R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB26_Msk /;" d +CAN_F7R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB26_Pos /;" d +CAN_F7R2_FB26 target/stm32f103xb.h /^#define CAN_F7R2_FB26 /;" d +CAN_F7R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB27_Msk /;" d +CAN_F7R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB27_Pos /;" d +CAN_F7R2_FB27 target/stm32f103xb.h /^#define CAN_F7R2_FB27 /;" d +CAN_F7R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB28_Msk /;" d +CAN_F7R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB28_Pos /;" d +CAN_F7R2_FB28 target/stm32f103xb.h /^#define CAN_F7R2_FB28 /;" d +CAN_F7R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB29_Msk /;" d +CAN_F7R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB29_Pos /;" d +CAN_F7R2_FB29 target/stm32f103xb.h /^#define CAN_F7R2_FB29 /;" d +CAN_F7R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB2_Msk /;" d +CAN_F7R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB2_Pos /;" d +CAN_F7R2_FB2 target/stm32f103xb.h /^#define CAN_F7R2_FB2 /;" d +CAN_F7R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB30_Msk /;" d +CAN_F7R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB30_Pos /;" d +CAN_F7R2_FB30 target/stm32f103xb.h /^#define CAN_F7R2_FB30 /;" d +CAN_F7R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB31_Msk /;" d +CAN_F7R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB31_Pos /;" d +CAN_F7R2_FB31 target/stm32f103xb.h /^#define CAN_F7R2_FB31 /;" d +CAN_F7R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB3_Msk /;" d +CAN_F7R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB3_Pos /;" d +CAN_F7R2_FB3 target/stm32f103xb.h /^#define CAN_F7R2_FB3 /;" d +CAN_F7R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB4_Msk /;" d +CAN_F7R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB4_Pos /;" d +CAN_F7R2_FB4 target/stm32f103xb.h /^#define CAN_F7R2_FB4 /;" d +CAN_F7R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB5_Msk /;" d +CAN_F7R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB5_Pos /;" d +CAN_F7R2_FB5 target/stm32f103xb.h /^#define CAN_F7R2_FB5 /;" d +CAN_F7R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB6_Msk /;" d +CAN_F7R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB6_Pos /;" d +CAN_F7R2_FB6 target/stm32f103xb.h /^#define CAN_F7R2_FB6 /;" d +CAN_F7R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB7_Msk /;" d +CAN_F7R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB7_Pos /;" d +CAN_F7R2_FB7 target/stm32f103xb.h /^#define CAN_F7R2_FB7 /;" d +CAN_F7R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB8_Msk /;" d +CAN_F7R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB8_Pos /;" d +CAN_F7R2_FB8 target/stm32f103xb.h /^#define CAN_F7R2_FB8 /;" d +CAN_F7R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F7R2_FB9_Msk /;" d +CAN_F7R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F7R2_FB9_Pos /;" d +CAN_F7R2_FB9 target/stm32f103xb.h /^#define CAN_F7R2_FB9 /;" d +CAN_F8R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB0_Msk /;" d +CAN_F8R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB0_Pos /;" d +CAN_F8R1_FB0 target/stm32f103xb.h /^#define CAN_F8R1_FB0 /;" d +CAN_F8R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB10_Msk /;" d +CAN_F8R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB10_Pos /;" d +CAN_F8R1_FB10 target/stm32f103xb.h /^#define CAN_F8R1_FB10 /;" d +CAN_F8R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB11_Msk /;" d +CAN_F8R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB11_Pos /;" d +CAN_F8R1_FB11 target/stm32f103xb.h /^#define CAN_F8R1_FB11 /;" d +CAN_F8R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB12_Msk /;" d +CAN_F8R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB12_Pos /;" d +CAN_F8R1_FB12 target/stm32f103xb.h /^#define CAN_F8R1_FB12 /;" d +CAN_F8R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB13_Msk /;" d +CAN_F8R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB13_Pos /;" d +CAN_F8R1_FB13 target/stm32f103xb.h /^#define CAN_F8R1_FB13 /;" d +CAN_F8R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB14_Msk /;" d +CAN_F8R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB14_Pos /;" d +CAN_F8R1_FB14 target/stm32f103xb.h /^#define CAN_F8R1_FB14 /;" d +CAN_F8R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB15_Msk /;" d +CAN_F8R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB15_Pos /;" d +CAN_F8R1_FB15 target/stm32f103xb.h /^#define CAN_F8R1_FB15 /;" d +CAN_F8R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB16_Msk /;" d +CAN_F8R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB16_Pos /;" d +CAN_F8R1_FB16 target/stm32f103xb.h /^#define CAN_F8R1_FB16 /;" d +CAN_F8R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB17_Msk /;" d +CAN_F8R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB17_Pos /;" d +CAN_F8R1_FB17 target/stm32f103xb.h /^#define CAN_F8R1_FB17 /;" d +CAN_F8R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB18_Msk /;" d +CAN_F8R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB18_Pos /;" d +CAN_F8R1_FB18 target/stm32f103xb.h /^#define CAN_F8R1_FB18 /;" d +CAN_F8R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB19_Msk /;" d +CAN_F8R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB19_Pos /;" d +CAN_F8R1_FB19 target/stm32f103xb.h /^#define CAN_F8R1_FB19 /;" d +CAN_F8R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB1_Msk /;" d +CAN_F8R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB1_Pos /;" d +CAN_F8R1_FB1 target/stm32f103xb.h /^#define CAN_F8R1_FB1 /;" d +CAN_F8R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB20_Msk /;" d +CAN_F8R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB20_Pos /;" d +CAN_F8R1_FB20 target/stm32f103xb.h /^#define CAN_F8R1_FB20 /;" d +CAN_F8R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB21_Msk /;" d +CAN_F8R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB21_Pos /;" d +CAN_F8R1_FB21 target/stm32f103xb.h /^#define CAN_F8R1_FB21 /;" d +CAN_F8R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB22_Msk /;" d +CAN_F8R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB22_Pos /;" d +CAN_F8R1_FB22 target/stm32f103xb.h /^#define CAN_F8R1_FB22 /;" d +CAN_F8R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB23_Msk /;" d +CAN_F8R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB23_Pos /;" d +CAN_F8R1_FB23 target/stm32f103xb.h /^#define CAN_F8R1_FB23 /;" d +CAN_F8R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB24_Msk /;" d +CAN_F8R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB24_Pos /;" d +CAN_F8R1_FB24 target/stm32f103xb.h /^#define CAN_F8R1_FB24 /;" d +CAN_F8R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB25_Msk /;" d +CAN_F8R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB25_Pos /;" d +CAN_F8R1_FB25 target/stm32f103xb.h /^#define CAN_F8R1_FB25 /;" d +CAN_F8R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB26_Msk /;" d +CAN_F8R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB26_Pos /;" d +CAN_F8R1_FB26 target/stm32f103xb.h /^#define CAN_F8R1_FB26 /;" d +CAN_F8R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB27_Msk /;" d +CAN_F8R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB27_Pos /;" d +CAN_F8R1_FB27 target/stm32f103xb.h /^#define CAN_F8R1_FB27 /;" d +CAN_F8R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB28_Msk /;" d +CAN_F8R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB28_Pos /;" d +CAN_F8R1_FB28 target/stm32f103xb.h /^#define CAN_F8R1_FB28 /;" d +CAN_F8R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB29_Msk /;" d +CAN_F8R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB29_Pos /;" d +CAN_F8R1_FB29 target/stm32f103xb.h /^#define CAN_F8R1_FB29 /;" d +CAN_F8R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB2_Msk /;" d +CAN_F8R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB2_Pos /;" d +CAN_F8R1_FB2 target/stm32f103xb.h /^#define CAN_F8R1_FB2 /;" d +CAN_F8R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB30_Msk /;" d +CAN_F8R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB30_Pos /;" d +CAN_F8R1_FB30 target/stm32f103xb.h /^#define CAN_F8R1_FB30 /;" d +CAN_F8R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB31_Msk /;" d +CAN_F8R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB31_Pos /;" d +CAN_F8R1_FB31 target/stm32f103xb.h /^#define CAN_F8R1_FB31 /;" d +CAN_F8R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB3_Msk /;" d +CAN_F8R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB3_Pos /;" d +CAN_F8R1_FB3 target/stm32f103xb.h /^#define CAN_F8R1_FB3 /;" d +CAN_F8R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB4_Msk /;" d +CAN_F8R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB4_Pos /;" d +CAN_F8R1_FB4 target/stm32f103xb.h /^#define CAN_F8R1_FB4 /;" d +CAN_F8R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB5_Msk /;" d +CAN_F8R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB5_Pos /;" d +CAN_F8R1_FB5 target/stm32f103xb.h /^#define CAN_F8R1_FB5 /;" d +CAN_F8R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB6_Msk /;" d +CAN_F8R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB6_Pos /;" d +CAN_F8R1_FB6 target/stm32f103xb.h /^#define CAN_F8R1_FB6 /;" d +CAN_F8R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB7_Msk /;" d +CAN_F8R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB7_Pos /;" d +CAN_F8R1_FB7 target/stm32f103xb.h /^#define CAN_F8R1_FB7 /;" d +CAN_F8R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB8_Msk /;" d +CAN_F8R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB8_Pos /;" d +CAN_F8R1_FB8 target/stm32f103xb.h /^#define CAN_F8R1_FB8 /;" d +CAN_F8R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F8R1_FB9_Msk /;" d +CAN_F8R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F8R1_FB9_Pos /;" d +CAN_F8R1_FB9 target/stm32f103xb.h /^#define CAN_F8R1_FB9 /;" d +CAN_F8R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB0_Msk /;" d +CAN_F8R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB0_Pos /;" d +CAN_F8R2_FB0 target/stm32f103xb.h /^#define CAN_F8R2_FB0 /;" d +CAN_F8R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB10_Msk /;" d +CAN_F8R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB10_Pos /;" d +CAN_F8R2_FB10 target/stm32f103xb.h /^#define CAN_F8R2_FB10 /;" d +CAN_F8R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB11_Msk /;" d +CAN_F8R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB11_Pos /;" d +CAN_F8R2_FB11 target/stm32f103xb.h /^#define CAN_F8R2_FB11 /;" d +CAN_F8R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB12_Msk /;" d +CAN_F8R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB12_Pos /;" d +CAN_F8R2_FB12 target/stm32f103xb.h /^#define CAN_F8R2_FB12 /;" d +CAN_F8R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB13_Msk /;" d +CAN_F8R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB13_Pos /;" d +CAN_F8R2_FB13 target/stm32f103xb.h /^#define CAN_F8R2_FB13 /;" d +CAN_F8R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB14_Msk /;" d +CAN_F8R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB14_Pos /;" d +CAN_F8R2_FB14 target/stm32f103xb.h /^#define CAN_F8R2_FB14 /;" d +CAN_F8R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB15_Msk /;" d +CAN_F8R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB15_Pos /;" d +CAN_F8R2_FB15 target/stm32f103xb.h /^#define CAN_F8R2_FB15 /;" d +CAN_F8R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB16_Msk /;" d +CAN_F8R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB16_Pos /;" d +CAN_F8R2_FB16 target/stm32f103xb.h /^#define CAN_F8R2_FB16 /;" d +CAN_F8R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB17_Msk /;" d +CAN_F8R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB17_Pos /;" d +CAN_F8R2_FB17 target/stm32f103xb.h /^#define CAN_F8R2_FB17 /;" d +CAN_F8R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB18_Msk /;" d +CAN_F8R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB18_Pos /;" d +CAN_F8R2_FB18 target/stm32f103xb.h /^#define CAN_F8R2_FB18 /;" d +CAN_F8R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB19_Msk /;" d +CAN_F8R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB19_Pos /;" d +CAN_F8R2_FB19 target/stm32f103xb.h /^#define CAN_F8R2_FB19 /;" d +CAN_F8R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB1_Msk /;" d +CAN_F8R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB1_Pos /;" d +CAN_F8R2_FB1 target/stm32f103xb.h /^#define CAN_F8R2_FB1 /;" d +CAN_F8R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB20_Msk /;" d +CAN_F8R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB20_Pos /;" d +CAN_F8R2_FB20 target/stm32f103xb.h /^#define CAN_F8R2_FB20 /;" d +CAN_F8R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB21_Msk /;" d +CAN_F8R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB21_Pos /;" d +CAN_F8R2_FB21 target/stm32f103xb.h /^#define CAN_F8R2_FB21 /;" d +CAN_F8R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB22_Msk /;" d +CAN_F8R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB22_Pos /;" d +CAN_F8R2_FB22 target/stm32f103xb.h /^#define CAN_F8R2_FB22 /;" d +CAN_F8R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB23_Msk /;" d +CAN_F8R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB23_Pos /;" d +CAN_F8R2_FB23 target/stm32f103xb.h /^#define CAN_F8R2_FB23 /;" d +CAN_F8R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB24_Msk /;" d +CAN_F8R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB24_Pos /;" d +CAN_F8R2_FB24 target/stm32f103xb.h /^#define CAN_F8R2_FB24 /;" d +CAN_F8R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB25_Msk /;" d +CAN_F8R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB25_Pos /;" d +CAN_F8R2_FB25 target/stm32f103xb.h /^#define CAN_F8R2_FB25 /;" d +CAN_F8R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB26_Msk /;" d +CAN_F8R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB26_Pos /;" d +CAN_F8R2_FB26 target/stm32f103xb.h /^#define CAN_F8R2_FB26 /;" d +CAN_F8R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB27_Msk /;" d +CAN_F8R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB27_Pos /;" d +CAN_F8R2_FB27 target/stm32f103xb.h /^#define CAN_F8R2_FB27 /;" d +CAN_F8R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB28_Msk /;" d +CAN_F8R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB28_Pos /;" d +CAN_F8R2_FB28 target/stm32f103xb.h /^#define CAN_F8R2_FB28 /;" d +CAN_F8R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB29_Msk /;" d +CAN_F8R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB29_Pos /;" d +CAN_F8R2_FB29 target/stm32f103xb.h /^#define CAN_F8R2_FB29 /;" d +CAN_F8R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB2_Msk /;" d +CAN_F8R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB2_Pos /;" d +CAN_F8R2_FB2 target/stm32f103xb.h /^#define CAN_F8R2_FB2 /;" d +CAN_F8R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB30_Msk /;" d +CAN_F8R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB30_Pos /;" d +CAN_F8R2_FB30 target/stm32f103xb.h /^#define CAN_F8R2_FB30 /;" d +CAN_F8R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB31_Msk /;" d +CAN_F8R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB31_Pos /;" d +CAN_F8R2_FB31 target/stm32f103xb.h /^#define CAN_F8R2_FB31 /;" d +CAN_F8R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB3_Msk /;" d +CAN_F8R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB3_Pos /;" d +CAN_F8R2_FB3 target/stm32f103xb.h /^#define CAN_F8R2_FB3 /;" d +CAN_F8R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB4_Msk /;" d +CAN_F8R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB4_Pos /;" d +CAN_F8R2_FB4 target/stm32f103xb.h /^#define CAN_F8R2_FB4 /;" d +CAN_F8R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB5_Msk /;" d +CAN_F8R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB5_Pos /;" d +CAN_F8R2_FB5 target/stm32f103xb.h /^#define CAN_F8R2_FB5 /;" d +CAN_F8R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB6_Msk /;" d +CAN_F8R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB6_Pos /;" d +CAN_F8R2_FB6 target/stm32f103xb.h /^#define CAN_F8R2_FB6 /;" d +CAN_F8R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB7_Msk /;" d +CAN_F8R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB7_Pos /;" d +CAN_F8R2_FB7 target/stm32f103xb.h /^#define CAN_F8R2_FB7 /;" d +CAN_F8R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB8_Msk /;" d +CAN_F8R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB8_Pos /;" d +CAN_F8R2_FB8 target/stm32f103xb.h /^#define CAN_F8R2_FB8 /;" d +CAN_F8R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F8R2_FB9_Msk /;" d +CAN_F8R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F8R2_FB9_Pos /;" d +CAN_F8R2_FB9 target/stm32f103xb.h /^#define CAN_F8R2_FB9 /;" d +CAN_F9R1_FB0_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB0_Msk /;" d +CAN_F9R1_FB0_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB0_Pos /;" d +CAN_F9R1_FB0 target/stm32f103xb.h /^#define CAN_F9R1_FB0 /;" d +CAN_F9R1_FB10_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB10_Msk /;" d +CAN_F9R1_FB10_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB10_Pos /;" d +CAN_F9R1_FB10 target/stm32f103xb.h /^#define CAN_F9R1_FB10 /;" d +CAN_F9R1_FB11_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB11_Msk /;" d +CAN_F9R1_FB11_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB11_Pos /;" d +CAN_F9R1_FB11 target/stm32f103xb.h /^#define CAN_F9R1_FB11 /;" d +CAN_F9R1_FB12_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB12_Msk /;" d +CAN_F9R1_FB12_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB12_Pos /;" d +CAN_F9R1_FB12 target/stm32f103xb.h /^#define CAN_F9R1_FB12 /;" d +CAN_F9R1_FB13_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB13_Msk /;" d +CAN_F9R1_FB13_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB13_Pos /;" d +CAN_F9R1_FB13 target/stm32f103xb.h /^#define CAN_F9R1_FB13 /;" d +CAN_F9R1_FB14_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB14_Msk /;" d +CAN_F9R1_FB14_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB14_Pos /;" d +CAN_F9R1_FB14 target/stm32f103xb.h /^#define CAN_F9R1_FB14 /;" d +CAN_F9R1_FB15_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB15_Msk /;" d +CAN_F9R1_FB15_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB15_Pos /;" d +CAN_F9R1_FB15 target/stm32f103xb.h /^#define CAN_F9R1_FB15 /;" d +CAN_F9R1_FB16_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB16_Msk /;" d +CAN_F9R1_FB16_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB16_Pos /;" d +CAN_F9R1_FB16 target/stm32f103xb.h /^#define CAN_F9R1_FB16 /;" d +CAN_F9R1_FB17_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB17_Msk /;" d +CAN_F9R1_FB17_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB17_Pos /;" d +CAN_F9R1_FB17 target/stm32f103xb.h /^#define CAN_F9R1_FB17 /;" d +CAN_F9R1_FB18_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB18_Msk /;" d +CAN_F9R1_FB18_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB18_Pos /;" d +CAN_F9R1_FB18 target/stm32f103xb.h /^#define CAN_F9R1_FB18 /;" d +CAN_F9R1_FB19_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB19_Msk /;" d +CAN_F9R1_FB19_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB19_Pos /;" d +CAN_F9R1_FB19 target/stm32f103xb.h /^#define CAN_F9R1_FB19 /;" d +CAN_F9R1_FB1_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB1_Msk /;" d +CAN_F9R1_FB1_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB1_Pos /;" d +CAN_F9R1_FB1 target/stm32f103xb.h /^#define CAN_F9R1_FB1 /;" d +CAN_F9R1_FB20_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB20_Msk /;" d +CAN_F9R1_FB20_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB20_Pos /;" d +CAN_F9R1_FB20 target/stm32f103xb.h /^#define CAN_F9R1_FB20 /;" d +CAN_F9R1_FB21_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB21_Msk /;" d +CAN_F9R1_FB21_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB21_Pos /;" d +CAN_F9R1_FB21 target/stm32f103xb.h /^#define CAN_F9R1_FB21 /;" d +CAN_F9R1_FB22_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB22_Msk /;" d +CAN_F9R1_FB22_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB22_Pos /;" d +CAN_F9R1_FB22 target/stm32f103xb.h /^#define CAN_F9R1_FB22 /;" d +CAN_F9R1_FB23_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB23_Msk /;" d +CAN_F9R1_FB23_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB23_Pos /;" d +CAN_F9R1_FB23 target/stm32f103xb.h /^#define CAN_F9R1_FB23 /;" d +CAN_F9R1_FB24_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB24_Msk /;" d +CAN_F9R1_FB24_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB24_Pos /;" d +CAN_F9R1_FB24 target/stm32f103xb.h /^#define CAN_F9R1_FB24 /;" d +CAN_F9R1_FB25_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB25_Msk /;" d +CAN_F9R1_FB25_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB25_Pos /;" d +CAN_F9R1_FB25 target/stm32f103xb.h /^#define CAN_F9R1_FB25 /;" d +CAN_F9R1_FB26_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB26_Msk /;" d +CAN_F9R1_FB26_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB26_Pos /;" d +CAN_F9R1_FB26 target/stm32f103xb.h /^#define CAN_F9R1_FB26 /;" d +CAN_F9R1_FB27_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB27_Msk /;" d +CAN_F9R1_FB27_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB27_Pos /;" d +CAN_F9R1_FB27 target/stm32f103xb.h /^#define CAN_F9R1_FB27 /;" d +CAN_F9R1_FB28_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB28_Msk /;" d +CAN_F9R1_FB28_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB28_Pos /;" d +CAN_F9R1_FB28 target/stm32f103xb.h /^#define CAN_F9R1_FB28 /;" d +CAN_F9R1_FB29_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB29_Msk /;" d +CAN_F9R1_FB29_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB29_Pos /;" d +CAN_F9R1_FB29 target/stm32f103xb.h /^#define CAN_F9R1_FB29 /;" d +CAN_F9R1_FB2_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB2_Msk /;" d +CAN_F9R1_FB2_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB2_Pos /;" d +CAN_F9R1_FB2 target/stm32f103xb.h /^#define CAN_F9R1_FB2 /;" d +CAN_F9R1_FB30_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB30_Msk /;" d +CAN_F9R1_FB30_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB30_Pos /;" d +CAN_F9R1_FB30 target/stm32f103xb.h /^#define CAN_F9R1_FB30 /;" d +CAN_F9R1_FB31_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB31_Msk /;" d +CAN_F9R1_FB31_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB31_Pos /;" d +CAN_F9R1_FB31 target/stm32f103xb.h /^#define CAN_F9R1_FB31 /;" d +CAN_F9R1_FB3_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB3_Msk /;" d +CAN_F9R1_FB3_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB3_Pos /;" d +CAN_F9R1_FB3 target/stm32f103xb.h /^#define CAN_F9R1_FB3 /;" d +CAN_F9R1_FB4_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB4_Msk /;" d +CAN_F9R1_FB4_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB4_Pos /;" d +CAN_F9R1_FB4 target/stm32f103xb.h /^#define CAN_F9R1_FB4 /;" d +CAN_F9R1_FB5_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB5_Msk /;" d +CAN_F9R1_FB5_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB5_Pos /;" d +CAN_F9R1_FB5 target/stm32f103xb.h /^#define CAN_F9R1_FB5 /;" d +CAN_F9R1_FB6_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB6_Msk /;" d +CAN_F9R1_FB6_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB6_Pos /;" d +CAN_F9R1_FB6 target/stm32f103xb.h /^#define CAN_F9R1_FB6 /;" d +CAN_F9R1_FB7_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB7_Msk /;" d +CAN_F9R1_FB7_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB7_Pos /;" d +CAN_F9R1_FB7 target/stm32f103xb.h /^#define CAN_F9R1_FB7 /;" d +CAN_F9R1_FB8_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB8_Msk /;" d +CAN_F9R1_FB8_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB8_Pos /;" d +CAN_F9R1_FB8 target/stm32f103xb.h /^#define CAN_F9R1_FB8 /;" d +CAN_F9R1_FB9_Msk target/stm32f103xb.h /^#define CAN_F9R1_FB9_Msk /;" d +CAN_F9R1_FB9_Pos target/stm32f103xb.h /^#define CAN_F9R1_FB9_Pos /;" d +CAN_F9R1_FB9 target/stm32f103xb.h /^#define CAN_F9R1_FB9 /;" d +CAN_F9R2_FB0_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB0_Msk /;" d +CAN_F9R2_FB0_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB0_Pos /;" d +CAN_F9R2_FB0 target/stm32f103xb.h /^#define CAN_F9R2_FB0 /;" d +CAN_F9R2_FB10_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB10_Msk /;" d +CAN_F9R2_FB10_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB10_Pos /;" d +CAN_F9R2_FB10 target/stm32f103xb.h /^#define CAN_F9R2_FB10 /;" d +CAN_F9R2_FB11_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB11_Msk /;" d +CAN_F9R2_FB11_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB11_Pos /;" d +CAN_F9R2_FB11 target/stm32f103xb.h /^#define CAN_F9R2_FB11 /;" d +CAN_F9R2_FB12_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB12_Msk /;" d +CAN_F9R2_FB12_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB12_Pos /;" d +CAN_F9R2_FB12 target/stm32f103xb.h /^#define CAN_F9R2_FB12 /;" d +CAN_F9R2_FB13_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB13_Msk /;" d +CAN_F9R2_FB13_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB13_Pos /;" d +CAN_F9R2_FB13 target/stm32f103xb.h /^#define CAN_F9R2_FB13 /;" d +CAN_F9R2_FB14_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB14_Msk /;" d +CAN_F9R2_FB14_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB14_Pos /;" d +CAN_F9R2_FB14 target/stm32f103xb.h /^#define CAN_F9R2_FB14 /;" d +CAN_F9R2_FB15_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB15_Msk /;" d +CAN_F9R2_FB15_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB15_Pos /;" d +CAN_F9R2_FB15 target/stm32f103xb.h /^#define CAN_F9R2_FB15 /;" d +CAN_F9R2_FB16_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB16_Msk /;" d +CAN_F9R2_FB16_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB16_Pos /;" d +CAN_F9R2_FB16 target/stm32f103xb.h /^#define CAN_F9R2_FB16 /;" d +CAN_F9R2_FB17_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB17_Msk /;" d +CAN_F9R2_FB17_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB17_Pos /;" d +CAN_F9R2_FB17 target/stm32f103xb.h /^#define CAN_F9R2_FB17 /;" d +CAN_F9R2_FB18_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB18_Msk /;" d +CAN_F9R2_FB18_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB18_Pos /;" d +CAN_F9R2_FB18 target/stm32f103xb.h /^#define CAN_F9R2_FB18 /;" d +CAN_F9R2_FB19_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB19_Msk /;" d +CAN_F9R2_FB19_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB19_Pos /;" d +CAN_F9R2_FB19 target/stm32f103xb.h /^#define CAN_F9R2_FB19 /;" d +CAN_F9R2_FB1_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB1_Msk /;" d +CAN_F9R2_FB1_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB1_Pos /;" d +CAN_F9R2_FB1 target/stm32f103xb.h /^#define CAN_F9R2_FB1 /;" d +CAN_F9R2_FB20_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB20_Msk /;" d +CAN_F9R2_FB20_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB20_Pos /;" d +CAN_F9R2_FB20 target/stm32f103xb.h /^#define CAN_F9R2_FB20 /;" d +CAN_F9R2_FB21_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB21_Msk /;" d +CAN_F9R2_FB21_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB21_Pos /;" d +CAN_F9R2_FB21 target/stm32f103xb.h /^#define CAN_F9R2_FB21 /;" d +CAN_F9R2_FB22_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB22_Msk /;" d +CAN_F9R2_FB22_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB22_Pos /;" d +CAN_F9R2_FB22 target/stm32f103xb.h /^#define CAN_F9R2_FB22 /;" d +CAN_F9R2_FB23_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB23_Msk /;" d +CAN_F9R2_FB23_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB23_Pos /;" d +CAN_F9R2_FB23 target/stm32f103xb.h /^#define CAN_F9R2_FB23 /;" d +CAN_F9R2_FB24_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB24_Msk /;" d +CAN_F9R2_FB24_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB24_Pos /;" d +CAN_F9R2_FB24 target/stm32f103xb.h /^#define CAN_F9R2_FB24 /;" d +CAN_F9R2_FB25_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB25_Msk /;" d +CAN_F9R2_FB25_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB25_Pos /;" d +CAN_F9R2_FB25 target/stm32f103xb.h /^#define CAN_F9R2_FB25 /;" d +CAN_F9R2_FB26_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB26_Msk /;" d +CAN_F9R2_FB26_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB26_Pos /;" d +CAN_F9R2_FB26 target/stm32f103xb.h /^#define CAN_F9R2_FB26 /;" d +CAN_F9R2_FB27_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB27_Msk /;" d +CAN_F9R2_FB27_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB27_Pos /;" d +CAN_F9R2_FB27 target/stm32f103xb.h /^#define CAN_F9R2_FB27 /;" d +CAN_F9R2_FB28_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB28_Msk /;" d +CAN_F9R2_FB28_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB28_Pos /;" d +CAN_F9R2_FB28 target/stm32f103xb.h /^#define CAN_F9R2_FB28 /;" d +CAN_F9R2_FB29_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB29_Msk /;" d +CAN_F9R2_FB29_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB29_Pos /;" d +CAN_F9R2_FB29 target/stm32f103xb.h /^#define CAN_F9R2_FB29 /;" d +CAN_F9R2_FB2_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB2_Msk /;" d +CAN_F9R2_FB2_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB2_Pos /;" d +CAN_F9R2_FB2 target/stm32f103xb.h /^#define CAN_F9R2_FB2 /;" d +CAN_F9R2_FB30_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB30_Msk /;" d +CAN_F9R2_FB30_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB30_Pos /;" d +CAN_F9R2_FB30 target/stm32f103xb.h /^#define CAN_F9R2_FB30 /;" d +CAN_F9R2_FB31_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB31_Msk /;" d +CAN_F9R2_FB31_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB31_Pos /;" d +CAN_F9R2_FB31 target/stm32f103xb.h /^#define CAN_F9R2_FB31 /;" d +CAN_F9R2_FB3_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB3_Msk /;" d +CAN_F9R2_FB3_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB3_Pos /;" d +CAN_F9R2_FB3 target/stm32f103xb.h /^#define CAN_F9R2_FB3 /;" d +CAN_F9R2_FB4_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB4_Msk /;" d +CAN_F9R2_FB4_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB4_Pos /;" d +CAN_F9R2_FB4 target/stm32f103xb.h /^#define CAN_F9R2_FB4 /;" d +CAN_F9R2_FB5_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB5_Msk /;" d +CAN_F9R2_FB5_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB5_Pos /;" d +CAN_F9R2_FB5 target/stm32f103xb.h /^#define CAN_F9R2_FB5 /;" d +CAN_F9R2_FB6_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB6_Msk /;" d +CAN_F9R2_FB6_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB6_Pos /;" d +CAN_F9R2_FB6 target/stm32f103xb.h /^#define CAN_F9R2_FB6 /;" d +CAN_F9R2_FB7_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB7_Msk /;" d +CAN_F9R2_FB7_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB7_Pos /;" d +CAN_F9R2_FB7 target/stm32f103xb.h /^#define CAN_F9R2_FB7 /;" d +CAN_F9R2_FB8_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB8_Msk /;" d +CAN_F9R2_FB8_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB8_Pos /;" d +CAN_F9R2_FB8 target/stm32f103xb.h /^#define CAN_F9R2_FB8 /;" d +CAN_F9R2_FB9_Msk target/stm32f103xb.h /^#define CAN_F9R2_FB9_Msk /;" d +CAN_F9R2_FB9_Pos target/stm32f103xb.h /^#define CAN_F9R2_FB9_Pos /;" d +CAN_F9R2_FB9 target/stm32f103xb.h /^#define CAN_F9R2_FB9 /;" d +CAN_FA1R_FACT0_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT0_Msk /;" d +CAN_FA1R_FACT0_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT0_Pos /;" d +CAN_FA1R_FACT0 target/stm32f103xb.h /^#define CAN_FA1R_FACT0 /;" d +CAN_FA1R_FACT10_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT10_Msk /;" d +CAN_FA1R_FACT10_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT10_Pos /;" d +CAN_FA1R_FACT10 target/stm32f103xb.h /^#define CAN_FA1R_FACT10 /;" d +CAN_FA1R_FACT11_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT11_Msk /;" d +CAN_FA1R_FACT11_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT11_Pos /;" d +CAN_FA1R_FACT11 target/stm32f103xb.h /^#define CAN_FA1R_FACT11 /;" d +CAN_FA1R_FACT12_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT12_Msk /;" d +CAN_FA1R_FACT12_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT12_Pos /;" d +CAN_FA1R_FACT12 target/stm32f103xb.h /^#define CAN_FA1R_FACT12 /;" d +CAN_FA1R_FACT13_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT13_Msk /;" d +CAN_FA1R_FACT13_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT13_Pos /;" d +CAN_FA1R_FACT13 target/stm32f103xb.h /^#define CAN_FA1R_FACT13 /;" d +CAN_FA1R_FACT1_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT1_Msk /;" d +CAN_FA1R_FACT1_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT1_Pos /;" d +CAN_FA1R_FACT1 target/stm32f103xb.h /^#define CAN_FA1R_FACT1 /;" d +CAN_FA1R_FACT2_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT2_Msk /;" d +CAN_FA1R_FACT2_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT2_Pos /;" d +CAN_FA1R_FACT2 target/stm32f103xb.h /^#define CAN_FA1R_FACT2 /;" d +CAN_FA1R_FACT3_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT3_Msk /;" d +CAN_FA1R_FACT3_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT3_Pos /;" d +CAN_FA1R_FACT3 target/stm32f103xb.h /^#define CAN_FA1R_FACT3 /;" d +CAN_FA1R_FACT4_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT4_Msk /;" d +CAN_FA1R_FACT4_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT4_Pos /;" d +CAN_FA1R_FACT4 target/stm32f103xb.h /^#define CAN_FA1R_FACT4 /;" d +CAN_FA1R_FACT5_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT5_Msk /;" d +CAN_FA1R_FACT5_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT5_Pos /;" d +CAN_FA1R_FACT5 target/stm32f103xb.h /^#define CAN_FA1R_FACT5 /;" d +CAN_FA1R_FACT6_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT6_Msk /;" d +CAN_FA1R_FACT6_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT6_Pos /;" d +CAN_FA1R_FACT6 target/stm32f103xb.h /^#define CAN_FA1R_FACT6 /;" d +CAN_FA1R_FACT7_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT7_Msk /;" d +CAN_FA1R_FACT7_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT7_Pos /;" d +CAN_FA1R_FACT7 target/stm32f103xb.h /^#define CAN_FA1R_FACT7 /;" d +CAN_FA1R_FACT8_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT8_Msk /;" d +CAN_FA1R_FACT8_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT8_Pos /;" d +CAN_FA1R_FACT8 target/stm32f103xb.h /^#define CAN_FA1R_FACT8 /;" d +CAN_FA1R_FACT9_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT9_Msk /;" d +CAN_FA1R_FACT9_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT9_Pos /;" d +CAN_FA1R_FACT9 target/stm32f103xb.h /^#define CAN_FA1R_FACT9 /;" d +CAN_FA1R_FACT_Msk target/stm32f103xb.h /^#define CAN_FA1R_FACT_Msk /;" d +CAN_FA1R_FACT_Pos target/stm32f103xb.h /^#define CAN_FA1R_FACT_Pos /;" d +CAN_FA1R_FACT target/stm32f103xb.h /^#define CAN_FA1R_FACT /;" d +CAN_FFA1R_FFA0_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA0_Msk /;" d +CAN_FFA1R_FFA0_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA0_Pos /;" d +CAN_FFA1R_FFA0 target/stm32f103xb.h /^#define CAN_FFA1R_FFA0 /;" d +CAN_FFA1R_FFA10_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA10_Msk /;" d +CAN_FFA1R_FFA10_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA10_Pos /;" d +CAN_FFA1R_FFA10 target/stm32f103xb.h /^#define CAN_FFA1R_FFA10 /;" d +CAN_FFA1R_FFA11_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA11_Msk /;" d +CAN_FFA1R_FFA11_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA11_Pos /;" d +CAN_FFA1R_FFA11 target/stm32f103xb.h /^#define CAN_FFA1R_FFA11 /;" d +CAN_FFA1R_FFA12_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA12_Msk /;" d +CAN_FFA1R_FFA12_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA12_Pos /;" d +CAN_FFA1R_FFA12 target/stm32f103xb.h /^#define CAN_FFA1R_FFA12 /;" d +CAN_FFA1R_FFA13_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA13_Msk /;" d +CAN_FFA1R_FFA13_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA13_Pos /;" d +CAN_FFA1R_FFA13 target/stm32f103xb.h /^#define CAN_FFA1R_FFA13 /;" d +CAN_FFA1R_FFA1_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA1_Msk /;" d +CAN_FFA1R_FFA1_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA1_Pos /;" d +CAN_FFA1R_FFA1 target/stm32f103xb.h /^#define CAN_FFA1R_FFA1 /;" d +CAN_FFA1R_FFA2_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA2_Msk /;" d +CAN_FFA1R_FFA2_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA2_Pos /;" d +CAN_FFA1R_FFA2 target/stm32f103xb.h /^#define CAN_FFA1R_FFA2 /;" d +CAN_FFA1R_FFA3_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA3_Msk /;" d +CAN_FFA1R_FFA3_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA3_Pos /;" d +CAN_FFA1R_FFA3 target/stm32f103xb.h /^#define CAN_FFA1R_FFA3 /;" d +CAN_FFA1R_FFA4_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA4_Msk /;" d +CAN_FFA1R_FFA4_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA4_Pos /;" d +CAN_FFA1R_FFA4 target/stm32f103xb.h /^#define CAN_FFA1R_FFA4 /;" d +CAN_FFA1R_FFA5_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA5_Msk /;" d +CAN_FFA1R_FFA5_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA5_Pos /;" d +CAN_FFA1R_FFA5 target/stm32f103xb.h /^#define CAN_FFA1R_FFA5 /;" d +CAN_FFA1R_FFA6_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA6_Msk /;" d +CAN_FFA1R_FFA6_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA6_Pos /;" d +CAN_FFA1R_FFA6 target/stm32f103xb.h /^#define CAN_FFA1R_FFA6 /;" d +CAN_FFA1R_FFA7_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA7_Msk /;" d +CAN_FFA1R_FFA7_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA7_Pos /;" d +CAN_FFA1R_FFA7 target/stm32f103xb.h /^#define CAN_FFA1R_FFA7 /;" d +CAN_FFA1R_FFA8_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA8_Msk /;" d +CAN_FFA1R_FFA8_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA8_Pos /;" d +CAN_FFA1R_FFA8 target/stm32f103xb.h /^#define CAN_FFA1R_FFA8 /;" d +CAN_FFA1R_FFA9_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA9_Msk /;" d +CAN_FFA1R_FFA9_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA9_Pos /;" d +CAN_FFA1R_FFA9 target/stm32f103xb.h /^#define CAN_FFA1R_FFA9 /;" d +CAN_FFA1R_FFA_Msk target/stm32f103xb.h /^#define CAN_FFA1R_FFA_Msk /;" d +CAN_FFA1R_FFA_Pos target/stm32f103xb.h /^#define CAN_FFA1R_FFA_Pos /;" d +CAN_FFA1R_FFA target/stm32f103xb.h /^#define CAN_FFA1R_FFA /;" d +CAN_FIFOMailBox_TypeDef target/stm32f103xb.h /^} CAN_FIFOMailBox_TypeDef;$/;" t typeref:struct:__anon72c4c37e0608 +CAN_FM1R_FBM0_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM0_Msk /;" d +CAN_FM1R_FBM0_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM0_Pos /;" d +CAN_FM1R_FBM0 target/stm32f103xb.h /^#define CAN_FM1R_FBM0 /;" d +CAN_FM1R_FBM10_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM10_Msk /;" d +CAN_FM1R_FBM10_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM10_Pos /;" d +CAN_FM1R_FBM10 target/stm32f103xb.h /^#define CAN_FM1R_FBM10 /;" d +CAN_FM1R_FBM11_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM11_Msk /;" d +CAN_FM1R_FBM11_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM11_Pos /;" d +CAN_FM1R_FBM11 target/stm32f103xb.h /^#define CAN_FM1R_FBM11 /;" d +CAN_FM1R_FBM12_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM12_Msk /;" d +CAN_FM1R_FBM12_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM12_Pos /;" d +CAN_FM1R_FBM12 target/stm32f103xb.h /^#define CAN_FM1R_FBM12 /;" d +CAN_FM1R_FBM13_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM13_Msk /;" d +CAN_FM1R_FBM13_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM13_Pos /;" d +CAN_FM1R_FBM13 target/stm32f103xb.h /^#define CAN_FM1R_FBM13 /;" d +CAN_FM1R_FBM1_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM1_Msk /;" d +CAN_FM1R_FBM1_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM1_Pos /;" d +CAN_FM1R_FBM1 target/stm32f103xb.h /^#define CAN_FM1R_FBM1 /;" d +CAN_FM1R_FBM2_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM2_Msk /;" d +CAN_FM1R_FBM2_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM2_Pos /;" d +CAN_FM1R_FBM2 target/stm32f103xb.h /^#define CAN_FM1R_FBM2 /;" d +CAN_FM1R_FBM3_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM3_Msk /;" d +CAN_FM1R_FBM3_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM3_Pos /;" d +CAN_FM1R_FBM3 target/stm32f103xb.h /^#define CAN_FM1R_FBM3 /;" d +CAN_FM1R_FBM4_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM4_Msk /;" d +CAN_FM1R_FBM4_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM4_Pos /;" d +CAN_FM1R_FBM4 target/stm32f103xb.h /^#define CAN_FM1R_FBM4 /;" d +CAN_FM1R_FBM5_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM5_Msk /;" d +CAN_FM1R_FBM5_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM5_Pos /;" d +CAN_FM1R_FBM5 target/stm32f103xb.h /^#define CAN_FM1R_FBM5 /;" d +CAN_FM1R_FBM6_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM6_Msk /;" d +CAN_FM1R_FBM6_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM6_Pos /;" d +CAN_FM1R_FBM6 target/stm32f103xb.h /^#define CAN_FM1R_FBM6 /;" d +CAN_FM1R_FBM7_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM7_Msk /;" d +CAN_FM1R_FBM7_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM7_Pos /;" d +CAN_FM1R_FBM7 target/stm32f103xb.h /^#define CAN_FM1R_FBM7 /;" d +CAN_FM1R_FBM8_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM8_Msk /;" d +CAN_FM1R_FBM8_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM8_Pos /;" d +CAN_FM1R_FBM8 target/stm32f103xb.h /^#define CAN_FM1R_FBM8 /;" d +CAN_FM1R_FBM9_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM9_Msk /;" d +CAN_FM1R_FBM9_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM9_Pos /;" d +CAN_FM1R_FBM9 target/stm32f103xb.h /^#define CAN_FM1R_FBM9 /;" d +CAN_FM1R_FBM_Msk target/stm32f103xb.h /^#define CAN_FM1R_FBM_Msk /;" d +CAN_FM1R_FBM_Pos target/stm32f103xb.h /^#define CAN_FM1R_FBM_Pos /;" d +CAN_FM1R_FBM target/stm32f103xb.h /^#define CAN_FM1R_FBM /;" d +CAN_FMR_CAN2SB_Msk target/stm32f103xb.h /^#define CAN_FMR_CAN2SB_Msk /;" d +CAN_FMR_CAN2SB_Pos target/stm32f103xb.h /^#define CAN_FMR_CAN2SB_Pos /;" d +CAN_FMR_CAN2SB target/stm32f103xb.h /^#define CAN_FMR_CAN2SB /;" d +CAN_FMR_FINIT_Msk target/stm32f103xb.h /^#define CAN_FMR_FINIT_Msk /;" d +CAN_FMR_FINIT_Pos target/stm32f103xb.h /^#define CAN_FMR_FINIT_Pos /;" d +CAN_FMR_FINIT target/stm32f103xb.h /^#define CAN_FMR_FINIT /;" d +CAN_FS1R_FSC0_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC0_Msk /;" d +CAN_FS1R_FSC0_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC0_Pos /;" d +CAN_FS1R_FSC0 target/stm32f103xb.h /^#define CAN_FS1R_FSC0 /;" d +CAN_FS1R_FSC10_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC10_Msk /;" d +CAN_FS1R_FSC10_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC10_Pos /;" d +CAN_FS1R_FSC10 target/stm32f103xb.h /^#define CAN_FS1R_FSC10 /;" d +CAN_FS1R_FSC11_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC11_Msk /;" d +CAN_FS1R_FSC11_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC11_Pos /;" d +CAN_FS1R_FSC11 target/stm32f103xb.h /^#define CAN_FS1R_FSC11 /;" d +CAN_FS1R_FSC12_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC12_Msk /;" d +CAN_FS1R_FSC12_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC12_Pos /;" d +CAN_FS1R_FSC12 target/stm32f103xb.h /^#define CAN_FS1R_FSC12 /;" d +CAN_FS1R_FSC13_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC13_Msk /;" d +CAN_FS1R_FSC13_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC13_Pos /;" d +CAN_FS1R_FSC13 target/stm32f103xb.h /^#define CAN_FS1R_FSC13 /;" d +CAN_FS1R_FSC1_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC1_Msk /;" d +CAN_FS1R_FSC1_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC1_Pos /;" d +CAN_FS1R_FSC1 target/stm32f103xb.h /^#define CAN_FS1R_FSC1 /;" d +CAN_FS1R_FSC2_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC2_Msk /;" d +CAN_FS1R_FSC2_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC2_Pos /;" d +CAN_FS1R_FSC2 target/stm32f103xb.h /^#define CAN_FS1R_FSC2 /;" d +CAN_FS1R_FSC3_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC3_Msk /;" d +CAN_FS1R_FSC3_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC3_Pos /;" d +CAN_FS1R_FSC3 target/stm32f103xb.h /^#define CAN_FS1R_FSC3 /;" d +CAN_FS1R_FSC4_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC4_Msk /;" d +CAN_FS1R_FSC4_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC4_Pos /;" d +CAN_FS1R_FSC4 target/stm32f103xb.h /^#define CAN_FS1R_FSC4 /;" d +CAN_FS1R_FSC5_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC5_Msk /;" d +CAN_FS1R_FSC5_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC5_Pos /;" d +CAN_FS1R_FSC5 target/stm32f103xb.h /^#define CAN_FS1R_FSC5 /;" d +CAN_FS1R_FSC6_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC6_Msk /;" d +CAN_FS1R_FSC6_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC6_Pos /;" d +CAN_FS1R_FSC6 target/stm32f103xb.h /^#define CAN_FS1R_FSC6 /;" d +CAN_FS1R_FSC7_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC7_Msk /;" d +CAN_FS1R_FSC7_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC7_Pos /;" d +CAN_FS1R_FSC7 target/stm32f103xb.h /^#define CAN_FS1R_FSC7 /;" d +CAN_FS1R_FSC8_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC8_Msk /;" d +CAN_FS1R_FSC8_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC8_Pos /;" d +CAN_FS1R_FSC8 target/stm32f103xb.h /^#define CAN_FS1R_FSC8 /;" d +CAN_FS1R_FSC9_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC9_Msk /;" d +CAN_FS1R_FSC9_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC9_Pos /;" d +CAN_FS1R_FSC9 target/stm32f103xb.h /^#define CAN_FS1R_FSC9 /;" d +CAN_FS1R_FSC_Msk target/stm32f103xb.h /^#define CAN_FS1R_FSC_Msk /;" d +CAN_FS1R_FSC_Pos target/stm32f103xb.h /^#define CAN_FS1R_FSC_Pos /;" d +CAN_FS1R_FSC target/stm32f103xb.h /^#define CAN_FS1R_FSC /;" d +CAN_FilterRegister_TypeDef target/stm32f103xb.h /^} CAN_FilterRegister_TypeDef;$/;" t typeref:struct:__anon72c4c37e0708 +CAN_IER_BOFIE_Msk target/stm32f103xb.h /^#define CAN_IER_BOFIE_Msk /;" d +CAN_IER_BOFIE_Pos target/stm32f103xb.h /^#define CAN_IER_BOFIE_Pos /;" d +CAN_IER_BOFIE target/stm32f103xb.h /^#define CAN_IER_BOFIE /;" d +CAN_IER_EPVIE_Msk target/stm32f103xb.h /^#define CAN_IER_EPVIE_Msk /;" d +CAN_IER_EPVIE_Pos target/stm32f103xb.h /^#define CAN_IER_EPVIE_Pos /;" d +CAN_IER_EPVIE target/stm32f103xb.h /^#define CAN_IER_EPVIE /;" d +CAN_IER_ERRIE_Msk target/stm32f103xb.h /^#define CAN_IER_ERRIE_Msk /;" d +CAN_IER_ERRIE_Pos target/stm32f103xb.h /^#define CAN_IER_ERRIE_Pos /;" d +CAN_IER_ERRIE target/stm32f103xb.h /^#define CAN_IER_ERRIE /;" d +CAN_IER_EWGIE_Msk target/stm32f103xb.h /^#define CAN_IER_EWGIE_Msk /;" d +CAN_IER_EWGIE_Pos target/stm32f103xb.h /^#define CAN_IER_EWGIE_Pos /;" d +CAN_IER_EWGIE target/stm32f103xb.h /^#define CAN_IER_EWGIE /;" d +CAN_IER_FFIE0_Msk target/stm32f103xb.h /^#define CAN_IER_FFIE0_Msk /;" d +CAN_IER_FFIE0_Pos target/stm32f103xb.h /^#define CAN_IER_FFIE0_Pos /;" d +CAN_IER_FFIE0 target/stm32f103xb.h /^#define CAN_IER_FFIE0 /;" d +CAN_IER_FFIE1_Msk target/stm32f103xb.h /^#define CAN_IER_FFIE1_Msk /;" d +CAN_IER_FFIE1_Pos target/stm32f103xb.h /^#define CAN_IER_FFIE1_Pos /;" d +CAN_IER_FFIE1 target/stm32f103xb.h /^#define CAN_IER_FFIE1 /;" d +CAN_IER_FMPIE0_Msk target/stm32f103xb.h /^#define CAN_IER_FMPIE0_Msk /;" d +CAN_IER_FMPIE0_Pos target/stm32f103xb.h /^#define CAN_IER_FMPIE0_Pos /;" d +CAN_IER_FMPIE0 target/stm32f103xb.h /^#define CAN_IER_FMPIE0 /;" d +CAN_IER_FMPIE1_Msk target/stm32f103xb.h /^#define CAN_IER_FMPIE1_Msk /;" d +CAN_IER_FMPIE1_Pos target/stm32f103xb.h /^#define CAN_IER_FMPIE1_Pos /;" d +CAN_IER_FMPIE1 target/stm32f103xb.h /^#define CAN_IER_FMPIE1 /;" d +CAN_IER_FOVIE0_Msk target/stm32f103xb.h /^#define CAN_IER_FOVIE0_Msk /;" d +CAN_IER_FOVIE0_Pos target/stm32f103xb.h /^#define CAN_IER_FOVIE0_Pos /;" d +CAN_IER_FOVIE0 target/stm32f103xb.h /^#define CAN_IER_FOVIE0 /;" d +CAN_IER_FOVIE1_Msk target/stm32f103xb.h /^#define CAN_IER_FOVIE1_Msk /;" d +CAN_IER_FOVIE1_Pos target/stm32f103xb.h /^#define CAN_IER_FOVIE1_Pos /;" d +CAN_IER_FOVIE1 target/stm32f103xb.h /^#define CAN_IER_FOVIE1 /;" d +CAN_IER_LECIE_Msk target/stm32f103xb.h /^#define CAN_IER_LECIE_Msk /;" d +CAN_IER_LECIE_Pos target/stm32f103xb.h /^#define CAN_IER_LECIE_Pos /;" d +CAN_IER_LECIE target/stm32f103xb.h /^#define CAN_IER_LECIE /;" d +CAN_IER_SLKIE_Msk target/stm32f103xb.h /^#define CAN_IER_SLKIE_Msk /;" d +CAN_IER_SLKIE_Pos target/stm32f103xb.h /^#define CAN_IER_SLKIE_Pos /;" d +CAN_IER_SLKIE target/stm32f103xb.h /^#define CAN_IER_SLKIE /;" d +CAN_IER_TMEIE_Msk target/stm32f103xb.h /^#define CAN_IER_TMEIE_Msk /;" d +CAN_IER_TMEIE_Pos target/stm32f103xb.h /^#define CAN_IER_TMEIE_Pos /;" d +CAN_IER_TMEIE target/stm32f103xb.h /^#define CAN_IER_TMEIE /;" d +CAN_IER_WKUIE_Msk target/stm32f103xb.h /^#define CAN_IER_WKUIE_Msk /;" d +CAN_IER_WKUIE_Pos target/stm32f103xb.h /^#define CAN_IER_WKUIE_Pos /;" d +CAN_IER_WKUIE target/stm32f103xb.h /^#define CAN_IER_WKUIE /;" d +CAN_MCR_ABOM_Msk target/stm32f103xb.h /^#define CAN_MCR_ABOM_Msk /;" d +CAN_MCR_ABOM_Pos target/stm32f103xb.h /^#define CAN_MCR_ABOM_Pos /;" d +CAN_MCR_ABOM target/stm32f103xb.h /^#define CAN_MCR_ABOM /;" d +CAN_MCR_AWUM_Msk target/stm32f103xb.h /^#define CAN_MCR_AWUM_Msk /;" d +CAN_MCR_AWUM_Pos target/stm32f103xb.h /^#define CAN_MCR_AWUM_Pos /;" d +CAN_MCR_AWUM target/stm32f103xb.h /^#define CAN_MCR_AWUM /;" d +CAN_MCR_DBF_Msk target/stm32f103xb.h /^#define CAN_MCR_DBF_Msk /;" d +CAN_MCR_DBF_Pos target/stm32f103xb.h /^#define CAN_MCR_DBF_Pos /;" d +CAN_MCR_DBF target/stm32f103xb.h /^#define CAN_MCR_DBF /;" d +CAN_MCR_INRQ_Msk target/stm32f103xb.h /^#define CAN_MCR_INRQ_Msk /;" d +CAN_MCR_INRQ_Pos target/stm32f103xb.h /^#define CAN_MCR_INRQ_Pos /;" d +CAN_MCR_INRQ target/stm32f103xb.h /^#define CAN_MCR_INRQ /;" d +CAN_MCR_NART_Msk target/stm32f103xb.h /^#define CAN_MCR_NART_Msk /;" d +CAN_MCR_NART_Pos target/stm32f103xb.h /^#define CAN_MCR_NART_Pos /;" d +CAN_MCR_NART target/stm32f103xb.h /^#define CAN_MCR_NART /;" d +CAN_MCR_RESET_Msk target/stm32f103xb.h /^#define CAN_MCR_RESET_Msk /;" d +CAN_MCR_RESET_Pos target/stm32f103xb.h /^#define CAN_MCR_RESET_Pos /;" d +CAN_MCR_RESET target/stm32f103xb.h /^#define CAN_MCR_RESET /;" d +CAN_MCR_RFLM_Msk target/stm32f103xb.h /^#define CAN_MCR_RFLM_Msk /;" d +CAN_MCR_RFLM_Pos target/stm32f103xb.h /^#define CAN_MCR_RFLM_Pos /;" d +CAN_MCR_RFLM target/stm32f103xb.h /^#define CAN_MCR_RFLM /;" d +CAN_MCR_SLEEP_Msk target/stm32f103xb.h /^#define CAN_MCR_SLEEP_Msk /;" d +CAN_MCR_SLEEP_Pos target/stm32f103xb.h /^#define CAN_MCR_SLEEP_Pos /;" d +CAN_MCR_SLEEP target/stm32f103xb.h /^#define CAN_MCR_SLEEP /;" d +CAN_MCR_TTCM_Msk target/stm32f103xb.h /^#define CAN_MCR_TTCM_Msk /;" d +CAN_MCR_TTCM_Pos target/stm32f103xb.h /^#define CAN_MCR_TTCM_Pos /;" d +CAN_MCR_TTCM target/stm32f103xb.h /^#define CAN_MCR_TTCM /;" d +CAN_MCR_TXFP_Msk target/stm32f103xb.h /^#define CAN_MCR_TXFP_Msk /;" d +CAN_MCR_TXFP_Pos target/stm32f103xb.h /^#define CAN_MCR_TXFP_Pos /;" d +CAN_MCR_TXFP target/stm32f103xb.h /^#define CAN_MCR_TXFP /;" d +CAN_MSR_ERRI_Msk target/stm32f103xb.h /^#define CAN_MSR_ERRI_Msk /;" d +CAN_MSR_ERRI_Pos target/stm32f103xb.h /^#define CAN_MSR_ERRI_Pos /;" d +CAN_MSR_ERRI target/stm32f103xb.h /^#define CAN_MSR_ERRI /;" d +CAN_MSR_INAK_Msk target/stm32f103xb.h /^#define CAN_MSR_INAK_Msk /;" d +CAN_MSR_INAK_Pos target/stm32f103xb.h /^#define CAN_MSR_INAK_Pos /;" d +CAN_MSR_INAK target/stm32f103xb.h /^#define CAN_MSR_INAK /;" d +CAN_MSR_RXM_Msk target/stm32f103xb.h /^#define CAN_MSR_RXM_Msk /;" d +CAN_MSR_RXM_Pos target/stm32f103xb.h /^#define CAN_MSR_RXM_Pos /;" d +CAN_MSR_RXM target/stm32f103xb.h /^#define CAN_MSR_RXM /;" d +CAN_MSR_RX_Msk target/stm32f103xb.h /^#define CAN_MSR_RX_Msk /;" d +CAN_MSR_RX_Pos target/stm32f103xb.h /^#define CAN_MSR_RX_Pos /;" d +CAN_MSR_RX target/stm32f103xb.h /^#define CAN_MSR_RX /;" d +CAN_MSR_SAMP_Msk target/stm32f103xb.h /^#define CAN_MSR_SAMP_Msk /;" d +CAN_MSR_SAMP_Pos target/stm32f103xb.h /^#define CAN_MSR_SAMP_Pos /;" d +CAN_MSR_SAMP target/stm32f103xb.h /^#define CAN_MSR_SAMP /;" d +CAN_MSR_SLAKI_Msk target/stm32f103xb.h /^#define CAN_MSR_SLAKI_Msk /;" d +CAN_MSR_SLAKI_Pos target/stm32f103xb.h /^#define CAN_MSR_SLAKI_Pos /;" d +CAN_MSR_SLAKI target/stm32f103xb.h /^#define CAN_MSR_SLAKI /;" d +CAN_MSR_SLAK_Msk target/stm32f103xb.h /^#define CAN_MSR_SLAK_Msk /;" d +CAN_MSR_SLAK_Pos target/stm32f103xb.h /^#define CAN_MSR_SLAK_Pos /;" d +CAN_MSR_SLAK target/stm32f103xb.h /^#define CAN_MSR_SLAK /;" d +CAN_MSR_TXM_Msk target/stm32f103xb.h /^#define CAN_MSR_TXM_Msk /;" d +CAN_MSR_TXM_Pos target/stm32f103xb.h /^#define CAN_MSR_TXM_Pos /;" d +CAN_MSR_TXM target/stm32f103xb.h /^#define CAN_MSR_TXM /;" d +CAN_MSR_WKUI_Msk target/stm32f103xb.h /^#define CAN_MSR_WKUI_Msk /;" d +CAN_MSR_WKUI_Pos target/stm32f103xb.h /^#define CAN_MSR_WKUI_Pos /;" d +CAN_MSR_WKUI target/stm32f103xb.h /^#define CAN_MSR_WKUI /;" d +CAN_RDH0R_DATA4_Msk target/stm32f103xb.h /^#define CAN_RDH0R_DATA4_Msk /;" d +CAN_RDH0R_DATA4_Pos target/stm32f103xb.h /^#define CAN_RDH0R_DATA4_Pos /;" d +CAN_RDH0R_DATA4 target/stm32f103xb.h /^#define CAN_RDH0R_DATA4 /;" d +CAN_RDH0R_DATA5_Msk target/stm32f103xb.h /^#define CAN_RDH0R_DATA5_Msk /;" d +CAN_RDH0R_DATA5_Pos target/stm32f103xb.h /^#define CAN_RDH0R_DATA5_Pos /;" d +CAN_RDH0R_DATA5 target/stm32f103xb.h /^#define CAN_RDH0R_DATA5 /;" d +CAN_RDH0R_DATA6_Msk target/stm32f103xb.h /^#define CAN_RDH0R_DATA6_Msk /;" d +CAN_RDH0R_DATA6_Pos target/stm32f103xb.h /^#define CAN_RDH0R_DATA6_Pos /;" d +CAN_RDH0R_DATA6 target/stm32f103xb.h /^#define CAN_RDH0R_DATA6 /;" d +CAN_RDH0R_DATA7_Msk target/stm32f103xb.h /^#define CAN_RDH0R_DATA7_Msk /;" d +CAN_RDH0R_DATA7_Pos target/stm32f103xb.h /^#define CAN_RDH0R_DATA7_Pos /;" d +CAN_RDH0R_DATA7 target/stm32f103xb.h /^#define CAN_RDH0R_DATA7 /;" d +CAN_RDH1R_DATA4_Msk target/stm32f103xb.h /^#define CAN_RDH1R_DATA4_Msk /;" d +CAN_RDH1R_DATA4_Pos target/stm32f103xb.h /^#define CAN_RDH1R_DATA4_Pos /;" d +CAN_RDH1R_DATA4 target/stm32f103xb.h /^#define CAN_RDH1R_DATA4 /;" d +CAN_RDH1R_DATA5_Msk target/stm32f103xb.h /^#define CAN_RDH1R_DATA5_Msk /;" d +CAN_RDH1R_DATA5_Pos target/stm32f103xb.h /^#define CAN_RDH1R_DATA5_Pos /;" d +CAN_RDH1R_DATA5 target/stm32f103xb.h /^#define CAN_RDH1R_DATA5 /;" d +CAN_RDH1R_DATA6_Msk target/stm32f103xb.h /^#define CAN_RDH1R_DATA6_Msk /;" d +CAN_RDH1R_DATA6_Pos target/stm32f103xb.h /^#define CAN_RDH1R_DATA6_Pos /;" d +CAN_RDH1R_DATA6 target/stm32f103xb.h /^#define CAN_RDH1R_DATA6 /;" d +CAN_RDH1R_DATA7_Msk target/stm32f103xb.h /^#define CAN_RDH1R_DATA7_Msk /;" d +CAN_RDH1R_DATA7_Pos target/stm32f103xb.h /^#define CAN_RDH1R_DATA7_Pos /;" d +CAN_RDH1R_DATA7 target/stm32f103xb.h /^#define CAN_RDH1R_DATA7 /;" d +CAN_RDL0R_DATA0_Msk target/stm32f103xb.h /^#define CAN_RDL0R_DATA0_Msk /;" d +CAN_RDL0R_DATA0_Pos target/stm32f103xb.h /^#define CAN_RDL0R_DATA0_Pos /;" d +CAN_RDL0R_DATA0 target/stm32f103xb.h /^#define CAN_RDL0R_DATA0 /;" d +CAN_RDL0R_DATA1_Msk target/stm32f103xb.h /^#define CAN_RDL0R_DATA1_Msk /;" d +CAN_RDL0R_DATA1_Pos target/stm32f103xb.h /^#define CAN_RDL0R_DATA1_Pos /;" d +CAN_RDL0R_DATA1 target/stm32f103xb.h /^#define CAN_RDL0R_DATA1 /;" d +CAN_RDL0R_DATA2_Msk target/stm32f103xb.h /^#define CAN_RDL0R_DATA2_Msk /;" d +CAN_RDL0R_DATA2_Pos target/stm32f103xb.h /^#define CAN_RDL0R_DATA2_Pos /;" d +CAN_RDL0R_DATA2 target/stm32f103xb.h /^#define CAN_RDL0R_DATA2 /;" d +CAN_RDL0R_DATA3_Msk target/stm32f103xb.h /^#define CAN_RDL0R_DATA3_Msk /;" d +CAN_RDL0R_DATA3_Pos target/stm32f103xb.h /^#define CAN_RDL0R_DATA3_Pos /;" d +CAN_RDL0R_DATA3 target/stm32f103xb.h /^#define CAN_RDL0R_DATA3 /;" d +CAN_RDL1R_DATA0_Msk target/stm32f103xb.h /^#define CAN_RDL1R_DATA0_Msk /;" d +CAN_RDL1R_DATA0_Pos target/stm32f103xb.h /^#define CAN_RDL1R_DATA0_Pos /;" d +CAN_RDL1R_DATA0 target/stm32f103xb.h /^#define CAN_RDL1R_DATA0 /;" d +CAN_RDL1R_DATA1_Msk target/stm32f103xb.h /^#define CAN_RDL1R_DATA1_Msk /;" d +CAN_RDL1R_DATA1_Pos target/stm32f103xb.h /^#define CAN_RDL1R_DATA1_Pos /;" d +CAN_RDL1R_DATA1 target/stm32f103xb.h /^#define CAN_RDL1R_DATA1 /;" d +CAN_RDL1R_DATA2_Msk target/stm32f103xb.h /^#define CAN_RDL1R_DATA2_Msk /;" d +CAN_RDL1R_DATA2_Pos target/stm32f103xb.h /^#define CAN_RDL1R_DATA2_Pos /;" d +CAN_RDL1R_DATA2 target/stm32f103xb.h /^#define CAN_RDL1R_DATA2 /;" d +CAN_RDL1R_DATA3_Msk target/stm32f103xb.h /^#define CAN_RDL1R_DATA3_Msk /;" d +CAN_RDL1R_DATA3_Pos target/stm32f103xb.h /^#define CAN_RDL1R_DATA3_Pos /;" d +CAN_RDL1R_DATA3 target/stm32f103xb.h /^#define CAN_RDL1R_DATA3 /;" d +CAN_RDT0R_DLC_Msk target/stm32f103xb.h /^#define CAN_RDT0R_DLC_Msk /;" d +CAN_RDT0R_DLC_Pos target/stm32f103xb.h /^#define CAN_RDT0R_DLC_Pos /;" d +CAN_RDT0R_DLC target/stm32f103xb.h /^#define CAN_RDT0R_DLC /;" d +CAN_RDT0R_FMI_Msk target/stm32f103xb.h /^#define CAN_RDT0R_FMI_Msk /;" d +CAN_RDT0R_FMI_Pos target/stm32f103xb.h /^#define CAN_RDT0R_FMI_Pos /;" d +CAN_RDT0R_FMI target/stm32f103xb.h /^#define CAN_RDT0R_FMI /;" d +CAN_RDT0R_TIME_Msk target/stm32f103xb.h /^#define CAN_RDT0R_TIME_Msk /;" d +CAN_RDT0R_TIME_Pos target/stm32f103xb.h /^#define CAN_RDT0R_TIME_Pos /;" d +CAN_RDT0R_TIME target/stm32f103xb.h /^#define CAN_RDT0R_TIME /;" d +CAN_RDT1R_DLC_Msk target/stm32f103xb.h /^#define CAN_RDT1R_DLC_Msk /;" d +CAN_RDT1R_DLC_Pos target/stm32f103xb.h /^#define CAN_RDT1R_DLC_Pos /;" d +CAN_RDT1R_DLC target/stm32f103xb.h /^#define CAN_RDT1R_DLC /;" d +CAN_RDT1R_FMI_Msk target/stm32f103xb.h /^#define CAN_RDT1R_FMI_Msk /;" d +CAN_RDT1R_FMI_Pos target/stm32f103xb.h /^#define CAN_RDT1R_FMI_Pos /;" d +CAN_RDT1R_FMI target/stm32f103xb.h /^#define CAN_RDT1R_FMI /;" d +CAN_RDT1R_TIME_Msk target/stm32f103xb.h /^#define CAN_RDT1R_TIME_Msk /;" d +CAN_RDT1R_TIME_Pos target/stm32f103xb.h /^#define CAN_RDT1R_TIME_Pos /;" d +CAN_RDT1R_TIME target/stm32f103xb.h /^#define CAN_RDT1R_TIME /;" d +CAN_RF0R_FMP0_Msk target/stm32f103xb.h /^#define CAN_RF0R_FMP0_Msk /;" d +CAN_RF0R_FMP0_Pos target/stm32f103xb.h /^#define CAN_RF0R_FMP0_Pos /;" d +CAN_RF0R_FMP0 target/stm32f103xb.h /^#define CAN_RF0R_FMP0 /;" d +CAN_RF0R_FOVR0_Msk target/stm32f103xb.h /^#define CAN_RF0R_FOVR0_Msk /;" d +CAN_RF0R_FOVR0_Pos target/stm32f103xb.h /^#define CAN_RF0R_FOVR0_Pos /;" d +CAN_RF0R_FOVR0 target/stm32f103xb.h /^#define CAN_RF0R_FOVR0 /;" d +CAN_RF0R_FULL0_Msk target/stm32f103xb.h /^#define CAN_RF0R_FULL0_Msk /;" d +CAN_RF0R_FULL0_Pos target/stm32f103xb.h /^#define CAN_RF0R_FULL0_Pos /;" d +CAN_RF0R_FULL0 target/stm32f103xb.h /^#define CAN_RF0R_FULL0 /;" d +CAN_RF0R_RFOM0_Msk target/stm32f103xb.h /^#define CAN_RF0R_RFOM0_Msk /;" d +CAN_RF0R_RFOM0_Pos target/stm32f103xb.h /^#define CAN_RF0R_RFOM0_Pos /;" d +CAN_RF0R_RFOM0 target/stm32f103xb.h /^#define CAN_RF0R_RFOM0 /;" d +CAN_RF1R_FMP1_Msk target/stm32f103xb.h /^#define CAN_RF1R_FMP1_Msk /;" d +CAN_RF1R_FMP1_Pos target/stm32f103xb.h /^#define CAN_RF1R_FMP1_Pos /;" d +CAN_RF1R_FMP1 target/stm32f103xb.h /^#define CAN_RF1R_FMP1 /;" d +CAN_RF1R_FOVR1_Msk target/stm32f103xb.h /^#define CAN_RF1R_FOVR1_Msk /;" d +CAN_RF1R_FOVR1_Pos target/stm32f103xb.h /^#define CAN_RF1R_FOVR1_Pos /;" d +CAN_RF1R_FOVR1 target/stm32f103xb.h /^#define CAN_RF1R_FOVR1 /;" d +CAN_RF1R_FULL1_Msk target/stm32f103xb.h /^#define CAN_RF1R_FULL1_Msk /;" d +CAN_RF1R_FULL1_Pos target/stm32f103xb.h /^#define CAN_RF1R_FULL1_Pos /;" d +CAN_RF1R_FULL1 target/stm32f103xb.h /^#define CAN_RF1R_FULL1 /;" d +CAN_RF1R_RFOM1_Msk target/stm32f103xb.h /^#define CAN_RF1R_RFOM1_Msk /;" d +CAN_RF1R_RFOM1_Pos target/stm32f103xb.h /^#define CAN_RF1R_RFOM1_Pos /;" d +CAN_RF1R_RFOM1 target/stm32f103xb.h /^#define CAN_RF1R_RFOM1 /;" d +CAN_RI0R_EXID_Msk target/stm32f103xb.h /^#define CAN_RI0R_EXID_Msk /;" d +CAN_RI0R_EXID_Pos target/stm32f103xb.h /^#define CAN_RI0R_EXID_Pos /;" d +CAN_RI0R_EXID target/stm32f103xb.h /^#define CAN_RI0R_EXID /;" d +CAN_RI0R_IDE_Msk target/stm32f103xb.h /^#define CAN_RI0R_IDE_Msk /;" d +CAN_RI0R_IDE_Pos target/stm32f103xb.h /^#define CAN_RI0R_IDE_Pos /;" d +CAN_RI0R_IDE target/stm32f103xb.h /^#define CAN_RI0R_IDE /;" d +CAN_RI0R_RTR_Msk target/stm32f103xb.h /^#define CAN_RI0R_RTR_Msk /;" d +CAN_RI0R_RTR_Pos target/stm32f103xb.h /^#define CAN_RI0R_RTR_Pos /;" d +CAN_RI0R_RTR target/stm32f103xb.h /^#define CAN_RI0R_RTR /;" d +CAN_RI0R_STID_Msk target/stm32f103xb.h /^#define CAN_RI0R_STID_Msk /;" d +CAN_RI0R_STID_Pos target/stm32f103xb.h /^#define CAN_RI0R_STID_Pos /;" d +CAN_RI0R_STID target/stm32f103xb.h /^#define CAN_RI0R_STID /;" d +CAN_RI1R_EXID_Msk target/stm32f103xb.h /^#define CAN_RI1R_EXID_Msk /;" d +CAN_RI1R_EXID_Pos target/stm32f103xb.h /^#define CAN_RI1R_EXID_Pos /;" d +CAN_RI1R_EXID target/stm32f103xb.h /^#define CAN_RI1R_EXID /;" d +CAN_RI1R_IDE_Msk target/stm32f103xb.h /^#define CAN_RI1R_IDE_Msk /;" d +CAN_RI1R_IDE_Pos target/stm32f103xb.h /^#define CAN_RI1R_IDE_Pos /;" d +CAN_RI1R_IDE target/stm32f103xb.h /^#define CAN_RI1R_IDE /;" d +CAN_RI1R_RTR_Msk target/stm32f103xb.h /^#define CAN_RI1R_RTR_Msk /;" d +CAN_RI1R_RTR_Pos target/stm32f103xb.h /^#define CAN_RI1R_RTR_Pos /;" d +CAN_RI1R_RTR target/stm32f103xb.h /^#define CAN_RI1R_RTR /;" d +CAN_RI1R_STID_Msk target/stm32f103xb.h /^#define CAN_RI1R_STID_Msk /;" d +CAN_RI1R_STID_Pos target/stm32f103xb.h /^#define CAN_RI1R_STID_Pos /;" d +CAN_RI1R_STID target/stm32f103xb.h /^#define CAN_RI1R_STID /;" d +CAN_TDH0R_DATA4_Msk target/stm32f103xb.h /^#define CAN_TDH0R_DATA4_Msk /;" d +CAN_TDH0R_DATA4_Pos target/stm32f103xb.h /^#define CAN_TDH0R_DATA4_Pos /;" d +CAN_TDH0R_DATA4 target/stm32f103xb.h /^#define CAN_TDH0R_DATA4 /;" d +CAN_TDH0R_DATA5_Msk target/stm32f103xb.h /^#define CAN_TDH0R_DATA5_Msk /;" d +CAN_TDH0R_DATA5_Pos target/stm32f103xb.h /^#define CAN_TDH0R_DATA5_Pos /;" d +CAN_TDH0R_DATA5 target/stm32f103xb.h /^#define CAN_TDH0R_DATA5 /;" d +CAN_TDH0R_DATA6_Msk target/stm32f103xb.h /^#define CAN_TDH0R_DATA6_Msk /;" d +CAN_TDH0R_DATA6_Pos target/stm32f103xb.h /^#define CAN_TDH0R_DATA6_Pos /;" d +CAN_TDH0R_DATA6 target/stm32f103xb.h /^#define CAN_TDH0R_DATA6 /;" d +CAN_TDH0R_DATA7_Msk target/stm32f103xb.h /^#define CAN_TDH0R_DATA7_Msk /;" d +CAN_TDH0R_DATA7_Pos target/stm32f103xb.h /^#define CAN_TDH0R_DATA7_Pos /;" d +CAN_TDH0R_DATA7 target/stm32f103xb.h /^#define CAN_TDH0R_DATA7 /;" d +CAN_TDH1R_DATA4_Msk target/stm32f103xb.h /^#define CAN_TDH1R_DATA4_Msk /;" d +CAN_TDH1R_DATA4_Pos target/stm32f103xb.h /^#define CAN_TDH1R_DATA4_Pos /;" d +CAN_TDH1R_DATA4 target/stm32f103xb.h /^#define CAN_TDH1R_DATA4 /;" d +CAN_TDH1R_DATA5_Msk target/stm32f103xb.h /^#define CAN_TDH1R_DATA5_Msk /;" d +CAN_TDH1R_DATA5_Pos target/stm32f103xb.h /^#define CAN_TDH1R_DATA5_Pos /;" d +CAN_TDH1R_DATA5 target/stm32f103xb.h /^#define CAN_TDH1R_DATA5 /;" d +CAN_TDH1R_DATA6_Msk target/stm32f103xb.h /^#define CAN_TDH1R_DATA6_Msk /;" d +CAN_TDH1R_DATA6_Pos target/stm32f103xb.h /^#define CAN_TDH1R_DATA6_Pos /;" d +CAN_TDH1R_DATA6 target/stm32f103xb.h /^#define CAN_TDH1R_DATA6 /;" d +CAN_TDH1R_DATA7_Msk target/stm32f103xb.h /^#define CAN_TDH1R_DATA7_Msk /;" d +CAN_TDH1R_DATA7_Pos target/stm32f103xb.h /^#define CAN_TDH1R_DATA7_Pos /;" d +CAN_TDH1R_DATA7 target/stm32f103xb.h /^#define CAN_TDH1R_DATA7 /;" d +CAN_TDH2R_DATA4_Msk target/stm32f103xb.h /^#define CAN_TDH2R_DATA4_Msk /;" d +CAN_TDH2R_DATA4_Pos target/stm32f103xb.h /^#define CAN_TDH2R_DATA4_Pos /;" d +CAN_TDH2R_DATA4 target/stm32f103xb.h /^#define CAN_TDH2R_DATA4 /;" d +CAN_TDH2R_DATA5_Msk target/stm32f103xb.h /^#define CAN_TDH2R_DATA5_Msk /;" d +CAN_TDH2R_DATA5_Pos target/stm32f103xb.h /^#define CAN_TDH2R_DATA5_Pos /;" d +CAN_TDH2R_DATA5 target/stm32f103xb.h /^#define CAN_TDH2R_DATA5 /;" d +CAN_TDH2R_DATA6_Msk target/stm32f103xb.h /^#define CAN_TDH2R_DATA6_Msk /;" d +CAN_TDH2R_DATA6_Pos target/stm32f103xb.h /^#define CAN_TDH2R_DATA6_Pos /;" d +CAN_TDH2R_DATA6 target/stm32f103xb.h /^#define CAN_TDH2R_DATA6 /;" d +CAN_TDH2R_DATA7_Msk target/stm32f103xb.h /^#define CAN_TDH2R_DATA7_Msk /;" d +CAN_TDH2R_DATA7_Pos target/stm32f103xb.h /^#define CAN_TDH2R_DATA7_Pos /;" d +CAN_TDH2R_DATA7 target/stm32f103xb.h /^#define CAN_TDH2R_DATA7 /;" d +CAN_TDL0R_DATA0_Msk target/stm32f103xb.h /^#define CAN_TDL0R_DATA0_Msk /;" d +CAN_TDL0R_DATA0_Pos target/stm32f103xb.h /^#define CAN_TDL0R_DATA0_Pos /;" d +CAN_TDL0R_DATA0 target/stm32f103xb.h /^#define CAN_TDL0R_DATA0 /;" d +CAN_TDL0R_DATA1_Msk target/stm32f103xb.h /^#define CAN_TDL0R_DATA1_Msk /;" d +CAN_TDL0R_DATA1_Pos target/stm32f103xb.h /^#define CAN_TDL0R_DATA1_Pos /;" d +CAN_TDL0R_DATA1 target/stm32f103xb.h /^#define CAN_TDL0R_DATA1 /;" d +CAN_TDL0R_DATA2_Msk target/stm32f103xb.h /^#define CAN_TDL0R_DATA2_Msk /;" d +CAN_TDL0R_DATA2_Pos target/stm32f103xb.h /^#define CAN_TDL0R_DATA2_Pos /;" d +CAN_TDL0R_DATA2 target/stm32f103xb.h /^#define CAN_TDL0R_DATA2 /;" d +CAN_TDL0R_DATA3_Msk target/stm32f103xb.h /^#define CAN_TDL0R_DATA3_Msk /;" d +CAN_TDL0R_DATA3_Pos target/stm32f103xb.h /^#define CAN_TDL0R_DATA3_Pos /;" d +CAN_TDL0R_DATA3 target/stm32f103xb.h /^#define CAN_TDL0R_DATA3 /;" d +CAN_TDL1R_DATA0_Msk target/stm32f103xb.h /^#define CAN_TDL1R_DATA0_Msk /;" d +CAN_TDL1R_DATA0_Pos target/stm32f103xb.h /^#define CAN_TDL1R_DATA0_Pos /;" d +CAN_TDL1R_DATA0 target/stm32f103xb.h /^#define CAN_TDL1R_DATA0 /;" d +CAN_TDL1R_DATA1_Msk target/stm32f103xb.h /^#define CAN_TDL1R_DATA1_Msk /;" d +CAN_TDL1R_DATA1_Pos target/stm32f103xb.h /^#define CAN_TDL1R_DATA1_Pos /;" d +CAN_TDL1R_DATA1 target/stm32f103xb.h /^#define CAN_TDL1R_DATA1 /;" d +CAN_TDL1R_DATA2_Msk target/stm32f103xb.h /^#define CAN_TDL1R_DATA2_Msk /;" d +CAN_TDL1R_DATA2_Pos target/stm32f103xb.h /^#define CAN_TDL1R_DATA2_Pos /;" d +CAN_TDL1R_DATA2 target/stm32f103xb.h /^#define CAN_TDL1R_DATA2 /;" d +CAN_TDL1R_DATA3_Msk target/stm32f103xb.h /^#define CAN_TDL1R_DATA3_Msk /;" d +CAN_TDL1R_DATA3_Pos target/stm32f103xb.h /^#define CAN_TDL1R_DATA3_Pos /;" d +CAN_TDL1R_DATA3 target/stm32f103xb.h /^#define CAN_TDL1R_DATA3 /;" d +CAN_TDL2R_DATA0_Msk target/stm32f103xb.h /^#define CAN_TDL2R_DATA0_Msk /;" d +CAN_TDL2R_DATA0_Pos target/stm32f103xb.h /^#define CAN_TDL2R_DATA0_Pos /;" d +CAN_TDL2R_DATA0 target/stm32f103xb.h /^#define CAN_TDL2R_DATA0 /;" d +CAN_TDL2R_DATA1_Msk target/stm32f103xb.h /^#define CAN_TDL2R_DATA1_Msk /;" d +CAN_TDL2R_DATA1_Pos target/stm32f103xb.h /^#define CAN_TDL2R_DATA1_Pos /;" d +CAN_TDL2R_DATA1 target/stm32f103xb.h /^#define CAN_TDL2R_DATA1 /;" d +CAN_TDL2R_DATA2_Msk target/stm32f103xb.h /^#define CAN_TDL2R_DATA2_Msk /;" d +CAN_TDL2R_DATA2_Pos target/stm32f103xb.h /^#define CAN_TDL2R_DATA2_Pos /;" d +CAN_TDL2R_DATA2 target/stm32f103xb.h /^#define CAN_TDL2R_DATA2 /;" d +CAN_TDL2R_DATA3_Msk target/stm32f103xb.h /^#define CAN_TDL2R_DATA3_Msk /;" d +CAN_TDL2R_DATA3_Pos target/stm32f103xb.h /^#define CAN_TDL2R_DATA3_Pos /;" d +CAN_TDL2R_DATA3 target/stm32f103xb.h /^#define CAN_TDL2R_DATA3 /;" d +CAN_TDT0R_DLC_Msk target/stm32f103xb.h /^#define CAN_TDT0R_DLC_Msk /;" d +CAN_TDT0R_DLC_Pos target/stm32f103xb.h /^#define CAN_TDT0R_DLC_Pos /;" d +CAN_TDT0R_DLC target/stm32f103xb.h /^#define CAN_TDT0R_DLC /;" d +CAN_TDT0R_TGT_Msk target/stm32f103xb.h /^#define CAN_TDT0R_TGT_Msk /;" d +CAN_TDT0R_TGT_Pos target/stm32f103xb.h /^#define CAN_TDT0R_TGT_Pos /;" d +CAN_TDT0R_TGT target/stm32f103xb.h /^#define CAN_TDT0R_TGT /;" d +CAN_TDT0R_TIME_Msk target/stm32f103xb.h /^#define CAN_TDT0R_TIME_Msk /;" d +CAN_TDT0R_TIME_Pos target/stm32f103xb.h /^#define CAN_TDT0R_TIME_Pos /;" d +CAN_TDT0R_TIME target/stm32f103xb.h /^#define CAN_TDT0R_TIME /;" d +CAN_TDT1R_DLC_Msk target/stm32f103xb.h /^#define CAN_TDT1R_DLC_Msk /;" d +CAN_TDT1R_DLC_Pos target/stm32f103xb.h /^#define CAN_TDT1R_DLC_Pos /;" d +CAN_TDT1R_DLC target/stm32f103xb.h /^#define CAN_TDT1R_DLC /;" d +CAN_TDT1R_TGT_Msk target/stm32f103xb.h /^#define CAN_TDT1R_TGT_Msk /;" d +CAN_TDT1R_TGT_Pos target/stm32f103xb.h /^#define CAN_TDT1R_TGT_Pos /;" d +CAN_TDT1R_TGT target/stm32f103xb.h /^#define CAN_TDT1R_TGT /;" d +CAN_TDT1R_TIME_Msk target/stm32f103xb.h /^#define CAN_TDT1R_TIME_Msk /;" d +CAN_TDT1R_TIME_Pos target/stm32f103xb.h /^#define CAN_TDT1R_TIME_Pos /;" d +CAN_TDT1R_TIME target/stm32f103xb.h /^#define CAN_TDT1R_TIME /;" d +CAN_TDT2R_DLC_Msk target/stm32f103xb.h /^#define CAN_TDT2R_DLC_Msk /;" d +CAN_TDT2R_DLC_Pos target/stm32f103xb.h /^#define CAN_TDT2R_DLC_Pos /;" d +CAN_TDT2R_DLC target/stm32f103xb.h /^#define CAN_TDT2R_DLC /;" d +CAN_TDT2R_TGT_Msk target/stm32f103xb.h /^#define CAN_TDT2R_TGT_Msk /;" d +CAN_TDT2R_TGT_Pos target/stm32f103xb.h /^#define CAN_TDT2R_TGT_Pos /;" d +CAN_TDT2R_TGT target/stm32f103xb.h /^#define CAN_TDT2R_TGT /;" d +CAN_TDT2R_TIME_Msk target/stm32f103xb.h /^#define CAN_TDT2R_TIME_Msk /;" d +CAN_TDT2R_TIME_Pos target/stm32f103xb.h /^#define CAN_TDT2R_TIME_Pos /;" d +CAN_TDT2R_TIME target/stm32f103xb.h /^#define CAN_TDT2R_TIME /;" d +CAN_TI0R_EXID_Msk target/stm32f103xb.h /^#define CAN_TI0R_EXID_Msk /;" d +CAN_TI0R_EXID_Pos target/stm32f103xb.h /^#define CAN_TI0R_EXID_Pos /;" d +CAN_TI0R_EXID target/stm32f103xb.h /^#define CAN_TI0R_EXID /;" d +CAN_TI0R_IDE_Msk target/stm32f103xb.h /^#define CAN_TI0R_IDE_Msk /;" d +CAN_TI0R_IDE_Pos target/stm32f103xb.h /^#define CAN_TI0R_IDE_Pos /;" d +CAN_TI0R_IDE target/stm32f103xb.h /^#define CAN_TI0R_IDE /;" d +CAN_TI0R_RTR_Msk target/stm32f103xb.h /^#define CAN_TI0R_RTR_Msk /;" d +CAN_TI0R_RTR_Pos target/stm32f103xb.h /^#define CAN_TI0R_RTR_Pos /;" d +CAN_TI0R_RTR target/stm32f103xb.h /^#define CAN_TI0R_RTR /;" d +CAN_TI0R_STID_Msk target/stm32f103xb.h /^#define CAN_TI0R_STID_Msk /;" d +CAN_TI0R_STID_Pos target/stm32f103xb.h /^#define CAN_TI0R_STID_Pos /;" d +CAN_TI0R_STID target/stm32f103xb.h /^#define CAN_TI0R_STID /;" d +CAN_TI0R_TXRQ_Msk target/stm32f103xb.h /^#define CAN_TI0R_TXRQ_Msk /;" d +CAN_TI0R_TXRQ_Pos target/stm32f103xb.h /^#define CAN_TI0R_TXRQ_Pos /;" d +CAN_TI0R_TXRQ target/stm32f103xb.h /^#define CAN_TI0R_TXRQ /;" d +CAN_TI1R_EXID_Msk target/stm32f103xb.h /^#define CAN_TI1R_EXID_Msk /;" d +CAN_TI1R_EXID_Pos target/stm32f103xb.h /^#define CAN_TI1R_EXID_Pos /;" d +CAN_TI1R_EXID target/stm32f103xb.h /^#define CAN_TI1R_EXID /;" d +CAN_TI1R_IDE_Msk target/stm32f103xb.h /^#define CAN_TI1R_IDE_Msk /;" d +CAN_TI1R_IDE_Pos target/stm32f103xb.h /^#define CAN_TI1R_IDE_Pos /;" d +CAN_TI1R_IDE target/stm32f103xb.h /^#define CAN_TI1R_IDE /;" d +CAN_TI1R_RTR_Msk target/stm32f103xb.h /^#define CAN_TI1R_RTR_Msk /;" d +CAN_TI1R_RTR_Pos target/stm32f103xb.h /^#define CAN_TI1R_RTR_Pos /;" d +CAN_TI1R_RTR target/stm32f103xb.h /^#define CAN_TI1R_RTR /;" d +CAN_TI1R_STID_Msk target/stm32f103xb.h /^#define CAN_TI1R_STID_Msk /;" d +CAN_TI1R_STID_Pos target/stm32f103xb.h /^#define CAN_TI1R_STID_Pos /;" d +CAN_TI1R_STID target/stm32f103xb.h /^#define CAN_TI1R_STID /;" d +CAN_TI1R_TXRQ_Msk target/stm32f103xb.h /^#define CAN_TI1R_TXRQ_Msk /;" d +CAN_TI1R_TXRQ_Pos target/stm32f103xb.h /^#define CAN_TI1R_TXRQ_Pos /;" d +CAN_TI1R_TXRQ target/stm32f103xb.h /^#define CAN_TI1R_TXRQ /;" d +CAN_TI2R_EXID_Msk target/stm32f103xb.h /^#define CAN_TI2R_EXID_Msk /;" d +CAN_TI2R_EXID_Pos target/stm32f103xb.h /^#define CAN_TI2R_EXID_Pos /;" d +CAN_TI2R_EXID target/stm32f103xb.h /^#define CAN_TI2R_EXID /;" d +CAN_TI2R_IDE_Msk target/stm32f103xb.h /^#define CAN_TI2R_IDE_Msk /;" d +CAN_TI2R_IDE_Pos target/stm32f103xb.h /^#define CAN_TI2R_IDE_Pos /;" d +CAN_TI2R_IDE target/stm32f103xb.h /^#define CAN_TI2R_IDE /;" d +CAN_TI2R_RTR_Msk target/stm32f103xb.h /^#define CAN_TI2R_RTR_Msk /;" d +CAN_TI2R_RTR_Pos target/stm32f103xb.h /^#define CAN_TI2R_RTR_Pos /;" d +CAN_TI2R_RTR target/stm32f103xb.h /^#define CAN_TI2R_RTR /;" d +CAN_TI2R_STID_Msk target/stm32f103xb.h /^#define CAN_TI2R_STID_Msk /;" d +CAN_TI2R_STID_Pos target/stm32f103xb.h /^#define CAN_TI2R_STID_Pos /;" d +CAN_TI2R_STID target/stm32f103xb.h /^#define CAN_TI2R_STID /;" d +CAN_TI2R_TXRQ_Msk target/stm32f103xb.h /^#define CAN_TI2R_TXRQ_Msk /;" d +CAN_TI2R_TXRQ_Pos target/stm32f103xb.h /^#define CAN_TI2R_TXRQ_Pos /;" d +CAN_TI2R_TXRQ target/stm32f103xb.h /^#define CAN_TI2R_TXRQ /;" d +CAN_TSR_ABRQ0_Msk target/stm32f103xb.h /^#define CAN_TSR_ABRQ0_Msk /;" d +CAN_TSR_ABRQ0_Pos target/stm32f103xb.h /^#define CAN_TSR_ABRQ0_Pos /;" d +CAN_TSR_ABRQ0 target/stm32f103xb.h /^#define CAN_TSR_ABRQ0 /;" d +CAN_TSR_ABRQ1_Msk target/stm32f103xb.h /^#define CAN_TSR_ABRQ1_Msk /;" d +CAN_TSR_ABRQ1_Pos target/stm32f103xb.h /^#define CAN_TSR_ABRQ1_Pos /;" d +CAN_TSR_ABRQ1 target/stm32f103xb.h /^#define CAN_TSR_ABRQ1 /;" d +CAN_TSR_ABRQ2_Msk target/stm32f103xb.h /^#define CAN_TSR_ABRQ2_Msk /;" d +CAN_TSR_ABRQ2_Pos target/stm32f103xb.h /^#define CAN_TSR_ABRQ2_Pos /;" d +CAN_TSR_ABRQ2 target/stm32f103xb.h /^#define CAN_TSR_ABRQ2 /;" d +CAN_TSR_ALST0_Msk target/stm32f103xb.h /^#define CAN_TSR_ALST0_Msk /;" d +CAN_TSR_ALST0_Pos target/stm32f103xb.h /^#define CAN_TSR_ALST0_Pos /;" d +CAN_TSR_ALST0 target/stm32f103xb.h /^#define CAN_TSR_ALST0 /;" d +CAN_TSR_ALST1_Msk target/stm32f103xb.h /^#define CAN_TSR_ALST1_Msk /;" d +CAN_TSR_ALST1_Pos target/stm32f103xb.h /^#define CAN_TSR_ALST1_Pos /;" d +CAN_TSR_ALST1 target/stm32f103xb.h /^#define CAN_TSR_ALST1 /;" d +CAN_TSR_ALST2_Msk target/stm32f103xb.h /^#define CAN_TSR_ALST2_Msk /;" d +CAN_TSR_ALST2_Pos target/stm32f103xb.h /^#define CAN_TSR_ALST2_Pos /;" d +CAN_TSR_ALST2 target/stm32f103xb.h /^#define CAN_TSR_ALST2 /;" d +CAN_TSR_CODE_Msk target/stm32f103xb.h /^#define CAN_TSR_CODE_Msk /;" d +CAN_TSR_CODE_Pos target/stm32f103xb.h /^#define CAN_TSR_CODE_Pos /;" d +CAN_TSR_CODE target/stm32f103xb.h /^#define CAN_TSR_CODE /;" d +CAN_TSR_LOW0_Msk target/stm32f103xb.h /^#define CAN_TSR_LOW0_Msk /;" d +CAN_TSR_LOW0_Pos target/stm32f103xb.h /^#define CAN_TSR_LOW0_Pos /;" d +CAN_TSR_LOW0 target/stm32f103xb.h /^#define CAN_TSR_LOW0 /;" d +CAN_TSR_LOW1_Msk target/stm32f103xb.h /^#define CAN_TSR_LOW1_Msk /;" d +CAN_TSR_LOW1_Pos target/stm32f103xb.h /^#define CAN_TSR_LOW1_Pos /;" d +CAN_TSR_LOW1 target/stm32f103xb.h /^#define CAN_TSR_LOW1 /;" d +CAN_TSR_LOW2_Msk target/stm32f103xb.h /^#define CAN_TSR_LOW2_Msk /;" d +CAN_TSR_LOW2_Pos target/stm32f103xb.h /^#define CAN_TSR_LOW2_Pos /;" d +CAN_TSR_LOW2 target/stm32f103xb.h /^#define CAN_TSR_LOW2 /;" d +CAN_TSR_LOW_Msk target/stm32f103xb.h /^#define CAN_TSR_LOW_Msk /;" d +CAN_TSR_LOW_Pos target/stm32f103xb.h /^#define CAN_TSR_LOW_Pos /;" d +CAN_TSR_LOW target/stm32f103xb.h /^#define CAN_TSR_LOW /;" d +CAN_TSR_RQCP0_Msk target/stm32f103xb.h /^#define CAN_TSR_RQCP0_Msk /;" d +CAN_TSR_RQCP0_Pos target/stm32f103xb.h /^#define CAN_TSR_RQCP0_Pos /;" d +CAN_TSR_RQCP0 target/stm32f103xb.h /^#define CAN_TSR_RQCP0 /;" d +CAN_TSR_RQCP1_Msk target/stm32f103xb.h /^#define CAN_TSR_RQCP1_Msk /;" d +CAN_TSR_RQCP1_Pos target/stm32f103xb.h /^#define CAN_TSR_RQCP1_Pos /;" d +CAN_TSR_RQCP1 target/stm32f103xb.h /^#define CAN_TSR_RQCP1 /;" d +CAN_TSR_RQCP2_Msk target/stm32f103xb.h /^#define CAN_TSR_RQCP2_Msk /;" d +CAN_TSR_RQCP2_Pos target/stm32f103xb.h /^#define CAN_TSR_RQCP2_Pos /;" d +CAN_TSR_RQCP2 target/stm32f103xb.h /^#define CAN_TSR_RQCP2 /;" d +CAN_TSR_TERR0_Msk target/stm32f103xb.h /^#define CAN_TSR_TERR0_Msk /;" d +CAN_TSR_TERR0_Pos target/stm32f103xb.h /^#define CAN_TSR_TERR0_Pos /;" d +CAN_TSR_TERR0 target/stm32f103xb.h /^#define CAN_TSR_TERR0 /;" d +CAN_TSR_TERR1_Msk target/stm32f103xb.h /^#define CAN_TSR_TERR1_Msk /;" d +CAN_TSR_TERR1_Pos target/stm32f103xb.h /^#define CAN_TSR_TERR1_Pos /;" d +CAN_TSR_TERR1 target/stm32f103xb.h /^#define CAN_TSR_TERR1 /;" d +CAN_TSR_TERR2_Msk target/stm32f103xb.h /^#define CAN_TSR_TERR2_Msk /;" d +CAN_TSR_TERR2_Pos target/stm32f103xb.h /^#define CAN_TSR_TERR2_Pos /;" d +CAN_TSR_TERR2 target/stm32f103xb.h /^#define CAN_TSR_TERR2 /;" d +CAN_TSR_TME0_Msk target/stm32f103xb.h /^#define CAN_TSR_TME0_Msk /;" d +CAN_TSR_TME0_Pos target/stm32f103xb.h /^#define CAN_TSR_TME0_Pos /;" d +CAN_TSR_TME0 target/stm32f103xb.h /^#define CAN_TSR_TME0 /;" d +CAN_TSR_TME1_Msk target/stm32f103xb.h /^#define CAN_TSR_TME1_Msk /;" d +CAN_TSR_TME1_Pos target/stm32f103xb.h /^#define CAN_TSR_TME1_Pos /;" d +CAN_TSR_TME1 target/stm32f103xb.h /^#define CAN_TSR_TME1 /;" d +CAN_TSR_TME2_Msk target/stm32f103xb.h /^#define CAN_TSR_TME2_Msk /;" d +CAN_TSR_TME2_Pos target/stm32f103xb.h /^#define CAN_TSR_TME2_Pos /;" d +CAN_TSR_TME2 target/stm32f103xb.h /^#define CAN_TSR_TME2 /;" d +CAN_TSR_TME_Msk target/stm32f103xb.h /^#define CAN_TSR_TME_Msk /;" d +CAN_TSR_TME_Pos target/stm32f103xb.h /^#define CAN_TSR_TME_Pos /;" d +CAN_TSR_TME target/stm32f103xb.h /^#define CAN_TSR_TME /;" d +CAN_TSR_TXOK0_Msk target/stm32f103xb.h /^#define CAN_TSR_TXOK0_Msk /;" d +CAN_TSR_TXOK0_Pos target/stm32f103xb.h /^#define CAN_TSR_TXOK0_Pos /;" d +CAN_TSR_TXOK0 target/stm32f103xb.h /^#define CAN_TSR_TXOK0 /;" d +CAN_TSR_TXOK1_Msk target/stm32f103xb.h /^#define CAN_TSR_TXOK1_Msk /;" d +CAN_TSR_TXOK1_Pos target/stm32f103xb.h /^#define CAN_TSR_TXOK1_Pos /;" d +CAN_TSR_TXOK1 target/stm32f103xb.h /^#define CAN_TSR_TXOK1 /;" d +CAN_TSR_TXOK2_Msk target/stm32f103xb.h /^#define CAN_TSR_TXOK2_Msk /;" d +CAN_TSR_TXOK2_Pos target/stm32f103xb.h /^#define CAN_TSR_TXOK2_Pos /;" d +CAN_TSR_TXOK2 target/stm32f103xb.h /^#define CAN_TSR_TXOK2 /;" d +CAN_TxMailBox_TypeDef target/stm32f103xb.h /^} CAN_TxMailBox_TypeDef;$/;" t typeref:struct:__anon72c4c37e0508 +CAN_TypeDef target/stm32f103xb.h /^} CAN_TypeDef;$/;" t typeref:struct:__anon72c4c37e0808 +CCER target/stm32f103xb.h /^ __IO uint32_t CCER; \/*!< TIM capture\/compare enable register, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCMR1 target/stm32f103xb.h /^ __IO uint32_t CCMR1; \/*!< TIM capture\/compare mode register 1, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCMR2 target/stm32f103xb.h /^ __IO uint32_t CCMR2; \/*!< TIM capture\/compare mode register 2, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCR1 target/stm32f103xb.h /^ __IO uint32_t CCR1; \/*!< TIM capture\/compare register 1, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCR2 target/stm32f103xb.h /^ __IO uint32_t CCR2; \/*!< TIM capture\/compare register 2, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCR3 target/stm32f103xb.h /^ __IO uint32_t CCR3; \/*!< TIM capture\/compare register 3, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCR4 target/stm32f103xb.h /^ __IO uint32_t CCR4; \/*!< TIM capture\/compare register 4, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CCR target/stm32f103xb.h /^ __IO uint32_t CCR;$/;" m struct:__anon72c4c37e0b08 typeref:typename:__IO uint32_t +CCR target/stm32f103xb.h /^ __IO uint32_t CCR;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +CEC_IRQHandler target/stm32f103xb.h /^#define CEC_IRQHandler /;" d +CEC_IRQn target/stm32f103xb.h /^#define CEC_IRQn /;" d +CFGR target/stm32f103xb.h /^ __IO uint32_t CFGR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +CFR target/stm32f103xb.h /^ __IO uint32_t CFR; \/*!< WWDG Configuration register, Address offset: 0x04 *\/$/;" m struct:__anon72c4c37e1c08 typeref:typename:__IO uint32_t +CIR target/stm32f103xb.h /^ __IO uint32_t CIR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +CLEAR_BIT target/stm32f1xx.h /^#define CLEAR_BIT(/;" d +CLEAR_REG target/stm32f1xx.h /^#define CLEAR_REG(/;" d +CLKCR target/stm32f103xb.h /^ __IO uint32_t CLKCR;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +CLOCK_CONFIG_END Untitled Folder/rcc.h /^ CLOCK_CONFIG_END$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_END drivers/rcc.h /^ CLOCK_CONFIG_END$/;" e enum:Clock_config +CLOCK_CONFIG_HSE_48MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSE_48MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSE_84MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSE_84MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSE_8MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSE_8MHz=0,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSE_96MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSE_96MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSI_16MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSI_16MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSI_48MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSI_48MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSI_84MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSI_84MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_HSI_96MHz Untitled Folder/rcc.h /^ CLOCK_CONFIG_HSI_96MHz,$/;" e enum:__anon571959e70103 +CLOCK_CONFIG_PERFORMANCE drivers/rcc.h /^ CLOCK_CONFIG_PERFORMANCE,$/;" e enum:Clock_config +CLOCK_CONFIG_POWERSAVE drivers/rcc.h /^ CLOCK_CONFIG_POWERSAVE,$/;" e enum:Clock_config +CMAR target/stm32f103xb.h /^ __IO uint32_t CMAR;$/;" m struct:__anon72c4c37e0b08 typeref:typename:__IO uint32_t +CMD target/stm32f103xb.h /^ __IO uint32_t CMD;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +CNDTR target/stm32f103xb.h /^ __IO uint32_t CNDTR;$/;" m struct:__anon72c4c37e0b08 typeref:typename:__IO uint32_t +CNTH target/stm32f103xb.h /^ __IO uint32_t CNTH;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +CNTL target/stm32f103xb.h /^ __IO uint32_t CNTL;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +CNTR target/stm32f103xb.h /^ __IO uint16_t CNTR; \/*!< Control register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +CNT target/stm32f103xb.h /^ __IO uint32_t CNT; \/*!< TIM counter register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CPAR target/stm32f103xb.h /^ __IO uint32_t CPAR;$/;" m struct:__anon72c4c37e0b08 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1; \/*!< ADC control register 1, used for ADC multimode (bits com/;" m struct:__anon72c4c37e0308 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1; \/*!< TIM control register 1, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1; \/*!< USART Control register 1, Address offset: 0x0C /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +CR1 target/stm32f103xb.h /^ __IO uint32_t CR1;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2; \/*!< ADC control register 2, used for ADC multimode (bits com/;" m struct:__anon72c4c37e0308 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2; \/*!< TIM control register 2, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2; \/*!< USART Control register 2, Address offset: 0x10 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +CR2 target/stm32f103xb.h /^ __IO uint32_t CR2;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +CR3 target/stm32f103xb.h /^ __IO uint32_t CR3; \/*!< USART Control register 3, Address offset: 0x14 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +CRCPR target/stm32f103xb.h /^ __IO uint32_t CRCPR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +CRC_BASE target/stm32f103xb.h /^#define CRC_BASE /;" d +CRC_CR_RESET_Msk target/stm32f103xb.h /^#define CRC_CR_RESET_Msk /;" d +CRC_CR_RESET_Pos target/stm32f103xb.h /^#define CRC_CR_RESET_Pos /;" d +CRC_CR_RESET target/stm32f103xb.h /^#define CRC_CR_RESET /;" d +CRC_DR_DR_Msk target/stm32f103xb.h /^#define CRC_DR_DR_Msk /;" d +CRC_DR_DR_Pos target/stm32f103xb.h /^#define CRC_DR_DR_Pos /;" d +CRC_DR_DR target/stm32f103xb.h /^#define CRC_DR_DR /;" d +CRC_IDR_IDR_Msk target/stm32f103xb.h /^#define CRC_IDR_IDR_Msk /;" d +CRC_IDR_IDR_Pos target/stm32f103xb.h /^#define CRC_IDR_IDR_Pos /;" d +CRC_IDR_IDR target/stm32f103xb.h /^#define CRC_IDR_IDR /;" d +CRC_TypeDef target/stm32f103xb.h /^} CRC_TypeDef;$/;" t typeref:struct:__anon72c4c37e0908 +CRC target/stm32f103xb.h /^#define CRC /;" d +CRH target/stm32f103xb.h /^ __IO uint32_t CRH;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +CRH target/stm32f103xb.h /^ __IO uint32_t CRH;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +CRL target/stm32f103xb.h /^ __IO uint32_t CRL;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +CRL target/stm32f103xb.h /^ __IO uint32_t CRL;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR; \/*!< CRC Control register, Address offset:/;" m struct:__anon72c4c37e0908 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR; \/*!< WWDG Control register, Address offset: 0x00 *\/$/;" m struct:__anon72c4c37e1c08 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR;$/;" m struct:__anon72c4c37e0a08 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR;$/;" m struct:__anon72c4c37e1408 typeref:typename:__IO uint32_t +CR target/stm32f103xb.h /^ __IO uint32_t CR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +CSR target/stm32f103xb.h /^ __IO uint32_t CSR;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +CSR target/stm32f103xb.h /^ __IO uint32_t CSR;$/;" m struct:__anon72c4c37e1408 typeref:typename:__IO uint32_t +CSR target/stm32f103xb.h /^ __IO uint32_t CSR;$/;" m struct:__anon72c4c37e1508 typeref:typename:__IO uint32_t +ClockConfig_t Untitled Folder/rcc.c /^struct ClockConfig_t {$/;" s file: +ClockConfig_t drivers/rcc.c /^struct ClockConfig_t {$/;" s file: +Clock_config drivers/rcc.h /^enum Clock_config {$/;" g +Clock_t Untitled Folder/rcc.h /^} Clock_t;$/;" t typeref:struct:_Clock_t +Clock_t drivers/rcc.h /^} Clock_t;$/;" t typeref:struct:_Clock_t +DADDR target/stm32f103xb.h /^ __IO uint16_t DADDR; \/*!< Device address register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +DBGMCU_BASE target/stm32f103xb.h /^#define DBGMCU_BASE /;" d +DBGMCU_CR_DBG_CAN1_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_CAN1_STOP_Msk /;" d +DBGMCU_CR_DBG_CAN1_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_CAN1_STOP_Pos /;" d +DBGMCU_CR_DBG_CAN1_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_CAN1_STOP /;" d +DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /;" d +DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos /;" d +DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /;" d +DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /;" d +DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos /;" d +DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT target/stm32f103xb.h /^#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /;" d +DBGMCU_CR_DBG_IWDG_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_IWDG_STOP_Msk /;" d +DBGMCU_CR_DBG_IWDG_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_IWDG_STOP_Pos /;" d +DBGMCU_CR_DBG_IWDG_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_IWDG_STOP /;" d +DBGMCU_CR_DBG_SLEEP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_SLEEP_Msk /;" d +DBGMCU_CR_DBG_SLEEP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_SLEEP_Pos /;" d +DBGMCU_CR_DBG_SLEEP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_SLEEP /;" d +DBGMCU_CR_DBG_STANDBY_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STANDBY_Msk /;" d +DBGMCU_CR_DBG_STANDBY_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STANDBY_Pos /;" d +DBGMCU_CR_DBG_STANDBY target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STANDBY /;" d +DBGMCU_CR_DBG_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STOP_Msk /;" d +DBGMCU_CR_DBG_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STOP_Pos /;" d +DBGMCU_CR_DBG_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_STOP /;" d +DBGMCU_CR_DBG_TIM1_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM1_STOP_Msk /;" d +DBGMCU_CR_DBG_TIM1_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM1_STOP_Pos /;" d +DBGMCU_CR_DBG_TIM1_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM1_STOP /;" d +DBGMCU_CR_DBG_TIM2_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM2_STOP_Msk /;" d +DBGMCU_CR_DBG_TIM2_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM2_STOP_Pos /;" d +DBGMCU_CR_DBG_TIM2_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM2_STOP /;" d +DBGMCU_CR_DBG_TIM3_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM3_STOP_Msk /;" d +DBGMCU_CR_DBG_TIM3_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM3_STOP_Pos /;" d +DBGMCU_CR_DBG_TIM3_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM3_STOP /;" d +DBGMCU_CR_DBG_TIM4_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM4_STOP_Msk /;" d +DBGMCU_CR_DBG_TIM4_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM4_STOP_Pos /;" d +DBGMCU_CR_DBG_TIM4_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_TIM4_STOP /;" d +DBGMCU_CR_DBG_WWDG_STOP_Msk target/stm32f103xb.h /^#define DBGMCU_CR_DBG_WWDG_STOP_Msk /;" d +DBGMCU_CR_DBG_WWDG_STOP_Pos target/stm32f103xb.h /^#define DBGMCU_CR_DBG_WWDG_STOP_Pos /;" d +DBGMCU_CR_DBG_WWDG_STOP target/stm32f103xb.h /^#define DBGMCU_CR_DBG_WWDG_STOP /;" d +DBGMCU_CR_TRACE_IOEN_Msk target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_IOEN_Msk /;" d +DBGMCU_CR_TRACE_IOEN_Pos target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_IOEN_Pos /;" d +DBGMCU_CR_TRACE_IOEN target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_IOEN /;" d +DBGMCU_CR_TRACE_MODE_0 target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_MODE_0 /;" d +DBGMCU_CR_TRACE_MODE_1 target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_MODE_1 /;" d +DBGMCU_CR_TRACE_MODE_Msk target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_MODE_Msk /;" d +DBGMCU_CR_TRACE_MODE_Pos target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_MODE_Pos /;" d +DBGMCU_CR_TRACE_MODE target/stm32f103xb.h /^#define DBGMCU_CR_TRACE_MODE /;" d +DBGMCU_IDCODE_DEV_ID_Msk target/stm32f103xb.h /^#define DBGMCU_IDCODE_DEV_ID_Msk /;" d +DBGMCU_IDCODE_DEV_ID_Pos target/stm32f103xb.h /^#define DBGMCU_IDCODE_DEV_ID_Pos /;" d +DBGMCU_IDCODE_DEV_ID target/stm32f103xb.h /^#define DBGMCU_IDCODE_DEV_ID /;" d +DBGMCU_IDCODE_REV_ID_0 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_0 /;" d +DBGMCU_IDCODE_REV_ID_10 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_10 /;" d +DBGMCU_IDCODE_REV_ID_11 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_11 /;" d +DBGMCU_IDCODE_REV_ID_12 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_12 /;" d +DBGMCU_IDCODE_REV_ID_13 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_13 /;" d +DBGMCU_IDCODE_REV_ID_14 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_14 /;" d +DBGMCU_IDCODE_REV_ID_15 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_15 /;" d +DBGMCU_IDCODE_REV_ID_1 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_1 /;" d +DBGMCU_IDCODE_REV_ID_2 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_2 /;" d +DBGMCU_IDCODE_REV_ID_3 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_3 /;" d +DBGMCU_IDCODE_REV_ID_4 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_4 /;" d +DBGMCU_IDCODE_REV_ID_5 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_5 /;" d +DBGMCU_IDCODE_REV_ID_6 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_6 /;" d +DBGMCU_IDCODE_REV_ID_7 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_7 /;" d +DBGMCU_IDCODE_REV_ID_8 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_8 /;" d +DBGMCU_IDCODE_REV_ID_9 target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_9 /;" d +DBGMCU_IDCODE_REV_ID_Msk target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_Msk /;" d +DBGMCU_IDCODE_REV_ID_Pos target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID_Pos /;" d +DBGMCU_IDCODE_REV_ID target/stm32f103xb.h /^#define DBGMCU_IDCODE_REV_ID /;" d +DBGMCU_TypeDef target/stm32f103xb.h /^}DBGMCU_TypeDef;$/;" t typeref:struct:__anon72c4c37e0a08 +DBGMCU target/stm32f103xb.h /^#define DBGMCU /;" d +DCOUNT target/stm32f103xb.h /^ __I uint32_t DCOUNT;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +DCR target/stm32f103xb.h /^ __IO uint32_t DCR; \/*!< TIM DMA control register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +DCTRL target/stm32f103xb.h /^ __IO uint32_t DCTRL;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +DIER target/stm32f103xb.h /^ __IO uint32_t DIER; \/*!< TIM DMA\/interrupt enable register, Address off/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +DISABLE target/stm32f1xx.h /^ DISABLE = 0, $/;" e enum:__anonbccbea710203 +DIVH target/stm32f103xb.h /^ __IO uint32_t DIVH;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +DIVL target/stm32f103xb.h /^ __IO uint32_t DIVL;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +DLEN target/stm32f103xb.h /^ __IO uint32_t DLEN;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +DMA1_BASE target/stm32f103xb.h /^#define DMA1_BASE /;" d +DMA1_Channel1_BASE target/stm32f103xb.h /^#define DMA1_Channel1_BASE /;" d +DMA1_Channel1_IRQn target/stm32f103xb.h /^ DMA1_Channel1_IRQn = 11, \/*!< DMA1 Channel 1 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel1 target/stm32f103xb.h /^#define DMA1_Channel1 /;" d +DMA1_Channel2_BASE target/stm32f103xb.h /^#define DMA1_Channel2_BASE /;" d +DMA1_Channel2_IRQn target/stm32f103xb.h /^ DMA1_Channel2_IRQn = 12, \/*!< DMA1 Channel 2 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel2 target/stm32f103xb.h /^#define DMA1_Channel2 /;" d +DMA1_Channel3_BASE target/stm32f103xb.h /^#define DMA1_Channel3_BASE /;" d +DMA1_Channel3_IRQn target/stm32f103xb.h /^ DMA1_Channel3_IRQn = 13, \/*!< DMA1 Channel 3 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel3 target/stm32f103xb.h /^#define DMA1_Channel3 /;" d +DMA1_Channel4_BASE target/stm32f103xb.h /^#define DMA1_Channel4_BASE /;" d +DMA1_Channel4_IRQn target/stm32f103xb.h /^ DMA1_Channel4_IRQn = 14, \/*!< DMA1 Channel 4 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel4 target/stm32f103xb.h /^#define DMA1_Channel4 /;" d +DMA1_Channel5_BASE target/stm32f103xb.h /^#define DMA1_Channel5_BASE /;" d +DMA1_Channel5_IRQn target/stm32f103xb.h /^ DMA1_Channel5_IRQn = 15, \/*!< DMA1 Channel 5 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel5 target/stm32f103xb.h /^#define DMA1_Channel5 /;" d +DMA1_Channel6_BASE target/stm32f103xb.h /^#define DMA1_Channel6_BASE /;" d +DMA1_Channel6_IRQn target/stm32f103xb.h /^ DMA1_Channel6_IRQn = 16, \/*!< DMA1 Channel 6 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel6 target/stm32f103xb.h /^#define DMA1_Channel6 /;" d +DMA1_Channel7_BASE target/stm32f103xb.h /^#define DMA1_Channel7_BASE /;" d +DMA1_Channel7_IRQn target/stm32f103xb.h /^ DMA1_Channel7_IRQn = 17, \/*!< DMA1 Channel 7 global Interrupt /;" e enum:__anon72c4c37e0103 +DMA1_Channel7 target/stm32f103xb.h /^#define DMA1_Channel7 /;" d +DMA1 target/stm32f103xb.h /^#define DMA1 /;" d +DMAR target/stm32f103xb.h /^ __IO uint32_t DMAR; \/*!< TIM DMA address for full transfer register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +DMA_CCR_CIRC_Msk target/stm32f103xb.h /^#define DMA_CCR_CIRC_Msk /;" d +DMA_CCR_CIRC_Pos target/stm32f103xb.h /^#define DMA_CCR_CIRC_Pos /;" d +DMA_CCR_CIRC target/stm32f103xb.h /^#define DMA_CCR_CIRC /;" d +DMA_CCR_DIR_Msk target/stm32f103xb.h /^#define DMA_CCR_DIR_Msk /;" d +DMA_CCR_DIR_Pos target/stm32f103xb.h /^#define DMA_CCR_DIR_Pos /;" d +DMA_CCR_DIR target/stm32f103xb.h /^#define DMA_CCR_DIR /;" d +DMA_CCR_EN_Msk target/stm32f103xb.h /^#define DMA_CCR_EN_Msk /;" d +DMA_CCR_EN_Pos target/stm32f103xb.h /^#define DMA_CCR_EN_Pos /;" d +DMA_CCR_EN target/stm32f103xb.h /^#define DMA_CCR_EN /;" d +DMA_CCR_HTIE_Msk target/stm32f103xb.h /^#define DMA_CCR_HTIE_Msk /;" d +DMA_CCR_HTIE_Pos target/stm32f103xb.h /^#define DMA_CCR_HTIE_Pos /;" d +DMA_CCR_HTIE target/stm32f103xb.h /^#define DMA_CCR_HTIE /;" d +DMA_CCR_MEM2MEM_Msk target/stm32f103xb.h /^#define DMA_CCR_MEM2MEM_Msk /;" d +DMA_CCR_MEM2MEM_Pos target/stm32f103xb.h /^#define DMA_CCR_MEM2MEM_Pos /;" d +DMA_CCR_MEM2MEM target/stm32f103xb.h /^#define DMA_CCR_MEM2MEM /;" d +DMA_CCR_MINC_Msk target/stm32f103xb.h /^#define DMA_CCR_MINC_Msk /;" d +DMA_CCR_MINC_Pos target/stm32f103xb.h /^#define DMA_CCR_MINC_Pos /;" d +DMA_CCR_MINC target/stm32f103xb.h /^#define DMA_CCR_MINC /;" d +DMA_CCR_MSIZE_0 target/stm32f103xb.h /^#define DMA_CCR_MSIZE_0 /;" d +DMA_CCR_MSIZE_1 target/stm32f103xb.h /^#define DMA_CCR_MSIZE_1 /;" d +DMA_CCR_MSIZE_Msk target/stm32f103xb.h /^#define DMA_CCR_MSIZE_Msk /;" d +DMA_CCR_MSIZE_Pos target/stm32f103xb.h /^#define DMA_CCR_MSIZE_Pos /;" d +DMA_CCR_MSIZE target/stm32f103xb.h /^#define DMA_CCR_MSIZE /;" d +DMA_CCR_PINC_Msk target/stm32f103xb.h /^#define DMA_CCR_PINC_Msk /;" d +DMA_CCR_PINC_Pos target/stm32f103xb.h /^#define DMA_CCR_PINC_Pos /;" d +DMA_CCR_PINC target/stm32f103xb.h /^#define DMA_CCR_PINC /;" d +DMA_CCR_PL_0 target/stm32f103xb.h /^#define DMA_CCR_PL_0 /;" d +DMA_CCR_PL_1 target/stm32f103xb.h /^#define DMA_CCR_PL_1 /;" d +DMA_CCR_PL_Msk target/stm32f103xb.h /^#define DMA_CCR_PL_Msk /;" d +DMA_CCR_PL_Pos target/stm32f103xb.h /^#define DMA_CCR_PL_Pos /;" d +DMA_CCR_PL target/stm32f103xb.h /^#define DMA_CCR_PL /;" d +DMA_CCR_PSIZE_0 target/stm32f103xb.h /^#define DMA_CCR_PSIZE_0 /;" d +DMA_CCR_PSIZE_1 target/stm32f103xb.h /^#define DMA_CCR_PSIZE_1 /;" d +DMA_CCR_PSIZE_Msk target/stm32f103xb.h /^#define DMA_CCR_PSIZE_Msk /;" d +DMA_CCR_PSIZE_Pos target/stm32f103xb.h /^#define DMA_CCR_PSIZE_Pos /;" d +DMA_CCR_PSIZE target/stm32f103xb.h /^#define DMA_CCR_PSIZE /;" d +DMA_CCR_TCIE_Msk target/stm32f103xb.h /^#define DMA_CCR_TCIE_Msk /;" d +DMA_CCR_TCIE_Pos target/stm32f103xb.h /^#define DMA_CCR_TCIE_Pos /;" d +DMA_CCR_TCIE target/stm32f103xb.h /^#define DMA_CCR_TCIE /;" d +DMA_CCR_TEIE_Msk target/stm32f103xb.h /^#define DMA_CCR_TEIE_Msk /;" d +DMA_CCR_TEIE_Pos target/stm32f103xb.h /^#define DMA_CCR_TEIE_Pos /;" d +DMA_CCR_TEIE target/stm32f103xb.h /^#define DMA_CCR_TEIE /;" d +DMA_CMAR_MA_Msk target/stm32f103xb.h /^#define DMA_CMAR_MA_Msk /;" d +DMA_CMAR_MA_Pos target/stm32f103xb.h /^#define DMA_CMAR_MA_Pos /;" d +DMA_CMAR_MA target/stm32f103xb.h /^#define DMA_CMAR_MA /;" d +DMA_CNDTR_NDT_Msk target/stm32f103xb.h /^#define DMA_CNDTR_NDT_Msk /;" d +DMA_CNDTR_NDT_Pos target/stm32f103xb.h /^#define DMA_CNDTR_NDT_Pos /;" d +DMA_CNDTR_NDT target/stm32f103xb.h /^#define DMA_CNDTR_NDT /;" d +DMA_CPAR_PA_Msk target/stm32f103xb.h /^#define DMA_CPAR_PA_Msk /;" d +DMA_CPAR_PA_Pos target/stm32f103xb.h /^#define DMA_CPAR_PA_Pos /;" d +DMA_CPAR_PA target/stm32f103xb.h /^#define DMA_CPAR_PA /;" d +DMA_Channel_TypeDef target/stm32f103xb.h /^} DMA_Channel_TypeDef;$/;" t typeref:struct:__anon72c4c37e0b08 +DMA_IFCR_CGIF1_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF1_Msk /;" d +DMA_IFCR_CGIF1_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF1_Pos /;" d +DMA_IFCR_CGIF1 target/stm32f103xb.h /^#define DMA_IFCR_CGIF1 /;" d +DMA_IFCR_CGIF2_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF2_Msk /;" d +DMA_IFCR_CGIF2_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF2_Pos /;" d +DMA_IFCR_CGIF2 target/stm32f103xb.h /^#define DMA_IFCR_CGIF2 /;" d +DMA_IFCR_CGIF3_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF3_Msk /;" d +DMA_IFCR_CGIF3_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF3_Pos /;" d +DMA_IFCR_CGIF3 target/stm32f103xb.h /^#define DMA_IFCR_CGIF3 /;" d +DMA_IFCR_CGIF4_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF4_Msk /;" d +DMA_IFCR_CGIF4_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF4_Pos /;" d +DMA_IFCR_CGIF4 target/stm32f103xb.h /^#define DMA_IFCR_CGIF4 /;" d +DMA_IFCR_CGIF5_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF5_Msk /;" d +DMA_IFCR_CGIF5_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF5_Pos /;" d +DMA_IFCR_CGIF5 target/stm32f103xb.h /^#define DMA_IFCR_CGIF5 /;" d +DMA_IFCR_CGIF6_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF6_Msk /;" d +DMA_IFCR_CGIF6_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF6_Pos /;" d +DMA_IFCR_CGIF6 target/stm32f103xb.h /^#define DMA_IFCR_CGIF6 /;" d +DMA_IFCR_CGIF7_Msk target/stm32f103xb.h /^#define DMA_IFCR_CGIF7_Msk /;" d +DMA_IFCR_CGIF7_Pos target/stm32f103xb.h /^#define DMA_IFCR_CGIF7_Pos /;" d +DMA_IFCR_CGIF7 target/stm32f103xb.h /^#define DMA_IFCR_CGIF7 /;" d +DMA_IFCR_CHTIF1_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF1_Msk /;" d +DMA_IFCR_CHTIF1_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF1_Pos /;" d +DMA_IFCR_CHTIF1 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF1 /;" d +DMA_IFCR_CHTIF2_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF2_Msk /;" d +DMA_IFCR_CHTIF2_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF2_Pos /;" d +DMA_IFCR_CHTIF2 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF2 /;" d +DMA_IFCR_CHTIF3_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF3_Msk /;" d +DMA_IFCR_CHTIF3_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF3_Pos /;" d +DMA_IFCR_CHTIF3 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF3 /;" d +DMA_IFCR_CHTIF4_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF4_Msk /;" d +DMA_IFCR_CHTIF4_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF4_Pos /;" d +DMA_IFCR_CHTIF4 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF4 /;" d +DMA_IFCR_CHTIF5_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF5_Msk /;" d +DMA_IFCR_CHTIF5_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF5_Pos /;" d +DMA_IFCR_CHTIF5 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF5 /;" d +DMA_IFCR_CHTIF6_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF6_Msk /;" d +DMA_IFCR_CHTIF6_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF6_Pos /;" d +DMA_IFCR_CHTIF6 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF6 /;" d +DMA_IFCR_CHTIF7_Msk target/stm32f103xb.h /^#define DMA_IFCR_CHTIF7_Msk /;" d +DMA_IFCR_CHTIF7_Pos target/stm32f103xb.h /^#define DMA_IFCR_CHTIF7_Pos /;" d +DMA_IFCR_CHTIF7 target/stm32f103xb.h /^#define DMA_IFCR_CHTIF7 /;" d +DMA_IFCR_CTCIF1_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF1_Msk /;" d +DMA_IFCR_CTCIF1_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF1_Pos /;" d +DMA_IFCR_CTCIF1 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF1 /;" d +DMA_IFCR_CTCIF2_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF2_Msk /;" d +DMA_IFCR_CTCIF2_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF2_Pos /;" d +DMA_IFCR_CTCIF2 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF2 /;" d +DMA_IFCR_CTCIF3_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF3_Msk /;" d +DMA_IFCR_CTCIF3_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF3_Pos /;" d +DMA_IFCR_CTCIF3 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF3 /;" d +DMA_IFCR_CTCIF4_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF4_Msk /;" d +DMA_IFCR_CTCIF4_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF4_Pos /;" d +DMA_IFCR_CTCIF4 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF4 /;" d +DMA_IFCR_CTCIF5_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF5_Msk /;" d +DMA_IFCR_CTCIF5_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF5_Pos /;" d +DMA_IFCR_CTCIF5 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF5 /;" d +DMA_IFCR_CTCIF6_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF6_Msk /;" d +DMA_IFCR_CTCIF6_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF6_Pos /;" d +DMA_IFCR_CTCIF6 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF6 /;" d +DMA_IFCR_CTCIF7_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTCIF7_Msk /;" d +DMA_IFCR_CTCIF7_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTCIF7_Pos /;" d +DMA_IFCR_CTCIF7 target/stm32f103xb.h /^#define DMA_IFCR_CTCIF7 /;" d +DMA_IFCR_CTEIF1_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF1_Msk /;" d +DMA_IFCR_CTEIF1_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF1_Pos /;" d +DMA_IFCR_CTEIF1 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF1 /;" d +DMA_IFCR_CTEIF2_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF2_Msk /;" d +DMA_IFCR_CTEIF2_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF2_Pos /;" d +DMA_IFCR_CTEIF2 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF2 /;" d +DMA_IFCR_CTEIF3_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF3_Msk /;" d +DMA_IFCR_CTEIF3_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF3_Pos /;" d +DMA_IFCR_CTEIF3 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF3 /;" d +DMA_IFCR_CTEIF4_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF4_Msk /;" d +DMA_IFCR_CTEIF4_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF4_Pos /;" d +DMA_IFCR_CTEIF4 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF4 /;" d +DMA_IFCR_CTEIF5_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF5_Msk /;" d +DMA_IFCR_CTEIF5_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF5_Pos /;" d +DMA_IFCR_CTEIF5 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF5 /;" d +DMA_IFCR_CTEIF6_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF6_Msk /;" d +DMA_IFCR_CTEIF6_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF6_Pos /;" d +DMA_IFCR_CTEIF6 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF6 /;" d +DMA_IFCR_CTEIF7_Msk target/stm32f103xb.h /^#define DMA_IFCR_CTEIF7_Msk /;" d +DMA_IFCR_CTEIF7_Pos target/stm32f103xb.h /^#define DMA_IFCR_CTEIF7_Pos /;" d +DMA_IFCR_CTEIF7 target/stm32f103xb.h /^#define DMA_IFCR_CTEIF7 /;" d +DMA_ISR_GIF1_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF1_Msk /;" d +DMA_ISR_GIF1_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF1_Pos /;" d +DMA_ISR_GIF1 target/stm32f103xb.h /^#define DMA_ISR_GIF1 /;" d +DMA_ISR_GIF2_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF2_Msk /;" d +DMA_ISR_GIF2_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF2_Pos /;" d +DMA_ISR_GIF2 target/stm32f103xb.h /^#define DMA_ISR_GIF2 /;" d +DMA_ISR_GIF3_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF3_Msk /;" d +DMA_ISR_GIF3_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF3_Pos /;" d +DMA_ISR_GIF3 target/stm32f103xb.h /^#define DMA_ISR_GIF3 /;" d +DMA_ISR_GIF4_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF4_Msk /;" d +DMA_ISR_GIF4_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF4_Pos /;" d +DMA_ISR_GIF4 target/stm32f103xb.h /^#define DMA_ISR_GIF4 /;" d +DMA_ISR_GIF5_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF5_Msk /;" d +DMA_ISR_GIF5_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF5_Pos /;" d +DMA_ISR_GIF5 target/stm32f103xb.h /^#define DMA_ISR_GIF5 /;" d +DMA_ISR_GIF6_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF6_Msk /;" d +DMA_ISR_GIF6_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF6_Pos /;" d +DMA_ISR_GIF6 target/stm32f103xb.h /^#define DMA_ISR_GIF6 /;" d +DMA_ISR_GIF7_Msk target/stm32f103xb.h /^#define DMA_ISR_GIF7_Msk /;" d +DMA_ISR_GIF7_Pos target/stm32f103xb.h /^#define DMA_ISR_GIF7_Pos /;" d +DMA_ISR_GIF7 target/stm32f103xb.h /^#define DMA_ISR_GIF7 /;" d +DMA_ISR_HTIF1_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF1_Msk /;" d +DMA_ISR_HTIF1_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF1_Pos /;" d +DMA_ISR_HTIF1 target/stm32f103xb.h /^#define DMA_ISR_HTIF1 /;" d +DMA_ISR_HTIF2_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF2_Msk /;" d +DMA_ISR_HTIF2_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF2_Pos /;" d +DMA_ISR_HTIF2 target/stm32f103xb.h /^#define DMA_ISR_HTIF2 /;" d +DMA_ISR_HTIF3_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF3_Msk /;" d +DMA_ISR_HTIF3_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF3_Pos /;" d +DMA_ISR_HTIF3 target/stm32f103xb.h /^#define DMA_ISR_HTIF3 /;" d +DMA_ISR_HTIF4_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF4_Msk /;" d +DMA_ISR_HTIF4_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF4_Pos /;" d +DMA_ISR_HTIF4 target/stm32f103xb.h /^#define DMA_ISR_HTIF4 /;" d +DMA_ISR_HTIF5_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF5_Msk /;" d +DMA_ISR_HTIF5_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF5_Pos /;" d +DMA_ISR_HTIF5 target/stm32f103xb.h /^#define DMA_ISR_HTIF5 /;" d +DMA_ISR_HTIF6_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF6_Msk /;" d +DMA_ISR_HTIF6_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF6_Pos /;" d +DMA_ISR_HTIF6 target/stm32f103xb.h /^#define DMA_ISR_HTIF6 /;" d +DMA_ISR_HTIF7_Msk target/stm32f103xb.h /^#define DMA_ISR_HTIF7_Msk /;" d +DMA_ISR_HTIF7_Pos target/stm32f103xb.h /^#define DMA_ISR_HTIF7_Pos /;" d +DMA_ISR_HTIF7 target/stm32f103xb.h /^#define DMA_ISR_HTIF7 /;" d +DMA_ISR_TCIF1_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF1_Msk /;" d +DMA_ISR_TCIF1_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF1_Pos /;" d +DMA_ISR_TCIF1 target/stm32f103xb.h /^#define DMA_ISR_TCIF1 /;" d +DMA_ISR_TCIF2_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF2_Msk /;" d +DMA_ISR_TCIF2_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF2_Pos /;" d +DMA_ISR_TCIF2 target/stm32f103xb.h /^#define DMA_ISR_TCIF2 /;" d +DMA_ISR_TCIF3_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF3_Msk /;" d +DMA_ISR_TCIF3_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF3_Pos /;" d +DMA_ISR_TCIF3 target/stm32f103xb.h /^#define DMA_ISR_TCIF3 /;" d +DMA_ISR_TCIF4_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF4_Msk /;" d +DMA_ISR_TCIF4_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF4_Pos /;" d +DMA_ISR_TCIF4 target/stm32f103xb.h /^#define DMA_ISR_TCIF4 /;" d +DMA_ISR_TCIF5_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF5_Msk /;" d +DMA_ISR_TCIF5_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF5_Pos /;" d +DMA_ISR_TCIF5 target/stm32f103xb.h /^#define DMA_ISR_TCIF5 /;" d +DMA_ISR_TCIF6_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF6_Msk /;" d +DMA_ISR_TCIF6_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF6_Pos /;" d +DMA_ISR_TCIF6 target/stm32f103xb.h /^#define DMA_ISR_TCIF6 /;" d +DMA_ISR_TCIF7_Msk target/stm32f103xb.h /^#define DMA_ISR_TCIF7_Msk /;" d +DMA_ISR_TCIF7_Pos target/stm32f103xb.h /^#define DMA_ISR_TCIF7_Pos /;" d +DMA_ISR_TCIF7 target/stm32f103xb.h /^#define DMA_ISR_TCIF7 /;" d +DMA_ISR_TEIF1_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF1_Msk /;" d +DMA_ISR_TEIF1_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF1_Pos /;" d +DMA_ISR_TEIF1 target/stm32f103xb.h /^#define DMA_ISR_TEIF1 /;" d +DMA_ISR_TEIF2_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF2_Msk /;" d +DMA_ISR_TEIF2_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF2_Pos /;" d +DMA_ISR_TEIF2 target/stm32f103xb.h /^#define DMA_ISR_TEIF2 /;" d +DMA_ISR_TEIF3_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF3_Msk /;" d +DMA_ISR_TEIF3_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF3_Pos /;" d +DMA_ISR_TEIF3 target/stm32f103xb.h /^#define DMA_ISR_TEIF3 /;" d +DMA_ISR_TEIF4_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF4_Msk /;" d +DMA_ISR_TEIF4_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF4_Pos /;" d +DMA_ISR_TEIF4 target/stm32f103xb.h /^#define DMA_ISR_TEIF4 /;" d +DMA_ISR_TEIF5_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF5_Msk /;" d +DMA_ISR_TEIF5_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF5_Pos /;" d +DMA_ISR_TEIF5 target/stm32f103xb.h /^#define DMA_ISR_TEIF5 /;" d +DMA_ISR_TEIF6_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF6_Msk /;" d +DMA_ISR_TEIF6_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF6_Pos /;" d +DMA_ISR_TEIF6 target/stm32f103xb.h /^#define DMA_ISR_TEIF6 /;" d +DMA_ISR_TEIF7_Msk target/stm32f103xb.h /^#define DMA_ISR_TEIF7_Msk /;" d +DMA_ISR_TEIF7_Pos target/stm32f103xb.h /^#define DMA_ISR_TEIF7_Pos /;" d +DMA_ISR_TEIF7 target/stm32f103xb.h /^#define DMA_ISR_TEIF7 /;" d +DMA_TypeDef target/stm32f103xb.h /^} DMA_TypeDef;$/;" t typeref:struct:__anon72c4c37e0c08 +DR10 target/stm32f103xb.h /^ __IO uint32_t DR10;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR1 target/stm32f103xb.h /^ __IO uint32_t DR1;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR2 target/stm32f103xb.h /^ __IO uint32_t DR2;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR3 target/stm32f103xb.h /^ __IO uint32_t DR3;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR4 target/stm32f103xb.h /^ __IO uint32_t DR4;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR5 target/stm32f103xb.h /^ __IO uint32_t DR5;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR6 target/stm32f103xb.h /^ __IO uint32_t DR6;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR7 target/stm32f103xb.h /^ __IO uint32_t DR7;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR8 target/stm32f103xb.h /^ __IO uint32_t DR8;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR9 target/stm32f103xb.h /^ __IO uint32_t DR9;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR; \/*!< ADC data register, used for ADC multimode (bits com/;" m struct:__anon72c4c37e0308 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR; \/*!< CRC Data register, Address offset:/;" m struct:__anon72c4c37e0908 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR; \/*!< USART Data register, Address offset: 0x04 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +DR target/stm32f103xb.h /^ __IO uint32_t DR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +DTIMER target/stm32f103xb.h /^ __IO uint32_t DTIMER;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +Data0 target/stm32f103xb.h /^ __IO uint16_t Data0;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +Data1 target/stm32f103xb.h /^ __IO uint16_t Data1;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +DebugMon_Handler Untitled Folder/sys_handlers.c /^void DebugMon_Handler(void)$/;" f typeref:typename:void +DebugMonitor_IRQn target/stm32f103xb.h /^ DebugMonitor_IRQn = -4, \/*!< 12 Cortex-M3 Debug Monitor Interrupt /;" e enum:__anon72c4c37e0103 +EGR target/stm32f103xb.h /^ __IO uint32_t EGR; \/*!< TIM event generation register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +EMR target/stm32f103xb.h /^ __IO uint32_t EMR;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +ENABLE target/stm32f1xx.h /^ ENABLE = !DISABLE$/;" e enum:__anonbccbea710203 +EP0R target/stm32f103xb.h /^ __IO uint16_t EP0R; \/*!< USB Endpoint 0 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP1R target/stm32f103xb.h /^ __IO uint16_t EP1R; \/*!< USB Endpoint 1 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP2R target/stm32f103xb.h /^ __IO uint16_t EP2R; \/*!< USB Endpoint 2 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP3R target/stm32f103xb.h /^ __IO uint16_t EP3R; \/*!< USB Endpoint 3 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP4R target/stm32f103xb.h /^ __IO uint16_t EP4R; \/*!< USB Endpoint 4 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP5R target/stm32f103xb.h /^ __IO uint16_t EP5R; \/*!< USB Endpoint 5 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP6R target/stm32f103xb.h /^ __IO uint16_t EP6R; \/*!< USB Endpoint 6 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +EP7R target/stm32f103xb.h /^ __IO uint16_t EP7R; \/*!< USB Endpoint 7 register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +ERROR target/stm32f1xx.h /^ ERROR = 0, $/;" e enum:__anonbccbea710303 +ESR target/stm32f103xb.h /^ __IO uint32_t ESR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +EVCR target/stm32f103xb.h /^ __IO uint32_t EVCR;$/;" m struct:__anon72c4c37e1108 typeref:typename:__IO uint32_t +EXTI0_IRQHandler drivers/io.c /^void EXTI0_IRQHandler() {$/;" f typeref:typename:void +EXTI0_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI0_IRQ_PRIORITY /;" d +EXTI0_IRQ_PRIORITY config.h /^#define EXTI0_IRQ_PRIORITY /;" d +EXTI0_IRQn target/stm32f103xb.h /^ EXTI0_IRQn = 6, \/*!< EXTI Line0 Interrupt /;" e enum:__anon72c4c37e0103 +EXTI15_10_IRQHandler drivers/io.c /^void EXTI15_10_IRQHandler() {$/;" f typeref:typename:void +EXTI15_10_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI15_10_IRQ_PRIORITY /;" d +EXTI15_10_IRQ_PRIORITY config.h /^#define EXTI15_10_IRQ_PRIORITY /;" d +EXTI15_10_IRQn target/stm32f103xb.h /^ EXTI15_10_IRQn = 40, \/*!< External Line[15:10] Interrupts /;" e enum:__anon72c4c37e0103 +EXTI1_IRQHandler drivers/io.c /^void EXTI1_IRQHandler() {$/;" f typeref:typename:void +EXTI1_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI1_IRQ_PRIORITY /;" d +EXTI1_IRQ_PRIORITY config.h /^#define EXTI1_IRQ_PRIORITY /;" d +EXTI1_IRQn target/stm32f103xb.h /^ EXTI1_IRQn = 7, \/*!< EXTI Line1 Interrupt /;" e enum:__anon72c4c37e0103 +EXTI2_IRQHandler drivers/io.c /^void EXTI2_IRQHandler() {$/;" f typeref:typename:void +EXTI2_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI2_IRQ_PRIORITY /;" d +EXTI2_IRQ_PRIORITY config.h /^#define EXTI2_IRQ_PRIORITY /;" d +EXTI2_IRQn target/stm32f103xb.h /^ EXTI2_IRQn = 8, \/*!< EXTI Line2 Interrupt /;" e enum:__anon72c4c37e0103 +EXTI3_IRQHandler drivers/io.c /^void EXTI3_IRQHandler() {$/;" f typeref:typename:void +EXTI3_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI3_IRQ_PRIORITY /;" d +EXTI3_IRQ_PRIORITY config.h /^#define EXTI3_IRQ_PRIORITY /;" d +EXTI3_IRQn target/stm32f103xb.h /^ EXTI3_IRQn = 9, \/*!< EXTI Line3 Interrupt /;" e enum:__anon72c4c37e0103 +EXTI4_IRQHandler drivers/io.c /^void EXTI4_IRQHandler() {$/;" f typeref:typename:void +EXTI4_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI4_IRQ_PRIORITY /;" d +EXTI4_IRQ_PRIORITY config.h /^#define EXTI4_IRQ_PRIORITY /;" d +EXTI4_IRQn target/stm32f103xb.h /^ EXTI4_IRQn = 10, \/*!< EXTI Line4 Interrupt /;" e enum:__anon72c4c37e0103 +EXTI9_5_IRQHandler drivers/io.c /^void EXTI9_5_IRQHandler() {$/;" f typeref:typename:void +EXTI9_5_IRQ_PRIORITY Untitled Folder/config.h /^#define EXTI9_5_IRQ_PRIORITY /;" d +EXTI9_5_IRQ_PRIORITY config.h /^#define EXTI9_5_IRQ_PRIORITY /;" d +EXTI9_5_IRQn target/stm32f103xb.h /^ EXTI9_5_IRQn = 23, \/*!< External Line[9:5] Interrupts /;" e enum:__anon72c4c37e0103 +EXTICR target/stm32f103xb.h /^ __IO uint32_t EXTICR[4];$/;" m struct:__anon72c4c37e1108 typeref:typename:__IO uint32_t[4] +EXTI_BASE target/stm32f103xb.h /^#define EXTI_BASE /;" d +EXTI_EMR_EM0 target/stm32f103xb.h /^#define EXTI_EMR_EM0 /;" d +EXTI_EMR_EM10 target/stm32f103xb.h /^#define EXTI_EMR_EM10 /;" d +EXTI_EMR_EM11 target/stm32f103xb.h /^#define EXTI_EMR_EM11 /;" d +EXTI_EMR_EM12 target/stm32f103xb.h /^#define EXTI_EMR_EM12 /;" d +EXTI_EMR_EM13 target/stm32f103xb.h /^#define EXTI_EMR_EM13 /;" d +EXTI_EMR_EM14 target/stm32f103xb.h /^#define EXTI_EMR_EM14 /;" d +EXTI_EMR_EM15 target/stm32f103xb.h /^#define EXTI_EMR_EM15 /;" d +EXTI_EMR_EM16 target/stm32f103xb.h /^#define EXTI_EMR_EM16 /;" d +EXTI_EMR_EM17 target/stm32f103xb.h /^#define EXTI_EMR_EM17 /;" d +EXTI_EMR_EM18 target/stm32f103xb.h /^#define EXTI_EMR_EM18 /;" d +EXTI_EMR_EM1 target/stm32f103xb.h /^#define EXTI_EMR_EM1 /;" d +EXTI_EMR_EM2 target/stm32f103xb.h /^#define EXTI_EMR_EM2 /;" d +EXTI_EMR_EM3 target/stm32f103xb.h /^#define EXTI_EMR_EM3 /;" d +EXTI_EMR_EM4 target/stm32f103xb.h /^#define EXTI_EMR_EM4 /;" d +EXTI_EMR_EM5 target/stm32f103xb.h /^#define EXTI_EMR_EM5 /;" d +EXTI_EMR_EM6 target/stm32f103xb.h /^#define EXTI_EMR_EM6 /;" d +EXTI_EMR_EM7 target/stm32f103xb.h /^#define EXTI_EMR_EM7 /;" d +EXTI_EMR_EM8 target/stm32f103xb.h /^#define EXTI_EMR_EM8 /;" d +EXTI_EMR_EM9 target/stm32f103xb.h /^#define EXTI_EMR_EM9 /;" d +EXTI_EMR_MR0_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR0_Msk /;" d +EXTI_EMR_MR0_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR0_Pos /;" d +EXTI_EMR_MR0 target/stm32f103xb.h /^#define EXTI_EMR_MR0 /;" d +EXTI_EMR_MR10_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR10_Msk /;" d +EXTI_EMR_MR10_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR10_Pos /;" d +EXTI_EMR_MR10 target/stm32f103xb.h /^#define EXTI_EMR_MR10 /;" d +EXTI_EMR_MR11_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR11_Msk /;" d +EXTI_EMR_MR11_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR11_Pos /;" d +EXTI_EMR_MR11 target/stm32f103xb.h /^#define EXTI_EMR_MR11 /;" d +EXTI_EMR_MR12_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR12_Msk /;" d +EXTI_EMR_MR12_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR12_Pos /;" d +EXTI_EMR_MR12 target/stm32f103xb.h /^#define EXTI_EMR_MR12 /;" d +EXTI_EMR_MR13_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR13_Msk /;" d +EXTI_EMR_MR13_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR13_Pos /;" d +EXTI_EMR_MR13 target/stm32f103xb.h /^#define EXTI_EMR_MR13 /;" d +EXTI_EMR_MR14_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR14_Msk /;" d +EXTI_EMR_MR14_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR14_Pos /;" d +EXTI_EMR_MR14 target/stm32f103xb.h /^#define EXTI_EMR_MR14 /;" d +EXTI_EMR_MR15_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR15_Msk /;" d +EXTI_EMR_MR15_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR15_Pos /;" d +EXTI_EMR_MR15 target/stm32f103xb.h /^#define EXTI_EMR_MR15 /;" d +EXTI_EMR_MR16_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR16_Msk /;" d +EXTI_EMR_MR16_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR16_Pos /;" d +EXTI_EMR_MR16 target/stm32f103xb.h /^#define EXTI_EMR_MR16 /;" d +EXTI_EMR_MR17_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR17_Msk /;" d +EXTI_EMR_MR17_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR17_Pos /;" d +EXTI_EMR_MR17 target/stm32f103xb.h /^#define EXTI_EMR_MR17 /;" d +EXTI_EMR_MR18_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR18_Msk /;" d +EXTI_EMR_MR18_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR18_Pos /;" d +EXTI_EMR_MR18 target/stm32f103xb.h /^#define EXTI_EMR_MR18 /;" d +EXTI_EMR_MR1_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR1_Msk /;" d +EXTI_EMR_MR1_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR1_Pos /;" d +EXTI_EMR_MR1 target/stm32f103xb.h /^#define EXTI_EMR_MR1 /;" d +EXTI_EMR_MR2_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR2_Msk /;" d +EXTI_EMR_MR2_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR2_Pos /;" d +EXTI_EMR_MR2 target/stm32f103xb.h /^#define EXTI_EMR_MR2 /;" d +EXTI_EMR_MR3_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR3_Msk /;" d +EXTI_EMR_MR3_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR3_Pos /;" d +EXTI_EMR_MR3 target/stm32f103xb.h /^#define EXTI_EMR_MR3 /;" d +EXTI_EMR_MR4_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR4_Msk /;" d +EXTI_EMR_MR4_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR4_Pos /;" d +EXTI_EMR_MR4 target/stm32f103xb.h /^#define EXTI_EMR_MR4 /;" d +EXTI_EMR_MR5_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR5_Msk /;" d +EXTI_EMR_MR5_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR5_Pos /;" d +EXTI_EMR_MR5 target/stm32f103xb.h /^#define EXTI_EMR_MR5 /;" d +EXTI_EMR_MR6_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR6_Msk /;" d +EXTI_EMR_MR6_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR6_Pos /;" d +EXTI_EMR_MR6 target/stm32f103xb.h /^#define EXTI_EMR_MR6 /;" d +EXTI_EMR_MR7_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR7_Msk /;" d +EXTI_EMR_MR7_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR7_Pos /;" d +EXTI_EMR_MR7 target/stm32f103xb.h /^#define EXTI_EMR_MR7 /;" d +EXTI_EMR_MR8_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR8_Msk /;" d +EXTI_EMR_MR8_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR8_Pos /;" d +EXTI_EMR_MR8 target/stm32f103xb.h /^#define EXTI_EMR_MR8 /;" d +EXTI_EMR_MR9_Msk target/stm32f103xb.h /^#define EXTI_EMR_MR9_Msk /;" d +EXTI_EMR_MR9_Pos target/stm32f103xb.h /^#define EXTI_EMR_MR9_Pos /;" d +EXTI_EMR_MR9 target/stm32f103xb.h /^#define EXTI_EMR_MR9 /;" d +EXTI_FTSR_FT0 target/stm32f103xb.h /^#define EXTI_FTSR_FT0 /;" d +EXTI_FTSR_FT10 target/stm32f103xb.h /^#define EXTI_FTSR_FT10 /;" d +EXTI_FTSR_FT11 target/stm32f103xb.h /^#define EXTI_FTSR_FT11 /;" d +EXTI_FTSR_FT12 target/stm32f103xb.h /^#define EXTI_FTSR_FT12 /;" d +EXTI_FTSR_FT13 target/stm32f103xb.h /^#define EXTI_FTSR_FT13 /;" d +EXTI_FTSR_FT14 target/stm32f103xb.h /^#define EXTI_FTSR_FT14 /;" d +EXTI_FTSR_FT15 target/stm32f103xb.h /^#define EXTI_FTSR_FT15 /;" d +EXTI_FTSR_FT16 target/stm32f103xb.h /^#define EXTI_FTSR_FT16 /;" d +EXTI_FTSR_FT17 target/stm32f103xb.h /^#define EXTI_FTSR_FT17 /;" d +EXTI_FTSR_FT18 target/stm32f103xb.h /^#define EXTI_FTSR_FT18 /;" d +EXTI_FTSR_FT1 target/stm32f103xb.h /^#define EXTI_FTSR_FT1 /;" d +EXTI_FTSR_FT2 target/stm32f103xb.h /^#define EXTI_FTSR_FT2 /;" d +EXTI_FTSR_FT3 target/stm32f103xb.h /^#define EXTI_FTSR_FT3 /;" d +EXTI_FTSR_FT4 target/stm32f103xb.h /^#define EXTI_FTSR_FT4 /;" d +EXTI_FTSR_FT5 target/stm32f103xb.h /^#define EXTI_FTSR_FT5 /;" d +EXTI_FTSR_FT6 target/stm32f103xb.h /^#define EXTI_FTSR_FT6 /;" d +EXTI_FTSR_FT7 target/stm32f103xb.h /^#define EXTI_FTSR_FT7 /;" d +EXTI_FTSR_FT8 target/stm32f103xb.h /^#define EXTI_FTSR_FT8 /;" d +EXTI_FTSR_FT9 target/stm32f103xb.h /^#define EXTI_FTSR_FT9 /;" d +EXTI_FTSR_TR0_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR0_Msk /;" d +EXTI_FTSR_TR0_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR0_Pos /;" d +EXTI_FTSR_TR0 target/stm32f103xb.h /^#define EXTI_FTSR_TR0 /;" d +EXTI_FTSR_TR10_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR10_Msk /;" d +EXTI_FTSR_TR10_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR10_Pos /;" d +EXTI_FTSR_TR10 target/stm32f103xb.h /^#define EXTI_FTSR_TR10 /;" d +EXTI_FTSR_TR11_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR11_Msk /;" d +EXTI_FTSR_TR11_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR11_Pos /;" d +EXTI_FTSR_TR11 target/stm32f103xb.h /^#define EXTI_FTSR_TR11 /;" d +EXTI_FTSR_TR12_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR12_Msk /;" d +EXTI_FTSR_TR12_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR12_Pos /;" d +EXTI_FTSR_TR12 target/stm32f103xb.h /^#define EXTI_FTSR_TR12 /;" d +EXTI_FTSR_TR13_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR13_Msk /;" d +EXTI_FTSR_TR13_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR13_Pos /;" d +EXTI_FTSR_TR13 target/stm32f103xb.h /^#define EXTI_FTSR_TR13 /;" d +EXTI_FTSR_TR14_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR14_Msk /;" d +EXTI_FTSR_TR14_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR14_Pos /;" d +EXTI_FTSR_TR14 target/stm32f103xb.h /^#define EXTI_FTSR_TR14 /;" d +EXTI_FTSR_TR15_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR15_Msk /;" d +EXTI_FTSR_TR15_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR15_Pos /;" d +EXTI_FTSR_TR15 target/stm32f103xb.h /^#define EXTI_FTSR_TR15 /;" d +EXTI_FTSR_TR16_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR16_Msk /;" d +EXTI_FTSR_TR16_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR16_Pos /;" d +EXTI_FTSR_TR16 target/stm32f103xb.h /^#define EXTI_FTSR_TR16 /;" d +EXTI_FTSR_TR17_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR17_Msk /;" d +EXTI_FTSR_TR17_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR17_Pos /;" d +EXTI_FTSR_TR17 target/stm32f103xb.h /^#define EXTI_FTSR_TR17 /;" d +EXTI_FTSR_TR18_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR18_Msk /;" d +EXTI_FTSR_TR18_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR18_Pos /;" d +EXTI_FTSR_TR18 target/stm32f103xb.h /^#define EXTI_FTSR_TR18 /;" d +EXTI_FTSR_TR1_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR1_Msk /;" d +EXTI_FTSR_TR1_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR1_Pos /;" d +EXTI_FTSR_TR1 target/stm32f103xb.h /^#define EXTI_FTSR_TR1 /;" d +EXTI_FTSR_TR2_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR2_Msk /;" d +EXTI_FTSR_TR2_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR2_Pos /;" d +EXTI_FTSR_TR2 target/stm32f103xb.h /^#define EXTI_FTSR_TR2 /;" d +EXTI_FTSR_TR3_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR3_Msk /;" d +EXTI_FTSR_TR3_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR3_Pos /;" d +EXTI_FTSR_TR3 target/stm32f103xb.h /^#define EXTI_FTSR_TR3 /;" d +EXTI_FTSR_TR4_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR4_Msk /;" d +EXTI_FTSR_TR4_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR4_Pos /;" d +EXTI_FTSR_TR4 target/stm32f103xb.h /^#define EXTI_FTSR_TR4 /;" d +EXTI_FTSR_TR5_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR5_Msk /;" d +EXTI_FTSR_TR5_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR5_Pos /;" d +EXTI_FTSR_TR5 target/stm32f103xb.h /^#define EXTI_FTSR_TR5 /;" d +EXTI_FTSR_TR6_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR6_Msk /;" d +EXTI_FTSR_TR6_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR6_Pos /;" d +EXTI_FTSR_TR6 target/stm32f103xb.h /^#define EXTI_FTSR_TR6 /;" d +EXTI_FTSR_TR7_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR7_Msk /;" d +EXTI_FTSR_TR7_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR7_Pos /;" d +EXTI_FTSR_TR7 target/stm32f103xb.h /^#define EXTI_FTSR_TR7 /;" d +EXTI_FTSR_TR8_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR8_Msk /;" d +EXTI_FTSR_TR8_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR8_Pos /;" d +EXTI_FTSR_TR8 target/stm32f103xb.h /^#define EXTI_FTSR_TR8 /;" d +EXTI_FTSR_TR9_Msk target/stm32f103xb.h /^#define EXTI_FTSR_TR9_Msk /;" d +EXTI_FTSR_TR9_Pos target/stm32f103xb.h /^#define EXTI_FTSR_TR9_Pos /;" d +EXTI_FTSR_TR9 target/stm32f103xb.h /^#define EXTI_FTSR_TR9 /;" d +EXTI_IMR_IM0 target/stm32f103xb.h /^#define EXTI_IMR_IM0 /;" d +EXTI_IMR_IM10 target/stm32f103xb.h /^#define EXTI_IMR_IM10 /;" d +EXTI_IMR_IM11 target/stm32f103xb.h /^#define EXTI_IMR_IM11 /;" d +EXTI_IMR_IM12 target/stm32f103xb.h /^#define EXTI_IMR_IM12 /;" d +EXTI_IMR_IM13 target/stm32f103xb.h /^#define EXTI_IMR_IM13 /;" d +EXTI_IMR_IM14 target/stm32f103xb.h /^#define EXTI_IMR_IM14 /;" d +EXTI_IMR_IM15 target/stm32f103xb.h /^#define EXTI_IMR_IM15 /;" d +EXTI_IMR_IM16 target/stm32f103xb.h /^#define EXTI_IMR_IM16 /;" d +EXTI_IMR_IM17 target/stm32f103xb.h /^#define EXTI_IMR_IM17 /;" d +EXTI_IMR_IM18 target/stm32f103xb.h /^#define EXTI_IMR_IM18 /;" d +EXTI_IMR_IM1 target/stm32f103xb.h /^#define EXTI_IMR_IM1 /;" d +EXTI_IMR_IM2 target/stm32f103xb.h /^#define EXTI_IMR_IM2 /;" d +EXTI_IMR_IM3 target/stm32f103xb.h /^#define EXTI_IMR_IM3 /;" d +EXTI_IMR_IM4 target/stm32f103xb.h /^#define EXTI_IMR_IM4 /;" d +EXTI_IMR_IM5 target/stm32f103xb.h /^#define EXTI_IMR_IM5 /;" d +EXTI_IMR_IM6 target/stm32f103xb.h /^#define EXTI_IMR_IM6 /;" d +EXTI_IMR_IM7 target/stm32f103xb.h /^#define EXTI_IMR_IM7 /;" d +EXTI_IMR_IM8 target/stm32f103xb.h /^#define EXTI_IMR_IM8 /;" d +EXTI_IMR_IM9 target/stm32f103xb.h /^#define EXTI_IMR_IM9 /;" d +EXTI_IMR_IM target/stm32f103xb.h /^#define EXTI_IMR_IM /;" d +EXTI_IMR_MR0_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR0_Msk /;" d +EXTI_IMR_MR0_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR0_Pos /;" d +EXTI_IMR_MR0 target/stm32f103xb.h /^#define EXTI_IMR_MR0 /;" d +EXTI_IMR_MR10_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR10_Msk /;" d +EXTI_IMR_MR10_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR10_Pos /;" d +EXTI_IMR_MR10 target/stm32f103xb.h /^#define EXTI_IMR_MR10 /;" d +EXTI_IMR_MR11_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR11_Msk /;" d +EXTI_IMR_MR11_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR11_Pos /;" d +EXTI_IMR_MR11 target/stm32f103xb.h /^#define EXTI_IMR_MR11 /;" d +EXTI_IMR_MR12_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR12_Msk /;" d +EXTI_IMR_MR12_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR12_Pos /;" d +EXTI_IMR_MR12 target/stm32f103xb.h /^#define EXTI_IMR_MR12 /;" d +EXTI_IMR_MR13_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR13_Msk /;" d +EXTI_IMR_MR13_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR13_Pos /;" d +EXTI_IMR_MR13 target/stm32f103xb.h /^#define EXTI_IMR_MR13 /;" d +EXTI_IMR_MR14_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR14_Msk /;" d +EXTI_IMR_MR14_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR14_Pos /;" d +EXTI_IMR_MR14 target/stm32f103xb.h /^#define EXTI_IMR_MR14 /;" d +EXTI_IMR_MR15_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR15_Msk /;" d +EXTI_IMR_MR15_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR15_Pos /;" d +EXTI_IMR_MR15 target/stm32f103xb.h /^#define EXTI_IMR_MR15 /;" d +EXTI_IMR_MR16_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR16_Msk /;" d +EXTI_IMR_MR16_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR16_Pos /;" d +EXTI_IMR_MR16 target/stm32f103xb.h /^#define EXTI_IMR_MR16 /;" d +EXTI_IMR_MR17_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR17_Msk /;" d +EXTI_IMR_MR17_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR17_Pos /;" d +EXTI_IMR_MR17 target/stm32f103xb.h /^#define EXTI_IMR_MR17 /;" d +EXTI_IMR_MR18_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR18_Msk /;" d +EXTI_IMR_MR18_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR18_Pos /;" d +EXTI_IMR_MR18 target/stm32f103xb.h /^#define EXTI_IMR_MR18 /;" d +EXTI_IMR_MR1_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR1_Msk /;" d +EXTI_IMR_MR1_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR1_Pos /;" d +EXTI_IMR_MR1 target/stm32f103xb.h /^#define EXTI_IMR_MR1 /;" d +EXTI_IMR_MR2_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR2_Msk /;" d +EXTI_IMR_MR2_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR2_Pos /;" d +EXTI_IMR_MR2 target/stm32f103xb.h /^#define EXTI_IMR_MR2 /;" d +EXTI_IMR_MR3_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR3_Msk /;" d +EXTI_IMR_MR3_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR3_Pos /;" d +EXTI_IMR_MR3 target/stm32f103xb.h /^#define EXTI_IMR_MR3 /;" d +EXTI_IMR_MR4_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR4_Msk /;" d +EXTI_IMR_MR4_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR4_Pos /;" d +EXTI_IMR_MR4 target/stm32f103xb.h /^#define EXTI_IMR_MR4 /;" d +EXTI_IMR_MR5_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR5_Msk /;" d +EXTI_IMR_MR5_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR5_Pos /;" d +EXTI_IMR_MR5 target/stm32f103xb.h /^#define EXTI_IMR_MR5 /;" d +EXTI_IMR_MR6_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR6_Msk /;" d +EXTI_IMR_MR6_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR6_Pos /;" d +EXTI_IMR_MR6 target/stm32f103xb.h /^#define EXTI_IMR_MR6 /;" d +EXTI_IMR_MR7_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR7_Msk /;" d +EXTI_IMR_MR7_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR7_Pos /;" d +EXTI_IMR_MR7 target/stm32f103xb.h /^#define EXTI_IMR_MR7 /;" d +EXTI_IMR_MR8_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR8_Msk /;" d +EXTI_IMR_MR8_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR8_Pos /;" d +EXTI_IMR_MR8 target/stm32f103xb.h /^#define EXTI_IMR_MR8 /;" d +EXTI_IMR_MR9_Msk target/stm32f103xb.h /^#define EXTI_IMR_MR9_Msk /;" d +EXTI_IMR_MR9_Pos target/stm32f103xb.h /^#define EXTI_IMR_MR9_Pos /;" d +EXTI_IMR_MR9 target/stm32f103xb.h /^#define EXTI_IMR_MR9 /;" d +EXTI_PR_PIF0 target/stm32f103xb.h /^#define EXTI_PR_PIF0 /;" d +EXTI_PR_PIF10 target/stm32f103xb.h /^#define EXTI_PR_PIF10 /;" d +EXTI_PR_PIF11 target/stm32f103xb.h /^#define EXTI_PR_PIF11 /;" d +EXTI_PR_PIF12 target/stm32f103xb.h /^#define EXTI_PR_PIF12 /;" d +EXTI_PR_PIF13 target/stm32f103xb.h /^#define EXTI_PR_PIF13 /;" d +EXTI_PR_PIF14 target/stm32f103xb.h /^#define EXTI_PR_PIF14 /;" d +EXTI_PR_PIF15 target/stm32f103xb.h /^#define EXTI_PR_PIF15 /;" d +EXTI_PR_PIF16 target/stm32f103xb.h /^#define EXTI_PR_PIF16 /;" d +EXTI_PR_PIF17 target/stm32f103xb.h /^#define EXTI_PR_PIF17 /;" d +EXTI_PR_PIF18 target/stm32f103xb.h /^#define EXTI_PR_PIF18 /;" d +EXTI_PR_PIF1 target/stm32f103xb.h /^#define EXTI_PR_PIF1 /;" d +EXTI_PR_PIF2 target/stm32f103xb.h /^#define EXTI_PR_PIF2 /;" d +EXTI_PR_PIF3 target/stm32f103xb.h /^#define EXTI_PR_PIF3 /;" d +EXTI_PR_PIF4 target/stm32f103xb.h /^#define EXTI_PR_PIF4 /;" d +EXTI_PR_PIF5 target/stm32f103xb.h /^#define EXTI_PR_PIF5 /;" d +EXTI_PR_PIF6 target/stm32f103xb.h /^#define EXTI_PR_PIF6 /;" d +EXTI_PR_PIF7 target/stm32f103xb.h /^#define EXTI_PR_PIF7 /;" d +EXTI_PR_PIF8 target/stm32f103xb.h /^#define EXTI_PR_PIF8 /;" d +EXTI_PR_PIF9 target/stm32f103xb.h /^#define EXTI_PR_PIF9 /;" d +EXTI_PR_PR0_Msk target/stm32f103xb.h /^#define EXTI_PR_PR0_Msk /;" d +EXTI_PR_PR0_Pos target/stm32f103xb.h /^#define EXTI_PR_PR0_Pos /;" d +EXTI_PR_PR0 target/stm32f103xb.h /^#define EXTI_PR_PR0 /;" d +EXTI_PR_PR10_Msk target/stm32f103xb.h /^#define EXTI_PR_PR10_Msk /;" d +EXTI_PR_PR10_Pos target/stm32f103xb.h /^#define EXTI_PR_PR10_Pos /;" d +EXTI_PR_PR10 target/stm32f103xb.h /^#define EXTI_PR_PR10 /;" d +EXTI_PR_PR11_Msk target/stm32f103xb.h /^#define EXTI_PR_PR11_Msk /;" d +EXTI_PR_PR11_Pos target/stm32f103xb.h /^#define EXTI_PR_PR11_Pos /;" d +EXTI_PR_PR11 target/stm32f103xb.h /^#define EXTI_PR_PR11 /;" d +EXTI_PR_PR12_Msk target/stm32f103xb.h /^#define EXTI_PR_PR12_Msk /;" d +EXTI_PR_PR12_Pos target/stm32f103xb.h /^#define EXTI_PR_PR12_Pos /;" d +EXTI_PR_PR12 target/stm32f103xb.h /^#define EXTI_PR_PR12 /;" d +EXTI_PR_PR13_Msk target/stm32f103xb.h /^#define EXTI_PR_PR13_Msk /;" d +EXTI_PR_PR13_Pos target/stm32f103xb.h /^#define EXTI_PR_PR13_Pos /;" d +EXTI_PR_PR13 target/stm32f103xb.h /^#define EXTI_PR_PR13 /;" d +EXTI_PR_PR14_Msk target/stm32f103xb.h /^#define EXTI_PR_PR14_Msk /;" d +EXTI_PR_PR14_Pos target/stm32f103xb.h /^#define EXTI_PR_PR14_Pos /;" d +EXTI_PR_PR14 target/stm32f103xb.h /^#define EXTI_PR_PR14 /;" d +EXTI_PR_PR15_Msk target/stm32f103xb.h /^#define EXTI_PR_PR15_Msk /;" d +EXTI_PR_PR15_Pos target/stm32f103xb.h /^#define EXTI_PR_PR15_Pos /;" d +EXTI_PR_PR15 target/stm32f103xb.h /^#define EXTI_PR_PR15 /;" d +EXTI_PR_PR16_Msk target/stm32f103xb.h /^#define EXTI_PR_PR16_Msk /;" d +EXTI_PR_PR16_Pos target/stm32f103xb.h /^#define EXTI_PR_PR16_Pos /;" d +EXTI_PR_PR16 target/stm32f103xb.h /^#define EXTI_PR_PR16 /;" d +EXTI_PR_PR17_Msk target/stm32f103xb.h /^#define EXTI_PR_PR17_Msk /;" d +EXTI_PR_PR17_Pos target/stm32f103xb.h /^#define EXTI_PR_PR17_Pos /;" d +EXTI_PR_PR17 target/stm32f103xb.h /^#define EXTI_PR_PR17 /;" d +EXTI_PR_PR18_Msk target/stm32f103xb.h /^#define EXTI_PR_PR18_Msk /;" d +EXTI_PR_PR18_Pos target/stm32f103xb.h /^#define EXTI_PR_PR18_Pos /;" d +EXTI_PR_PR18 target/stm32f103xb.h /^#define EXTI_PR_PR18 /;" d +EXTI_PR_PR1_Msk target/stm32f103xb.h /^#define EXTI_PR_PR1_Msk /;" d +EXTI_PR_PR1_Pos target/stm32f103xb.h /^#define EXTI_PR_PR1_Pos /;" d +EXTI_PR_PR1 target/stm32f103xb.h /^#define EXTI_PR_PR1 /;" d +EXTI_PR_PR2_Msk target/stm32f103xb.h /^#define EXTI_PR_PR2_Msk /;" d +EXTI_PR_PR2_Pos target/stm32f103xb.h /^#define EXTI_PR_PR2_Pos /;" d +EXTI_PR_PR2 target/stm32f103xb.h /^#define EXTI_PR_PR2 /;" d +EXTI_PR_PR3_Msk target/stm32f103xb.h /^#define EXTI_PR_PR3_Msk /;" d +EXTI_PR_PR3_Pos target/stm32f103xb.h /^#define EXTI_PR_PR3_Pos /;" d +EXTI_PR_PR3 target/stm32f103xb.h /^#define EXTI_PR_PR3 /;" d +EXTI_PR_PR4_Msk target/stm32f103xb.h /^#define EXTI_PR_PR4_Msk /;" d +EXTI_PR_PR4_Pos target/stm32f103xb.h /^#define EXTI_PR_PR4_Pos /;" d +EXTI_PR_PR4 target/stm32f103xb.h /^#define EXTI_PR_PR4 /;" d +EXTI_PR_PR5_Msk target/stm32f103xb.h /^#define EXTI_PR_PR5_Msk /;" d +EXTI_PR_PR5_Pos target/stm32f103xb.h /^#define EXTI_PR_PR5_Pos /;" d +EXTI_PR_PR5 target/stm32f103xb.h /^#define EXTI_PR_PR5 /;" d +EXTI_PR_PR6_Msk target/stm32f103xb.h /^#define EXTI_PR_PR6_Msk /;" d +EXTI_PR_PR6_Pos target/stm32f103xb.h /^#define EXTI_PR_PR6_Pos /;" d +EXTI_PR_PR6 target/stm32f103xb.h /^#define EXTI_PR_PR6 /;" d +EXTI_PR_PR7_Msk target/stm32f103xb.h /^#define EXTI_PR_PR7_Msk /;" d +EXTI_PR_PR7_Pos target/stm32f103xb.h /^#define EXTI_PR_PR7_Pos /;" d +EXTI_PR_PR7 target/stm32f103xb.h /^#define EXTI_PR_PR7 /;" d +EXTI_PR_PR8_Msk target/stm32f103xb.h /^#define EXTI_PR_PR8_Msk /;" d +EXTI_PR_PR8_Pos target/stm32f103xb.h /^#define EXTI_PR_PR8_Pos /;" d +EXTI_PR_PR8 target/stm32f103xb.h /^#define EXTI_PR_PR8 /;" d +EXTI_PR_PR9_Msk target/stm32f103xb.h /^#define EXTI_PR_PR9_Msk /;" d +EXTI_PR_PR9_Pos target/stm32f103xb.h /^#define EXTI_PR_PR9_Pos /;" d +EXTI_PR_PR9 target/stm32f103xb.h /^#define EXTI_PR_PR9 /;" d +EXTI_RTSR_RT0 target/stm32f103xb.h /^#define EXTI_RTSR_RT0 /;" d +EXTI_RTSR_RT10 target/stm32f103xb.h /^#define EXTI_RTSR_RT10 /;" d +EXTI_RTSR_RT11 target/stm32f103xb.h /^#define EXTI_RTSR_RT11 /;" d +EXTI_RTSR_RT12 target/stm32f103xb.h /^#define EXTI_RTSR_RT12 /;" d +EXTI_RTSR_RT13 target/stm32f103xb.h /^#define EXTI_RTSR_RT13 /;" d +EXTI_RTSR_RT14 target/stm32f103xb.h /^#define EXTI_RTSR_RT14 /;" d +EXTI_RTSR_RT15 target/stm32f103xb.h /^#define EXTI_RTSR_RT15 /;" d +EXTI_RTSR_RT16 target/stm32f103xb.h /^#define EXTI_RTSR_RT16 /;" d +EXTI_RTSR_RT17 target/stm32f103xb.h /^#define EXTI_RTSR_RT17 /;" d +EXTI_RTSR_RT18 target/stm32f103xb.h /^#define EXTI_RTSR_RT18 /;" d +EXTI_RTSR_RT1 target/stm32f103xb.h /^#define EXTI_RTSR_RT1 /;" d +EXTI_RTSR_RT2 target/stm32f103xb.h /^#define EXTI_RTSR_RT2 /;" d +EXTI_RTSR_RT3 target/stm32f103xb.h /^#define EXTI_RTSR_RT3 /;" d +EXTI_RTSR_RT4 target/stm32f103xb.h /^#define EXTI_RTSR_RT4 /;" d +EXTI_RTSR_RT5 target/stm32f103xb.h /^#define EXTI_RTSR_RT5 /;" d +EXTI_RTSR_RT6 target/stm32f103xb.h /^#define EXTI_RTSR_RT6 /;" d +EXTI_RTSR_RT7 target/stm32f103xb.h /^#define EXTI_RTSR_RT7 /;" d +EXTI_RTSR_RT8 target/stm32f103xb.h /^#define EXTI_RTSR_RT8 /;" d +EXTI_RTSR_RT9 target/stm32f103xb.h /^#define EXTI_RTSR_RT9 /;" d +EXTI_RTSR_TR0_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR0_Msk /;" d +EXTI_RTSR_TR0_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR0_Pos /;" d +EXTI_RTSR_TR0 target/stm32f103xb.h /^#define EXTI_RTSR_TR0 /;" d +EXTI_RTSR_TR10_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR10_Msk /;" d +EXTI_RTSR_TR10_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR10_Pos /;" d +EXTI_RTSR_TR10 target/stm32f103xb.h /^#define EXTI_RTSR_TR10 /;" d +EXTI_RTSR_TR11_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR11_Msk /;" d +EXTI_RTSR_TR11_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR11_Pos /;" d +EXTI_RTSR_TR11 target/stm32f103xb.h /^#define EXTI_RTSR_TR11 /;" d +EXTI_RTSR_TR12_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR12_Msk /;" d +EXTI_RTSR_TR12_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR12_Pos /;" d +EXTI_RTSR_TR12 target/stm32f103xb.h /^#define EXTI_RTSR_TR12 /;" d +EXTI_RTSR_TR13_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR13_Msk /;" d +EXTI_RTSR_TR13_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR13_Pos /;" d +EXTI_RTSR_TR13 target/stm32f103xb.h /^#define EXTI_RTSR_TR13 /;" d +EXTI_RTSR_TR14_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR14_Msk /;" d +EXTI_RTSR_TR14_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR14_Pos /;" d +EXTI_RTSR_TR14 target/stm32f103xb.h /^#define EXTI_RTSR_TR14 /;" d +EXTI_RTSR_TR15_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR15_Msk /;" d +EXTI_RTSR_TR15_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR15_Pos /;" d +EXTI_RTSR_TR15 target/stm32f103xb.h /^#define EXTI_RTSR_TR15 /;" d +EXTI_RTSR_TR16_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR16_Msk /;" d +EXTI_RTSR_TR16_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR16_Pos /;" d +EXTI_RTSR_TR16 target/stm32f103xb.h /^#define EXTI_RTSR_TR16 /;" d +EXTI_RTSR_TR17_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR17_Msk /;" d +EXTI_RTSR_TR17_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR17_Pos /;" d +EXTI_RTSR_TR17 target/stm32f103xb.h /^#define EXTI_RTSR_TR17 /;" d +EXTI_RTSR_TR18_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR18_Msk /;" d +EXTI_RTSR_TR18_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR18_Pos /;" d +EXTI_RTSR_TR18 target/stm32f103xb.h /^#define EXTI_RTSR_TR18 /;" d +EXTI_RTSR_TR1_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR1_Msk /;" d +EXTI_RTSR_TR1_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR1_Pos /;" d +EXTI_RTSR_TR1 target/stm32f103xb.h /^#define EXTI_RTSR_TR1 /;" d +EXTI_RTSR_TR2_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR2_Msk /;" d +EXTI_RTSR_TR2_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR2_Pos /;" d +EXTI_RTSR_TR2 target/stm32f103xb.h /^#define EXTI_RTSR_TR2 /;" d +EXTI_RTSR_TR3_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR3_Msk /;" d +EXTI_RTSR_TR3_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR3_Pos /;" d +EXTI_RTSR_TR3 target/stm32f103xb.h /^#define EXTI_RTSR_TR3 /;" d +EXTI_RTSR_TR4_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR4_Msk /;" d +EXTI_RTSR_TR4_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR4_Pos /;" d +EXTI_RTSR_TR4 target/stm32f103xb.h /^#define EXTI_RTSR_TR4 /;" d +EXTI_RTSR_TR5_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR5_Msk /;" d +EXTI_RTSR_TR5_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR5_Pos /;" d +EXTI_RTSR_TR5 target/stm32f103xb.h /^#define EXTI_RTSR_TR5 /;" d +EXTI_RTSR_TR6_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR6_Msk /;" d +EXTI_RTSR_TR6_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR6_Pos /;" d +EXTI_RTSR_TR6 target/stm32f103xb.h /^#define EXTI_RTSR_TR6 /;" d +EXTI_RTSR_TR7_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR7_Msk /;" d +EXTI_RTSR_TR7_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR7_Pos /;" d +EXTI_RTSR_TR7 target/stm32f103xb.h /^#define EXTI_RTSR_TR7 /;" d +EXTI_RTSR_TR8_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR8_Msk /;" d +EXTI_RTSR_TR8_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR8_Pos /;" d +EXTI_RTSR_TR8 target/stm32f103xb.h /^#define EXTI_RTSR_TR8 /;" d +EXTI_RTSR_TR9_Msk target/stm32f103xb.h /^#define EXTI_RTSR_TR9_Msk /;" d +EXTI_RTSR_TR9_Pos target/stm32f103xb.h /^#define EXTI_RTSR_TR9_Pos /;" d +EXTI_RTSR_TR9 target/stm32f103xb.h /^#define EXTI_RTSR_TR9 /;" d +EXTI_SWIER_SWI0 target/stm32f103xb.h /^#define EXTI_SWIER_SWI0 /;" d +EXTI_SWIER_SWI10 target/stm32f103xb.h /^#define EXTI_SWIER_SWI10 /;" d +EXTI_SWIER_SWI11 target/stm32f103xb.h /^#define EXTI_SWIER_SWI11 /;" d +EXTI_SWIER_SWI12 target/stm32f103xb.h /^#define EXTI_SWIER_SWI12 /;" d +EXTI_SWIER_SWI13 target/stm32f103xb.h /^#define EXTI_SWIER_SWI13 /;" d +EXTI_SWIER_SWI14 target/stm32f103xb.h /^#define EXTI_SWIER_SWI14 /;" d +EXTI_SWIER_SWI15 target/stm32f103xb.h /^#define EXTI_SWIER_SWI15 /;" d +EXTI_SWIER_SWI16 target/stm32f103xb.h /^#define EXTI_SWIER_SWI16 /;" d +EXTI_SWIER_SWI17 target/stm32f103xb.h /^#define EXTI_SWIER_SWI17 /;" d +EXTI_SWIER_SWI18 target/stm32f103xb.h /^#define EXTI_SWIER_SWI18 /;" d +EXTI_SWIER_SWI1 target/stm32f103xb.h /^#define EXTI_SWIER_SWI1 /;" d +EXTI_SWIER_SWI2 target/stm32f103xb.h /^#define EXTI_SWIER_SWI2 /;" d +EXTI_SWIER_SWI3 target/stm32f103xb.h /^#define EXTI_SWIER_SWI3 /;" d +EXTI_SWIER_SWI4 target/stm32f103xb.h /^#define EXTI_SWIER_SWI4 /;" d +EXTI_SWIER_SWI5 target/stm32f103xb.h /^#define EXTI_SWIER_SWI5 /;" d +EXTI_SWIER_SWI6 target/stm32f103xb.h /^#define EXTI_SWIER_SWI6 /;" d +EXTI_SWIER_SWI7 target/stm32f103xb.h /^#define EXTI_SWIER_SWI7 /;" d +EXTI_SWIER_SWI8 target/stm32f103xb.h /^#define EXTI_SWIER_SWI8 /;" d +EXTI_SWIER_SWI9 target/stm32f103xb.h /^#define EXTI_SWIER_SWI9 /;" d +EXTI_SWIER_SWIER0_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER0_Msk /;" d +EXTI_SWIER_SWIER0_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER0_Pos /;" d +EXTI_SWIER_SWIER0 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER0 /;" d +EXTI_SWIER_SWIER10_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER10_Msk /;" d +EXTI_SWIER_SWIER10_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER10_Pos /;" d +EXTI_SWIER_SWIER10 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER10 /;" d +EXTI_SWIER_SWIER11_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER11_Msk /;" d +EXTI_SWIER_SWIER11_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER11_Pos /;" d +EXTI_SWIER_SWIER11 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER11 /;" d +EXTI_SWIER_SWIER12_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER12_Msk /;" d +EXTI_SWIER_SWIER12_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER12_Pos /;" d +EXTI_SWIER_SWIER12 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER12 /;" d +EXTI_SWIER_SWIER13_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER13_Msk /;" d +EXTI_SWIER_SWIER13_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER13_Pos /;" d +EXTI_SWIER_SWIER13 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER13 /;" d +EXTI_SWIER_SWIER14_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER14_Msk /;" d +EXTI_SWIER_SWIER14_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER14_Pos /;" d +EXTI_SWIER_SWIER14 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER14 /;" d +EXTI_SWIER_SWIER15_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER15_Msk /;" d +EXTI_SWIER_SWIER15_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER15_Pos /;" d +EXTI_SWIER_SWIER15 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER15 /;" d +EXTI_SWIER_SWIER16_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER16_Msk /;" d +EXTI_SWIER_SWIER16_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER16_Pos /;" d +EXTI_SWIER_SWIER16 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER16 /;" d +EXTI_SWIER_SWIER17_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER17_Msk /;" d +EXTI_SWIER_SWIER17_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER17_Pos /;" d +EXTI_SWIER_SWIER17 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER17 /;" d +EXTI_SWIER_SWIER18_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER18_Msk /;" d +EXTI_SWIER_SWIER18_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER18_Pos /;" d +EXTI_SWIER_SWIER18 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER18 /;" d +EXTI_SWIER_SWIER1_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER1_Msk /;" d +EXTI_SWIER_SWIER1_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER1_Pos /;" d +EXTI_SWIER_SWIER1 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER1 /;" d +EXTI_SWIER_SWIER2_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER2_Msk /;" d +EXTI_SWIER_SWIER2_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER2_Pos /;" d +EXTI_SWIER_SWIER2 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER2 /;" d +EXTI_SWIER_SWIER3_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER3_Msk /;" d +EXTI_SWIER_SWIER3_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER3_Pos /;" d +EXTI_SWIER_SWIER3 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER3 /;" d +EXTI_SWIER_SWIER4_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER4_Msk /;" d +EXTI_SWIER_SWIER4_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER4_Pos /;" d +EXTI_SWIER_SWIER4 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER4 /;" d +EXTI_SWIER_SWIER5_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER5_Msk /;" d +EXTI_SWIER_SWIER5_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER5_Pos /;" d +EXTI_SWIER_SWIER5 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER5 /;" d +EXTI_SWIER_SWIER6_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER6_Msk /;" d +EXTI_SWIER_SWIER6_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER6_Pos /;" d +EXTI_SWIER_SWIER6 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER6 /;" d +EXTI_SWIER_SWIER7_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER7_Msk /;" d +EXTI_SWIER_SWIER7_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER7_Pos /;" d +EXTI_SWIER_SWIER7 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER7 /;" d +EXTI_SWIER_SWIER8_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER8_Msk /;" d +EXTI_SWIER_SWIER8_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER8_Pos /;" d +EXTI_SWIER_SWIER8 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER8 /;" d +EXTI_SWIER_SWIER9_Msk target/stm32f103xb.h /^#define EXTI_SWIER_SWIER9_Msk /;" d +EXTI_SWIER_SWIER9_Pos target/stm32f103xb.h /^#define EXTI_SWIER_SWIER9_Pos /;" d +EXTI_SWIER_SWIER9 target/stm32f103xb.h /^#define EXTI_SWIER_SWIER9 /;" d +EXTI_TypeDef target/stm32f103xb.h /^} EXTI_TypeDef;$/;" t typeref:struct:__anon72c4c37e0d08 +EXTI target/stm32f103xb.h /^#define EXTI /;" d +ErrorStatus target/stm32f1xx.h /^} ErrorStatus;$/;" t typeref:enum:__anonbccbea710303 +FA1R target/stm32f103xb.h /^ __IO uint32_t FA1R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +FFA1R target/stm32f103xb.h /^ __IO uint32_t FFA1R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +FIFOCNT target/stm32f103xb.h /^ __I uint32_t FIFOCNT;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +FIFO target/stm32f103xb.h /^ __IO uint32_t FIFO;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +FLASHSIZE_BASE target/stm32f103xb.h /^#define FLASHSIZE_BASE /;" d +FLASH_ACR_HLFCYA_Msk target/stm32f103xb.h /^#define FLASH_ACR_HLFCYA_Msk /;" d +FLASH_ACR_HLFCYA_Pos target/stm32f103xb.h /^#define FLASH_ACR_HLFCYA_Pos /;" d +FLASH_ACR_HLFCYA target/stm32f103xb.h /^#define FLASH_ACR_HLFCYA /;" d +FLASH_ACR_LATENCY_0 target/stm32f103xb.h /^#define FLASH_ACR_LATENCY_0 /;" d +FLASH_ACR_LATENCY_1 target/stm32f103xb.h /^#define FLASH_ACR_LATENCY_1 /;" d +FLASH_ACR_LATENCY_2 target/stm32f103xb.h /^#define FLASH_ACR_LATENCY_2 /;" d +FLASH_ACR_LATENCY_Msk target/stm32f103xb.h /^#define FLASH_ACR_LATENCY_Msk /;" d +FLASH_ACR_LATENCY_Pos target/stm32f103xb.h /^#define FLASH_ACR_LATENCY_Pos /;" d +FLASH_ACR_LATENCY target/stm32f103xb.h /^#define FLASH_ACR_LATENCY /;" d +FLASH_ACR_PRFTBE_Msk target/stm32f103xb.h /^#define FLASH_ACR_PRFTBE_Msk /;" d +FLASH_ACR_PRFTBE_Pos target/stm32f103xb.h /^#define FLASH_ACR_PRFTBE_Pos /;" d +FLASH_ACR_PRFTBE target/stm32f103xb.h /^#define FLASH_ACR_PRFTBE /;" d +FLASH_ACR_PRFTBS_Msk target/stm32f103xb.h /^#define FLASH_ACR_PRFTBS_Msk /;" d +FLASH_ACR_PRFTBS_Pos target/stm32f103xb.h /^#define FLASH_ACR_PRFTBS_Pos /;" d +FLASH_ACR_PRFTBS target/stm32f103xb.h /^#define FLASH_ACR_PRFTBS /;" d +FLASH_AR_FAR_Msk target/stm32f103xb.h /^#define FLASH_AR_FAR_Msk /;" d +FLASH_AR_FAR_Pos target/stm32f103xb.h /^#define FLASH_AR_FAR_Pos /;" d +FLASH_AR_FAR target/stm32f103xb.h /^#define FLASH_AR_FAR /;" d +FLASH_BANK1_END target/stm32f103xb.h /^#define FLASH_BANK1_END /;" d +FLASH_BASE target/stm32f103xb.h /^#define FLASH_BASE /;" d +FLASH_CR_EOPIE_Msk target/stm32f103xb.h /^#define FLASH_CR_EOPIE_Msk /;" d +FLASH_CR_EOPIE_Pos target/stm32f103xb.h /^#define FLASH_CR_EOPIE_Pos /;" d +FLASH_CR_EOPIE target/stm32f103xb.h /^#define FLASH_CR_EOPIE /;" d +FLASH_CR_ERRIE_Msk target/stm32f103xb.h /^#define FLASH_CR_ERRIE_Msk /;" d +FLASH_CR_ERRIE_Pos target/stm32f103xb.h /^#define FLASH_CR_ERRIE_Pos /;" d +FLASH_CR_ERRIE target/stm32f103xb.h /^#define FLASH_CR_ERRIE /;" d +FLASH_CR_LOCK_Msk target/stm32f103xb.h /^#define FLASH_CR_LOCK_Msk /;" d +FLASH_CR_LOCK_Pos target/stm32f103xb.h /^#define FLASH_CR_LOCK_Pos /;" d +FLASH_CR_LOCK target/stm32f103xb.h /^#define FLASH_CR_LOCK /;" d +FLASH_CR_MER_Msk target/stm32f103xb.h /^#define FLASH_CR_MER_Msk /;" d +FLASH_CR_MER_Pos target/stm32f103xb.h /^#define FLASH_CR_MER_Pos /;" d +FLASH_CR_MER target/stm32f103xb.h /^#define FLASH_CR_MER /;" d +FLASH_CR_OPTER_Msk target/stm32f103xb.h /^#define FLASH_CR_OPTER_Msk /;" d +FLASH_CR_OPTER_Pos target/stm32f103xb.h /^#define FLASH_CR_OPTER_Pos /;" d +FLASH_CR_OPTER target/stm32f103xb.h /^#define FLASH_CR_OPTER /;" d +FLASH_CR_OPTPG_Msk target/stm32f103xb.h /^#define FLASH_CR_OPTPG_Msk /;" d +FLASH_CR_OPTPG_Pos target/stm32f103xb.h /^#define FLASH_CR_OPTPG_Pos /;" d +FLASH_CR_OPTPG target/stm32f103xb.h /^#define FLASH_CR_OPTPG /;" d +FLASH_CR_OPTWRE_Msk target/stm32f103xb.h /^#define FLASH_CR_OPTWRE_Msk /;" d +FLASH_CR_OPTWRE_Pos target/stm32f103xb.h /^#define FLASH_CR_OPTWRE_Pos /;" d +FLASH_CR_OPTWRE target/stm32f103xb.h /^#define FLASH_CR_OPTWRE /;" d +FLASH_CR_PER_Msk target/stm32f103xb.h /^#define FLASH_CR_PER_Msk /;" d +FLASH_CR_PER_Pos target/stm32f103xb.h /^#define FLASH_CR_PER_Pos /;" d +FLASH_CR_PER target/stm32f103xb.h /^#define FLASH_CR_PER /;" d +FLASH_CR_PG_Msk target/stm32f103xb.h /^#define FLASH_CR_PG_Msk /;" d +FLASH_CR_PG_Pos target/stm32f103xb.h /^#define FLASH_CR_PG_Pos /;" d +FLASH_CR_PG target/stm32f103xb.h /^#define FLASH_CR_PG /;" d +FLASH_CR_STRT_Msk target/stm32f103xb.h /^#define FLASH_CR_STRT_Msk /;" d +FLASH_CR_STRT_Pos target/stm32f103xb.h /^#define FLASH_CR_STRT_Pos /;" d +FLASH_CR_STRT target/stm32f103xb.h /^#define FLASH_CR_STRT /;" d +FLASH_DATA0_DATA0_Msk target/stm32f103xb.h /^#define FLASH_DATA0_DATA0_Msk /;" d +FLASH_DATA0_DATA0_Pos target/stm32f103xb.h /^#define FLASH_DATA0_DATA0_Pos /;" d +FLASH_DATA0_DATA0 target/stm32f103xb.h /^#define FLASH_DATA0_DATA0 /;" d +FLASH_DATA0_nDATA0_Msk target/stm32f103xb.h /^#define FLASH_DATA0_nDATA0_Msk /;" d +FLASH_DATA0_nDATA0_Pos target/stm32f103xb.h /^#define FLASH_DATA0_nDATA0_Pos /;" d +FLASH_DATA0_nDATA0 target/stm32f103xb.h /^#define FLASH_DATA0_nDATA0 /;" d +FLASH_DATA1_DATA1_Msk target/stm32f103xb.h /^#define FLASH_DATA1_DATA1_Msk /;" d +FLASH_DATA1_DATA1_Pos target/stm32f103xb.h /^#define FLASH_DATA1_DATA1_Pos /;" d +FLASH_DATA1_DATA1 target/stm32f103xb.h /^#define FLASH_DATA1_DATA1 /;" d +FLASH_DATA1_nDATA1_Msk target/stm32f103xb.h /^#define FLASH_DATA1_nDATA1_Msk /;" d +FLASH_DATA1_nDATA1_Pos target/stm32f103xb.h /^#define FLASH_DATA1_nDATA1_Pos /;" d +FLASH_DATA1_nDATA1 target/stm32f103xb.h /^#define FLASH_DATA1_nDATA1 /;" d +FLASH_IRQn target/stm32f103xb.h /^ FLASH_IRQn = 4, \/*!< FLASH global Interrupt /;" e enum:__anon72c4c37e0103 +FLASH_KEY1_Msk target/stm32f103xb.h /^#define FLASH_KEY1_Msk /;" d +FLASH_KEY1_Pos target/stm32f103xb.h /^#define FLASH_KEY1_Pos /;" d +FLASH_KEY1 target/stm32f103xb.h /^#define FLASH_KEY1 /;" d +FLASH_KEY2_Msk target/stm32f103xb.h /^#define FLASH_KEY2_Msk /;" d +FLASH_KEY2_Pos target/stm32f103xb.h /^#define FLASH_KEY2_Pos /;" d +FLASH_KEY2 target/stm32f103xb.h /^#define FLASH_KEY2 /;" d +FLASH_KEYR_FKEYR_Msk target/stm32f103xb.h /^#define FLASH_KEYR_FKEYR_Msk /;" d +FLASH_KEYR_FKEYR_Pos target/stm32f103xb.h /^#define FLASH_KEYR_FKEYR_Pos /;" d +FLASH_KEYR_FKEYR target/stm32f103xb.h /^#define FLASH_KEYR_FKEYR /;" d +FLASH_OBR_DATA0_Msk target/stm32f103xb.h /^#define FLASH_OBR_DATA0_Msk /;" d +FLASH_OBR_DATA0_Pos target/stm32f103xb.h /^#define FLASH_OBR_DATA0_Pos /;" d +FLASH_OBR_DATA0 target/stm32f103xb.h /^#define FLASH_OBR_DATA0 /;" d +FLASH_OBR_DATA1_Msk target/stm32f103xb.h /^#define FLASH_OBR_DATA1_Msk /;" d +FLASH_OBR_DATA1_Pos target/stm32f103xb.h /^#define FLASH_OBR_DATA1_Pos /;" d +FLASH_OBR_DATA1 target/stm32f103xb.h /^#define FLASH_OBR_DATA1 /;" d +FLASH_OBR_IWDG_SW_Msk target/stm32f103xb.h /^#define FLASH_OBR_IWDG_SW_Msk /;" d +FLASH_OBR_IWDG_SW_Pos target/stm32f103xb.h /^#define FLASH_OBR_IWDG_SW_Pos /;" d +FLASH_OBR_IWDG_SW target/stm32f103xb.h /^#define FLASH_OBR_IWDG_SW /;" d +FLASH_OBR_OPTERR_Msk target/stm32f103xb.h /^#define FLASH_OBR_OPTERR_Msk /;" d +FLASH_OBR_OPTERR_Pos target/stm32f103xb.h /^#define FLASH_OBR_OPTERR_Pos /;" d +FLASH_OBR_OPTERR target/stm32f103xb.h /^#define FLASH_OBR_OPTERR /;" d +FLASH_OBR_RDPRT_Msk target/stm32f103xb.h /^#define FLASH_OBR_RDPRT_Msk /;" d +FLASH_OBR_RDPRT_Pos target/stm32f103xb.h /^#define FLASH_OBR_RDPRT_Pos /;" d +FLASH_OBR_RDPRT target/stm32f103xb.h /^#define FLASH_OBR_RDPRT /;" d +FLASH_OBR_USER_Msk target/stm32f103xb.h /^#define FLASH_OBR_USER_Msk /;" d +FLASH_OBR_USER_Pos target/stm32f103xb.h /^#define FLASH_OBR_USER_Pos /;" d +FLASH_OBR_USER target/stm32f103xb.h /^#define FLASH_OBR_USER /;" d +FLASH_OBR_nRST_STDBY_Msk target/stm32f103xb.h /^#define FLASH_OBR_nRST_STDBY_Msk /;" d +FLASH_OBR_nRST_STDBY_Pos target/stm32f103xb.h /^#define FLASH_OBR_nRST_STDBY_Pos /;" d +FLASH_OBR_nRST_STDBY target/stm32f103xb.h /^#define FLASH_OBR_nRST_STDBY /;" d +FLASH_OBR_nRST_STOP_Msk target/stm32f103xb.h /^#define FLASH_OBR_nRST_STOP_Msk /;" d +FLASH_OBR_nRST_STOP_Pos target/stm32f103xb.h /^#define FLASH_OBR_nRST_STOP_Pos /;" d +FLASH_OBR_nRST_STOP target/stm32f103xb.h /^#define FLASH_OBR_nRST_STOP /;" d +FLASH_OPTKEY1 target/stm32f103xb.h /^#define FLASH_OPTKEY1 /;" d +FLASH_OPTKEY2 target/stm32f103xb.h /^#define FLASH_OPTKEY2 /;" d +FLASH_OPTKEYR_OPTKEYR_Msk target/stm32f103xb.h /^#define FLASH_OPTKEYR_OPTKEYR_Msk /;" d +FLASH_OPTKEYR_OPTKEYR_Pos target/stm32f103xb.h /^#define FLASH_OPTKEYR_OPTKEYR_Pos /;" d +FLASH_OPTKEYR_OPTKEYR target/stm32f103xb.h /^#define FLASH_OPTKEYR_OPTKEYR /;" d +FLASH_RDP_RDP_Msk target/stm32f103xb.h /^#define FLASH_RDP_RDP_Msk /;" d +FLASH_RDP_RDP_Pos target/stm32f103xb.h /^#define FLASH_RDP_RDP_Pos /;" d +FLASH_RDP_RDP target/stm32f103xb.h /^#define FLASH_RDP_RDP /;" d +FLASH_RDP_nRDP_Msk target/stm32f103xb.h /^#define FLASH_RDP_nRDP_Msk /;" d +FLASH_RDP_nRDP_Pos target/stm32f103xb.h /^#define FLASH_RDP_nRDP_Pos /;" d +FLASH_RDP_nRDP target/stm32f103xb.h /^#define FLASH_RDP_nRDP /;" d +FLASH_R_BASE target/stm32f103xb.h /^#define FLASH_R_BASE /;" d +FLASH_SR_BSY_Msk target/stm32f103xb.h /^#define FLASH_SR_BSY_Msk /;" d +FLASH_SR_BSY_Pos target/stm32f103xb.h /^#define FLASH_SR_BSY_Pos /;" d +FLASH_SR_BSY target/stm32f103xb.h /^#define FLASH_SR_BSY /;" d +FLASH_SR_EOP_Msk target/stm32f103xb.h /^#define FLASH_SR_EOP_Msk /;" d +FLASH_SR_EOP_Pos target/stm32f103xb.h /^#define FLASH_SR_EOP_Pos /;" d +FLASH_SR_EOP target/stm32f103xb.h /^#define FLASH_SR_EOP /;" d +FLASH_SR_PGERR_Msk target/stm32f103xb.h /^#define FLASH_SR_PGERR_Msk /;" d +FLASH_SR_PGERR_Pos target/stm32f103xb.h /^#define FLASH_SR_PGERR_Pos /;" d +FLASH_SR_PGERR target/stm32f103xb.h /^#define FLASH_SR_PGERR /;" d +FLASH_SR_WRPRTERR_Msk target/stm32f103xb.h /^#define FLASH_SR_WRPRTERR_Msk /;" d +FLASH_SR_WRPRTERR_Pos target/stm32f103xb.h /^#define FLASH_SR_WRPRTERR_Pos /;" d +FLASH_SR_WRPRTERR target/stm32f103xb.h /^#define FLASH_SR_WRPRTERR /;" d +FLASH_TypeDef target/stm32f103xb.h /^} FLASH_TypeDef;$/;" t typeref:struct:__anon72c4c37e0e08 +FLASH_USER_USER_Msk target/stm32f103xb.h /^#define FLASH_USER_USER_Msk /;" d +FLASH_USER_USER_Pos target/stm32f103xb.h /^#define FLASH_USER_USER_Pos /;" d +FLASH_USER_USER target/stm32f103xb.h /^#define FLASH_USER_USER /;" d +FLASH_USER_nUSER_Msk target/stm32f103xb.h /^#define FLASH_USER_nUSER_Msk /;" d +FLASH_USER_nUSER_Pos target/stm32f103xb.h /^#define FLASH_USER_nUSER_Pos /;" d +FLASH_USER_nUSER target/stm32f103xb.h /^#define FLASH_USER_nUSER /;" d +FLASH_WRP0_WRP0_Msk target/stm32f103xb.h /^#define FLASH_WRP0_WRP0_Msk /;" d +FLASH_WRP0_WRP0_Pos target/stm32f103xb.h /^#define FLASH_WRP0_WRP0_Pos /;" d +FLASH_WRP0_WRP0 target/stm32f103xb.h /^#define FLASH_WRP0_WRP0 /;" d +FLASH_WRP0_nWRP0_Msk target/stm32f103xb.h /^#define FLASH_WRP0_nWRP0_Msk /;" d +FLASH_WRP0_nWRP0_Pos target/stm32f103xb.h /^#define FLASH_WRP0_nWRP0_Pos /;" d +FLASH_WRP0_nWRP0 target/stm32f103xb.h /^#define FLASH_WRP0_nWRP0 /;" d +FLASH_WRP1_WRP1_Msk target/stm32f103xb.h /^#define FLASH_WRP1_WRP1_Msk /;" d +FLASH_WRP1_WRP1_Pos target/stm32f103xb.h /^#define FLASH_WRP1_WRP1_Pos /;" d +FLASH_WRP1_WRP1 target/stm32f103xb.h /^#define FLASH_WRP1_WRP1 /;" d +FLASH_WRP1_nWRP1_Msk target/stm32f103xb.h /^#define FLASH_WRP1_nWRP1_Msk /;" d +FLASH_WRP1_nWRP1_Pos target/stm32f103xb.h /^#define FLASH_WRP1_nWRP1_Pos /;" d +FLASH_WRP1_nWRP1 target/stm32f103xb.h /^#define FLASH_WRP1_nWRP1 /;" d +FLASH_WRP2_WRP2_Msk target/stm32f103xb.h /^#define FLASH_WRP2_WRP2_Msk /;" d +FLASH_WRP2_WRP2_Pos target/stm32f103xb.h /^#define FLASH_WRP2_WRP2_Pos /;" d +FLASH_WRP2_WRP2 target/stm32f103xb.h /^#define FLASH_WRP2_WRP2 /;" d +FLASH_WRP2_nWRP2_Msk target/stm32f103xb.h /^#define FLASH_WRP2_nWRP2_Msk /;" d +FLASH_WRP2_nWRP2_Pos target/stm32f103xb.h /^#define FLASH_WRP2_nWRP2_Pos /;" d +FLASH_WRP2_nWRP2 target/stm32f103xb.h /^#define FLASH_WRP2_nWRP2 /;" d +FLASH_WRP3_WRP3_Msk target/stm32f103xb.h /^#define FLASH_WRP3_WRP3_Msk /;" d +FLASH_WRP3_WRP3_Pos target/stm32f103xb.h /^#define FLASH_WRP3_WRP3_Pos /;" d +FLASH_WRP3_WRP3 target/stm32f103xb.h /^#define FLASH_WRP3_WRP3 /;" d +FLASH_WRP3_nWRP3_Msk target/stm32f103xb.h /^#define FLASH_WRP3_nWRP3_Msk /;" d +FLASH_WRP3_nWRP3_Pos target/stm32f103xb.h /^#define FLASH_WRP3_nWRP3_Pos /;" d +FLASH_WRP3_nWRP3 target/stm32f103xb.h /^#define FLASH_WRP3_nWRP3 /;" d +FLASH_WRPR_WRP_Msk target/stm32f103xb.h /^#define FLASH_WRPR_WRP_Msk /;" d +FLASH_WRPR_WRP_Pos target/stm32f103xb.h /^#define FLASH_WRPR_WRP_Pos /;" d +FLASH_WRPR_WRP target/stm32f103xb.h /^#define FLASH_WRPR_WRP /;" d +FLASH target/stm32f103xb.h /^#define FLASH /;" d +FM1R target/stm32f103xb.h /^ __IO uint32_t FM1R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +FMR target/stm32f103xb.h /^ __IO uint32_t FMR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +FNR target/stm32f103xb.h /^ __IO uint16_t FNR; \/*!< Frame number register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +FR1 target/stm32f103xb.h /^ __IO uint32_t FR1;$/;" m struct:__anon72c4c37e0708 typeref:typename:__IO uint32_t +FR2 target/stm32f103xb.h /^ __IO uint32_t FR2;$/;" m struct:__anon72c4c37e0708 typeref:typename:__IO uint32_t +FS1R target/stm32f103xb.h /^ __IO uint32_t FS1R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +FTSR target/stm32f103xb.h /^ __IO uint32_t FTSR;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +FlagStatus target/stm32f1xx.h /^} FlagStatus, ITStatus;$/;" t typeref:enum:__anonbccbea710103 +FunctionalState target/stm32f1xx.h /^} FunctionalState;$/;" t typeref:enum:__anonbccbea710203 +GPIOA_BASE target/stm32f103xb.h /^#define GPIOA_BASE /;" d +GPIOA target/stm32f103xb.h /^#define GPIOA /;" d +GPIOB_BASE target/stm32f103xb.h /^#define GPIOB_BASE /;" d +GPIOB target/stm32f103xb.h /^#define GPIOB /;" d +GPIOC_BASE target/stm32f103xb.h /^#define GPIOC_BASE /;" d +GPIOC target/stm32f103xb.h /^#define GPIOC /;" d +GPIOD_BASE target/stm32f103xb.h /^#define GPIOD_BASE /;" d +GPIOD target/stm32f103xb.h /^#define GPIOD /;" d +GPIOE_BASE target/stm32f103xb.h /^#define GPIOE_BASE /;" d +GPIOE target/stm32f103xb.h /^#define GPIOE /;" d +GPIO_BRR_BR0_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR0_Msk /;" d +GPIO_BRR_BR0_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR0_Pos /;" d +GPIO_BRR_BR0 target/stm32f103xb.h /^#define GPIO_BRR_BR0 /;" d +GPIO_BRR_BR10_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR10_Msk /;" d +GPIO_BRR_BR10_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR10_Pos /;" d +GPIO_BRR_BR10 target/stm32f103xb.h /^#define GPIO_BRR_BR10 /;" d +GPIO_BRR_BR11_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR11_Msk /;" d +GPIO_BRR_BR11_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR11_Pos /;" d +GPIO_BRR_BR11 target/stm32f103xb.h /^#define GPIO_BRR_BR11 /;" d +GPIO_BRR_BR12_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR12_Msk /;" d +GPIO_BRR_BR12_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR12_Pos /;" d +GPIO_BRR_BR12 target/stm32f103xb.h /^#define GPIO_BRR_BR12 /;" d +GPIO_BRR_BR13_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR13_Msk /;" d +GPIO_BRR_BR13_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR13_Pos /;" d +GPIO_BRR_BR13 target/stm32f103xb.h /^#define GPIO_BRR_BR13 /;" d +GPIO_BRR_BR14_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR14_Msk /;" d +GPIO_BRR_BR14_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR14_Pos /;" d +GPIO_BRR_BR14 target/stm32f103xb.h /^#define GPIO_BRR_BR14 /;" d +GPIO_BRR_BR15_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR15_Msk /;" d +GPIO_BRR_BR15_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR15_Pos /;" d +GPIO_BRR_BR15 target/stm32f103xb.h /^#define GPIO_BRR_BR15 /;" d +GPIO_BRR_BR1_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR1_Msk /;" d +GPIO_BRR_BR1_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR1_Pos /;" d +GPIO_BRR_BR1 target/stm32f103xb.h /^#define GPIO_BRR_BR1 /;" d +GPIO_BRR_BR2_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR2_Msk /;" d +GPIO_BRR_BR2_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR2_Pos /;" d +GPIO_BRR_BR2 target/stm32f103xb.h /^#define GPIO_BRR_BR2 /;" d +GPIO_BRR_BR3_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR3_Msk /;" d +GPIO_BRR_BR3_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR3_Pos /;" d +GPIO_BRR_BR3 target/stm32f103xb.h /^#define GPIO_BRR_BR3 /;" d +GPIO_BRR_BR4_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR4_Msk /;" d +GPIO_BRR_BR4_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR4_Pos /;" d +GPIO_BRR_BR4 target/stm32f103xb.h /^#define GPIO_BRR_BR4 /;" d +GPIO_BRR_BR5_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR5_Msk /;" d +GPIO_BRR_BR5_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR5_Pos /;" d +GPIO_BRR_BR5 target/stm32f103xb.h /^#define GPIO_BRR_BR5 /;" d +GPIO_BRR_BR6_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR6_Msk /;" d +GPIO_BRR_BR6_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR6_Pos /;" d +GPIO_BRR_BR6 target/stm32f103xb.h /^#define GPIO_BRR_BR6 /;" d +GPIO_BRR_BR7_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR7_Msk /;" d +GPIO_BRR_BR7_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR7_Pos /;" d +GPIO_BRR_BR7 target/stm32f103xb.h /^#define GPIO_BRR_BR7 /;" d +GPIO_BRR_BR8_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR8_Msk /;" d +GPIO_BRR_BR8_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR8_Pos /;" d +GPIO_BRR_BR8 target/stm32f103xb.h /^#define GPIO_BRR_BR8 /;" d +GPIO_BRR_BR9_Msk target/stm32f103xb.h /^#define GPIO_BRR_BR9_Msk /;" d +GPIO_BRR_BR9_Pos target/stm32f103xb.h /^#define GPIO_BRR_BR9_Pos /;" d +GPIO_BRR_BR9 target/stm32f103xb.h /^#define GPIO_BRR_BR9 /;" d +GPIO_BSRR_BR0_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR0_Msk /;" d +GPIO_BSRR_BR0_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR0_Pos /;" d +GPIO_BSRR_BR0 target/stm32f103xb.h /^#define GPIO_BSRR_BR0 /;" d +GPIO_BSRR_BR10_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR10_Msk /;" d +GPIO_BSRR_BR10_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR10_Pos /;" d +GPIO_BSRR_BR10 target/stm32f103xb.h /^#define GPIO_BSRR_BR10 /;" d +GPIO_BSRR_BR11_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR11_Msk /;" d +GPIO_BSRR_BR11_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR11_Pos /;" d +GPIO_BSRR_BR11 target/stm32f103xb.h /^#define GPIO_BSRR_BR11 /;" d +GPIO_BSRR_BR12_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR12_Msk /;" d +GPIO_BSRR_BR12_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR12_Pos /;" d +GPIO_BSRR_BR12 target/stm32f103xb.h /^#define GPIO_BSRR_BR12 /;" d +GPIO_BSRR_BR13_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR13_Msk /;" d +GPIO_BSRR_BR13_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR13_Pos /;" d +GPIO_BSRR_BR13 target/stm32f103xb.h /^#define GPIO_BSRR_BR13 /;" d +GPIO_BSRR_BR14_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR14_Msk /;" d +GPIO_BSRR_BR14_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR14_Pos /;" d +GPIO_BSRR_BR14 target/stm32f103xb.h /^#define GPIO_BSRR_BR14 /;" d +GPIO_BSRR_BR15_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR15_Msk /;" d +GPIO_BSRR_BR15_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR15_Pos /;" d +GPIO_BSRR_BR15 target/stm32f103xb.h /^#define GPIO_BSRR_BR15 /;" d +GPIO_BSRR_BR1_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR1_Msk /;" d +GPIO_BSRR_BR1_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR1_Pos /;" d +GPIO_BSRR_BR1 target/stm32f103xb.h /^#define GPIO_BSRR_BR1 /;" d +GPIO_BSRR_BR2_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR2_Msk /;" d +GPIO_BSRR_BR2_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR2_Pos /;" d +GPIO_BSRR_BR2 target/stm32f103xb.h /^#define GPIO_BSRR_BR2 /;" d +GPIO_BSRR_BR3_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR3_Msk /;" d +GPIO_BSRR_BR3_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR3_Pos /;" d +GPIO_BSRR_BR3 target/stm32f103xb.h /^#define GPIO_BSRR_BR3 /;" d +GPIO_BSRR_BR4_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR4_Msk /;" d +GPIO_BSRR_BR4_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR4_Pos /;" d +GPIO_BSRR_BR4 target/stm32f103xb.h /^#define GPIO_BSRR_BR4 /;" d +GPIO_BSRR_BR5_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR5_Msk /;" d +GPIO_BSRR_BR5_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR5_Pos /;" d +GPIO_BSRR_BR5 target/stm32f103xb.h /^#define GPIO_BSRR_BR5 /;" d +GPIO_BSRR_BR6_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR6_Msk /;" d +GPIO_BSRR_BR6_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR6_Pos /;" d +GPIO_BSRR_BR6 target/stm32f103xb.h /^#define GPIO_BSRR_BR6 /;" d +GPIO_BSRR_BR7_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR7_Msk /;" d +GPIO_BSRR_BR7_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR7_Pos /;" d +GPIO_BSRR_BR7 target/stm32f103xb.h /^#define GPIO_BSRR_BR7 /;" d +GPIO_BSRR_BR8_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR8_Msk /;" d +GPIO_BSRR_BR8_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR8_Pos /;" d +GPIO_BSRR_BR8 target/stm32f103xb.h /^#define GPIO_BSRR_BR8 /;" d +GPIO_BSRR_BR9_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BR9_Msk /;" d +GPIO_BSRR_BR9_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BR9_Pos /;" d +GPIO_BSRR_BR9 target/stm32f103xb.h /^#define GPIO_BSRR_BR9 /;" d +GPIO_BSRR_BS0_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS0_Msk /;" d +GPIO_BSRR_BS0_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS0_Pos /;" d +GPIO_BSRR_BS0 target/stm32f103xb.h /^#define GPIO_BSRR_BS0 /;" d +GPIO_BSRR_BS10_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS10_Msk /;" d +GPIO_BSRR_BS10_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS10_Pos /;" d +GPIO_BSRR_BS10 target/stm32f103xb.h /^#define GPIO_BSRR_BS10 /;" d +GPIO_BSRR_BS11_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS11_Msk /;" d +GPIO_BSRR_BS11_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS11_Pos /;" d +GPIO_BSRR_BS11 target/stm32f103xb.h /^#define GPIO_BSRR_BS11 /;" d +GPIO_BSRR_BS12_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS12_Msk /;" d +GPIO_BSRR_BS12_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS12_Pos /;" d +GPIO_BSRR_BS12 target/stm32f103xb.h /^#define GPIO_BSRR_BS12 /;" d +GPIO_BSRR_BS13_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS13_Msk /;" d +GPIO_BSRR_BS13_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS13_Pos /;" d +GPIO_BSRR_BS13 target/stm32f103xb.h /^#define GPIO_BSRR_BS13 /;" d +GPIO_BSRR_BS14_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS14_Msk /;" d +GPIO_BSRR_BS14_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS14_Pos /;" d +GPIO_BSRR_BS14 target/stm32f103xb.h /^#define GPIO_BSRR_BS14 /;" d +GPIO_BSRR_BS15_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS15_Msk /;" d +GPIO_BSRR_BS15_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS15_Pos /;" d +GPIO_BSRR_BS15 target/stm32f103xb.h /^#define GPIO_BSRR_BS15 /;" d +GPIO_BSRR_BS1_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS1_Msk /;" d +GPIO_BSRR_BS1_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS1_Pos /;" d +GPIO_BSRR_BS1 target/stm32f103xb.h /^#define GPIO_BSRR_BS1 /;" d +GPIO_BSRR_BS2_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS2_Msk /;" d +GPIO_BSRR_BS2_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS2_Pos /;" d +GPIO_BSRR_BS2 target/stm32f103xb.h /^#define GPIO_BSRR_BS2 /;" d +GPIO_BSRR_BS3_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS3_Msk /;" d +GPIO_BSRR_BS3_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS3_Pos /;" d +GPIO_BSRR_BS3 target/stm32f103xb.h /^#define GPIO_BSRR_BS3 /;" d +GPIO_BSRR_BS4_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS4_Msk /;" d +GPIO_BSRR_BS4_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS4_Pos /;" d +GPIO_BSRR_BS4 target/stm32f103xb.h /^#define GPIO_BSRR_BS4 /;" d +GPIO_BSRR_BS5_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS5_Msk /;" d +GPIO_BSRR_BS5_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS5_Pos /;" d +GPIO_BSRR_BS5 target/stm32f103xb.h /^#define GPIO_BSRR_BS5 /;" d +GPIO_BSRR_BS6_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS6_Msk /;" d +GPIO_BSRR_BS6_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS6_Pos /;" d +GPIO_BSRR_BS6 target/stm32f103xb.h /^#define GPIO_BSRR_BS6 /;" d +GPIO_BSRR_BS7_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS7_Msk /;" d +GPIO_BSRR_BS7_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS7_Pos /;" d +GPIO_BSRR_BS7 target/stm32f103xb.h /^#define GPIO_BSRR_BS7 /;" d +GPIO_BSRR_BS8_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS8_Msk /;" d +GPIO_BSRR_BS8_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS8_Pos /;" d +GPIO_BSRR_BS8 target/stm32f103xb.h /^#define GPIO_BSRR_BS8 /;" d +GPIO_BSRR_BS9_Msk target/stm32f103xb.h /^#define GPIO_BSRR_BS9_Msk /;" d +GPIO_BSRR_BS9_Pos target/stm32f103xb.h /^#define GPIO_BSRR_BS9_Pos /;" d +GPIO_BSRR_BS9 target/stm32f103xb.h /^#define GPIO_BSRR_BS9 /;" d +GPIO_CRH_CNF10_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF10_0 /;" d +GPIO_CRH_CNF10_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF10_1 /;" d +GPIO_CRH_CNF10_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF10_Msk /;" d +GPIO_CRH_CNF10_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF10_Pos /;" d +GPIO_CRH_CNF10 target/stm32f103xb.h /^#define GPIO_CRH_CNF10 /;" d +GPIO_CRH_CNF11_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF11_0 /;" d +GPIO_CRH_CNF11_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF11_1 /;" d +GPIO_CRH_CNF11_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF11_Msk /;" d +GPIO_CRH_CNF11_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF11_Pos /;" d +GPIO_CRH_CNF11 target/stm32f103xb.h /^#define GPIO_CRH_CNF11 /;" d +GPIO_CRH_CNF12_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF12_0 /;" d +GPIO_CRH_CNF12_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF12_1 /;" d +GPIO_CRH_CNF12_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF12_Msk /;" d +GPIO_CRH_CNF12_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF12_Pos /;" d +GPIO_CRH_CNF12 target/stm32f103xb.h /^#define GPIO_CRH_CNF12 /;" d +GPIO_CRH_CNF13_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF13_0 /;" d +GPIO_CRH_CNF13_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF13_1 /;" d +GPIO_CRH_CNF13_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF13_Msk /;" d +GPIO_CRH_CNF13_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF13_Pos /;" d +GPIO_CRH_CNF13 target/stm32f103xb.h /^#define GPIO_CRH_CNF13 /;" d +GPIO_CRH_CNF14_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF14_0 /;" d +GPIO_CRH_CNF14_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF14_1 /;" d +GPIO_CRH_CNF14_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF14_Msk /;" d +GPIO_CRH_CNF14_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF14_Pos /;" d +GPIO_CRH_CNF14 target/stm32f103xb.h /^#define GPIO_CRH_CNF14 /;" d +GPIO_CRH_CNF15_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF15_0 /;" d +GPIO_CRH_CNF15_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF15_1 /;" d +GPIO_CRH_CNF15_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF15_Msk /;" d +GPIO_CRH_CNF15_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF15_Pos /;" d +GPIO_CRH_CNF15 target/stm32f103xb.h /^#define GPIO_CRH_CNF15 /;" d +GPIO_CRH_CNF8_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF8_0 /;" d +GPIO_CRH_CNF8_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF8_1 /;" d +GPIO_CRH_CNF8_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF8_Msk /;" d +GPIO_CRH_CNF8_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF8_Pos /;" d +GPIO_CRH_CNF8 target/stm32f103xb.h /^#define GPIO_CRH_CNF8 /;" d +GPIO_CRH_CNF9_0 target/stm32f103xb.h /^#define GPIO_CRH_CNF9_0 /;" d +GPIO_CRH_CNF9_1 target/stm32f103xb.h /^#define GPIO_CRH_CNF9_1 /;" d +GPIO_CRH_CNF9_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF9_Msk /;" d +GPIO_CRH_CNF9_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF9_Pos /;" d +GPIO_CRH_CNF9 target/stm32f103xb.h /^#define GPIO_CRH_CNF9 /;" d +GPIO_CRH_CNF_Msk target/stm32f103xb.h /^#define GPIO_CRH_CNF_Msk /;" d +GPIO_CRH_CNF_Pos target/stm32f103xb.h /^#define GPIO_CRH_CNF_Pos /;" d +GPIO_CRH_CNF target/stm32f103xb.h /^#define GPIO_CRH_CNF /;" d +GPIO_CRH_MODE10_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE10_0 /;" d +GPIO_CRH_MODE10_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE10_1 /;" d +GPIO_CRH_MODE10_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE10_Msk /;" d +GPIO_CRH_MODE10_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE10_Pos /;" d +GPIO_CRH_MODE10 target/stm32f103xb.h /^#define GPIO_CRH_MODE10 /;" d +GPIO_CRH_MODE11_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE11_0 /;" d +GPIO_CRH_MODE11_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE11_1 /;" d +GPIO_CRH_MODE11_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE11_Msk /;" d +GPIO_CRH_MODE11_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE11_Pos /;" d +GPIO_CRH_MODE11 target/stm32f103xb.h /^#define GPIO_CRH_MODE11 /;" d +GPIO_CRH_MODE12_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE12_0 /;" d +GPIO_CRH_MODE12_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE12_1 /;" d +GPIO_CRH_MODE12_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE12_Msk /;" d +GPIO_CRH_MODE12_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE12_Pos /;" d +GPIO_CRH_MODE12 target/stm32f103xb.h /^#define GPIO_CRH_MODE12 /;" d +GPIO_CRH_MODE13_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE13_0 /;" d +GPIO_CRH_MODE13_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE13_1 /;" d +GPIO_CRH_MODE13_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE13_Msk /;" d +GPIO_CRH_MODE13_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE13_Pos /;" d +GPIO_CRH_MODE13 target/stm32f103xb.h /^#define GPIO_CRH_MODE13 /;" d +GPIO_CRH_MODE14_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE14_0 /;" d +GPIO_CRH_MODE14_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE14_1 /;" d +GPIO_CRH_MODE14_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE14_Msk /;" d +GPIO_CRH_MODE14_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE14_Pos /;" d +GPIO_CRH_MODE14 target/stm32f103xb.h /^#define GPIO_CRH_MODE14 /;" d +GPIO_CRH_MODE15_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE15_0 /;" d +GPIO_CRH_MODE15_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE15_1 /;" d +GPIO_CRH_MODE15_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE15_Msk /;" d +GPIO_CRH_MODE15_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE15_Pos /;" d +GPIO_CRH_MODE15 target/stm32f103xb.h /^#define GPIO_CRH_MODE15 /;" d +GPIO_CRH_MODE8_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE8_0 /;" d +GPIO_CRH_MODE8_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE8_1 /;" d +GPIO_CRH_MODE8_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE8_Msk /;" d +GPIO_CRH_MODE8_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE8_Pos /;" d +GPIO_CRH_MODE8 target/stm32f103xb.h /^#define GPIO_CRH_MODE8 /;" d +GPIO_CRH_MODE9_0 target/stm32f103xb.h /^#define GPIO_CRH_MODE9_0 /;" d +GPIO_CRH_MODE9_1 target/stm32f103xb.h /^#define GPIO_CRH_MODE9_1 /;" d +GPIO_CRH_MODE9_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE9_Msk /;" d +GPIO_CRH_MODE9_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE9_Pos /;" d +GPIO_CRH_MODE9 target/stm32f103xb.h /^#define GPIO_CRH_MODE9 /;" d +GPIO_CRH_MODE_Msk target/stm32f103xb.h /^#define GPIO_CRH_MODE_Msk /;" d +GPIO_CRH_MODE_Pos target/stm32f103xb.h /^#define GPIO_CRH_MODE_Pos /;" d +GPIO_CRH_MODE target/stm32f103xb.h /^#define GPIO_CRH_MODE /;" d +GPIO_CRL_CNF0_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF0_0 /;" d +GPIO_CRL_CNF0_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF0_1 /;" d +GPIO_CRL_CNF0_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF0_Msk /;" d +GPIO_CRL_CNF0_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF0_Pos /;" d +GPIO_CRL_CNF0 target/stm32f103xb.h /^#define GPIO_CRL_CNF0 /;" d +GPIO_CRL_CNF1_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF1_0 /;" d +GPIO_CRL_CNF1_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF1_1 /;" d +GPIO_CRL_CNF1_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF1_Msk /;" d +GPIO_CRL_CNF1_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF1_Pos /;" d +GPIO_CRL_CNF1 target/stm32f103xb.h /^#define GPIO_CRL_CNF1 /;" d +GPIO_CRL_CNF2_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF2_0 /;" d +GPIO_CRL_CNF2_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF2_1 /;" d +GPIO_CRL_CNF2_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF2_Msk /;" d +GPIO_CRL_CNF2_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF2_Pos /;" d +GPIO_CRL_CNF2 target/stm32f103xb.h /^#define GPIO_CRL_CNF2 /;" d +GPIO_CRL_CNF3_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF3_0 /;" d +GPIO_CRL_CNF3_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF3_1 /;" d +GPIO_CRL_CNF3_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF3_Msk /;" d +GPIO_CRL_CNF3_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF3_Pos /;" d +GPIO_CRL_CNF3 target/stm32f103xb.h /^#define GPIO_CRL_CNF3 /;" d +GPIO_CRL_CNF4_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF4_0 /;" d +GPIO_CRL_CNF4_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF4_1 /;" d +GPIO_CRL_CNF4_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF4_Msk /;" d +GPIO_CRL_CNF4_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF4_Pos /;" d +GPIO_CRL_CNF4 target/stm32f103xb.h /^#define GPIO_CRL_CNF4 /;" d +GPIO_CRL_CNF5_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF5_0 /;" d +GPIO_CRL_CNF5_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF5_1 /;" d +GPIO_CRL_CNF5_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF5_Msk /;" d +GPIO_CRL_CNF5_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF5_Pos /;" d +GPIO_CRL_CNF5 target/stm32f103xb.h /^#define GPIO_CRL_CNF5 /;" d +GPIO_CRL_CNF6_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF6_0 /;" d +GPIO_CRL_CNF6_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF6_1 /;" d +GPIO_CRL_CNF6_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF6_Msk /;" d +GPIO_CRL_CNF6_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF6_Pos /;" d +GPIO_CRL_CNF6 target/stm32f103xb.h /^#define GPIO_CRL_CNF6 /;" d +GPIO_CRL_CNF7_0 target/stm32f103xb.h /^#define GPIO_CRL_CNF7_0 /;" d +GPIO_CRL_CNF7_1 target/stm32f103xb.h /^#define GPIO_CRL_CNF7_1 /;" d +GPIO_CRL_CNF7_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF7_Msk /;" d +GPIO_CRL_CNF7_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF7_Pos /;" d +GPIO_CRL_CNF7 target/stm32f103xb.h /^#define GPIO_CRL_CNF7 /;" d +GPIO_CRL_CNF_Msk target/stm32f103xb.h /^#define GPIO_CRL_CNF_Msk /;" d +GPIO_CRL_CNF_Pos target/stm32f103xb.h /^#define GPIO_CRL_CNF_Pos /;" d +GPIO_CRL_CNF target/stm32f103xb.h /^#define GPIO_CRL_CNF /;" d +GPIO_CRL_MODE0_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE0_0 /;" d +GPIO_CRL_MODE0_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE0_1 /;" d +GPIO_CRL_MODE0_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE0_Msk /;" d +GPIO_CRL_MODE0_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE0_Pos /;" d +GPIO_CRL_MODE0 target/stm32f103xb.h /^#define GPIO_CRL_MODE0 /;" d +GPIO_CRL_MODE1_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE1_0 /;" d +GPIO_CRL_MODE1_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE1_1 /;" d +GPIO_CRL_MODE1_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE1_Msk /;" d +GPIO_CRL_MODE1_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE1_Pos /;" d +GPIO_CRL_MODE1 target/stm32f103xb.h /^#define GPIO_CRL_MODE1 /;" d +GPIO_CRL_MODE2_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE2_0 /;" d +GPIO_CRL_MODE2_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE2_1 /;" d +GPIO_CRL_MODE2_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE2_Msk /;" d +GPIO_CRL_MODE2_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE2_Pos /;" d +GPIO_CRL_MODE2 target/stm32f103xb.h /^#define GPIO_CRL_MODE2 /;" d +GPIO_CRL_MODE3_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE3_0 /;" d +GPIO_CRL_MODE3_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE3_1 /;" d +GPIO_CRL_MODE3_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE3_Msk /;" d +GPIO_CRL_MODE3_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE3_Pos /;" d +GPIO_CRL_MODE3 target/stm32f103xb.h /^#define GPIO_CRL_MODE3 /;" d +GPIO_CRL_MODE4_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE4_0 /;" d +GPIO_CRL_MODE4_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE4_1 /;" d +GPIO_CRL_MODE4_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE4_Msk /;" d +GPIO_CRL_MODE4_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE4_Pos /;" d +GPIO_CRL_MODE4 target/stm32f103xb.h /^#define GPIO_CRL_MODE4 /;" d +GPIO_CRL_MODE5_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE5_0 /;" d +GPIO_CRL_MODE5_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE5_1 /;" d +GPIO_CRL_MODE5_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE5_Msk /;" d +GPIO_CRL_MODE5_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE5_Pos /;" d +GPIO_CRL_MODE5 target/stm32f103xb.h /^#define GPIO_CRL_MODE5 /;" d +GPIO_CRL_MODE6_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE6_0 /;" d +GPIO_CRL_MODE6_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE6_1 /;" d +GPIO_CRL_MODE6_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE6_Msk /;" d +GPIO_CRL_MODE6_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE6_Pos /;" d +GPIO_CRL_MODE6 target/stm32f103xb.h /^#define GPIO_CRL_MODE6 /;" d +GPIO_CRL_MODE7_0 target/stm32f103xb.h /^#define GPIO_CRL_MODE7_0 /;" d +GPIO_CRL_MODE7_1 target/stm32f103xb.h /^#define GPIO_CRL_MODE7_1 /;" d +GPIO_CRL_MODE7_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE7_Msk /;" d +GPIO_CRL_MODE7_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE7_Pos /;" d +GPIO_CRL_MODE7 target/stm32f103xb.h /^#define GPIO_CRL_MODE7 /;" d +GPIO_CRL_MODE_Msk target/stm32f103xb.h /^#define GPIO_CRL_MODE_Msk /;" d +GPIO_CRL_MODE_Pos target/stm32f103xb.h /^#define GPIO_CRL_MODE_Pos /;" d +GPIO_CRL_MODE target/stm32f103xb.h /^#define GPIO_CRL_MODE /;" d +GPIO_IDR_IDR0_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR0_Msk /;" d +GPIO_IDR_IDR0_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR0_Pos /;" d +GPIO_IDR_IDR0 target/stm32f103xb.h /^#define GPIO_IDR_IDR0 /;" d +GPIO_IDR_IDR10_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR10_Msk /;" d +GPIO_IDR_IDR10_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR10_Pos /;" d +GPIO_IDR_IDR10 target/stm32f103xb.h /^#define GPIO_IDR_IDR10 /;" d +GPIO_IDR_IDR11_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR11_Msk /;" d +GPIO_IDR_IDR11_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR11_Pos /;" d +GPIO_IDR_IDR11 target/stm32f103xb.h /^#define GPIO_IDR_IDR11 /;" d +GPIO_IDR_IDR12_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR12_Msk /;" d +GPIO_IDR_IDR12_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR12_Pos /;" d +GPIO_IDR_IDR12 target/stm32f103xb.h /^#define GPIO_IDR_IDR12 /;" d +GPIO_IDR_IDR13_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR13_Msk /;" d +GPIO_IDR_IDR13_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR13_Pos /;" d +GPIO_IDR_IDR13 target/stm32f103xb.h /^#define GPIO_IDR_IDR13 /;" d +GPIO_IDR_IDR14_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR14_Msk /;" d +GPIO_IDR_IDR14_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR14_Pos /;" d +GPIO_IDR_IDR14 target/stm32f103xb.h /^#define GPIO_IDR_IDR14 /;" d +GPIO_IDR_IDR15_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR15_Msk /;" d +GPIO_IDR_IDR15_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR15_Pos /;" d +GPIO_IDR_IDR15 target/stm32f103xb.h /^#define GPIO_IDR_IDR15 /;" d +GPIO_IDR_IDR1_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR1_Msk /;" d +GPIO_IDR_IDR1_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR1_Pos /;" d +GPIO_IDR_IDR1 target/stm32f103xb.h /^#define GPIO_IDR_IDR1 /;" d +GPIO_IDR_IDR2_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR2_Msk /;" d +GPIO_IDR_IDR2_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR2_Pos /;" d +GPIO_IDR_IDR2 target/stm32f103xb.h /^#define GPIO_IDR_IDR2 /;" d +GPIO_IDR_IDR3_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR3_Msk /;" d +GPIO_IDR_IDR3_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR3_Pos /;" d +GPIO_IDR_IDR3 target/stm32f103xb.h /^#define GPIO_IDR_IDR3 /;" d +GPIO_IDR_IDR4_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR4_Msk /;" d +GPIO_IDR_IDR4_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR4_Pos /;" d +GPIO_IDR_IDR4 target/stm32f103xb.h /^#define GPIO_IDR_IDR4 /;" d +GPIO_IDR_IDR5_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR5_Msk /;" d +GPIO_IDR_IDR5_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR5_Pos /;" d +GPIO_IDR_IDR5 target/stm32f103xb.h /^#define GPIO_IDR_IDR5 /;" d +GPIO_IDR_IDR6_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR6_Msk /;" d +GPIO_IDR_IDR6_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR6_Pos /;" d +GPIO_IDR_IDR6 target/stm32f103xb.h /^#define GPIO_IDR_IDR6 /;" d +GPIO_IDR_IDR7_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR7_Msk /;" d +GPIO_IDR_IDR7_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR7_Pos /;" d +GPIO_IDR_IDR7 target/stm32f103xb.h /^#define GPIO_IDR_IDR7 /;" d +GPIO_IDR_IDR8_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR8_Msk /;" d +GPIO_IDR_IDR8_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR8_Pos /;" d +GPIO_IDR_IDR8 target/stm32f103xb.h /^#define GPIO_IDR_IDR8 /;" d +GPIO_IDR_IDR9_Msk target/stm32f103xb.h /^#define GPIO_IDR_IDR9_Msk /;" d +GPIO_IDR_IDR9_Pos target/stm32f103xb.h /^#define GPIO_IDR_IDR9_Pos /;" d +GPIO_IDR_IDR9 target/stm32f103xb.h /^#define GPIO_IDR_IDR9 /;" d +GPIO_LCKR_LCK0_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK0_Msk /;" d +GPIO_LCKR_LCK0_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK0_Pos /;" d +GPIO_LCKR_LCK0 target/stm32f103xb.h /^#define GPIO_LCKR_LCK0 /;" d +GPIO_LCKR_LCK10_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK10_Msk /;" d +GPIO_LCKR_LCK10_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK10_Pos /;" d +GPIO_LCKR_LCK10 target/stm32f103xb.h /^#define GPIO_LCKR_LCK10 /;" d +GPIO_LCKR_LCK11_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK11_Msk /;" d +GPIO_LCKR_LCK11_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK11_Pos /;" d +GPIO_LCKR_LCK11 target/stm32f103xb.h /^#define GPIO_LCKR_LCK11 /;" d +GPIO_LCKR_LCK12_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK12_Msk /;" d +GPIO_LCKR_LCK12_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK12_Pos /;" d +GPIO_LCKR_LCK12 target/stm32f103xb.h /^#define GPIO_LCKR_LCK12 /;" d +GPIO_LCKR_LCK13_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK13_Msk /;" d +GPIO_LCKR_LCK13_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK13_Pos /;" d +GPIO_LCKR_LCK13 target/stm32f103xb.h /^#define GPIO_LCKR_LCK13 /;" d +GPIO_LCKR_LCK14_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK14_Msk /;" d +GPIO_LCKR_LCK14_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK14_Pos /;" d +GPIO_LCKR_LCK14 target/stm32f103xb.h /^#define GPIO_LCKR_LCK14 /;" d +GPIO_LCKR_LCK15_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK15_Msk /;" d +GPIO_LCKR_LCK15_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK15_Pos /;" d +GPIO_LCKR_LCK15 target/stm32f103xb.h /^#define GPIO_LCKR_LCK15 /;" d +GPIO_LCKR_LCK1_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK1_Msk /;" d +GPIO_LCKR_LCK1_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK1_Pos /;" d +GPIO_LCKR_LCK1 target/stm32f103xb.h /^#define GPIO_LCKR_LCK1 /;" d +GPIO_LCKR_LCK2_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK2_Msk /;" d +GPIO_LCKR_LCK2_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK2_Pos /;" d +GPIO_LCKR_LCK2 target/stm32f103xb.h /^#define GPIO_LCKR_LCK2 /;" d +GPIO_LCKR_LCK3_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK3_Msk /;" d +GPIO_LCKR_LCK3_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK3_Pos /;" d +GPIO_LCKR_LCK3 target/stm32f103xb.h /^#define GPIO_LCKR_LCK3 /;" d +GPIO_LCKR_LCK4_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK4_Msk /;" d +GPIO_LCKR_LCK4_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK4_Pos /;" d +GPIO_LCKR_LCK4 target/stm32f103xb.h /^#define GPIO_LCKR_LCK4 /;" d +GPIO_LCKR_LCK5_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK5_Msk /;" d +GPIO_LCKR_LCK5_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK5_Pos /;" d +GPIO_LCKR_LCK5 target/stm32f103xb.h /^#define GPIO_LCKR_LCK5 /;" d +GPIO_LCKR_LCK6_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK6_Msk /;" d +GPIO_LCKR_LCK6_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK6_Pos /;" d +GPIO_LCKR_LCK6 target/stm32f103xb.h /^#define GPIO_LCKR_LCK6 /;" d +GPIO_LCKR_LCK7_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK7_Msk /;" d +GPIO_LCKR_LCK7_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK7_Pos /;" d +GPIO_LCKR_LCK7 target/stm32f103xb.h /^#define GPIO_LCKR_LCK7 /;" d +GPIO_LCKR_LCK8_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK8_Msk /;" d +GPIO_LCKR_LCK8_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK8_Pos /;" d +GPIO_LCKR_LCK8 target/stm32f103xb.h /^#define GPIO_LCKR_LCK8 /;" d +GPIO_LCKR_LCK9_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCK9_Msk /;" d +GPIO_LCKR_LCK9_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCK9_Pos /;" d +GPIO_LCKR_LCK9 target/stm32f103xb.h /^#define GPIO_LCKR_LCK9 /;" d +GPIO_LCKR_LCKK_Msk target/stm32f103xb.h /^#define GPIO_LCKR_LCKK_Msk /;" d +GPIO_LCKR_LCKK_Pos target/stm32f103xb.h /^#define GPIO_LCKR_LCKK_Pos /;" d +GPIO_LCKR_LCKK target/stm32f103xb.h /^#define GPIO_LCKR_LCKK /;" d +GPIO_ODR_ODR0_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR0_Msk /;" d +GPIO_ODR_ODR0_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR0_Pos /;" d +GPIO_ODR_ODR0 target/stm32f103xb.h /^#define GPIO_ODR_ODR0 /;" d +GPIO_ODR_ODR10_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR10_Msk /;" d +GPIO_ODR_ODR10_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR10_Pos /;" d +GPIO_ODR_ODR10 target/stm32f103xb.h /^#define GPIO_ODR_ODR10 /;" d +GPIO_ODR_ODR11_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR11_Msk /;" d +GPIO_ODR_ODR11_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR11_Pos /;" d +GPIO_ODR_ODR11 target/stm32f103xb.h /^#define GPIO_ODR_ODR11 /;" d +GPIO_ODR_ODR12_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR12_Msk /;" d +GPIO_ODR_ODR12_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR12_Pos /;" d +GPIO_ODR_ODR12 target/stm32f103xb.h /^#define GPIO_ODR_ODR12 /;" d +GPIO_ODR_ODR13_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR13_Msk /;" d +GPIO_ODR_ODR13_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR13_Pos /;" d +GPIO_ODR_ODR13 target/stm32f103xb.h /^#define GPIO_ODR_ODR13 /;" d +GPIO_ODR_ODR14_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR14_Msk /;" d +GPIO_ODR_ODR14_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR14_Pos /;" d +GPIO_ODR_ODR14 target/stm32f103xb.h /^#define GPIO_ODR_ODR14 /;" d +GPIO_ODR_ODR15_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR15_Msk /;" d +GPIO_ODR_ODR15_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR15_Pos /;" d +GPIO_ODR_ODR15 target/stm32f103xb.h /^#define GPIO_ODR_ODR15 /;" d +GPIO_ODR_ODR1_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR1_Msk /;" d +GPIO_ODR_ODR1_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR1_Pos /;" d +GPIO_ODR_ODR1 target/stm32f103xb.h /^#define GPIO_ODR_ODR1 /;" d +GPIO_ODR_ODR2_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR2_Msk /;" d +GPIO_ODR_ODR2_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR2_Pos /;" d +GPIO_ODR_ODR2 target/stm32f103xb.h /^#define GPIO_ODR_ODR2 /;" d +GPIO_ODR_ODR3_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR3_Msk /;" d +GPIO_ODR_ODR3_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR3_Pos /;" d +GPIO_ODR_ODR3 target/stm32f103xb.h /^#define GPIO_ODR_ODR3 /;" d +GPIO_ODR_ODR4_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR4_Msk /;" d +GPIO_ODR_ODR4_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR4_Pos /;" d +GPIO_ODR_ODR4 target/stm32f103xb.h /^#define GPIO_ODR_ODR4 /;" d +GPIO_ODR_ODR5_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR5_Msk /;" d +GPIO_ODR_ODR5_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR5_Pos /;" d +GPIO_ODR_ODR5 target/stm32f103xb.h /^#define GPIO_ODR_ODR5 /;" d +GPIO_ODR_ODR6_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR6_Msk /;" d +GPIO_ODR_ODR6_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR6_Pos /;" d +GPIO_ODR_ODR6 target/stm32f103xb.h /^#define GPIO_ODR_ODR6 /;" d +GPIO_ODR_ODR7_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR7_Msk /;" d +GPIO_ODR_ODR7_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR7_Pos /;" d +GPIO_ODR_ODR7 target/stm32f103xb.h /^#define GPIO_ODR_ODR7 /;" d +GPIO_ODR_ODR8_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR8_Msk /;" d +GPIO_ODR_ODR8_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR8_Pos /;" d +GPIO_ODR_ODR8 target/stm32f103xb.h /^#define GPIO_ODR_ODR8 /;" d +GPIO_ODR_ODR9_Msk target/stm32f103xb.h /^#define GPIO_ODR_ODR9_Msk /;" d +GPIO_ODR_ODR9_Pos target/stm32f103xb.h /^#define GPIO_ODR_ODR9_Pos /;" d +GPIO_ODR_ODR9 target/stm32f103xb.h /^#define GPIO_ODR_ODR9 /;" d +GPIO_TypeDef target/stm32f103xb.h /^} GPIO_TypeDef;$/;" t typeref:struct:__anon72c4c37e1008 +GTPR target/stm32f103xb.h /^ __IO uint32_t GTPR; \/*!< USART Guard time and prescaler register, Address offset: 0x18 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +HTR target/stm32f103xb.h /^ __IO uint32_t HTR;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +HardFault_Handler Untitled Folder/sys_handlers.c /^void HardFault_Handler(void)$/;" f typeref:typename:void +HardFault_IRQn target/stm32f103xb.h /^ HardFault_IRQn = -13, \/*!< 3 Cortex-M3 Hard Fault Interrupt /;" e enum:__anon72c4c37e0103 +I2C1_BASE target/stm32f103xb.h /^#define I2C1_BASE /;" d +I2C1_ER_IRQn target/stm32f103xb.h /^ I2C1_ER_IRQn = 32, \/*!< I2C1 Error Interrupt /;" e enum:__anon72c4c37e0103 +I2C1_EV_IRQn target/stm32f103xb.h /^ I2C1_EV_IRQn = 31, \/*!< I2C1 Event Interrupt /;" e enum:__anon72c4c37e0103 +I2C1_IRQERR_PRIORITY Untitled Folder/config.h /^#define I2C1_IRQERR_PRIORITY /;" d +I2C1_IRQERR_PRIORITY config.h /^#define I2C1_IRQERR_PRIORITY /;" d +I2C1_IRQ_PRIORITY Untitled Folder/config.h /^#define I2C1_IRQ_PRIORITY /;" d +I2C1_IRQ_PRIORITY config.h /^#define I2C1_IRQ_PRIORITY /;" d +I2C1 target/stm32f103xb.h /^#define I2C1 /;" d +I2C2_BASE target/stm32f103xb.h /^#define I2C2_BASE /;" d +I2C2_ER_IRQn target/stm32f103xb.h /^ I2C2_ER_IRQn = 34, \/*!< I2C2 Error Interrupt /;" e enum:__anon72c4c37e0103 +I2C2_EV_IRQn target/stm32f103xb.h /^ I2C2_EV_IRQn = 33, \/*!< I2C2 Event Interrupt /;" e enum:__anon72c4c37e0103 +I2C2_IRQERR_PRIORITY Untitled Folder/config.h /^#define I2C2_IRQERR_PRIORITY /;" d +I2C2_IRQERR_PRIORITY config.h /^#define I2C2_IRQERR_PRIORITY /;" d +I2C2_IRQ_PRIORITY Untitled Folder/config.h /^#define I2C2_IRQ_PRIORITY /;" d +I2C2_IRQ_PRIORITY config.h /^#define I2C2_IRQ_PRIORITY /;" d +I2C2 target/stm32f103xb.h /^#define I2C2 /;" d +I2C3_IRQERR_PRIORITY Untitled Folder/config.h /^#define I2C3_IRQERR_PRIORITY /;" d +I2C3_IRQERR_PRIORITY config.h /^#define I2C3_IRQERR_PRIORITY /;" d +I2C3_IRQ_PRIORITY Untitled Folder/config.h /^#define I2C3_IRQ_PRIORITY /;" d +I2C3_IRQ_PRIORITY config.h /^#define I2C3_IRQ_PRIORITY /;" d +I2C_CCR_CCR_Msk target/stm32f103xb.h /^#define I2C_CCR_CCR_Msk /;" d +I2C_CCR_CCR_Pos target/stm32f103xb.h /^#define I2C_CCR_CCR_Pos /;" d +I2C_CCR_CCR target/stm32f103xb.h /^#define I2C_CCR_CCR /;" d +I2C_CCR_DUTY_Msk target/stm32f103xb.h /^#define I2C_CCR_DUTY_Msk /;" d +I2C_CCR_DUTY_Pos target/stm32f103xb.h /^#define I2C_CCR_DUTY_Pos /;" d +I2C_CCR_DUTY target/stm32f103xb.h /^#define I2C_CCR_DUTY /;" d +I2C_CCR_FS_Msk target/stm32f103xb.h /^#define I2C_CCR_FS_Msk /;" d +I2C_CCR_FS_Pos target/stm32f103xb.h /^#define I2C_CCR_FS_Pos /;" d +I2C_CCR_FS target/stm32f103xb.h /^#define I2C_CCR_FS /;" d +I2C_CR1_ACK_Msk target/stm32f103xb.h /^#define I2C_CR1_ACK_Msk /;" d +I2C_CR1_ACK_Pos target/stm32f103xb.h /^#define I2C_CR1_ACK_Pos /;" d +I2C_CR1_ACK target/stm32f103xb.h /^#define I2C_CR1_ACK /;" d +I2C_CR1_ALERT_Msk target/stm32f103xb.h /^#define I2C_CR1_ALERT_Msk /;" d +I2C_CR1_ALERT_Pos target/stm32f103xb.h /^#define I2C_CR1_ALERT_Pos /;" d +I2C_CR1_ALERT target/stm32f103xb.h /^#define I2C_CR1_ALERT /;" d +I2C_CR1_ENARP_Msk target/stm32f103xb.h /^#define I2C_CR1_ENARP_Msk /;" d +I2C_CR1_ENARP_Pos target/stm32f103xb.h /^#define I2C_CR1_ENARP_Pos /;" d +I2C_CR1_ENARP target/stm32f103xb.h /^#define I2C_CR1_ENARP /;" d +I2C_CR1_ENGC_Msk target/stm32f103xb.h /^#define I2C_CR1_ENGC_Msk /;" d +I2C_CR1_ENGC_Pos target/stm32f103xb.h /^#define I2C_CR1_ENGC_Pos /;" d +I2C_CR1_ENGC target/stm32f103xb.h /^#define I2C_CR1_ENGC /;" d +I2C_CR1_ENPEC_Msk target/stm32f103xb.h /^#define I2C_CR1_ENPEC_Msk /;" d +I2C_CR1_ENPEC_Pos target/stm32f103xb.h /^#define I2C_CR1_ENPEC_Pos /;" d +I2C_CR1_ENPEC target/stm32f103xb.h /^#define I2C_CR1_ENPEC /;" d +I2C_CR1_NOSTRETCH_Msk target/stm32f103xb.h /^#define I2C_CR1_NOSTRETCH_Msk /;" d +I2C_CR1_NOSTRETCH_Pos target/stm32f103xb.h /^#define I2C_CR1_NOSTRETCH_Pos /;" d +I2C_CR1_NOSTRETCH target/stm32f103xb.h /^#define I2C_CR1_NOSTRETCH /;" d +I2C_CR1_PEC_Msk target/stm32f103xb.h /^#define I2C_CR1_PEC_Msk /;" d +I2C_CR1_PEC_Pos target/stm32f103xb.h /^#define I2C_CR1_PEC_Pos /;" d +I2C_CR1_PEC target/stm32f103xb.h /^#define I2C_CR1_PEC /;" d +I2C_CR1_PE_Msk target/stm32f103xb.h /^#define I2C_CR1_PE_Msk /;" d +I2C_CR1_PE_Pos target/stm32f103xb.h /^#define I2C_CR1_PE_Pos /;" d +I2C_CR1_PE target/stm32f103xb.h /^#define I2C_CR1_PE /;" d +I2C_CR1_POS_Msk target/stm32f103xb.h /^#define I2C_CR1_POS_Msk /;" d +I2C_CR1_POS_Pos target/stm32f103xb.h /^#define I2C_CR1_POS_Pos /;" d +I2C_CR1_POS target/stm32f103xb.h /^#define I2C_CR1_POS /;" d +I2C_CR1_SMBTYPE_Msk target/stm32f103xb.h /^#define I2C_CR1_SMBTYPE_Msk /;" d +I2C_CR1_SMBTYPE_Pos target/stm32f103xb.h /^#define I2C_CR1_SMBTYPE_Pos /;" d +I2C_CR1_SMBTYPE target/stm32f103xb.h /^#define I2C_CR1_SMBTYPE /;" d +I2C_CR1_SMBUS_Msk target/stm32f103xb.h /^#define I2C_CR1_SMBUS_Msk /;" d +I2C_CR1_SMBUS_Pos target/stm32f103xb.h /^#define I2C_CR1_SMBUS_Pos /;" d +I2C_CR1_SMBUS target/stm32f103xb.h /^#define I2C_CR1_SMBUS /;" d +I2C_CR1_START_Msk target/stm32f103xb.h /^#define I2C_CR1_START_Msk /;" d +I2C_CR1_START_Pos target/stm32f103xb.h /^#define I2C_CR1_START_Pos /;" d +I2C_CR1_START target/stm32f103xb.h /^#define I2C_CR1_START /;" d +I2C_CR1_STOP_Msk target/stm32f103xb.h /^#define I2C_CR1_STOP_Msk /;" d +I2C_CR1_STOP_Pos target/stm32f103xb.h /^#define I2C_CR1_STOP_Pos /;" d +I2C_CR1_STOP target/stm32f103xb.h /^#define I2C_CR1_STOP /;" d +I2C_CR1_SWRST_Msk target/stm32f103xb.h /^#define I2C_CR1_SWRST_Msk /;" d +I2C_CR1_SWRST_Pos target/stm32f103xb.h /^#define I2C_CR1_SWRST_Pos /;" d +I2C_CR1_SWRST target/stm32f103xb.h /^#define I2C_CR1_SWRST /;" d +I2C_CR2_DMAEN_Msk target/stm32f103xb.h /^#define I2C_CR2_DMAEN_Msk /;" d +I2C_CR2_DMAEN_Pos target/stm32f103xb.h /^#define I2C_CR2_DMAEN_Pos /;" d +I2C_CR2_DMAEN target/stm32f103xb.h /^#define I2C_CR2_DMAEN /;" d +I2C_CR2_FREQ_0 target/stm32f103xb.h /^#define I2C_CR2_FREQ_0 /;" d +I2C_CR2_FREQ_1 target/stm32f103xb.h /^#define I2C_CR2_FREQ_1 /;" d +I2C_CR2_FREQ_2 target/stm32f103xb.h /^#define I2C_CR2_FREQ_2 /;" d +I2C_CR2_FREQ_3 target/stm32f103xb.h /^#define I2C_CR2_FREQ_3 /;" d +I2C_CR2_FREQ_4 target/stm32f103xb.h /^#define I2C_CR2_FREQ_4 /;" d +I2C_CR2_FREQ_5 target/stm32f103xb.h /^#define I2C_CR2_FREQ_5 /;" d +I2C_CR2_FREQ_Msk target/stm32f103xb.h /^#define I2C_CR2_FREQ_Msk /;" d +I2C_CR2_FREQ_Pos target/stm32f103xb.h /^#define I2C_CR2_FREQ_Pos /;" d +I2C_CR2_FREQ target/stm32f103xb.h /^#define I2C_CR2_FREQ /;" d +I2C_CR2_ITBUFEN_Msk target/stm32f103xb.h /^#define I2C_CR2_ITBUFEN_Msk /;" d +I2C_CR2_ITBUFEN_Pos target/stm32f103xb.h /^#define I2C_CR2_ITBUFEN_Pos /;" d +I2C_CR2_ITBUFEN target/stm32f103xb.h /^#define I2C_CR2_ITBUFEN /;" d +I2C_CR2_ITERREN_Msk target/stm32f103xb.h /^#define I2C_CR2_ITERREN_Msk /;" d +I2C_CR2_ITERREN_Pos target/stm32f103xb.h /^#define I2C_CR2_ITERREN_Pos /;" d +I2C_CR2_ITERREN target/stm32f103xb.h /^#define I2C_CR2_ITERREN /;" d +I2C_CR2_ITEVTEN_Msk target/stm32f103xb.h /^#define I2C_CR2_ITEVTEN_Msk /;" d +I2C_CR2_ITEVTEN_Pos target/stm32f103xb.h /^#define I2C_CR2_ITEVTEN_Pos /;" d +I2C_CR2_ITEVTEN target/stm32f103xb.h /^#define I2C_CR2_ITEVTEN /;" d +I2C_CR2_LAST_Msk target/stm32f103xb.h /^#define I2C_CR2_LAST_Msk /;" d +I2C_CR2_LAST_Pos target/stm32f103xb.h /^#define I2C_CR2_LAST_Pos /;" d +I2C_CR2_LAST target/stm32f103xb.h /^#define I2C_CR2_LAST /;" d +I2C_DR_DR_Msk target/stm32f103xb.h /^#define I2C_DR_DR_Msk /;" d +I2C_DR_DR_Pos target/stm32f103xb.h /^#define I2C_DR_DR_Pos /;" d +I2C_DR_DR target/stm32f103xb.h /^#define I2C_DR_DR /;" d +I2C_OAR1_ADD0_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD0_Msk /;" d +I2C_OAR1_ADD0_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD0_Pos /;" d +I2C_OAR1_ADD0 target/stm32f103xb.h /^#define I2C_OAR1_ADD0 /;" d +I2C_OAR1_ADD1_7 target/stm32f103xb.h /^#define I2C_OAR1_ADD1_7 /;" d +I2C_OAR1_ADD1_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD1_Msk /;" d +I2C_OAR1_ADD1_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD1_Pos /;" d +I2C_OAR1_ADD1 target/stm32f103xb.h /^#define I2C_OAR1_ADD1 /;" d +I2C_OAR1_ADD2_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD2_Msk /;" d +I2C_OAR1_ADD2_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD2_Pos /;" d +I2C_OAR1_ADD2 target/stm32f103xb.h /^#define I2C_OAR1_ADD2 /;" d +I2C_OAR1_ADD3_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD3_Msk /;" d +I2C_OAR1_ADD3_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD3_Pos /;" d +I2C_OAR1_ADD3 target/stm32f103xb.h /^#define I2C_OAR1_ADD3 /;" d +I2C_OAR1_ADD4_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD4_Msk /;" d +I2C_OAR1_ADD4_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD4_Pos /;" d +I2C_OAR1_ADD4 target/stm32f103xb.h /^#define I2C_OAR1_ADD4 /;" d +I2C_OAR1_ADD5_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD5_Msk /;" d +I2C_OAR1_ADD5_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD5_Pos /;" d +I2C_OAR1_ADD5 target/stm32f103xb.h /^#define I2C_OAR1_ADD5 /;" d +I2C_OAR1_ADD6_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD6_Msk /;" d +I2C_OAR1_ADD6_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD6_Pos /;" d +I2C_OAR1_ADD6 target/stm32f103xb.h /^#define I2C_OAR1_ADD6 /;" d +I2C_OAR1_ADD7_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD7_Msk /;" d +I2C_OAR1_ADD7_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD7_Pos /;" d +I2C_OAR1_ADD7 target/stm32f103xb.h /^#define I2C_OAR1_ADD7 /;" d +I2C_OAR1_ADD8_9 target/stm32f103xb.h /^#define I2C_OAR1_ADD8_9 /;" d +I2C_OAR1_ADD8_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD8_Msk /;" d +I2C_OAR1_ADD8_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD8_Pos /;" d +I2C_OAR1_ADD8 target/stm32f103xb.h /^#define I2C_OAR1_ADD8 /;" d +I2C_OAR1_ADD9_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADD9_Msk /;" d +I2C_OAR1_ADD9_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADD9_Pos /;" d +I2C_OAR1_ADD9 target/stm32f103xb.h /^#define I2C_OAR1_ADD9 /;" d +I2C_OAR1_ADDMODE_Msk target/stm32f103xb.h /^#define I2C_OAR1_ADDMODE_Msk /;" d +I2C_OAR1_ADDMODE_Pos target/stm32f103xb.h /^#define I2C_OAR1_ADDMODE_Pos /;" d +I2C_OAR1_ADDMODE target/stm32f103xb.h /^#define I2C_OAR1_ADDMODE /;" d +I2C_OAR2_ADD2_Msk target/stm32f103xb.h /^#define I2C_OAR2_ADD2_Msk /;" d +I2C_OAR2_ADD2_Pos target/stm32f103xb.h /^#define I2C_OAR2_ADD2_Pos /;" d +I2C_OAR2_ADD2 target/stm32f103xb.h /^#define I2C_OAR2_ADD2 /;" d +I2C_OAR2_ENDUAL_Msk target/stm32f103xb.h /^#define I2C_OAR2_ENDUAL_Msk /;" d +I2C_OAR2_ENDUAL_Pos target/stm32f103xb.h /^#define I2C_OAR2_ENDUAL_Pos /;" d +I2C_OAR2_ENDUAL target/stm32f103xb.h /^#define I2C_OAR2_ENDUAL /;" d +I2C_SR1_ADD10_Msk target/stm32f103xb.h /^#define I2C_SR1_ADD10_Msk /;" d +I2C_SR1_ADD10_Pos target/stm32f103xb.h /^#define I2C_SR1_ADD10_Pos /;" d +I2C_SR1_ADD10 target/stm32f103xb.h /^#define I2C_SR1_ADD10 /;" d +I2C_SR1_ADDR_Msk target/stm32f103xb.h /^#define I2C_SR1_ADDR_Msk /;" d +I2C_SR1_ADDR_Pos target/stm32f103xb.h /^#define I2C_SR1_ADDR_Pos /;" d +I2C_SR1_ADDR target/stm32f103xb.h /^#define I2C_SR1_ADDR /;" d +I2C_SR1_AF_Msk target/stm32f103xb.h /^#define I2C_SR1_AF_Msk /;" d +I2C_SR1_AF_Pos target/stm32f103xb.h /^#define I2C_SR1_AF_Pos /;" d +I2C_SR1_AF target/stm32f103xb.h /^#define I2C_SR1_AF /;" d +I2C_SR1_ARLO_Msk target/stm32f103xb.h /^#define I2C_SR1_ARLO_Msk /;" d +I2C_SR1_ARLO_Pos target/stm32f103xb.h /^#define I2C_SR1_ARLO_Pos /;" d +I2C_SR1_ARLO target/stm32f103xb.h /^#define I2C_SR1_ARLO /;" d +I2C_SR1_BERR_Msk target/stm32f103xb.h /^#define I2C_SR1_BERR_Msk /;" d +I2C_SR1_BERR_Pos target/stm32f103xb.h /^#define I2C_SR1_BERR_Pos /;" d +I2C_SR1_BERR target/stm32f103xb.h /^#define I2C_SR1_BERR /;" d +I2C_SR1_BTF_Msk target/stm32f103xb.h /^#define I2C_SR1_BTF_Msk /;" d +I2C_SR1_BTF_Pos target/stm32f103xb.h /^#define I2C_SR1_BTF_Pos /;" d +I2C_SR1_BTF target/stm32f103xb.h /^#define I2C_SR1_BTF /;" d +I2C_SR1_OVR_Msk target/stm32f103xb.h /^#define I2C_SR1_OVR_Msk /;" d +I2C_SR1_OVR_Pos target/stm32f103xb.h /^#define I2C_SR1_OVR_Pos /;" d +I2C_SR1_OVR target/stm32f103xb.h /^#define I2C_SR1_OVR /;" d +I2C_SR1_PECERR_Msk target/stm32f103xb.h /^#define I2C_SR1_PECERR_Msk /;" d +I2C_SR1_PECERR_Pos target/stm32f103xb.h /^#define I2C_SR1_PECERR_Pos /;" d +I2C_SR1_PECERR target/stm32f103xb.h /^#define I2C_SR1_PECERR /;" d +I2C_SR1_RXNE_Msk target/stm32f103xb.h /^#define I2C_SR1_RXNE_Msk /;" d +I2C_SR1_RXNE_Pos target/stm32f103xb.h /^#define I2C_SR1_RXNE_Pos /;" d +I2C_SR1_RXNE target/stm32f103xb.h /^#define I2C_SR1_RXNE /;" d +I2C_SR1_SB_Msk target/stm32f103xb.h /^#define I2C_SR1_SB_Msk /;" d +I2C_SR1_SB_Pos target/stm32f103xb.h /^#define I2C_SR1_SB_Pos /;" d +I2C_SR1_SB target/stm32f103xb.h /^#define I2C_SR1_SB /;" d +I2C_SR1_SMBALERT_Msk target/stm32f103xb.h /^#define I2C_SR1_SMBALERT_Msk /;" d +I2C_SR1_SMBALERT_Pos target/stm32f103xb.h /^#define I2C_SR1_SMBALERT_Pos /;" d +I2C_SR1_SMBALERT target/stm32f103xb.h /^#define I2C_SR1_SMBALERT /;" d +I2C_SR1_STOPF_Msk target/stm32f103xb.h /^#define I2C_SR1_STOPF_Msk /;" d +I2C_SR1_STOPF_Pos target/stm32f103xb.h /^#define I2C_SR1_STOPF_Pos /;" d +I2C_SR1_STOPF target/stm32f103xb.h /^#define I2C_SR1_STOPF /;" d +I2C_SR1_TIMEOUT_Msk target/stm32f103xb.h /^#define I2C_SR1_TIMEOUT_Msk /;" d +I2C_SR1_TIMEOUT_Pos target/stm32f103xb.h /^#define I2C_SR1_TIMEOUT_Pos /;" d +I2C_SR1_TIMEOUT target/stm32f103xb.h /^#define I2C_SR1_TIMEOUT /;" d +I2C_SR1_TXE_Msk target/stm32f103xb.h /^#define I2C_SR1_TXE_Msk /;" d +I2C_SR1_TXE_Pos target/stm32f103xb.h /^#define I2C_SR1_TXE_Pos /;" d +I2C_SR1_TXE target/stm32f103xb.h /^#define I2C_SR1_TXE /;" d +I2C_SR2_BUSY_Msk target/stm32f103xb.h /^#define I2C_SR2_BUSY_Msk /;" d +I2C_SR2_BUSY_Pos target/stm32f103xb.h /^#define I2C_SR2_BUSY_Pos /;" d +I2C_SR2_BUSY target/stm32f103xb.h /^#define I2C_SR2_BUSY /;" d +I2C_SR2_DUALF_Msk target/stm32f103xb.h /^#define I2C_SR2_DUALF_Msk /;" d +I2C_SR2_DUALF_Pos target/stm32f103xb.h /^#define I2C_SR2_DUALF_Pos /;" d +I2C_SR2_DUALF target/stm32f103xb.h /^#define I2C_SR2_DUALF /;" d +I2C_SR2_GENCALL_Msk target/stm32f103xb.h /^#define I2C_SR2_GENCALL_Msk /;" d +I2C_SR2_GENCALL_Pos target/stm32f103xb.h /^#define I2C_SR2_GENCALL_Pos /;" d +I2C_SR2_GENCALL target/stm32f103xb.h /^#define I2C_SR2_GENCALL /;" d +I2C_SR2_MSL_Msk target/stm32f103xb.h /^#define I2C_SR2_MSL_Msk /;" d +I2C_SR2_MSL_Pos target/stm32f103xb.h /^#define I2C_SR2_MSL_Pos /;" d +I2C_SR2_MSL target/stm32f103xb.h /^#define I2C_SR2_MSL /;" d +I2C_SR2_PEC_Msk target/stm32f103xb.h /^#define I2C_SR2_PEC_Msk /;" d +I2C_SR2_PEC_Pos target/stm32f103xb.h /^#define I2C_SR2_PEC_Pos /;" d +I2C_SR2_PEC target/stm32f103xb.h /^#define I2C_SR2_PEC /;" d +I2C_SR2_SMBDEFAULT_Msk target/stm32f103xb.h /^#define I2C_SR2_SMBDEFAULT_Msk /;" d +I2C_SR2_SMBDEFAULT_Pos target/stm32f103xb.h /^#define I2C_SR2_SMBDEFAULT_Pos /;" d +I2C_SR2_SMBDEFAULT target/stm32f103xb.h /^#define I2C_SR2_SMBDEFAULT /;" d +I2C_SR2_SMBHOST_Msk target/stm32f103xb.h /^#define I2C_SR2_SMBHOST_Msk /;" d +I2C_SR2_SMBHOST_Pos target/stm32f103xb.h /^#define I2C_SR2_SMBHOST_Pos /;" d +I2C_SR2_SMBHOST target/stm32f103xb.h /^#define I2C_SR2_SMBHOST /;" d +I2C_SR2_TRA_Msk target/stm32f103xb.h /^#define I2C_SR2_TRA_Msk /;" d +I2C_SR2_TRA_Pos target/stm32f103xb.h /^#define I2C_SR2_TRA_Pos /;" d +I2C_SR2_TRA target/stm32f103xb.h /^#define I2C_SR2_TRA /;" d +I2C_TRISE_TRISE_Msk target/stm32f103xb.h /^#define I2C_TRISE_TRISE_Msk /;" d +I2C_TRISE_TRISE_Pos target/stm32f103xb.h /^#define I2C_TRISE_TRISE_Pos /;" d +I2C_TRISE_TRISE target/stm32f103xb.h /^#define I2C_TRISE_TRISE /;" d +I2C_TypeDef target/stm32f103xb.h /^} I2C_TypeDef;$/;" t typeref:struct:__anon72c4c37e1208 +I2SCFGR target/stm32f103xb.h /^ __IO uint32_t I2SCFGR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +ICR target/stm32f103xb.h /^ __IO uint32_t ICR;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +IDCODE target/stm32f103xb.h /^ __IO uint32_t IDCODE;$/;" m struct:__anon72c4c37e0a08 typeref:typename:__IO uint32_t +IDR target/stm32f103xb.h /^ __IO uint32_t IDR;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +IDR target/stm32f103xb.h /^ __IO uint8_t IDR; \/*!< CRC Independent data register, Address offset:/;" m struct:__anon72c4c37e0908 typeref:typename:__IO uint8_t +IER target/stm32f103xb.h /^ __IO uint32_t IER;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +IFCR target/stm32f103xb.h /^ __IO uint32_t IFCR;$/;" m struct:__anon72c4c37e0c08 typeref:typename:__IO uint32_t +IMR target/stm32f103xb.h /^ __IO uint32_t IMR;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +IRQn_Type target/stm32f103xb.h /^} IRQn_Type;$/;" t typeref:enum:__anon72c4c37e0103 +ISR target/stm32f103xb.h /^ __IO uint32_t ISR;$/;" m struct:__anon72c4c37e0c08 typeref:typename:__IO uint32_t +ISTR target/stm32f103xb.h /^ __IO uint16_t ISTR; \/*!< Interrupt status register, Address o/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +IS_ADC_ALL_INSTANCE target/stm32f103xb.h /^#define IS_ADC_ALL_INSTANCE(/;" d +IS_ADC_COMMON_INSTANCE target/stm32f103xb.h /^#define IS_ADC_COMMON_INSTANCE(/;" d +IS_ADC_DMA_CAPABILITY_INSTANCE target/stm32f103xb.h /^#define IS_ADC_DMA_CAPABILITY_INSTANCE(/;" d +IS_ADC_MULTIMODE_MASTER_INSTANCE target/stm32f103xb.h /^#define IS_ADC_MULTIMODE_MASTER_INSTANCE(/;" d +IS_CAN_ALL_INSTANCE target/stm32f103xb.h /^#define IS_CAN_ALL_INSTANCE(/;" d +IS_CRC_ALL_INSTANCE target/stm32f103xb.h /^#define IS_CRC_ALL_INSTANCE(/;" d +IS_DMA_ALL_INSTANCE target/stm32f103xb.h /^#define IS_DMA_ALL_INSTANCE(/;" d +IS_FUNCTIONAL_STATE target/stm32f1xx.h /^#define IS_FUNCTIONAL_STATE(/;" d +IS_GPIO_AF_INSTANCE target/stm32f103xb.h /^#define IS_GPIO_AF_INSTANCE(/;" d +IS_GPIO_ALL_INSTANCE target/stm32f103xb.h /^#define IS_GPIO_ALL_INSTANCE(/;" d +IS_GPIO_LOCK_INSTANCE target/stm32f103xb.h /^#define IS_GPIO_LOCK_INSTANCE(/;" d +IS_I2C_ALL_INSTANCE target/stm32f103xb.h /^#define IS_I2C_ALL_INSTANCE(/;" d +IS_IRDA_INSTANCE target/stm32f103xb.h /^#define IS_IRDA_INSTANCE(/;" d +IS_IWDG_ALL_INSTANCE target/stm32f103xb.h /^#define IS_IWDG_ALL_INSTANCE(/;" d +IS_RTC_ALL_INSTANCE target/stm32f103xb.h /^#define IS_RTC_ALL_INSTANCE(/;" d +IS_SMARTCARD_INSTANCE target/stm32f103xb.h /^#define IS_SMARTCARD_INSTANCE(/;" d +IS_SMBUS_ALL_INSTANCE target/stm32f103xb.h /^#define IS_SMBUS_ALL_INSTANCE /;" d +IS_SPI_ALL_INSTANCE target/stm32f103xb.h /^#define IS_SPI_ALL_INSTANCE(/;" d +IS_TIM_32B_COUNTER_INSTANCE target/stm32f103xb.h /^#define IS_TIM_32B_COUNTER_INSTANCE(/;" d +IS_TIM_ADVANCED_INSTANCE target/stm32f103xb.h /^#define IS_TIM_ADVANCED_INSTANCE(/;" d +IS_TIM_BREAK_INSTANCE target/stm32f103xb.h /^#define IS_TIM_BREAK_INSTANCE(/;" d +IS_TIM_CC1_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CC1_INSTANCE(/;" d +IS_TIM_CC2_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CC2_INSTANCE(/;" d +IS_TIM_CC3_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CC3_INSTANCE(/;" d +IS_TIM_CC4_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CC4_INSTANCE(/;" d +IS_TIM_CCXN_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CCXN_INSTANCE(/;" d +IS_TIM_CCX_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CCX_INSTANCE(/;" d +IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(/;" d +IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(/;" d +IS_TIM_CLOCKSOURCE_ITRX_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(/;" d +IS_TIM_CLOCKSOURCE_TIX_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(/;" d +IS_TIM_CLOCK_DIVISION_INSTANCE target/stm32f103xb.h /^#define IS_TIM_CLOCK_DIVISION_INSTANCE(/;" d +IS_TIM_COMMUTATION_EVENT_INSTANCE target/stm32f103xb.h /^#define IS_TIM_COMMUTATION_EVENT_INSTANCE(/;" d +IS_TIM_COUNTER_MODE_SELECT_INSTANCE target/stm32f103xb.h /^#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(/;" d +IS_TIM_DMABURST_INSTANCE target/stm32f103xb.h /^#define IS_TIM_DMABURST_INSTANCE(/;" d +IS_TIM_DMA_CC_INSTANCE target/stm32f103xb.h /^#define IS_TIM_DMA_CC_INSTANCE(/;" d +IS_TIM_DMA_INSTANCE target/stm32f103xb.h /^#define IS_TIM_DMA_INSTANCE(/;" d +IS_TIM_ENCODER_INTERFACE_INSTANCE target/stm32f103xb.h /^#define IS_TIM_ENCODER_INTERFACE_INSTANCE(/;" d +IS_TIM_ETR_INSTANCE target/stm32f103xb.h /^#define IS_TIM_ETR_INSTANCE(/;" d +IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE target/stm32f103xb.h /^#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(/;" d +IS_TIM_INSTANCE target/stm32f103xb.h /^#define IS_TIM_INSTANCE(/;" d +IS_TIM_MASTER_INSTANCE target/stm32f103xb.h /^#define IS_TIM_MASTER_INSTANCE(/;" d +IS_TIM_OCXREF_CLEAR_INSTANCE target/stm32f103xb.h /^#define IS_TIM_OCXREF_CLEAR_INSTANCE(/;" d +IS_TIM_REPETITION_COUNTER_INSTANCE target/stm32f103xb.h /^#define IS_TIM_REPETITION_COUNTER_INSTANCE(/;" d +IS_TIM_SLAVE_INSTANCE target/stm32f103xb.h /^#define IS_TIM_SLAVE_INSTANCE(/;" d +IS_TIM_XOR_INSTANCE target/stm32f103xb.h /^#define IS_TIM_XOR_INSTANCE(/;" d +IS_UART_DMA_INSTANCE target/stm32f103xb.h /^#define IS_UART_DMA_INSTANCE(/;" d +IS_UART_HALFDUPLEX_INSTANCE target/stm32f103xb.h /^#define IS_UART_HALFDUPLEX_INSTANCE(/;" d +IS_UART_HWFLOW_INSTANCE target/stm32f103xb.h /^#define IS_UART_HWFLOW_INSTANCE(/;" d +IS_UART_INSTANCE target/stm32f103xb.h /^#define IS_UART_INSTANCE(/;" d +IS_UART_LIN_INSTANCE target/stm32f103xb.h /^#define IS_UART_LIN_INSTANCE(/;" d +IS_UART_MULTIPROCESSOR_INSTANCE target/stm32f103xb.h /^#define IS_UART_MULTIPROCESSOR_INSTANCE(/;" d +IS_USART_INSTANCE target/stm32f103xb.h /^#define IS_USART_INSTANCE(/;" d +IS_USB_ALL_INSTANCE target/stm32f103xb.h /^#define IS_USB_ALL_INSTANCE(/;" d +IS_WWDG_ALL_INSTANCE target/stm32f103xb.h /^#define IS_WWDG_ALL_INSTANCE(/;" d +ITStatus target/stm32f1xx.h /^} FlagStatus, ITStatus;$/;" t typeref:enum:__anonbccbea710103 +IWDG_BASE target/stm32f103xb.h /^#define IWDG_BASE /;" d +IWDG_KR_KEY_Msk target/stm32f103xb.h /^#define IWDG_KR_KEY_Msk /;" d +IWDG_KR_KEY_Pos target/stm32f103xb.h /^#define IWDG_KR_KEY_Pos /;" d +IWDG_KR_KEY target/stm32f103xb.h /^#define IWDG_KR_KEY /;" d +IWDG_PR_PR_0 target/stm32f103xb.h /^#define IWDG_PR_PR_0 /;" d +IWDG_PR_PR_1 target/stm32f103xb.h /^#define IWDG_PR_PR_1 /;" d +IWDG_PR_PR_2 target/stm32f103xb.h /^#define IWDG_PR_PR_2 /;" d +IWDG_PR_PR_Msk target/stm32f103xb.h /^#define IWDG_PR_PR_Msk /;" d +IWDG_PR_PR_Pos target/stm32f103xb.h /^#define IWDG_PR_PR_Pos /;" d +IWDG_PR_PR target/stm32f103xb.h /^#define IWDG_PR_PR /;" d +IWDG_RLR_RL_Msk target/stm32f103xb.h /^#define IWDG_RLR_RL_Msk /;" d +IWDG_RLR_RL_Pos target/stm32f103xb.h /^#define IWDG_RLR_RL_Pos /;" d +IWDG_RLR_RL target/stm32f103xb.h /^#define IWDG_RLR_RL /;" d +IWDG_SR_PVU_Msk target/stm32f103xb.h /^#define IWDG_SR_PVU_Msk /;" d +IWDG_SR_PVU_Pos target/stm32f103xb.h /^#define IWDG_SR_PVU_Pos /;" d +IWDG_SR_PVU target/stm32f103xb.h /^#define IWDG_SR_PVU /;" d +IWDG_SR_RVU_Msk target/stm32f103xb.h /^#define IWDG_SR_RVU_Msk /;" d +IWDG_SR_RVU_Pos target/stm32f103xb.h /^#define IWDG_SR_RVU_Pos /;" d +IWDG_SR_RVU target/stm32f103xb.h /^#define IWDG_SR_RVU /;" d +IWDG_TypeDef target/stm32f103xb.h /^} IWDG_TypeDef;$/;" t typeref:struct:__anon72c4c37e1308 +IWDG target/stm32f103xb.h /^#define IWDG /;" d +JDR1 target/stm32f103xb.h /^ __IO uint32_t JDR1;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JDR2 target/stm32f103xb.h /^ __IO uint32_t JDR2;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JDR3 target/stm32f103xb.h /^ __IO uint32_t JDR3;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JDR4 target/stm32f103xb.h /^ __IO uint32_t JDR4;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JOFR1 target/stm32f103xb.h /^ __IO uint32_t JOFR1;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JOFR2 target/stm32f103xb.h /^ __IO uint32_t JOFR2;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JOFR3 target/stm32f103xb.h /^ __IO uint32_t JOFR3;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JOFR4 target/stm32f103xb.h /^ __IO uint32_t JOFR4;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +JSQR target/stm32f103xb.h /^ __IO uint32_t JSQR;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +KEYR target/stm32f103xb.h /^ __IO uint32_t KEYR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +KR target/stm32f103xb.h /^ __IO uint32_t KR; \/*!< Key register, Address offset:/;" m struct:__anon72c4c37e1308 typeref:typename:__IO uint32_t +LCKR target/stm32f103xb.h /^ __IO uint32_t LCKR;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +LTR target/stm32f103xb.h /^ __IO uint32_t LTR;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +MAPR2 target/stm32f103xb.h /^ __IO uint32_t MAPR2; $/;" m struct:__anon72c4c37e1108 typeref:typename:__IO uint32_t +MAPR target/stm32f103xb.h /^ __IO uint32_t MAPR;$/;" m struct:__anon72c4c37e1108 typeref:typename:__IO uint32_t +MASK target/stm32f103xb.h /^ __IO uint32_t MASK;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +MBED_CMSIS_NVIC_H Untitled Folder/cmsis_nvic.h /^#define MBED_CMSIS_NVIC_H$/;" d +MCR target/stm32f103xb.h /^ __IO uint32_t MCR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +MODIFY_REG target/stm32f1xx.h /^#define MODIFY_REG(/;" d +MSR target/stm32f103xb.h /^ __IO uint32_t MSR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +MemManage_Handler Untitled Folder/sys_handlers.c /^void MemManage_Handler(void)$/;" f typeref:typename:void +MemoryManagement_IRQn target/stm32f103xb.h /^ MemoryManagement_IRQn = -12, \/*!< 4 Cortex-M3 Memory Management Interrupt /;" e enum:__anon72c4c37e0103 +NMI_Handler Untitled Folder/sys_handlers.c /^void NMI_Handler(void)$/;" f typeref:typename:void +NVIC_NUM_VECTORS Untitled Folder/cmsis_nvic.h /^#define NVIC_NUM_VECTORS /;" d +NVIC_RAM_VECTOR_ADDRESS Untitled Folder/cmsis_nvic.h /^#define NVIC_RAM_VECTOR_ADDRESS /;" d +NonMaskableInt_IRQn target/stm32f103xb.h /^ NonMaskableInt_IRQn = -14, \/*!< 2 Non Maskable Interrupt /;" e enum:__anon72c4c37e0103 +OAR1 target/stm32f103xb.h /^ __IO uint32_t OAR1;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +OAR2 target/stm32f103xb.h /^ __IO uint32_t OAR2;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +OBR target/stm32f103xb.h /^ __IO uint32_t OBR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +OB_BASE target/stm32f103xb.h /^#define OB_BASE /;" d +OB_TypeDef target/stm32f103xb.h /^} OB_TypeDef;$/;" t typeref:struct:__anon72c4c37e0f08 +OB target/stm32f103xb.h /^#define OB /;" d +ODR target/stm32f103xb.h /^ __IO uint32_t ODR;$/;" m struct:__anon72c4c37e1008 typeref:typename:__IO uint32_t +OPTKEYR target/stm32f103xb.h /^ __IO uint32_t OPTKEYR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +OR target/stm32f103xb.h /^ __IO uint32_t OR; \/*!< TIM option register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +OTG_FS_WKUP_IRQHandler target/stm32f103xb.h /^#define OTG_FS_WKUP_IRQHandler /;" d +OTG_FS_WKUP_IRQn target/stm32f103xb.h /^#define OTG_FS_WKUP_IRQn /;" d +OnIO drivers/io.h /^typedef void (*OnIO)();$/;" t typeref:typename:void (*)() +OnTick drivers/timer.h /^typedef void (*OnTick)(void);$/;" t typeref:typename:void (*)(void) +PERIPH_BASE target/stm32f103xb.h /^#define PERIPH_BASE /;" d +PERIPH_BB_BASE target/stm32f103xb.h /^#define PERIPH_BB_BASE /;" d +PIN_0 drivers/io.h /^#define PIN_0 /;" d +PIN_10 drivers/io.h /^#define PIN_10 /;" d +PIN_11 drivers/io.h /^#define PIN_11 /;" d +PIN_12 drivers/io.h /^#define PIN_12 /;" d +PIN_13 drivers/io.h /^#define PIN_13 /;" d +PIN_14 drivers/io.h /^#define PIN_14 /;" d +PIN_15 drivers/io.h /^#define PIN_15 /;" d +PIN_1 drivers/io.h /^#define PIN_1 /;" d +PIN_2 drivers/io.h /^#define PIN_2 /;" d +PIN_3 drivers/io.h /^#define PIN_3 /;" d +PIN_4 drivers/io.h /^#define PIN_4 /;" d +PIN_5 drivers/io.h /^#define PIN_5 /;" d +PIN_6 drivers/io.h /^#define PIN_6 /;" d +PIN_7 drivers/io.h /^#define PIN_7 /;" d +PIN_8 drivers/io.h /^#define PIN_8 /;" d +PIN_9 drivers/io.h /^#define PIN_9 /;" d +PIN_ALL drivers/io.h /^#define PIN_ALL /;" d +PIN_MODE_ALTFUNC drivers/io.h /^#define PIN_MODE_ALTFUNC /;" d +PIN_MODE_ANALOG drivers/io.h /^#define PIN_MODE_ANALOG /;" d +PIN_MODE_INPUT drivers/io.h /^#define PIN_MODE_INPUT /;" d +PIN_MODE_OUTPUT drivers/io.h /^#define PIN_MODE_OUTPUT /;" d +PIN_OPT_AF0 drivers/io.h /^#define PIN_OPT_AF0 /;" d +PIN_OPT_AF10 drivers/io.h /^#define PIN_OPT_AF10 /;" d +PIN_OPT_AF11 drivers/io.h /^#define PIN_OPT_AF11 /;" d +PIN_OPT_AF12 drivers/io.h /^#define PIN_OPT_AF12 /;" d +PIN_OPT_AF13 drivers/io.h /^#define PIN_OPT_AF13 /;" d +PIN_OPT_AF14 drivers/io.h /^#define PIN_OPT_AF14 /;" d +PIN_OPT_AF15 drivers/io.h /^#define PIN_OPT_AF15 /;" d +PIN_OPT_AF1 drivers/io.h /^#define PIN_OPT_AF1 /;" d +PIN_OPT_AF2 drivers/io.h /^#define PIN_OPT_AF2 /;" d +PIN_OPT_AF3 drivers/io.h /^#define PIN_OPT_AF3 /;" d +PIN_OPT_AF4 drivers/io.h /^#define PIN_OPT_AF4 /;" d +PIN_OPT_AF5 drivers/io.h /^#define PIN_OPT_AF5 /;" d +PIN_OPT_AF6 drivers/io.h /^#define PIN_OPT_AF6 /;" d +PIN_OPT_AF7 drivers/io.h /^#define PIN_OPT_AF7 /;" d +PIN_OPT_AF8 drivers/io.h /^#define PIN_OPT_AF8 /;" d +PIN_OPT_AF9 drivers/io.h /^#define PIN_OPT_AF9 /;" d +PIN_OPT_IRQ_EDGE_BOTH drivers/io.h /^#define PIN_OPT_IRQ_EDGE_BOTH /;" d +PIN_OPT_IRQ_EDGE_FALL drivers/io.h /^#define PIN_OPT_IRQ_EDGE_FALL /;" d +PIN_OPT_IRQ_EDGE_RISE drivers/io.h /^#define PIN_OPT_IRQ_EDGE_RISE /;" d +PIN_OPT_NONE drivers/io.h /^#define PIN_OPT_NONE /;" d +PIN_OPT_OUTPUT_OPENDRAIN drivers/io.h /^#define PIN_OPT_OUTPUT_OPENDRAIN /;" d +PIN_OPT_OUTPUT_PUSHPULL drivers/io.h /^#define PIN_OPT_OUTPUT_PUSHPULL /;" d +PIN_OPT_OUTPUT_SPEED_FAST drivers/io.h /^#define PIN_OPT_OUTPUT_SPEED_FAST /;" d +PIN_OPT_OUTPUT_SPEED_LOW drivers/io.h /^#define PIN_OPT_OUTPUT_SPEED_LOW /;" d +PIN_OPT_OUTPUT_SPEED_MEDIUM drivers/io.h /^#define PIN_OPT_OUTPUT_SPEED_MEDIUM /;" d +PIN_OPT_RESISTOR_NONE drivers/io.h /^#define PIN_OPT_RESISTOR_NONE /;" d +PIN_OPT_RESISTOR_PULLDOWN drivers/io.h /^#define PIN_OPT_RESISTOR_PULLDOWN /;" d +PIN_OPT_RESISTOR_PULLUP drivers/io.h /^#define PIN_OPT_RESISTOR_PULLUP /;" d +POSITION_VAL target/stm32f1xx.h /^#define POSITION_VAL(/;" d +POWER target/stm32f103xb.h /^ __IO uint32_t POWER;$/;" m struct:__anon72c4c37e1708 typeref:typename:__IO uint32_t +PRLH target/stm32f103xb.h /^ __IO uint32_t PRLH;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +PRLL target/stm32f103xb.h /^ __IO uint32_t PRLL;$/;" m struct:__anon72c4c37e1608 typeref:typename:__IO uint32_t +PR target/stm32f103xb.h /^ __IO uint32_t PR; \/*!< Prescaler register, Address offset:/;" m struct:__anon72c4c37e1308 typeref:typename:__IO uint32_t +PR target/stm32f103xb.h /^ __IO uint32_t PR;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +PSC target/stm32f103xb.h /^ __IO uint32_t PSC; \/*!< TIM prescaler register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +PVD_IRQn target/stm32f103xb.h /^ PVD_IRQn = 1, \/*!< PVD through EXTI Line detection Interrupt /;" e enum:__anon72c4c37e0103 +PWM_CHANNEL_1 drivers/timer.h /^#define PWM_CHANNEL_1 /;" d +PWM_CHANNEL_2 drivers/timer.h /^#define PWM_CHANNEL_2 /;" d +PWM_CHANNEL_3 drivers/timer.h /^#define PWM_CHANNEL_3 /;" d +PWM_CHANNEL_4 drivers/timer.h /^#define PWM_CHANNEL_4 /;" d +PWR_BASE target/stm32f103xb.h /^#define PWR_BASE /;" d +PWR_CR_CSBF_Msk target/stm32f103xb.h /^#define PWR_CR_CSBF_Msk /;" d +PWR_CR_CSBF_Pos target/stm32f103xb.h /^#define PWR_CR_CSBF_Pos /;" d +PWR_CR_CSBF target/stm32f103xb.h /^#define PWR_CR_CSBF /;" d +PWR_CR_CWUF_Msk target/stm32f103xb.h /^#define PWR_CR_CWUF_Msk /;" d +PWR_CR_CWUF_Pos target/stm32f103xb.h /^#define PWR_CR_CWUF_Pos /;" d +PWR_CR_CWUF target/stm32f103xb.h /^#define PWR_CR_CWUF /;" d +PWR_CR_DBP_Msk target/stm32f103xb.h /^#define PWR_CR_DBP_Msk /;" d +PWR_CR_DBP_Pos target/stm32f103xb.h /^#define PWR_CR_DBP_Pos /;" d +PWR_CR_DBP target/stm32f103xb.h /^#define PWR_CR_DBP /;" d +PWR_CR_LPDS_Msk target/stm32f103xb.h /^#define PWR_CR_LPDS_Msk /;" d +PWR_CR_LPDS_Pos target/stm32f103xb.h /^#define PWR_CR_LPDS_Pos /;" d +PWR_CR_LPDS target/stm32f103xb.h /^#define PWR_CR_LPDS /;" d +PWR_CR_PDDS_Msk target/stm32f103xb.h /^#define PWR_CR_PDDS_Msk /;" d +PWR_CR_PDDS_Pos target/stm32f103xb.h /^#define PWR_CR_PDDS_Pos /;" d +PWR_CR_PDDS target/stm32f103xb.h /^#define PWR_CR_PDDS /;" d +PWR_CR_PLS_0 target/stm32f103xb.h /^#define PWR_CR_PLS_0 /;" d +PWR_CR_PLS_1 target/stm32f103xb.h /^#define PWR_CR_PLS_1 /;" d +PWR_CR_PLS_2V2 target/stm32f103xb.h /^#define PWR_CR_PLS_2V2 /;" d +PWR_CR_PLS_2V3 target/stm32f103xb.h /^#define PWR_CR_PLS_2V3 /;" d +PWR_CR_PLS_2V4 target/stm32f103xb.h /^#define PWR_CR_PLS_2V4 /;" d +PWR_CR_PLS_2V5 target/stm32f103xb.h /^#define PWR_CR_PLS_2V5 /;" d +PWR_CR_PLS_2V6 target/stm32f103xb.h /^#define PWR_CR_PLS_2V6 /;" d +PWR_CR_PLS_2V7 target/stm32f103xb.h /^#define PWR_CR_PLS_2V7 /;" d +PWR_CR_PLS_2V8 target/stm32f103xb.h /^#define PWR_CR_PLS_2V8 /;" d +PWR_CR_PLS_2V9 target/stm32f103xb.h /^#define PWR_CR_PLS_2V9 /;" d +PWR_CR_PLS_2 target/stm32f103xb.h /^#define PWR_CR_PLS_2 /;" d +PWR_CR_PLS_LEV0 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV0 /;" d +PWR_CR_PLS_LEV1 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV1 /;" d +PWR_CR_PLS_LEV2 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV2 /;" d +PWR_CR_PLS_LEV3 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV3 /;" d +PWR_CR_PLS_LEV4 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV4 /;" d +PWR_CR_PLS_LEV5 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV5 /;" d +PWR_CR_PLS_LEV6 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV6 /;" d +PWR_CR_PLS_LEV7 target/stm32f103xb.h /^#define PWR_CR_PLS_LEV7 /;" d +PWR_CR_PLS_Msk target/stm32f103xb.h /^#define PWR_CR_PLS_Msk /;" d +PWR_CR_PLS_Pos target/stm32f103xb.h /^#define PWR_CR_PLS_Pos /;" d +PWR_CR_PLS target/stm32f103xb.h /^#define PWR_CR_PLS /;" d +PWR_CR_PVDE_Msk target/stm32f103xb.h /^#define PWR_CR_PVDE_Msk /;" d +PWR_CR_PVDE_Pos target/stm32f103xb.h /^#define PWR_CR_PVDE_Pos /;" d +PWR_CR_PVDE target/stm32f103xb.h /^#define PWR_CR_PVDE /;" d +PWR_CSR_EWUP_Msk target/stm32f103xb.h /^#define PWR_CSR_EWUP_Msk /;" d +PWR_CSR_EWUP_Pos target/stm32f103xb.h /^#define PWR_CSR_EWUP_Pos /;" d +PWR_CSR_EWUP target/stm32f103xb.h /^#define PWR_CSR_EWUP /;" d +PWR_CSR_PVDO_Msk target/stm32f103xb.h /^#define PWR_CSR_PVDO_Msk /;" d +PWR_CSR_PVDO_Pos target/stm32f103xb.h /^#define PWR_CSR_PVDO_Pos /;" d +PWR_CSR_PVDO target/stm32f103xb.h /^#define PWR_CSR_PVDO /;" d +PWR_CSR_SBF_Msk target/stm32f103xb.h /^#define PWR_CSR_SBF_Msk /;" d +PWR_CSR_SBF_Pos target/stm32f103xb.h /^#define PWR_CSR_SBF_Pos /;" d +PWR_CSR_SBF target/stm32f103xb.h /^#define PWR_CSR_SBF /;" d +PWR_CSR_WUF_Msk target/stm32f103xb.h /^#define PWR_CSR_WUF_Msk /;" d +PWR_CSR_WUF_Pos target/stm32f103xb.h /^#define PWR_CSR_WUF_Pos /;" d +PWR_CSR_WUF target/stm32f103xb.h /^#define PWR_CSR_WUF /;" d +PWR_TypeDef target/stm32f103xb.h /^} PWR_TypeDef;$/;" t typeref:struct:__anon72c4c37e1408 +PWR target/stm32f103xb.h /^#define PWR /;" d +PendSV_Handler Untitled Folder/sys_handlers.c /^void PendSV_Handler(void)$/;" f typeref:typename:void +PendSV_IRQn target/stm32f103xb.h /^ PendSV_IRQn = -2, \/*!< 14 Cortex-M3 Pend SV Interrupt /;" e enum:__anon72c4c37e0103 +RCC_AHBENR_CRCEN_Msk target/stm32f103xb.h /^#define RCC_AHBENR_CRCEN_Msk /;" d +RCC_AHBENR_CRCEN_Pos target/stm32f103xb.h /^#define RCC_AHBENR_CRCEN_Pos /;" d +RCC_AHBENR_CRCEN target/stm32f103xb.h /^#define RCC_AHBENR_CRCEN /;" d +RCC_AHBENR_DMA1EN_Msk target/stm32f103xb.h /^#define RCC_AHBENR_DMA1EN_Msk /;" d +RCC_AHBENR_DMA1EN_Pos target/stm32f103xb.h /^#define RCC_AHBENR_DMA1EN_Pos /;" d +RCC_AHBENR_DMA1EN target/stm32f103xb.h /^#define RCC_AHBENR_DMA1EN /;" d +RCC_AHBENR_FLITFEN_Msk target/stm32f103xb.h /^#define RCC_AHBENR_FLITFEN_Msk /;" d +RCC_AHBENR_FLITFEN_Pos target/stm32f103xb.h /^#define RCC_AHBENR_FLITFEN_Pos /;" d +RCC_AHBENR_FLITFEN target/stm32f103xb.h /^#define RCC_AHBENR_FLITFEN /;" d +RCC_AHBENR_SRAMEN_Msk target/stm32f103xb.h /^#define RCC_AHBENR_SRAMEN_Msk /;" d +RCC_AHBENR_SRAMEN_Pos target/stm32f103xb.h /^#define RCC_AHBENR_SRAMEN_Pos /;" d +RCC_AHBENR_SRAMEN target/stm32f103xb.h /^#define RCC_AHBENR_SRAMEN /;" d +RCC_APB1ENR_BKPEN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_BKPEN_Msk /;" d +RCC_APB1ENR_BKPEN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_BKPEN_Pos /;" d +RCC_APB1ENR_BKPEN target/stm32f103xb.h /^#define RCC_APB1ENR_BKPEN /;" d +RCC_APB1ENR_CAN1EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_CAN1EN_Msk /;" d +RCC_APB1ENR_CAN1EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_CAN1EN_Pos /;" d +RCC_APB1ENR_CAN1EN target/stm32f103xb.h /^#define RCC_APB1ENR_CAN1EN /;" d +RCC_APB1ENR_I2C1EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_I2C1EN_Msk /;" d +RCC_APB1ENR_I2C1EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_I2C1EN_Pos /;" d +RCC_APB1ENR_I2C1EN target/stm32f103xb.h /^#define RCC_APB1ENR_I2C1EN /;" d +RCC_APB1ENR_I2C2EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_I2C2EN_Msk /;" d +RCC_APB1ENR_I2C2EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_I2C2EN_Pos /;" d +RCC_APB1ENR_I2C2EN target/stm32f103xb.h /^#define RCC_APB1ENR_I2C2EN /;" d +RCC_APB1ENR_PWREN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_PWREN_Msk /;" d +RCC_APB1ENR_PWREN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_PWREN_Pos /;" d +RCC_APB1ENR_PWREN target/stm32f103xb.h /^#define RCC_APB1ENR_PWREN /;" d +RCC_APB1ENR_SPI2EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_SPI2EN_Msk /;" d +RCC_APB1ENR_SPI2EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_SPI2EN_Pos /;" d +RCC_APB1ENR_SPI2EN target/stm32f103xb.h /^#define RCC_APB1ENR_SPI2EN /;" d +RCC_APB1ENR_TIM2EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_TIM2EN_Msk /;" d +RCC_APB1ENR_TIM2EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_TIM2EN_Pos /;" d +RCC_APB1ENR_TIM2EN target/stm32f103xb.h /^#define RCC_APB1ENR_TIM2EN /;" d +RCC_APB1ENR_TIM3EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_TIM3EN_Msk /;" d +RCC_APB1ENR_TIM3EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_TIM3EN_Pos /;" d +RCC_APB1ENR_TIM3EN target/stm32f103xb.h /^#define RCC_APB1ENR_TIM3EN /;" d +RCC_APB1ENR_TIM4EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_TIM4EN_Msk /;" d +RCC_APB1ENR_TIM4EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_TIM4EN_Pos /;" d +RCC_APB1ENR_TIM4EN target/stm32f103xb.h /^#define RCC_APB1ENR_TIM4EN /;" d +RCC_APB1ENR_USART2EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_USART2EN_Msk /;" d +RCC_APB1ENR_USART2EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_USART2EN_Pos /;" d +RCC_APB1ENR_USART2EN target/stm32f103xb.h /^#define RCC_APB1ENR_USART2EN /;" d +RCC_APB1ENR_USART3EN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_USART3EN_Msk /;" d +RCC_APB1ENR_USART3EN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_USART3EN_Pos /;" d +RCC_APB1ENR_USART3EN target/stm32f103xb.h /^#define RCC_APB1ENR_USART3EN /;" d +RCC_APB1ENR_USBEN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_USBEN_Msk /;" d +RCC_APB1ENR_USBEN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_USBEN_Pos /;" d +RCC_APB1ENR_USBEN target/stm32f103xb.h /^#define RCC_APB1ENR_USBEN /;" d +RCC_APB1ENR_WWDGEN_Msk target/stm32f103xb.h /^#define RCC_APB1ENR_WWDGEN_Msk /;" d +RCC_APB1ENR_WWDGEN_Pos target/stm32f103xb.h /^#define RCC_APB1ENR_WWDGEN_Pos /;" d +RCC_APB1ENR_WWDGEN target/stm32f103xb.h /^#define RCC_APB1ENR_WWDGEN /;" d +RCC_APB1RSTR_BKPRST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_BKPRST_Msk /;" d +RCC_APB1RSTR_BKPRST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_BKPRST_Pos /;" d +RCC_APB1RSTR_BKPRST target/stm32f103xb.h /^#define RCC_APB1RSTR_BKPRST /;" d +RCC_APB1RSTR_CAN1RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_CAN1RST_Msk /;" d +RCC_APB1RSTR_CAN1RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_CAN1RST_Pos /;" d +RCC_APB1RSTR_CAN1RST target/stm32f103xb.h /^#define RCC_APB1RSTR_CAN1RST /;" d +RCC_APB1RSTR_I2C1RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C1RST_Msk /;" d +RCC_APB1RSTR_I2C1RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C1RST_Pos /;" d +RCC_APB1RSTR_I2C1RST target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C1RST /;" d +RCC_APB1RSTR_I2C2RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C2RST_Msk /;" d +RCC_APB1RSTR_I2C2RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C2RST_Pos /;" d +RCC_APB1RSTR_I2C2RST target/stm32f103xb.h /^#define RCC_APB1RSTR_I2C2RST /;" d +RCC_APB1RSTR_PWRRST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_PWRRST_Msk /;" d +RCC_APB1RSTR_PWRRST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_PWRRST_Pos /;" d +RCC_APB1RSTR_PWRRST target/stm32f103xb.h /^#define RCC_APB1RSTR_PWRRST /;" d +RCC_APB1RSTR_SPI2RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_SPI2RST_Msk /;" d +RCC_APB1RSTR_SPI2RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_SPI2RST_Pos /;" d +RCC_APB1RSTR_SPI2RST target/stm32f103xb.h /^#define RCC_APB1RSTR_SPI2RST /;" d +RCC_APB1RSTR_TIM2RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM2RST_Msk /;" d +RCC_APB1RSTR_TIM2RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM2RST_Pos /;" d +RCC_APB1RSTR_TIM2RST target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM2RST /;" d +RCC_APB1RSTR_TIM3RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM3RST_Msk /;" d +RCC_APB1RSTR_TIM3RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM3RST_Pos /;" d +RCC_APB1RSTR_TIM3RST target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM3RST /;" d +RCC_APB1RSTR_TIM4RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM4RST_Msk /;" d +RCC_APB1RSTR_TIM4RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM4RST_Pos /;" d +RCC_APB1RSTR_TIM4RST target/stm32f103xb.h /^#define RCC_APB1RSTR_TIM4RST /;" d +RCC_APB1RSTR_USART2RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_USART2RST_Msk /;" d +RCC_APB1RSTR_USART2RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_USART2RST_Pos /;" d +RCC_APB1RSTR_USART2RST target/stm32f103xb.h /^#define RCC_APB1RSTR_USART2RST /;" d +RCC_APB1RSTR_USART3RST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_USART3RST_Msk /;" d +RCC_APB1RSTR_USART3RST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_USART3RST_Pos /;" d +RCC_APB1RSTR_USART3RST target/stm32f103xb.h /^#define RCC_APB1RSTR_USART3RST /;" d +RCC_APB1RSTR_USBRST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_USBRST_Msk /;" d +RCC_APB1RSTR_USBRST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_USBRST_Pos /;" d +RCC_APB1RSTR_USBRST target/stm32f103xb.h /^#define RCC_APB1RSTR_USBRST /;" d +RCC_APB1RSTR_WWDGRST_Msk target/stm32f103xb.h /^#define RCC_APB1RSTR_WWDGRST_Msk /;" d +RCC_APB1RSTR_WWDGRST_Pos target/stm32f103xb.h /^#define RCC_APB1RSTR_WWDGRST_Pos /;" d +RCC_APB1RSTR_WWDGRST target/stm32f103xb.h /^#define RCC_APB1RSTR_WWDGRST /;" d +RCC_APB2ENR_ADC1EN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_ADC1EN_Msk /;" d +RCC_APB2ENR_ADC1EN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_ADC1EN_Pos /;" d +RCC_APB2ENR_ADC1EN target/stm32f103xb.h /^#define RCC_APB2ENR_ADC1EN /;" d +RCC_APB2ENR_ADC2EN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_ADC2EN_Msk /;" d +RCC_APB2ENR_ADC2EN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_ADC2EN_Pos /;" d +RCC_APB2ENR_ADC2EN target/stm32f103xb.h /^#define RCC_APB2ENR_ADC2EN /;" d +RCC_APB2ENR_AFIOEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_AFIOEN_Msk /;" d +RCC_APB2ENR_AFIOEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_AFIOEN_Pos /;" d +RCC_APB2ENR_AFIOEN target/stm32f103xb.h /^#define RCC_APB2ENR_AFIOEN /;" d +RCC_APB2ENR_IOPAEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_IOPAEN_Msk /;" d +RCC_APB2ENR_IOPAEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_IOPAEN_Pos /;" d +RCC_APB2ENR_IOPAEN target/stm32f103xb.h /^#define RCC_APB2ENR_IOPAEN /;" d +RCC_APB2ENR_IOPBEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_IOPBEN_Msk /;" d +RCC_APB2ENR_IOPBEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_IOPBEN_Pos /;" d +RCC_APB2ENR_IOPBEN target/stm32f103xb.h /^#define RCC_APB2ENR_IOPBEN /;" d +RCC_APB2ENR_IOPCEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_IOPCEN_Msk /;" d +RCC_APB2ENR_IOPCEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_IOPCEN_Pos /;" d +RCC_APB2ENR_IOPCEN target/stm32f103xb.h /^#define RCC_APB2ENR_IOPCEN /;" d +RCC_APB2ENR_IOPDEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_IOPDEN_Msk /;" d +RCC_APB2ENR_IOPDEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_IOPDEN_Pos /;" d +RCC_APB2ENR_IOPDEN target/stm32f103xb.h /^#define RCC_APB2ENR_IOPDEN /;" d +RCC_APB2ENR_IOPEEN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_IOPEEN_Msk /;" d +RCC_APB2ENR_IOPEEN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_IOPEEN_Pos /;" d +RCC_APB2ENR_IOPEEN target/stm32f103xb.h /^#define RCC_APB2ENR_IOPEEN /;" d +RCC_APB2ENR_SPI1EN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_SPI1EN_Msk /;" d +RCC_APB2ENR_SPI1EN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_SPI1EN_Pos /;" d +RCC_APB2ENR_SPI1EN target/stm32f103xb.h /^#define RCC_APB2ENR_SPI1EN /;" d +RCC_APB2ENR_TIM1EN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_TIM1EN_Msk /;" d +RCC_APB2ENR_TIM1EN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_TIM1EN_Pos /;" d +RCC_APB2ENR_TIM1EN target/stm32f103xb.h /^#define RCC_APB2ENR_TIM1EN /;" d +RCC_APB2ENR_USART1EN_Msk target/stm32f103xb.h /^#define RCC_APB2ENR_USART1EN_Msk /;" d +RCC_APB2ENR_USART1EN_Pos target/stm32f103xb.h /^#define RCC_APB2ENR_USART1EN_Pos /;" d +RCC_APB2ENR_USART1EN target/stm32f103xb.h /^#define RCC_APB2ENR_USART1EN /;" d +RCC_APB2RSTR_ADC1RST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC1RST_Msk /;" d +RCC_APB2RSTR_ADC1RST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC1RST_Pos /;" d +RCC_APB2RSTR_ADC1RST target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC1RST /;" d +RCC_APB2RSTR_ADC2RST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC2RST_Msk /;" d +RCC_APB2RSTR_ADC2RST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC2RST_Pos /;" d +RCC_APB2RSTR_ADC2RST target/stm32f103xb.h /^#define RCC_APB2RSTR_ADC2RST /;" d +RCC_APB2RSTR_AFIORST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_AFIORST_Msk /;" d +RCC_APB2RSTR_AFIORST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_AFIORST_Pos /;" d +RCC_APB2RSTR_AFIORST target/stm32f103xb.h /^#define RCC_APB2RSTR_AFIORST /;" d +RCC_APB2RSTR_IOPARST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPARST_Msk /;" d +RCC_APB2RSTR_IOPARST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPARST_Pos /;" d +RCC_APB2RSTR_IOPARST target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPARST /;" d +RCC_APB2RSTR_IOPBRST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPBRST_Msk /;" d +RCC_APB2RSTR_IOPBRST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPBRST_Pos /;" d +RCC_APB2RSTR_IOPBRST target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPBRST /;" d +RCC_APB2RSTR_IOPCRST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPCRST_Msk /;" d +RCC_APB2RSTR_IOPCRST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPCRST_Pos /;" d +RCC_APB2RSTR_IOPCRST target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPCRST /;" d +RCC_APB2RSTR_IOPDRST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPDRST_Msk /;" d +RCC_APB2RSTR_IOPDRST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPDRST_Pos /;" d +RCC_APB2RSTR_IOPDRST target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPDRST /;" d +RCC_APB2RSTR_IOPERST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPERST_Msk /;" d +RCC_APB2RSTR_IOPERST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPERST_Pos /;" d +RCC_APB2RSTR_IOPERST target/stm32f103xb.h /^#define RCC_APB2RSTR_IOPERST /;" d +RCC_APB2RSTR_SPI1RST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_SPI1RST_Msk /;" d +RCC_APB2RSTR_SPI1RST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_SPI1RST_Pos /;" d +RCC_APB2RSTR_SPI1RST target/stm32f103xb.h /^#define RCC_APB2RSTR_SPI1RST /;" d +RCC_APB2RSTR_TIM1RST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_TIM1RST_Msk /;" d +RCC_APB2RSTR_TIM1RST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_TIM1RST_Pos /;" d +RCC_APB2RSTR_TIM1RST target/stm32f103xb.h /^#define RCC_APB2RSTR_TIM1RST /;" d +RCC_APB2RSTR_USART1RST_Msk target/stm32f103xb.h /^#define RCC_APB2RSTR_USART1RST_Msk /;" d +RCC_APB2RSTR_USART1RST_Pos target/stm32f103xb.h /^#define RCC_APB2RSTR_USART1RST_Pos /;" d +RCC_APB2RSTR_USART1RST target/stm32f103xb.h /^#define RCC_APB2RSTR_USART1RST /;" d +RCC_BASE target/stm32f103xb.h /^#define RCC_BASE /;" d +RCC_BDCR_BDRST_Msk target/stm32f103xb.h /^#define RCC_BDCR_BDRST_Msk /;" d +RCC_BDCR_BDRST_Pos target/stm32f103xb.h /^#define RCC_BDCR_BDRST_Pos /;" d +RCC_BDCR_BDRST target/stm32f103xb.h /^#define RCC_BDCR_BDRST /;" d +RCC_BDCR_LSEBYP_Msk target/stm32f103xb.h /^#define RCC_BDCR_LSEBYP_Msk /;" d +RCC_BDCR_LSEBYP_Pos target/stm32f103xb.h /^#define RCC_BDCR_LSEBYP_Pos /;" d +RCC_BDCR_LSEBYP target/stm32f103xb.h /^#define RCC_BDCR_LSEBYP /;" d +RCC_BDCR_LSEON_Msk target/stm32f103xb.h /^#define RCC_BDCR_LSEON_Msk /;" d +RCC_BDCR_LSEON_Pos target/stm32f103xb.h /^#define RCC_BDCR_LSEON_Pos /;" d +RCC_BDCR_LSEON target/stm32f103xb.h /^#define RCC_BDCR_LSEON /;" d +RCC_BDCR_LSERDY_Msk target/stm32f103xb.h /^#define RCC_BDCR_LSERDY_Msk /;" d +RCC_BDCR_LSERDY_Pos target/stm32f103xb.h /^#define RCC_BDCR_LSERDY_Pos /;" d +RCC_BDCR_LSERDY target/stm32f103xb.h /^#define RCC_BDCR_LSERDY /;" d +RCC_BDCR_RTCEN_Msk target/stm32f103xb.h /^#define RCC_BDCR_RTCEN_Msk /;" d +RCC_BDCR_RTCEN_Pos target/stm32f103xb.h /^#define RCC_BDCR_RTCEN_Pos /;" d +RCC_BDCR_RTCEN target/stm32f103xb.h /^#define RCC_BDCR_RTCEN /;" d +RCC_BDCR_RTCSEL_0 target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_0 /;" d +RCC_BDCR_RTCSEL_1 target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_1 /;" d +RCC_BDCR_RTCSEL_HSE target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_HSE /;" d +RCC_BDCR_RTCSEL_LSE target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_LSE /;" d +RCC_BDCR_RTCSEL_LSI target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_LSI /;" d +RCC_BDCR_RTCSEL_Msk target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_Msk /;" d +RCC_BDCR_RTCSEL_NOCLOCK target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_NOCLOCK /;" d +RCC_BDCR_RTCSEL_Pos target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL_Pos /;" d +RCC_BDCR_RTCSEL target/stm32f103xb.h /^#define RCC_BDCR_RTCSEL /;" d +RCC_CFGR_ADCPRE_0 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_0 /;" d +RCC_CFGR_ADCPRE_1 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_1 /;" d +RCC_CFGR_ADCPRE_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_DIV2 /;" d +RCC_CFGR_ADCPRE_DIV4 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_DIV4 /;" d +RCC_CFGR_ADCPRE_DIV6 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_DIV6 /;" d +RCC_CFGR_ADCPRE_DIV8 target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_DIV8 /;" d +RCC_CFGR_ADCPRE_Msk target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_Msk /;" d +RCC_CFGR_ADCPRE_Pos target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE_Pos /;" d +RCC_CFGR_ADCPRE target/stm32f103xb.h /^#define RCC_CFGR_ADCPRE /;" d +RCC_CFGR_HPRE_0 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_0 /;" d +RCC_CFGR_HPRE_1 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_1 /;" d +RCC_CFGR_HPRE_2 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_2 /;" d +RCC_CFGR_HPRE_3 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_3 /;" d +RCC_CFGR_HPRE_DIV128 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV128 /;" d +RCC_CFGR_HPRE_DIV16 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV16 /;" d +RCC_CFGR_HPRE_DIV1 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV1 /;" d +RCC_CFGR_HPRE_DIV256 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV256 /;" d +RCC_CFGR_HPRE_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV2 /;" d +RCC_CFGR_HPRE_DIV4 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV4 /;" d +RCC_CFGR_HPRE_DIV512 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV512 /;" d +RCC_CFGR_HPRE_DIV64 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV64 /;" d +RCC_CFGR_HPRE_DIV8 target/stm32f103xb.h /^#define RCC_CFGR_HPRE_DIV8 /;" d +RCC_CFGR_HPRE_DIV_128 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_128 /;" d file: +RCC_CFGR_HPRE_DIV_128 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_128 /;" d file: +RCC_CFGR_HPRE_DIV_16 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_16 /;" d file: +RCC_CFGR_HPRE_DIV_16 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_16 /;" d file: +RCC_CFGR_HPRE_DIV_256 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_256 /;" d file: +RCC_CFGR_HPRE_DIV_256 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_256 /;" d file: +RCC_CFGR_HPRE_DIV_2 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_2 /;" d file: +RCC_CFGR_HPRE_DIV_2 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_2 /;" d file: +RCC_CFGR_HPRE_DIV_4 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_4 /;" d file: +RCC_CFGR_HPRE_DIV_4 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_4 /;" d file: +RCC_CFGR_HPRE_DIV_512 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_512 /;" d file: +RCC_CFGR_HPRE_DIV_512 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_512 /;" d file: +RCC_CFGR_HPRE_DIV_64 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_64 /;" d file: +RCC_CFGR_HPRE_DIV_64 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_64 /;" d file: +RCC_CFGR_HPRE_DIV_8 Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_8 /;" d file: +RCC_CFGR_HPRE_DIV_8 drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_8 /;" d file: +RCC_CFGR_HPRE_DIV_NONE Untitled Folder/rcc.c /^#define RCC_CFGR_HPRE_DIV_NONE /;" d file: +RCC_CFGR_HPRE_DIV_NONE drivers/rcc.c /^#define RCC_CFGR_HPRE_DIV_NONE /;" d file: +RCC_CFGR_HPRE_Msk target/stm32f103xb.h /^#define RCC_CFGR_HPRE_Msk /;" d +RCC_CFGR_HPRE_Pos target/stm32f103xb.h /^#define RCC_CFGR_HPRE_Pos /;" d +RCC_CFGR_HPRE target/stm32f103xb.h /^#define RCC_CFGR_HPRE /;" d +RCC_CFGR_MCOSEL_0 target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_0 /;" d +RCC_CFGR_MCOSEL_1 target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_1 /;" d +RCC_CFGR_MCOSEL_2 target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_2 /;" d +RCC_CFGR_MCOSEL_HSE target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_HSE /;" d +RCC_CFGR_MCOSEL_HSI target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_HSI /;" d +RCC_CFGR_MCOSEL_NOCLOCK target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_NOCLOCK /;" d +RCC_CFGR_MCOSEL_PLL_DIV2 target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_PLL_DIV2 /;" d +RCC_CFGR_MCOSEL_SYSCLK target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL_SYSCLK /;" d +RCC_CFGR_MCOSEL target/stm32f103xb.h /^ #define RCC_CFGR_MCOSEL /;" d +RCC_CFGR_MCO_0 target/stm32f103xb.h /^#define RCC_CFGR_MCO_0 /;" d +RCC_CFGR_MCO_1 target/stm32f103xb.h /^#define RCC_CFGR_MCO_1 /;" d +RCC_CFGR_MCO_2 target/stm32f103xb.h /^#define RCC_CFGR_MCO_2 /;" d +RCC_CFGR_MCO_HSE target/stm32f103xb.h /^#define RCC_CFGR_MCO_HSE /;" d +RCC_CFGR_MCO_HSI target/stm32f103xb.h /^#define RCC_CFGR_MCO_HSI /;" d +RCC_CFGR_MCO_Msk target/stm32f103xb.h /^#define RCC_CFGR_MCO_Msk /;" d +RCC_CFGR_MCO_NOCLOCK target/stm32f103xb.h /^#define RCC_CFGR_MCO_NOCLOCK /;" d +RCC_CFGR_MCO_PLLCLK_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_MCO_PLLCLK_DIV2 /;" d +RCC_CFGR_MCO_Pos target/stm32f103xb.h /^#define RCC_CFGR_MCO_Pos /;" d +RCC_CFGR_MCO_SYSCLK target/stm32f103xb.h /^#define RCC_CFGR_MCO_SYSCLK /;" d +RCC_CFGR_MCO target/stm32f103xb.h /^#define RCC_CFGR_MCO /;" d +RCC_CFGR_PLLMULL10_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL10_Msk /;" d +RCC_CFGR_PLLMULL10_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL10_Pos /;" d +RCC_CFGR_PLLMULL10 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL10 /;" d +RCC_CFGR_PLLMULL11_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL11_Msk /;" d +RCC_CFGR_PLLMULL11_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL11_Pos /;" d +RCC_CFGR_PLLMULL11 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL11 /;" d +RCC_CFGR_PLLMULL12_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL12_Msk /;" d +RCC_CFGR_PLLMULL12_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL12_Pos /;" d +RCC_CFGR_PLLMULL12 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL12 /;" d +RCC_CFGR_PLLMULL13_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL13_Msk /;" d +RCC_CFGR_PLLMULL13_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL13_Pos /;" d +RCC_CFGR_PLLMULL13 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL13 /;" d +RCC_CFGR_PLLMULL14_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL14_Msk /;" d +RCC_CFGR_PLLMULL14_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL14_Pos /;" d +RCC_CFGR_PLLMULL14 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL14 /;" d +RCC_CFGR_PLLMULL15_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL15_Msk /;" d +RCC_CFGR_PLLMULL15_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL15_Pos /;" d +RCC_CFGR_PLLMULL15 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL15 /;" d +RCC_CFGR_PLLMULL16_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL16_Msk /;" d +RCC_CFGR_PLLMULL16_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL16_Pos /;" d +RCC_CFGR_PLLMULL16 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL16 /;" d +RCC_CFGR_PLLMULL2 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL2 /;" d +RCC_CFGR_PLLMULL3_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL3_Msk /;" d +RCC_CFGR_PLLMULL3_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL3_Pos /;" d +RCC_CFGR_PLLMULL3 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL3 /;" d +RCC_CFGR_PLLMULL4_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL4_Msk /;" d +RCC_CFGR_PLLMULL4_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL4_Pos /;" d +RCC_CFGR_PLLMULL4 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL4 /;" d +RCC_CFGR_PLLMULL5_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL5_Msk /;" d +RCC_CFGR_PLLMULL5_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL5_Pos /;" d +RCC_CFGR_PLLMULL5 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL5 /;" d +RCC_CFGR_PLLMULL6_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL6_Msk /;" d +RCC_CFGR_PLLMULL6_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL6_Pos /;" d +RCC_CFGR_PLLMULL6 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL6 /;" d +RCC_CFGR_PLLMULL7_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL7_Msk /;" d +RCC_CFGR_PLLMULL7_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL7_Pos /;" d +RCC_CFGR_PLLMULL7 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL7 /;" d +RCC_CFGR_PLLMULL8_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL8_Msk /;" d +RCC_CFGR_PLLMULL8_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL8_Pos /;" d +RCC_CFGR_PLLMULL8 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL8 /;" d +RCC_CFGR_PLLMULL9_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL9_Msk /;" d +RCC_CFGR_PLLMULL9_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL9_Pos /;" d +RCC_CFGR_PLLMULL9 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL9 /;" d +RCC_CFGR_PLLMULL_0 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_0 /;" d +RCC_CFGR_PLLMULL_1 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_1 /;" d +RCC_CFGR_PLLMULL_2 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_2 /;" d +RCC_CFGR_PLLMULL_3 target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_3 /;" d +RCC_CFGR_PLLMULL_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_Msk /;" d +RCC_CFGR_PLLMULL_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL_Pos /;" d +RCC_CFGR_PLLMULL target/stm32f103xb.h /^#define RCC_CFGR_PLLMULL /;" d +RCC_CFGR_PLLMUL drivers/rcc.c /^#define RCC_CFGR_PLLMUL(/;" d file: +RCC_CFGR_PLLSRC_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLSRC_Msk /;" d +RCC_CFGR_PLLSRC_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLSRC_Pos /;" d +RCC_CFGR_PLLSRC target/stm32f103xb.h /^#define RCC_CFGR_PLLSRC /;" d +RCC_CFGR_PLLXTPRE_HSE_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_PLLXTPRE_HSE_DIV2 /;" d +RCC_CFGR_PLLXTPRE_HSE target/stm32f103xb.h /^#define RCC_CFGR_PLLXTPRE_HSE /;" d +RCC_CFGR_PLLXTPRE_Msk target/stm32f103xb.h /^#define RCC_CFGR_PLLXTPRE_Msk /;" d +RCC_CFGR_PLLXTPRE_Pos target/stm32f103xb.h /^#define RCC_CFGR_PLLXTPRE_Pos /;" d +RCC_CFGR_PLLXTPRE target/stm32f103xb.h /^#define RCC_CFGR_PLLXTPRE /;" d +RCC_CFGR_PPRE1_0 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_0 /;" d +RCC_CFGR_PPRE1_1 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_1 /;" d +RCC_CFGR_PPRE1_2 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_2 /;" d +RCC_CFGR_PPRE1_DIV16 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_DIV16 /;" d +RCC_CFGR_PPRE1_DIV1 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_DIV1 /;" d +RCC_CFGR_PPRE1_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_DIV2 /;" d +RCC_CFGR_PPRE1_DIV4 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_DIV4 /;" d +RCC_CFGR_PPRE1_DIV8 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_DIV8 /;" d +RCC_CFGR_PPRE1_Msk target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_Msk /;" d +RCC_CFGR_PPRE1_Pos target/stm32f103xb.h /^#define RCC_CFGR_PPRE1_Pos /;" d +RCC_CFGR_PPRE1 target/stm32f103xb.h /^#define RCC_CFGR_PPRE1 /;" d +RCC_CFGR_PPRE2_0 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_0 /;" d +RCC_CFGR_PPRE2_1 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_1 /;" d +RCC_CFGR_PPRE2_2 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_2 /;" d +RCC_CFGR_PPRE2_DIV16 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_DIV16 /;" d +RCC_CFGR_PPRE2_DIV1 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_DIV1 /;" d +RCC_CFGR_PPRE2_DIV2 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_DIV2 /;" d +RCC_CFGR_PPRE2_DIV4 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_DIV4 /;" d +RCC_CFGR_PPRE2_DIV8 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_DIV8 /;" d +RCC_CFGR_PPRE2_Msk target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_Msk /;" d +RCC_CFGR_PPRE2_Pos target/stm32f103xb.h /^#define RCC_CFGR_PPRE2_Pos /;" d +RCC_CFGR_PPRE2 target/stm32f103xb.h /^#define RCC_CFGR_PPRE2 /;" d +RCC_CFGR_PPRE_DIV_16 Untitled Folder/rcc.c /^#define RCC_CFGR_PPRE_DIV_16 /;" d file: +RCC_CFGR_PPRE_DIV_16 drivers/rcc.c /^#define RCC_CFGR_PPRE_DIV_16 /;" d file: +RCC_CFGR_PPRE_DIV_2 Untitled Folder/rcc.c /^#define RCC_CFGR_PPRE_DIV_2 /;" d file: +RCC_CFGR_PPRE_DIV_2 drivers/rcc.c /^#define RCC_CFGR_PPRE_DIV_2 /;" d file: +RCC_CFGR_PPRE_DIV_4 Untitled Folder/rcc.c /^#define RCC_CFGR_PPRE_DIV_4 /;" d file: +RCC_CFGR_PPRE_DIV_4 drivers/rcc.c /^#define RCC_CFGR_PPRE_DIV_4 /;" d file: +RCC_CFGR_PPRE_DIV_8 Untitled Folder/rcc.c /^#define RCC_CFGR_PPRE_DIV_8 /;" d file: +RCC_CFGR_PPRE_DIV_8 drivers/rcc.c /^#define RCC_CFGR_PPRE_DIV_8 /;" d file: +RCC_CFGR_PPRE_DIV_NONE Untitled Folder/rcc.c /^#define RCC_CFGR_PPRE_DIV_NONE /;" d file: +RCC_CFGR_PPRE_DIV_NONE drivers/rcc.c /^#define RCC_CFGR_PPRE_DIV_NONE /;" d file: +RCC_CFGR_SWS_0 target/stm32f103xb.h /^#define RCC_CFGR_SWS_0 /;" d +RCC_CFGR_SWS_1 target/stm32f103xb.h /^#define RCC_CFGR_SWS_1 /;" d +RCC_CFGR_SWS_HSE target/stm32f103xb.h /^#define RCC_CFGR_SWS_HSE /;" d +RCC_CFGR_SWS_HSI target/stm32f103xb.h /^#define RCC_CFGR_SWS_HSI /;" d +RCC_CFGR_SWS_Msk target/stm32f103xb.h /^#define RCC_CFGR_SWS_Msk /;" d +RCC_CFGR_SWS_PLL target/stm32f103xb.h /^#define RCC_CFGR_SWS_PLL /;" d +RCC_CFGR_SWS_Pos target/stm32f103xb.h /^#define RCC_CFGR_SWS_Pos /;" d +RCC_CFGR_SWS target/stm32f103xb.h /^#define RCC_CFGR_SWS /;" d +RCC_CFGR_SW_0 target/stm32f103xb.h /^#define RCC_CFGR_SW_0 /;" d +RCC_CFGR_SW_1 target/stm32f103xb.h /^#define RCC_CFGR_SW_1 /;" d +RCC_CFGR_SW_HSE target/stm32f103xb.h /^#define RCC_CFGR_SW_HSE /;" d +RCC_CFGR_SW_HSI target/stm32f103xb.h /^#define RCC_CFGR_SW_HSI /;" d +RCC_CFGR_SW_Msk target/stm32f103xb.h /^#define RCC_CFGR_SW_Msk /;" d +RCC_CFGR_SW_PLL target/stm32f103xb.h /^#define RCC_CFGR_SW_PLL /;" d +RCC_CFGR_SW_Pos target/stm32f103xb.h /^#define RCC_CFGR_SW_Pos /;" d +RCC_CFGR_SW target/stm32f103xb.h /^#define RCC_CFGR_SW /;" d +RCC_CFGR_USBPRE_Msk target/stm32f103xb.h /^#define RCC_CFGR_USBPRE_Msk /;" d +RCC_CFGR_USBPRE_Pos target/stm32f103xb.h /^#define RCC_CFGR_USBPRE_Pos /;" d +RCC_CFGR_USBPRE target/stm32f103xb.h /^#define RCC_CFGR_USBPRE /;" d +RCC_CIR_CSSC_Msk target/stm32f103xb.h /^#define RCC_CIR_CSSC_Msk /;" d +RCC_CIR_CSSC_Pos target/stm32f103xb.h /^#define RCC_CIR_CSSC_Pos /;" d +RCC_CIR_CSSC target/stm32f103xb.h /^#define RCC_CIR_CSSC /;" d +RCC_CIR_CSSF_Msk target/stm32f103xb.h /^#define RCC_CIR_CSSF_Msk /;" d +RCC_CIR_CSSF_Pos target/stm32f103xb.h /^#define RCC_CIR_CSSF_Pos /;" d +RCC_CIR_CSSF target/stm32f103xb.h /^#define RCC_CIR_CSSF /;" d +RCC_CIR_HSERDYC_Msk target/stm32f103xb.h /^#define RCC_CIR_HSERDYC_Msk /;" d +RCC_CIR_HSERDYC_Pos target/stm32f103xb.h /^#define RCC_CIR_HSERDYC_Pos /;" d +RCC_CIR_HSERDYC target/stm32f103xb.h /^#define RCC_CIR_HSERDYC /;" d +RCC_CIR_HSERDYF_Msk target/stm32f103xb.h /^#define RCC_CIR_HSERDYF_Msk /;" d +RCC_CIR_HSERDYF_Pos target/stm32f103xb.h /^#define RCC_CIR_HSERDYF_Pos /;" d +RCC_CIR_HSERDYF target/stm32f103xb.h /^#define RCC_CIR_HSERDYF /;" d +RCC_CIR_HSERDYIE_Msk target/stm32f103xb.h /^#define RCC_CIR_HSERDYIE_Msk /;" d +RCC_CIR_HSERDYIE_Pos target/stm32f103xb.h /^#define RCC_CIR_HSERDYIE_Pos /;" d +RCC_CIR_HSERDYIE target/stm32f103xb.h /^#define RCC_CIR_HSERDYIE /;" d +RCC_CIR_HSIRDYC_Msk target/stm32f103xb.h /^#define RCC_CIR_HSIRDYC_Msk /;" d +RCC_CIR_HSIRDYC_Pos target/stm32f103xb.h /^#define RCC_CIR_HSIRDYC_Pos /;" d +RCC_CIR_HSIRDYC target/stm32f103xb.h /^#define RCC_CIR_HSIRDYC /;" d +RCC_CIR_HSIRDYF_Msk target/stm32f103xb.h /^#define RCC_CIR_HSIRDYF_Msk /;" d +RCC_CIR_HSIRDYF_Pos target/stm32f103xb.h /^#define RCC_CIR_HSIRDYF_Pos /;" d +RCC_CIR_HSIRDYF target/stm32f103xb.h /^#define RCC_CIR_HSIRDYF /;" d +RCC_CIR_HSIRDYIE_Msk target/stm32f103xb.h /^#define RCC_CIR_HSIRDYIE_Msk /;" d +RCC_CIR_HSIRDYIE_Pos target/stm32f103xb.h /^#define RCC_CIR_HSIRDYIE_Pos /;" d +RCC_CIR_HSIRDYIE target/stm32f103xb.h /^#define RCC_CIR_HSIRDYIE /;" d +RCC_CIR_LSERDYC_Msk target/stm32f103xb.h /^#define RCC_CIR_LSERDYC_Msk /;" d +RCC_CIR_LSERDYC_Pos target/stm32f103xb.h /^#define RCC_CIR_LSERDYC_Pos /;" d +RCC_CIR_LSERDYC target/stm32f103xb.h /^#define RCC_CIR_LSERDYC /;" d +RCC_CIR_LSERDYF_Msk target/stm32f103xb.h /^#define RCC_CIR_LSERDYF_Msk /;" d +RCC_CIR_LSERDYF_Pos target/stm32f103xb.h /^#define RCC_CIR_LSERDYF_Pos /;" d +RCC_CIR_LSERDYF target/stm32f103xb.h /^#define RCC_CIR_LSERDYF /;" d +RCC_CIR_LSERDYIE_Msk target/stm32f103xb.h /^#define RCC_CIR_LSERDYIE_Msk /;" d +RCC_CIR_LSERDYIE_Pos target/stm32f103xb.h /^#define RCC_CIR_LSERDYIE_Pos /;" d +RCC_CIR_LSERDYIE target/stm32f103xb.h /^#define RCC_CIR_LSERDYIE /;" d +RCC_CIR_LSIRDYC_Msk target/stm32f103xb.h /^#define RCC_CIR_LSIRDYC_Msk /;" d +RCC_CIR_LSIRDYC_Pos target/stm32f103xb.h /^#define RCC_CIR_LSIRDYC_Pos /;" d +RCC_CIR_LSIRDYC target/stm32f103xb.h /^#define RCC_CIR_LSIRDYC /;" d +RCC_CIR_LSIRDYF_Msk target/stm32f103xb.h /^#define RCC_CIR_LSIRDYF_Msk /;" d +RCC_CIR_LSIRDYF_Pos target/stm32f103xb.h /^#define RCC_CIR_LSIRDYF_Pos /;" d +RCC_CIR_LSIRDYF target/stm32f103xb.h /^#define RCC_CIR_LSIRDYF /;" d +RCC_CIR_LSIRDYIE_Msk target/stm32f103xb.h /^#define RCC_CIR_LSIRDYIE_Msk /;" d +RCC_CIR_LSIRDYIE_Pos target/stm32f103xb.h /^#define RCC_CIR_LSIRDYIE_Pos /;" d +RCC_CIR_LSIRDYIE target/stm32f103xb.h /^#define RCC_CIR_LSIRDYIE /;" d +RCC_CIR_PLLRDYC_Msk target/stm32f103xb.h /^#define RCC_CIR_PLLRDYC_Msk /;" d +RCC_CIR_PLLRDYC_Pos target/stm32f103xb.h /^#define RCC_CIR_PLLRDYC_Pos /;" d +RCC_CIR_PLLRDYC target/stm32f103xb.h /^#define RCC_CIR_PLLRDYC /;" d +RCC_CIR_PLLRDYF_Msk target/stm32f103xb.h /^#define RCC_CIR_PLLRDYF_Msk /;" d +RCC_CIR_PLLRDYF_Pos target/stm32f103xb.h /^#define RCC_CIR_PLLRDYF_Pos /;" d +RCC_CIR_PLLRDYF target/stm32f103xb.h /^#define RCC_CIR_PLLRDYF /;" d +RCC_CIR_PLLRDYIE_Msk target/stm32f103xb.h /^#define RCC_CIR_PLLRDYIE_Msk /;" d +RCC_CIR_PLLRDYIE_Pos target/stm32f103xb.h /^#define RCC_CIR_PLLRDYIE_Pos /;" d +RCC_CIR_PLLRDYIE target/stm32f103xb.h /^#define RCC_CIR_PLLRDYIE /;" d +RCC_CR_CSSON_Msk target/stm32f103xb.h /^#define RCC_CR_CSSON_Msk /;" d +RCC_CR_CSSON_Pos target/stm32f103xb.h /^#define RCC_CR_CSSON_Pos /;" d +RCC_CR_CSSON target/stm32f103xb.h /^#define RCC_CR_CSSON /;" d +RCC_CR_HSEBYP_Msk target/stm32f103xb.h /^#define RCC_CR_HSEBYP_Msk /;" d +RCC_CR_HSEBYP_Pos target/stm32f103xb.h /^#define RCC_CR_HSEBYP_Pos /;" d +RCC_CR_HSEBYP target/stm32f103xb.h /^#define RCC_CR_HSEBYP /;" d +RCC_CR_HSEON_Msk target/stm32f103xb.h /^#define RCC_CR_HSEON_Msk /;" d +RCC_CR_HSEON_Pos target/stm32f103xb.h /^#define RCC_CR_HSEON_Pos /;" d +RCC_CR_HSEON target/stm32f103xb.h /^#define RCC_CR_HSEON /;" d +RCC_CR_HSERDY_Msk target/stm32f103xb.h /^#define RCC_CR_HSERDY_Msk /;" d +RCC_CR_HSERDY_Pos target/stm32f103xb.h /^#define RCC_CR_HSERDY_Pos /;" d +RCC_CR_HSERDY target/stm32f103xb.h /^#define RCC_CR_HSERDY /;" d +RCC_CR_HSICAL_Msk target/stm32f103xb.h /^#define RCC_CR_HSICAL_Msk /;" d +RCC_CR_HSICAL_Pos target/stm32f103xb.h /^#define RCC_CR_HSICAL_Pos /;" d +RCC_CR_HSICAL target/stm32f103xb.h /^#define RCC_CR_HSICAL /;" d +RCC_CR_HSION_Msk target/stm32f103xb.h /^#define RCC_CR_HSION_Msk /;" d +RCC_CR_HSION_Pos target/stm32f103xb.h /^#define RCC_CR_HSION_Pos /;" d +RCC_CR_HSION target/stm32f103xb.h /^#define RCC_CR_HSION /;" d +RCC_CR_HSIRDY_Msk target/stm32f103xb.h /^#define RCC_CR_HSIRDY_Msk /;" d +RCC_CR_HSIRDY_Pos target/stm32f103xb.h /^#define RCC_CR_HSIRDY_Pos /;" d +RCC_CR_HSIRDY target/stm32f103xb.h /^#define RCC_CR_HSIRDY /;" d +RCC_CR_HSITRIM_Msk target/stm32f103xb.h /^#define RCC_CR_HSITRIM_Msk /;" d +RCC_CR_HSITRIM_Pos target/stm32f103xb.h /^#define RCC_CR_HSITRIM_Pos /;" d +RCC_CR_HSITRIM target/stm32f103xb.h /^#define RCC_CR_HSITRIM /;" d +RCC_CR_PLLON_Msk target/stm32f103xb.h /^#define RCC_CR_PLLON_Msk /;" d +RCC_CR_PLLON_Pos target/stm32f103xb.h /^#define RCC_CR_PLLON_Pos /;" d +RCC_CR_PLLON target/stm32f103xb.h /^#define RCC_CR_PLLON /;" d +RCC_CR_PLLRDY_Msk target/stm32f103xb.h /^#define RCC_CR_PLLRDY_Msk /;" d +RCC_CR_PLLRDY_Pos target/stm32f103xb.h /^#define RCC_CR_PLLRDY_Pos /;" d +RCC_CR_PLLRDY target/stm32f103xb.h /^#define RCC_CR_PLLRDY /;" d +RCC_CSR_IWDGRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_IWDGRSTF_Msk /;" d +RCC_CSR_IWDGRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_IWDGRSTF_Pos /;" d +RCC_CSR_IWDGRSTF target/stm32f103xb.h /^#define RCC_CSR_IWDGRSTF /;" d +RCC_CSR_LPWRRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_LPWRRSTF_Msk /;" d +RCC_CSR_LPWRRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_LPWRRSTF_Pos /;" d +RCC_CSR_LPWRRSTF target/stm32f103xb.h /^#define RCC_CSR_LPWRRSTF /;" d +RCC_CSR_LSION_Msk target/stm32f103xb.h /^#define RCC_CSR_LSION_Msk /;" d +RCC_CSR_LSION_Pos target/stm32f103xb.h /^#define RCC_CSR_LSION_Pos /;" d +RCC_CSR_LSION target/stm32f103xb.h /^#define RCC_CSR_LSION /;" d +RCC_CSR_LSIRDY_Msk target/stm32f103xb.h /^#define RCC_CSR_LSIRDY_Msk /;" d +RCC_CSR_LSIRDY_Pos target/stm32f103xb.h /^#define RCC_CSR_LSIRDY_Pos /;" d +RCC_CSR_LSIRDY target/stm32f103xb.h /^#define RCC_CSR_LSIRDY /;" d +RCC_CSR_PINRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_PINRSTF_Msk /;" d +RCC_CSR_PINRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_PINRSTF_Pos /;" d +RCC_CSR_PINRSTF target/stm32f103xb.h /^#define RCC_CSR_PINRSTF /;" d +RCC_CSR_PORRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_PORRSTF_Msk /;" d +RCC_CSR_PORRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_PORRSTF_Pos /;" d +RCC_CSR_PORRSTF target/stm32f103xb.h /^#define RCC_CSR_PORRSTF /;" d +RCC_CSR_RMVF_Msk target/stm32f103xb.h /^#define RCC_CSR_RMVF_Msk /;" d +RCC_CSR_RMVF_Pos target/stm32f103xb.h /^#define RCC_CSR_RMVF_Pos /;" d +RCC_CSR_RMVF target/stm32f103xb.h /^#define RCC_CSR_RMVF /;" d +RCC_CSR_SFTRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_SFTRSTF_Msk /;" d +RCC_CSR_SFTRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_SFTRSTF_Pos /;" d +RCC_CSR_SFTRSTF target/stm32f103xb.h /^#define RCC_CSR_SFTRSTF /;" d +RCC_CSR_WWDGRSTF_Msk target/stm32f103xb.h /^#define RCC_CSR_WWDGRSTF_Msk /;" d +RCC_CSR_WWDGRSTF_Pos target/stm32f103xb.h /^#define RCC_CSR_WWDGRSTF_Pos /;" d +RCC_CSR_WWDGRSTF target/stm32f103xb.h /^#define RCC_CSR_WWDGRSTF /;" d +RCC_HSE_MAX target/stm32f103xb.h /^#define RCC_HSE_MAX /;" d +RCC_HSE_MIN target/stm32f103xb.h /^#define RCC_HSE_MIN /;" d +RCC_HSE Untitled Folder/rcc.c /^ RCC_HSE,$/;" e enum:rcc_osc file: +RCC_HSE drivers/rcc.c /^ RCC_HSE,$/;" e enum:rcc_osc file: +RCC_HSI Untitled Folder/rcc.c /^ RCC_HSI,$/;" e enum:rcc_osc file: +RCC_HSI drivers/rcc.c /^ RCC_HSI,$/;" e enum:rcc_osc file: +RCC_IRQn target/stm32f103xb.h /^ RCC_IRQn = 5, \/*!< RCC global Interrupt /;" e enum:__anon72c4c37e0103 +RCC_LSE Untitled Folder/rcc.c /^ RCC_LSE$/;" e enum:rcc_osc file: +RCC_LSE drivers/rcc.c /^ RCC_LSE$/;" e enum:rcc_osc file: +RCC_LSI Untitled Folder/rcc.c /^ RCC_LSI,$/;" e enum:rcc_osc file: +RCC_LSI drivers/rcc.c /^ RCC_LSI,$/;" e enum:rcc_osc file: +RCC_MAX_FREQUENCY target/stm32f103xb.h /^#define RCC_MAX_FREQUENCY /;" d +RCC_PLLI2S Untitled Folder/rcc.c /^ RCC_PLLI2S,$/;" e enum:rcc_osc file: +RCC_PLL Untitled Folder/rcc.c /^ RCC_PLL,$/;" e enum:rcc_osc file: +RCC_PLL drivers/rcc.c /^ RCC_PLL,$/;" e enum:rcc_osc file: +RCC_TypeDef target/stm32f103xb.h /^} RCC_TypeDef;$/;" t typeref:struct:__anon72c4c37e1508 +RCC target/stm32f103xb.h /^#define RCC /;" d +RCR target/stm32f103xb.h /^ __IO uint32_t RCR; \/*!< TIM repetition counter register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +RDHR target/stm32f103xb.h /^ __IO uint32_t RDHR;$/;" m struct:__anon72c4c37e0608 typeref:typename:__IO uint32_t +RDLR target/stm32f103xb.h /^ __IO uint32_t RDLR;$/;" m struct:__anon72c4c37e0608 typeref:typename:__IO uint32_t +RDP_KEY_Msk target/stm32f103xb.h /^#define RDP_KEY_Msk /;" d +RDP_KEY_Pos target/stm32f103xb.h /^#define RDP_KEY_Pos /;" d +RDP_KEY target/stm32f103xb.h /^#define RDP_KEY /;" d +RDP target/stm32f103xb.h /^ __IO uint16_t RDP;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +RDTR target/stm32f103xb.h /^ __IO uint32_t RDTR;$/;" m struct:__anon72c4c37e0608 typeref:typename:__IO uint32_t +READ_BIT target/stm32f1xx.h /^#define READ_BIT(/;" d +READ_REG target/stm32f1xx.h /^#define READ_REG(/;" d +RESERVED0 target/stm32f103xb.h /^ __IO uint16_t RESERVED0; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED0 target/stm32f103xb.h /^ uint32_t RESERVED0;$/;" m struct:__anon72c4c37e0408 typeref:typename:uint32_t +RESERVED0 target/stm32f103xb.h /^ uint32_t RESERVED0[2];$/;" m struct:__anon72c4c37e1708 typeref:typename:uint32_t[2] +RESERVED0 target/stm32f103xb.h /^ uint32_t RESERVED0[88];$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t[88] +RESERVED0 target/stm32f103xb.h /^ uint32_t RESERVED0;$/;" m struct:__anon72c4c37e1108 typeref:typename:uint32_t +RESERVED0 target/stm32f103xb.h /^ uint8_t RESERVED0; \/*!< Reserved, Address offset:/;" m struct:__anon72c4c37e0908 typeref:typename:uint8_t +RESERVED1 target/stm32f103xb.h /^ __IO uint16_t RESERVED1; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED1 target/stm32f103xb.h /^ uint16_t RESERVED1; \/*!< Reserved, Address offset:/;" m struct:__anon72c4c37e0908 typeref:typename:uint16_t +RESERVED1 target/stm32f103xb.h /^ uint32_t RESERVED1[12];$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t[12] +RESERVED1 target/stm32f103xb.h /^ uint32_t RESERVED1[13];$/;" m struct:__anon72c4c37e1708 typeref:typename:uint32_t[13] +RESERVED2 target/stm32f103xb.h /^ __IO uint16_t RESERVED2; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED2 target/stm32f103xb.h /^ uint32_t RESERVED2;$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t +RESERVED3 target/stm32f103xb.h /^ __IO uint16_t RESERVED3; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED3 target/stm32f103xb.h /^ uint32_t RESERVED3;$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t +RESERVED4 target/stm32f103xb.h /^ __IO uint16_t RESERVED4; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED4 target/stm32f103xb.h /^ uint32_t RESERVED4;$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t +RESERVED5 target/stm32f103xb.h /^ __IO uint16_t RESERVED5; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED5 target/stm32f103xb.h /^ uint32_t RESERVED5[8];$/;" m struct:__anon72c4c37e0808 typeref:typename:uint32_t[8] +RESERVED6 target/stm32f103xb.h /^ __IO uint16_t RESERVED6; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED7 target/stm32f103xb.h /^ __IO uint16_t RESERVED7[17]; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t[17] +RESERVED8 target/stm32f103xb.h /^ __IO uint16_t RESERVED8; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED9 target/stm32f103xb.h /^ __IO uint16_t RESERVED9; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVEDA target/stm32f103xb.h /^ __IO uint16_t RESERVEDA; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVEDB target/stm32f103xb.h /^ __IO uint16_t RESERVEDB; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVEDC target/stm32f103xb.h /^ __IO uint16_t RESERVEDC; \/*!< Reserved *\/ $/;" m struct:__anon72c4c37e1b08 typeref:typename:__IO uint16_t +RESERVED target/stm32f103xb.h /^ __IO uint32_t RESERVED;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +RESERVED target/stm32f103xb.h /^ uint32_t RESERVED[16];$/;" m struct:__anon72c4c37e0308 typeref:typename:uint32_t[16] +RESET target/stm32f1xx.h /^ RESET = 0, $/;" e enum:__anonbccbea710103 +RESP1 target/stm32f103xb.h /^ __I uint32_t RESP1;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +RESP2 target/stm32f103xb.h /^ __I uint32_t RESP2;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +RESP3 target/stm32f103xb.h /^ __I uint32_t RESP3;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +RESP4 target/stm32f103xb.h /^ __I uint32_t RESP4;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +RESPCMD target/stm32f103xb.h /^ __I uint32_t RESPCMD;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +RF0R target/stm32f103xb.h /^ __IO uint32_t RF0R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +RF1R target/stm32f103xb.h /^ __IO uint32_t RF1R;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +RIR target/stm32f103xb.h /^ __IO uint32_t RIR;$/;" m struct:__anon72c4c37e0608 typeref:typename:__IO uint32_t +RLR target/stm32f103xb.h /^ __IO uint32_t RLR; \/*!< Reload register, Address offset:/;" m struct:__anon72c4c37e1308 typeref:typename:__IO uint32_t +RTCCR target/stm32f103xb.h /^ __IO uint32_t RTCCR;$/;" m struct:__anon72c4c37e0408 typeref:typename:__IO uint32_t +RTC_ALRH_RTC_ALR_Msk target/stm32f103xb.h /^#define RTC_ALRH_RTC_ALR_Msk /;" d +RTC_ALRH_RTC_ALR_Pos target/stm32f103xb.h /^#define RTC_ALRH_RTC_ALR_Pos /;" d +RTC_ALRH_RTC_ALR target/stm32f103xb.h /^#define RTC_ALRH_RTC_ALR /;" d +RTC_ALRL_RTC_ALR_Msk target/stm32f103xb.h /^#define RTC_ALRL_RTC_ALR_Msk /;" d +RTC_ALRL_RTC_ALR_Pos target/stm32f103xb.h /^#define RTC_ALRL_RTC_ALR_Pos /;" d +RTC_ALRL_RTC_ALR target/stm32f103xb.h /^#define RTC_ALRL_RTC_ALR /;" d +RTC_Alarm_IRQn target/stm32f103xb.h /^ RTC_Alarm_IRQn = 41, \/*!< RTC Alarm through EXTI Line Interrupt /;" e enum:__anon72c4c37e0103 +RTC_BASE target/stm32f103xb.h /^#define RTC_BASE /;" d +RTC_BKP_NUMBER target/stm32f103xb.h /^#define RTC_BKP_NUMBER /;" d +RTC_CNTH_RTC_CNT_Msk target/stm32f103xb.h /^#define RTC_CNTH_RTC_CNT_Msk /;" d +RTC_CNTH_RTC_CNT_Pos target/stm32f103xb.h /^#define RTC_CNTH_RTC_CNT_Pos /;" d +RTC_CNTH_RTC_CNT target/stm32f103xb.h /^#define RTC_CNTH_RTC_CNT /;" d +RTC_CNTL_RTC_CNT_Msk target/stm32f103xb.h /^#define RTC_CNTL_RTC_CNT_Msk /;" d +RTC_CNTL_RTC_CNT_Pos target/stm32f103xb.h /^#define RTC_CNTL_RTC_CNT_Pos /;" d +RTC_CNTL_RTC_CNT target/stm32f103xb.h /^#define RTC_CNTL_RTC_CNT /;" d +RTC_CRH_ALRIE_Msk target/stm32f103xb.h /^#define RTC_CRH_ALRIE_Msk /;" d +RTC_CRH_ALRIE_Pos target/stm32f103xb.h /^#define RTC_CRH_ALRIE_Pos /;" d +RTC_CRH_ALRIE target/stm32f103xb.h /^#define RTC_CRH_ALRIE /;" d +RTC_CRH_OWIE_Msk target/stm32f103xb.h /^#define RTC_CRH_OWIE_Msk /;" d +RTC_CRH_OWIE_Pos target/stm32f103xb.h /^#define RTC_CRH_OWIE_Pos /;" d +RTC_CRH_OWIE target/stm32f103xb.h /^#define RTC_CRH_OWIE /;" d +RTC_CRH_SECIE_Msk target/stm32f103xb.h /^#define RTC_CRH_SECIE_Msk /;" d +RTC_CRH_SECIE_Pos target/stm32f103xb.h /^#define RTC_CRH_SECIE_Pos /;" d +RTC_CRH_SECIE target/stm32f103xb.h /^#define RTC_CRH_SECIE /;" d +RTC_CRL_ALRF_Msk target/stm32f103xb.h /^#define RTC_CRL_ALRF_Msk /;" d +RTC_CRL_ALRF_Pos target/stm32f103xb.h /^#define RTC_CRL_ALRF_Pos /;" d +RTC_CRL_ALRF target/stm32f103xb.h /^#define RTC_CRL_ALRF /;" d +RTC_CRL_CNF_Msk target/stm32f103xb.h /^#define RTC_CRL_CNF_Msk /;" d +RTC_CRL_CNF_Pos target/stm32f103xb.h /^#define RTC_CRL_CNF_Pos /;" d +RTC_CRL_CNF target/stm32f103xb.h /^#define RTC_CRL_CNF /;" d +RTC_CRL_OWF_Msk target/stm32f103xb.h /^#define RTC_CRL_OWF_Msk /;" d +RTC_CRL_OWF_Pos target/stm32f103xb.h /^#define RTC_CRL_OWF_Pos /;" d +RTC_CRL_OWF target/stm32f103xb.h /^#define RTC_CRL_OWF /;" d +RTC_CRL_RSF_Msk target/stm32f103xb.h /^#define RTC_CRL_RSF_Msk /;" d +RTC_CRL_RSF_Pos target/stm32f103xb.h /^#define RTC_CRL_RSF_Pos /;" d +RTC_CRL_RSF target/stm32f103xb.h /^#define RTC_CRL_RSF /;" d +RTC_CRL_RTOFF_Msk target/stm32f103xb.h /^#define RTC_CRL_RTOFF_Msk /;" d +RTC_CRL_RTOFF_Pos target/stm32f103xb.h /^#define RTC_CRL_RTOFF_Pos /;" d +RTC_CRL_RTOFF target/stm32f103xb.h /^#define RTC_CRL_RTOFF /;" d +RTC_CRL_SECF_Msk target/stm32f103xb.h /^#define RTC_CRL_SECF_Msk /;" d +RTC_CRL_SECF_Pos target/stm32f103xb.h /^#define RTC_CRL_SECF_Pos /;" d +RTC_CRL_SECF target/stm32f103xb.h /^#define RTC_CRL_SECF /;" d +RTC_DIVH_RTC_DIV_Msk target/stm32f103xb.h /^#define RTC_DIVH_RTC_DIV_Msk /;" d +RTC_DIVH_RTC_DIV_Pos target/stm32f103xb.h /^#define RTC_DIVH_RTC_DIV_Pos /;" d +RTC_DIVH_RTC_DIV target/stm32f103xb.h /^#define RTC_DIVH_RTC_DIV /;" d +RTC_DIVL_RTC_DIV_Msk target/stm32f103xb.h /^#define RTC_DIVL_RTC_DIV_Msk /;" d +RTC_DIVL_RTC_DIV_Pos target/stm32f103xb.h /^#define RTC_DIVL_RTC_DIV_Pos /;" d +RTC_DIVL_RTC_DIV target/stm32f103xb.h /^#define RTC_DIVL_RTC_DIV /;" d +RTC_IRQn target/stm32f103xb.h /^ RTC_IRQn = 3, \/*!< RTC global Interrupt /;" e enum:__anon72c4c37e0103 +RTC_PRLH_PRL_Msk target/stm32f103xb.h /^#define RTC_PRLH_PRL_Msk /;" d +RTC_PRLH_PRL_Pos target/stm32f103xb.h /^#define RTC_PRLH_PRL_Pos /;" d +RTC_PRLH_PRL target/stm32f103xb.h /^#define RTC_PRLH_PRL /;" d +RTC_PRLL_PRL_Msk target/stm32f103xb.h /^#define RTC_PRLL_PRL_Msk /;" d +RTC_PRLL_PRL_Pos target/stm32f103xb.h /^#define RTC_PRLL_PRL_Pos /;" d +RTC_PRLL_PRL target/stm32f103xb.h /^#define RTC_PRLL_PRL /;" d +RTC_TypeDef target/stm32f103xb.h /^} RTC_TypeDef;$/;" t typeref:struct:__anon72c4c37e1608 +RTC target/stm32f103xb.h /^#define RTC /;" d +RTSR target/stm32f103xb.h /^ __IO uint32_t RTSR;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +RXCRCR target/stm32f103xb.h /^ __IO uint32_t RXCRCR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +SDIO_ARG_CMDARG_Msk target/stm32f103xb.h /^#define SDIO_ARG_CMDARG_Msk /;" d +SDIO_ARG_CMDARG_Pos target/stm32f103xb.h /^#define SDIO_ARG_CMDARG_Pos /;" d +SDIO_ARG_CMDARG target/stm32f103xb.h /^#define SDIO_ARG_CMDARG /;" d +SDIO_BASE target/stm32f103xb.h /^#define SDIO_BASE /;" d +SDIO_CLKCR_BYPASS_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_BYPASS_Msk /;" d +SDIO_CLKCR_BYPASS_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_BYPASS_Pos /;" d +SDIO_CLKCR_BYPASS target/stm32f103xb.h /^#define SDIO_CLKCR_BYPASS /;" d +SDIO_CLKCR_CLKDIV_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_CLKDIV_Msk /;" d +SDIO_CLKCR_CLKDIV_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_CLKDIV_Pos /;" d +SDIO_CLKCR_CLKDIV target/stm32f103xb.h /^#define SDIO_CLKCR_CLKDIV /;" d +SDIO_CLKCR_CLKEN_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_CLKEN_Msk /;" d +SDIO_CLKCR_CLKEN_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_CLKEN_Pos /;" d +SDIO_CLKCR_CLKEN target/stm32f103xb.h /^#define SDIO_CLKCR_CLKEN /;" d +SDIO_CLKCR_HWFC_EN_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_HWFC_EN_Msk /;" d +SDIO_CLKCR_HWFC_EN_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_HWFC_EN_Pos /;" d +SDIO_CLKCR_HWFC_EN target/stm32f103xb.h /^#define SDIO_CLKCR_HWFC_EN /;" d +SDIO_CLKCR_NEGEDGE_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_NEGEDGE_Msk /;" d +SDIO_CLKCR_NEGEDGE_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_NEGEDGE_Pos /;" d +SDIO_CLKCR_NEGEDGE target/stm32f103xb.h /^#define SDIO_CLKCR_NEGEDGE /;" d +SDIO_CLKCR_PWRSAV_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_PWRSAV_Msk /;" d +SDIO_CLKCR_PWRSAV_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_PWRSAV_Pos /;" d +SDIO_CLKCR_PWRSAV target/stm32f103xb.h /^#define SDIO_CLKCR_PWRSAV /;" d +SDIO_CLKCR_WIDBUS_0 target/stm32f103xb.h /^#define SDIO_CLKCR_WIDBUS_0 /;" d +SDIO_CLKCR_WIDBUS_1 target/stm32f103xb.h /^#define SDIO_CLKCR_WIDBUS_1 /;" d +SDIO_CLKCR_WIDBUS_Msk target/stm32f103xb.h /^#define SDIO_CLKCR_WIDBUS_Msk /;" d +SDIO_CLKCR_WIDBUS_Pos target/stm32f103xb.h /^#define SDIO_CLKCR_WIDBUS_Pos /;" d +SDIO_CLKCR_WIDBUS target/stm32f103xb.h /^#define SDIO_CLKCR_WIDBUS /;" d +SDIO_CMD_CEATACMD_Msk target/stm32f103xb.h /^#define SDIO_CMD_CEATACMD_Msk /;" d +SDIO_CMD_CEATACMD_Pos target/stm32f103xb.h /^#define SDIO_CMD_CEATACMD_Pos /;" d +SDIO_CMD_CEATACMD target/stm32f103xb.h /^#define SDIO_CMD_CEATACMD /;" d +SDIO_CMD_CMDINDEX_Msk target/stm32f103xb.h /^#define SDIO_CMD_CMDINDEX_Msk /;" d +SDIO_CMD_CMDINDEX_Pos target/stm32f103xb.h /^#define SDIO_CMD_CMDINDEX_Pos /;" d +SDIO_CMD_CMDINDEX target/stm32f103xb.h /^#define SDIO_CMD_CMDINDEX /;" d +SDIO_CMD_CPSMEN_Msk target/stm32f103xb.h /^#define SDIO_CMD_CPSMEN_Msk /;" d +SDIO_CMD_CPSMEN_Pos target/stm32f103xb.h /^#define SDIO_CMD_CPSMEN_Pos /;" d +SDIO_CMD_CPSMEN target/stm32f103xb.h /^#define SDIO_CMD_CPSMEN /;" d +SDIO_CMD_ENCMDCOMPL_Msk target/stm32f103xb.h /^#define SDIO_CMD_ENCMDCOMPL_Msk /;" d +SDIO_CMD_ENCMDCOMPL_Pos target/stm32f103xb.h /^#define SDIO_CMD_ENCMDCOMPL_Pos /;" d +SDIO_CMD_ENCMDCOMPL target/stm32f103xb.h /^#define SDIO_CMD_ENCMDCOMPL /;" d +SDIO_CMD_NIEN_Msk target/stm32f103xb.h /^#define SDIO_CMD_NIEN_Msk /;" d +SDIO_CMD_NIEN_Pos target/stm32f103xb.h /^#define SDIO_CMD_NIEN_Pos /;" d +SDIO_CMD_NIEN target/stm32f103xb.h /^#define SDIO_CMD_NIEN /;" d +SDIO_CMD_SDIOSUSPEND_Msk target/stm32f103xb.h /^#define SDIO_CMD_SDIOSUSPEND_Msk /;" d +SDIO_CMD_SDIOSUSPEND_Pos target/stm32f103xb.h /^#define SDIO_CMD_SDIOSUSPEND_Pos /;" d +SDIO_CMD_SDIOSUSPEND target/stm32f103xb.h /^#define SDIO_CMD_SDIOSUSPEND /;" d +SDIO_CMD_WAITINT_Msk target/stm32f103xb.h /^#define SDIO_CMD_WAITINT_Msk /;" d +SDIO_CMD_WAITINT_Pos target/stm32f103xb.h /^#define SDIO_CMD_WAITINT_Pos /;" d +SDIO_CMD_WAITINT target/stm32f103xb.h /^#define SDIO_CMD_WAITINT /;" d +SDIO_CMD_WAITPEND_Msk target/stm32f103xb.h /^#define SDIO_CMD_WAITPEND_Msk /;" d +SDIO_CMD_WAITPEND_Pos target/stm32f103xb.h /^#define SDIO_CMD_WAITPEND_Pos /;" d +SDIO_CMD_WAITPEND target/stm32f103xb.h /^#define SDIO_CMD_WAITPEND /;" d +SDIO_CMD_WAITRESP_0 target/stm32f103xb.h /^#define SDIO_CMD_WAITRESP_0 /;" d +SDIO_CMD_WAITRESP_1 target/stm32f103xb.h /^#define SDIO_CMD_WAITRESP_1 /;" d +SDIO_CMD_WAITRESP_Msk target/stm32f103xb.h /^#define SDIO_CMD_WAITRESP_Msk /;" d +SDIO_CMD_WAITRESP_Pos target/stm32f103xb.h /^#define SDIO_CMD_WAITRESP_Pos /;" d +SDIO_CMD_WAITRESP target/stm32f103xb.h /^#define SDIO_CMD_WAITRESP /;" d +SDIO_DCOUNT_DATACOUNT_Msk target/stm32f103xb.h /^#define SDIO_DCOUNT_DATACOUNT_Msk /;" d +SDIO_DCOUNT_DATACOUNT_Pos target/stm32f103xb.h /^#define SDIO_DCOUNT_DATACOUNT_Pos /;" d +SDIO_DCOUNT_DATACOUNT target/stm32f103xb.h /^#define SDIO_DCOUNT_DATACOUNT /;" d +SDIO_DCTRL_DBLOCKSIZE_0 target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_0 /;" d +SDIO_DCTRL_DBLOCKSIZE_1 target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_1 /;" d +SDIO_DCTRL_DBLOCKSIZE_2 target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_2 /;" d +SDIO_DCTRL_DBLOCKSIZE_3 target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_3 /;" d +SDIO_DCTRL_DBLOCKSIZE_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_Msk /;" d +SDIO_DCTRL_DBLOCKSIZE_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE_Pos /;" d +SDIO_DCTRL_DBLOCKSIZE target/stm32f103xb.h /^#define SDIO_DCTRL_DBLOCKSIZE /;" d +SDIO_DCTRL_DMAEN_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_DMAEN_Msk /;" d +SDIO_DCTRL_DMAEN_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_DMAEN_Pos /;" d +SDIO_DCTRL_DMAEN target/stm32f103xb.h /^#define SDIO_DCTRL_DMAEN /;" d +SDIO_DCTRL_DTDIR_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_DTDIR_Msk /;" d +SDIO_DCTRL_DTDIR_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_DTDIR_Pos /;" d +SDIO_DCTRL_DTDIR target/stm32f103xb.h /^#define SDIO_DCTRL_DTDIR /;" d +SDIO_DCTRL_DTEN_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_DTEN_Msk /;" d +SDIO_DCTRL_DTEN_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_DTEN_Pos /;" d +SDIO_DCTRL_DTEN target/stm32f103xb.h /^#define SDIO_DCTRL_DTEN /;" d +SDIO_DCTRL_DTMODE_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_DTMODE_Msk /;" d +SDIO_DCTRL_DTMODE_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_DTMODE_Pos /;" d +SDIO_DCTRL_DTMODE target/stm32f103xb.h /^#define SDIO_DCTRL_DTMODE /;" d +SDIO_DCTRL_RWMOD_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_RWMOD_Msk /;" d +SDIO_DCTRL_RWMOD_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_RWMOD_Pos /;" d +SDIO_DCTRL_RWMOD target/stm32f103xb.h /^#define SDIO_DCTRL_RWMOD /;" d +SDIO_DCTRL_RWSTART_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTART_Msk /;" d +SDIO_DCTRL_RWSTART_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTART_Pos /;" d +SDIO_DCTRL_RWSTART target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTART /;" d +SDIO_DCTRL_RWSTOP_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTOP_Msk /;" d +SDIO_DCTRL_RWSTOP_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTOP_Pos /;" d +SDIO_DCTRL_RWSTOP target/stm32f103xb.h /^#define SDIO_DCTRL_RWSTOP /;" d +SDIO_DCTRL_SDIOEN_Msk target/stm32f103xb.h /^#define SDIO_DCTRL_SDIOEN_Msk /;" d +SDIO_DCTRL_SDIOEN_Pos target/stm32f103xb.h /^#define SDIO_DCTRL_SDIOEN_Pos /;" d +SDIO_DCTRL_SDIOEN target/stm32f103xb.h /^#define SDIO_DCTRL_SDIOEN /;" d +SDIO_DLEN_DATALENGTH_Msk target/stm32f103xb.h /^#define SDIO_DLEN_DATALENGTH_Msk /;" d +SDIO_DLEN_DATALENGTH_Pos target/stm32f103xb.h /^#define SDIO_DLEN_DATALENGTH_Pos /;" d +SDIO_DLEN_DATALENGTH target/stm32f103xb.h /^#define SDIO_DLEN_DATALENGTH /;" d +SDIO_DTIMER_DATATIME_Msk target/stm32f103xb.h /^#define SDIO_DTIMER_DATATIME_Msk /;" d +SDIO_DTIMER_DATATIME_Pos target/stm32f103xb.h /^#define SDIO_DTIMER_DATATIME_Pos /;" d +SDIO_DTIMER_DATATIME target/stm32f103xb.h /^#define SDIO_DTIMER_DATATIME /;" d +SDIO_FIFOCNT_FIFOCOUNT_Msk target/stm32f103xb.h /^#define SDIO_FIFOCNT_FIFOCOUNT_Msk /;" d +SDIO_FIFOCNT_FIFOCOUNT_Pos target/stm32f103xb.h /^#define SDIO_FIFOCNT_FIFOCOUNT_Pos /;" d +SDIO_FIFOCNT_FIFOCOUNT target/stm32f103xb.h /^#define SDIO_FIFOCNT_FIFOCOUNT /;" d +SDIO_FIFO_FIFODATA_Msk target/stm32f103xb.h /^#define SDIO_FIFO_FIFODATA_Msk /;" d +SDIO_FIFO_FIFODATA_Pos target/stm32f103xb.h /^#define SDIO_FIFO_FIFODATA_Pos /;" d +SDIO_FIFO_FIFODATA target/stm32f103xb.h /^#define SDIO_FIFO_FIFODATA /;" d +SDIO_ICR_CCRCFAILC_Msk target/stm32f103xb.h /^#define SDIO_ICR_CCRCFAILC_Msk /;" d +SDIO_ICR_CCRCFAILC_Pos target/stm32f103xb.h /^#define SDIO_ICR_CCRCFAILC_Pos /;" d +SDIO_ICR_CCRCFAILC target/stm32f103xb.h /^#define SDIO_ICR_CCRCFAILC /;" d +SDIO_ICR_CEATAENDC_Msk target/stm32f103xb.h /^#define SDIO_ICR_CEATAENDC_Msk /;" d +SDIO_ICR_CEATAENDC_Pos target/stm32f103xb.h /^#define SDIO_ICR_CEATAENDC_Pos /;" d +SDIO_ICR_CEATAENDC target/stm32f103xb.h /^#define SDIO_ICR_CEATAENDC /;" d +SDIO_ICR_CMDRENDC_Msk target/stm32f103xb.h /^#define SDIO_ICR_CMDRENDC_Msk /;" d +SDIO_ICR_CMDRENDC_Pos target/stm32f103xb.h /^#define SDIO_ICR_CMDRENDC_Pos /;" d +SDIO_ICR_CMDRENDC target/stm32f103xb.h /^#define SDIO_ICR_CMDRENDC /;" d +SDIO_ICR_CMDSENTC_Msk target/stm32f103xb.h /^#define SDIO_ICR_CMDSENTC_Msk /;" d +SDIO_ICR_CMDSENTC_Pos target/stm32f103xb.h /^#define SDIO_ICR_CMDSENTC_Pos /;" d +SDIO_ICR_CMDSENTC target/stm32f103xb.h /^#define SDIO_ICR_CMDSENTC /;" d +SDIO_ICR_CTIMEOUTC_Msk target/stm32f103xb.h /^#define SDIO_ICR_CTIMEOUTC_Msk /;" d +SDIO_ICR_CTIMEOUTC_Pos target/stm32f103xb.h /^#define SDIO_ICR_CTIMEOUTC_Pos /;" d +SDIO_ICR_CTIMEOUTC target/stm32f103xb.h /^#define SDIO_ICR_CTIMEOUTC /;" d +SDIO_ICR_DATAENDC_Msk target/stm32f103xb.h /^#define SDIO_ICR_DATAENDC_Msk /;" d +SDIO_ICR_DATAENDC_Pos target/stm32f103xb.h /^#define SDIO_ICR_DATAENDC_Pos /;" d +SDIO_ICR_DATAENDC target/stm32f103xb.h /^#define SDIO_ICR_DATAENDC /;" d +SDIO_ICR_DBCKENDC_Msk target/stm32f103xb.h /^#define SDIO_ICR_DBCKENDC_Msk /;" d +SDIO_ICR_DBCKENDC_Pos target/stm32f103xb.h /^#define SDIO_ICR_DBCKENDC_Pos /;" d +SDIO_ICR_DBCKENDC target/stm32f103xb.h /^#define SDIO_ICR_DBCKENDC /;" d +SDIO_ICR_DCRCFAILC_Msk target/stm32f103xb.h /^#define SDIO_ICR_DCRCFAILC_Msk /;" d +SDIO_ICR_DCRCFAILC_Pos target/stm32f103xb.h /^#define SDIO_ICR_DCRCFAILC_Pos /;" d +SDIO_ICR_DCRCFAILC target/stm32f103xb.h /^#define SDIO_ICR_DCRCFAILC /;" d +SDIO_ICR_DTIMEOUTC_Msk target/stm32f103xb.h /^#define SDIO_ICR_DTIMEOUTC_Msk /;" d +SDIO_ICR_DTIMEOUTC_Pos target/stm32f103xb.h /^#define SDIO_ICR_DTIMEOUTC_Pos /;" d +SDIO_ICR_DTIMEOUTC target/stm32f103xb.h /^#define SDIO_ICR_DTIMEOUTC /;" d +SDIO_ICR_RXOVERRC_Msk target/stm32f103xb.h /^#define SDIO_ICR_RXOVERRC_Msk /;" d +SDIO_ICR_RXOVERRC_Pos target/stm32f103xb.h /^#define SDIO_ICR_RXOVERRC_Pos /;" d +SDIO_ICR_RXOVERRC target/stm32f103xb.h /^#define SDIO_ICR_RXOVERRC /;" d +SDIO_ICR_SDIOITC_Msk target/stm32f103xb.h /^#define SDIO_ICR_SDIOITC_Msk /;" d +SDIO_ICR_SDIOITC_Pos target/stm32f103xb.h /^#define SDIO_ICR_SDIOITC_Pos /;" d +SDIO_ICR_SDIOITC target/stm32f103xb.h /^#define SDIO_ICR_SDIOITC /;" d +SDIO_ICR_STBITERRC_Msk target/stm32f103xb.h /^#define SDIO_ICR_STBITERRC_Msk /;" d +SDIO_ICR_STBITERRC_Pos target/stm32f103xb.h /^#define SDIO_ICR_STBITERRC_Pos /;" d +SDIO_ICR_STBITERRC target/stm32f103xb.h /^#define SDIO_ICR_STBITERRC /;" d +SDIO_ICR_TXUNDERRC_Msk target/stm32f103xb.h /^#define SDIO_ICR_TXUNDERRC_Msk /;" d +SDIO_ICR_TXUNDERRC_Pos target/stm32f103xb.h /^#define SDIO_ICR_TXUNDERRC_Pos /;" d +SDIO_ICR_TXUNDERRC target/stm32f103xb.h /^#define SDIO_ICR_TXUNDERRC /;" d +SDIO_MASK_CCRCFAILIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CCRCFAILIE_Msk /;" d +SDIO_MASK_CCRCFAILIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CCRCFAILIE_Pos /;" d +SDIO_MASK_CCRCFAILIE target/stm32f103xb.h /^#define SDIO_MASK_CCRCFAILIE /;" d +SDIO_MASK_CEATAENDIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CEATAENDIE_Msk /;" d +SDIO_MASK_CEATAENDIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CEATAENDIE_Pos /;" d +SDIO_MASK_CEATAENDIE target/stm32f103xb.h /^#define SDIO_MASK_CEATAENDIE /;" d +SDIO_MASK_CMDACTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CMDACTIE_Msk /;" d +SDIO_MASK_CMDACTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CMDACTIE_Pos /;" d +SDIO_MASK_CMDACTIE target/stm32f103xb.h /^#define SDIO_MASK_CMDACTIE /;" d +SDIO_MASK_CMDRENDIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CMDRENDIE_Msk /;" d +SDIO_MASK_CMDRENDIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CMDRENDIE_Pos /;" d +SDIO_MASK_CMDRENDIE target/stm32f103xb.h /^#define SDIO_MASK_CMDRENDIE /;" d +SDIO_MASK_CMDSENTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CMDSENTIE_Msk /;" d +SDIO_MASK_CMDSENTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CMDSENTIE_Pos /;" d +SDIO_MASK_CMDSENTIE target/stm32f103xb.h /^#define SDIO_MASK_CMDSENTIE /;" d +SDIO_MASK_CTIMEOUTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_CTIMEOUTIE_Msk /;" d +SDIO_MASK_CTIMEOUTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_CTIMEOUTIE_Pos /;" d +SDIO_MASK_CTIMEOUTIE target/stm32f103xb.h /^#define SDIO_MASK_CTIMEOUTIE /;" d +SDIO_MASK_DATAENDIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_DATAENDIE_Msk /;" d +SDIO_MASK_DATAENDIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_DATAENDIE_Pos /;" d +SDIO_MASK_DATAENDIE target/stm32f103xb.h /^#define SDIO_MASK_DATAENDIE /;" d +SDIO_MASK_DBCKENDIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_DBCKENDIE_Msk /;" d +SDIO_MASK_DBCKENDIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_DBCKENDIE_Pos /;" d +SDIO_MASK_DBCKENDIE target/stm32f103xb.h /^#define SDIO_MASK_DBCKENDIE /;" d +SDIO_MASK_DCRCFAILIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_DCRCFAILIE_Msk /;" d +SDIO_MASK_DCRCFAILIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_DCRCFAILIE_Pos /;" d +SDIO_MASK_DCRCFAILIE target/stm32f103xb.h /^#define SDIO_MASK_DCRCFAILIE /;" d +SDIO_MASK_DTIMEOUTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_DTIMEOUTIE_Msk /;" d +SDIO_MASK_DTIMEOUTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_DTIMEOUTIE_Pos /;" d +SDIO_MASK_DTIMEOUTIE target/stm32f103xb.h /^#define SDIO_MASK_DTIMEOUTIE /;" d +SDIO_MASK_RXACTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXACTIE_Msk /;" d +SDIO_MASK_RXACTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXACTIE_Pos /;" d +SDIO_MASK_RXACTIE target/stm32f103xb.h /^#define SDIO_MASK_RXACTIE /;" d +SDIO_MASK_RXDAVLIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXDAVLIE_Msk /;" d +SDIO_MASK_RXDAVLIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXDAVLIE_Pos /;" d +SDIO_MASK_RXDAVLIE target/stm32f103xb.h /^#define SDIO_MASK_RXDAVLIE /;" d +SDIO_MASK_RXFIFOEIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOEIE_Msk /;" d +SDIO_MASK_RXFIFOEIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOEIE_Pos /;" d +SDIO_MASK_RXFIFOEIE target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOEIE /;" d +SDIO_MASK_RXFIFOFIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOFIE_Msk /;" d +SDIO_MASK_RXFIFOFIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOFIE_Pos /;" d +SDIO_MASK_RXFIFOFIE target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOFIE /;" d +SDIO_MASK_RXFIFOHFIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOHFIE_Msk /;" d +SDIO_MASK_RXFIFOHFIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOHFIE_Pos /;" d +SDIO_MASK_RXFIFOHFIE target/stm32f103xb.h /^#define SDIO_MASK_RXFIFOHFIE /;" d +SDIO_MASK_RXOVERRIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_RXOVERRIE_Msk /;" d +SDIO_MASK_RXOVERRIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_RXOVERRIE_Pos /;" d +SDIO_MASK_RXOVERRIE target/stm32f103xb.h /^#define SDIO_MASK_RXOVERRIE /;" d +SDIO_MASK_SDIOITIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_SDIOITIE_Msk /;" d +SDIO_MASK_SDIOITIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_SDIOITIE_Pos /;" d +SDIO_MASK_SDIOITIE target/stm32f103xb.h /^#define SDIO_MASK_SDIOITIE /;" d +SDIO_MASK_STBITERRIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_STBITERRIE_Msk /;" d +SDIO_MASK_STBITERRIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_STBITERRIE_Pos /;" d +SDIO_MASK_STBITERRIE target/stm32f103xb.h /^#define SDIO_MASK_STBITERRIE /;" d +SDIO_MASK_TXACTIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXACTIE_Msk /;" d +SDIO_MASK_TXACTIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXACTIE_Pos /;" d +SDIO_MASK_TXACTIE target/stm32f103xb.h /^#define SDIO_MASK_TXACTIE /;" d +SDIO_MASK_TXDAVLIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXDAVLIE_Msk /;" d +SDIO_MASK_TXDAVLIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXDAVLIE_Pos /;" d +SDIO_MASK_TXDAVLIE target/stm32f103xb.h /^#define SDIO_MASK_TXDAVLIE /;" d +SDIO_MASK_TXFIFOEIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOEIE_Msk /;" d +SDIO_MASK_TXFIFOEIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOEIE_Pos /;" d +SDIO_MASK_TXFIFOEIE target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOEIE /;" d +SDIO_MASK_TXFIFOFIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOFIE_Msk /;" d +SDIO_MASK_TXFIFOFIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOFIE_Pos /;" d +SDIO_MASK_TXFIFOFIE target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOFIE /;" d +SDIO_MASK_TXFIFOHEIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOHEIE_Msk /;" d +SDIO_MASK_TXFIFOHEIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOHEIE_Pos /;" d +SDIO_MASK_TXFIFOHEIE target/stm32f103xb.h /^#define SDIO_MASK_TXFIFOHEIE /;" d +SDIO_MASK_TXUNDERRIE_Msk target/stm32f103xb.h /^#define SDIO_MASK_TXUNDERRIE_Msk /;" d +SDIO_MASK_TXUNDERRIE_Pos target/stm32f103xb.h /^#define SDIO_MASK_TXUNDERRIE_Pos /;" d +SDIO_MASK_TXUNDERRIE target/stm32f103xb.h /^#define SDIO_MASK_TXUNDERRIE /;" d +SDIO_POWER_PWRCTRL_0 target/stm32f103xb.h /^#define SDIO_POWER_PWRCTRL_0 /;" d +SDIO_POWER_PWRCTRL_1 target/stm32f103xb.h /^#define SDIO_POWER_PWRCTRL_1 /;" d +SDIO_POWER_PWRCTRL_Msk target/stm32f103xb.h /^#define SDIO_POWER_PWRCTRL_Msk /;" d +SDIO_POWER_PWRCTRL_Pos target/stm32f103xb.h /^#define SDIO_POWER_PWRCTRL_Pos /;" d +SDIO_POWER_PWRCTRL target/stm32f103xb.h /^#define SDIO_POWER_PWRCTRL /;" d +SDIO_RESP0_CARDSTATUS0_Msk target/stm32f103xb.h /^#define SDIO_RESP0_CARDSTATUS0_Msk /;" d +SDIO_RESP0_CARDSTATUS0_Pos target/stm32f103xb.h /^#define SDIO_RESP0_CARDSTATUS0_Pos /;" d +SDIO_RESP0_CARDSTATUS0 target/stm32f103xb.h /^#define SDIO_RESP0_CARDSTATUS0 /;" d +SDIO_RESP1_CARDSTATUS1_Msk target/stm32f103xb.h /^#define SDIO_RESP1_CARDSTATUS1_Msk /;" d +SDIO_RESP1_CARDSTATUS1_Pos target/stm32f103xb.h /^#define SDIO_RESP1_CARDSTATUS1_Pos /;" d +SDIO_RESP1_CARDSTATUS1 target/stm32f103xb.h /^#define SDIO_RESP1_CARDSTATUS1 /;" d +SDIO_RESP2_CARDSTATUS2_Msk target/stm32f103xb.h /^#define SDIO_RESP2_CARDSTATUS2_Msk /;" d +SDIO_RESP2_CARDSTATUS2_Pos target/stm32f103xb.h /^#define SDIO_RESP2_CARDSTATUS2_Pos /;" d +SDIO_RESP2_CARDSTATUS2 target/stm32f103xb.h /^#define SDIO_RESP2_CARDSTATUS2 /;" d +SDIO_RESP3_CARDSTATUS3_Msk target/stm32f103xb.h /^#define SDIO_RESP3_CARDSTATUS3_Msk /;" d +SDIO_RESP3_CARDSTATUS3_Pos target/stm32f103xb.h /^#define SDIO_RESP3_CARDSTATUS3_Pos /;" d +SDIO_RESP3_CARDSTATUS3 target/stm32f103xb.h /^#define SDIO_RESP3_CARDSTATUS3 /;" d +SDIO_RESP4_CARDSTATUS4_Msk target/stm32f103xb.h /^#define SDIO_RESP4_CARDSTATUS4_Msk /;" d +SDIO_RESP4_CARDSTATUS4_Pos target/stm32f103xb.h /^#define SDIO_RESP4_CARDSTATUS4_Pos /;" d +SDIO_RESP4_CARDSTATUS4 target/stm32f103xb.h /^#define SDIO_RESP4_CARDSTATUS4 /;" d +SDIO_RESPCMD_RESPCMD_Msk target/stm32f103xb.h /^#define SDIO_RESPCMD_RESPCMD_Msk /;" d +SDIO_RESPCMD_RESPCMD_Pos target/stm32f103xb.h /^#define SDIO_RESPCMD_RESPCMD_Pos /;" d +SDIO_RESPCMD_RESPCMD target/stm32f103xb.h /^#define SDIO_RESPCMD_RESPCMD /;" d +SDIO_STA_CCRCFAIL_Msk target/stm32f103xb.h /^#define SDIO_STA_CCRCFAIL_Msk /;" d +SDIO_STA_CCRCFAIL_Pos target/stm32f103xb.h /^#define SDIO_STA_CCRCFAIL_Pos /;" d +SDIO_STA_CCRCFAIL target/stm32f103xb.h /^#define SDIO_STA_CCRCFAIL /;" d +SDIO_STA_CEATAEND_Msk target/stm32f103xb.h /^#define SDIO_STA_CEATAEND_Msk /;" d +SDIO_STA_CEATAEND_Pos target/stm32f103xb.h /^#define SDIO_STA_CEATAEND_Pos /;" d +SDIO_STA_CEATAEND target/stm32f103xb.h /^#define SDIO_STA_CEATAEND /;" d +SDIO_STA_CMDACT_Msk target/stm32f103xb.h /^#define SDIO_STA_CMDACT_Msk /;" d +SDIO_STA_CMDACT_Pos target/stm32f103xb.h /^#define SDIO_STA_CMDACT_Pos /;" d +SDIO_STA_CMDACT target/stm32f103xb.h /^#define SDIO_STA_CMDACT /;" d +SDIO_STA_CMDREND_Msk target/stm32f103xb.h /^#define SDIO_STA_CMDREND_Msk /;" d +SDIO_STA_CMDREND_Pos target/stm32f103xb.h /^#define SDIO_STA_CMDREND_Pos /;" d +SDIO_STA_CMDREND target/stm32f103xb.h /^#define SDIO_STA_CMDREND /;" d +SDIO_STA_CMDSENT_Msk target/stm32f103xb.h /^#define SDIO_STA_CMDSENT_Msk /;" d +SDIO_STA_CMDSENT_Pos target/stm32f103xb.h /^#define SDIO_STA_CMDSENT_Pos /;" d +SDIO_STA_CMDSENT target/stm32f103xb.h /^#define SDIO_STA_CMDSENT /;" d +SDIO_STA_CTIMEOUT_Msk target/stm32f103xb.h /^#define SDIO_STA_CTIMEOUT_Msk /;" d +SDIO_STA_CTIMEOUT_Pos target/stm32f103xb.h /^#define SDIO_STA_CTIMEOUT_Pos /;" d +SDIO_STA_CTIMEOUT target/stm32f103xb.h /^#define SDIO_STA_CTIMEOUT /;" d +SDIO_STA_DATAEND_Msk target/stm32f103xb.h /^#define SDIO_STA_DATAEND_Msk /;" d +SDIO_STA_DATAEND_Pos target/stm32f103xb.h /^#define SDIO_STA_DATAEND_Pos /;" d +SDIO_STA_DATAEND target/stm32f103xb.h /^#define SDIO_STA_DATAEND /;" d +SDIO_STA_DBCKEND_Msk target/stm32f103xb.h /^#define SDIO_STA_DBCKEND_Msk /;" d +SDIO_STA_DBCKEND_Pos target/stm32f103xb.h /^#define SDIO_STA_DBCKEND_Pos /;" d +SDIO_STA_DBCKEND target/stm32f103xb.h /^#define SDIO_STA_DBCKEND /;" d +SDIO_STA_DCRCFAIL_Msk target/stm32f103xb.h /^#define SDIO_STA_DCRCFAIL_Msk /;" d +SDIO_STA_DCRCFAIL_Pos target/stm32f103xb.h /^#define SDIO_STA_DCRCFAIL_Pos /;" d +SDIO_STA_DCRCFAIL target/stm32f103xb.h /^#define SDIO_STA_DCRCFAIL /;" d +SDIO_STA_DTIMEOUT_Msk target/stm32f103xb.h /^#define SDIO_STA_DTIMEOUT_Msk /;" d +SDIO_STA_DTIMEOUT_Pos target/stm32f103xb.h /^#define SDIO_STA_DTIMEOUT_Pos /;" d +SDIO_STA_DTIMEOUT target/stm32f103xb.h /^#define SDIO_STA_DTIMEOUT /;" d +SDIO_STA_RXACT_Msk target/stm32f103xb.h /^#define SDIO_STA_RXACT_Msk /;" d +SDIO_STA_RXACT_Pos target/stm32f103xb.h /^#define SDIO_STA_RXACT_Pos /;" d +SDIO_STA_RXACT target/stm32f103xb.h /^#define SDIO_STA_RXACT /;" d +SDIO_STA_RXDAVL_Msk target/stm32f103xb.h /^#define SDIO_STA_RXDAVL_Msk /;" d +SDIO_STA_RXDAVL_Pos target/stm32f103xb.h /^#define SDIO_STA_RXDAVL_Pos /;" d +SDIO_STA_RXDAVL target/stm32f103xb.h /^#define SDIO_STA_RXDAVL /;" d +SDIO_STA_RXFIFOE_Msk target/stm32f103xb.h /^#define SDIO_STA_RXFIFOE_Msk /;" d +SDIO_STA_RXFIFOE_Pos target/stm32f103xb.h /^#define SDIO_STA_RXFIFOE_Pos /;" d +SDIO_STA_RXFIFOE target/stm32f103xb.h /^#define SDIO_STA_RXFIFOE /;" d +SDIO_STA_RXFIFOF_Msk target/stm32f103xb.h /^#define SDIO_STA_RXFIFOF_Msk /;" d +SDIO_STA_RXFIFOF_Pos target/stm32f103xb.h /^#define SDIO_STA_RXFIFOF_Pos /;" d +SDIO_STA_RXFIFOF target/stm32f103xb.h /^#define SDIO_STA_RXFIFOF /;" d +SDIO_STA_RXFIFOHF_Msk target/stm32f103xb.h /^#define SDIO_STA_RXFIFOHF_Msk /;" d +SDIO_STA_RXFIFOHF_Pos target/stm32f103xb.h /^#define SDIO_STA_RXFIFOHF_Pos /;" d +SDIO_STA_RXFIFOHF target/stm32f103xb.h /^#define SDIO_STA_RXFIFOHF /;" d +SDIO_STA_RXOVERR_Msk target/stm32f103xb.h /^#define SDIO_STA_RXOVERR_Msk /;" d +SDIO_STA_RXOVERR_Pos target/stm32f103xb.h /^#define SDIO_STA_RXOVERR_Pos /;" d +SDIO_STA_RXOVERR target/stm32f103xb.h /^#define SDIO_STA_RXOVERR /;" d +SDIO_STA_SDIOIT_Msk target/stm32f103xb.h /^#define SDIO_STA_SDIOIT_Msk /;" d +SDIO_STA_SDIOIT_Pos target/stm32f103xb.h /^#define SDIO_STA_SDIOIT_Pos /;" d +SDIO_STA_SDIOIT target/stm32f103xb.h /^#define SDIO_STA_SDIOIT /;" d +SDIO_STA_STBITERR_Msk target/stm32f103xb.h /^#define SDIO_STA_STBITERR_Msk /;" d +SDIO_STA_STBITERR_Pos target/stm32f103xb.h /^#define SDIO_STA_STBITERR_Pos /;" d +SDIO_STA_STBITERR target/stm32f103xb.h /^#define SDIO_STA_STBITERR /;" d +SDIO_STA_TXACT_Msk target/stm32f103xb.h /^#define SDIO_STA_TXACT_Msk /;" d +SDIO_STA_TXACT_Pos target/stm32f103xb.h /^#define SDIO_STA_TXACT_Pos /;" d +SDIO_STA_TXACT target/stm32f103xb.h /^#define SDIO_STA_TXACT /;" d +SDIO_STA_TXDAVL_Msk target/stm32f103xb.h /^#define SDIO_STA_TXDAVL_Msk /;" d +SDIO_STA_TXDAVL_Pos target/stm32f103xb.h /^#define SDIO_STA_TXDAVL_Pos /;" d +SDIO_STA_TXDAVL target/stm32f103xb.h /^#define SDIO_STA_TXDAVL /;" d +SDIO_STA_TXFIFOE_Msk target/stm32f103xb.h /^#define SDIO_STA_TXFIFOE_Msk /;" d +SDIO_STA_TXFIFOE_Pos target/stm32f103xb.h /^#define SDIO_STA_TXFIFOE_Pos /;" d +SDIO_STA_TXFIFOE target/stm32f103xb.h /^#define SDIO_STA_TXFIFOE /;" d +SDIO_STA_TXFIFOF_Msk target/stm32f103xb.h /^#define SDIO_STA_TXFIFOF_Msk /;" d +SDIO_STA_TXFIFOF_Pos target/stm32f103xb.h /^#define SDIO_STA_TXFIFOF_Pos /;" d +SDIO_STA_TXFIFOF target/stm32f103xb.h /^#define SDIO_STA_TXFIFOF /;" d +SDIO_STA_TXFIFOHE_Msk target/stm32f103xb.h /^#define SDIO_STA_TXFIFOHE_Msk /;" d +SDIO_STA_TXFIFOHE_Pos target/stm32f103xb.h /^#define SDIO_STA_TXFIFOHE_Pos /;" d +SDIO_STA_TXFIFOHE target/stm32f103xb.h /^#define SDIO_STA_TXFIFOHE /;" d +SDIO_STA_TXUNDERR_Msk target/stm32f103xb.h /^#define SDIO_STA_TXUNDERR_Msk /;" d +SDIO_STA_TXUNDERR_Pos target/stm32f103xb.h /^#define SDIO_STA_TXUNDERR_Pos /;" d +SDIO_STA_TXUNDERR target/stm32f103xb.h /^#define SDIO_STA_TXUNDERR /;" d +SDIO_TypeDef target/stm32f103xb.h /^} SDIO_TypeDef;$/;" t typeref:struct:__anon72c4c37e1708 +SDIO target/stm32f103xb.h /^#define SDIO /;" d +SET_BIT target/stm32f1xx.h /^#define SET_BIT(/;" d +SET target/stm32f1xx.h /^ SET = !RESET$/;" e enum:__anonbccbea710103 +SMCR target/stm32f103xb.h /^ __IO uint32_t SMCR; \/*!< TIM slave Mode Control register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +SMPR1 target/stm32f103xb.h /^ __IO uint32_t SMPR1;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SMPR2 target/stm32f103xb.h /^ __IO uint32_t SMPR2;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SPI1_BASE target/stm32f103xb.h /^#define SPI1_BASE /;" d +SPI1_IRQ_PRIORITY Untitled Folder/config.h /^#define SPI1_IRQ_PRIORITY /;" d +SPI1_IRQ_PRIORITY config.h /^#define SPI1_IRQ_PRIORITY /;" d +SPI1_IRQn target/stm32f103xb.h /^ SPI1_IRQn = 35, \/*!< SPI1 global Interrupt /;" e enum:__anon72c4c37e0103 +SPI1 target/stm32f103xb.h /^#define SPI1 /;" d +SPI2_BASE target/stm32f103xb.h /^#define SPI2_BASE /;" d +SPI2_IRQ_PRIORITY Untitled Folder/config.h /^#define SPI2_IRQ_PRIORITY /;" d +SPI2_IRQ_PRIORITY config.h /^#define SPI2_IRQ_PRIORITY /;" d +SPI2_IRQn target/stm32f103xb.h /^ SPI2_IRQn = 36, \/*!< SPI2 global Interrupt /;" e enum:__anon72c4c37e0103 +SPI2 target/stm32f103xb.h /^#define SPI2 /;" d +SPI3_IRQ_PRIORITY Untitled Folder/config.h /^#define SPI3_IRQ_PRIORITY /;" d +SPI3_IRQ_PRIORITY config.h /^#define SPI3_IRQ_PRIORITY /;" d +SPI4_IRQ_PRIORITY Untitled Folder/config.h /^#define SPI4_IRQ_PRIORITY /;" d +SPI4_IRQ_PRIORITY config.h /^#define SPI4_IRQ_PRIORITY /;" d +SPI5_IRQ_PRIORITY Untitled Folder/config.h /^#define SPI5_IRQ_PRIORITY /;" d +SPI5_IRQ_PRIORITY config.h /^#define SPI5_IRQ_PRIORITY /;" d +SPI_CR1_BIDIMODE_Msk target/stm32f103xb.h /^#define SPI_CR1_BIDIMODE_Msk /;" d +SPI_CR1_BIDIMODE_Pos target/stm32f103xb.h /^#define SPI_CR1_BIDIMODE_Pos /;" d +SPI_CR1_BIDIMODE target/stm32f103xb.h /^#define SPI_CR1_BIDIMODE /;" d +SPI_CR1_BIDIOE_Msk target/stm32f103xb.h /^#define SPI_CR1_BIDIOE_Msk /;" d +SPI_CR1_BIDIOE_Pos target/stm32f103xb.h /^#define SPI_CR1_BIDIOE_Pos /;" d +SPI_CR1_BIDIOE target/stm32f103xb.h /^#define SPI_CR1_BIDIOE /;" d +SPI_CR1_BR_0 target/stm32f103xb.h /^#define SPI_CR1_BR_0 /;" d +SPI_CR1_BR_1 target/stm32f103xb.h /^#define SPI_CR1_BR_1 /;" d +SPI_CR1_BR_2 target/stm32f103xb.h /^#define SPI_CR1_BR_2 /;" d +SPI_CR1_BR_Msk target/stm32f103xb.h /^#define SPI_CR1_BR_Msk /;" d +SPI_CR1_BR_Pos target/stm32f103xb.h /^#define SPI_CR1_BR_Pos /;" d +SPI_CR1_BR target/stm32f103xb.h /^#define SPI_CR1_BR /;" d +SPI_CR1_CPHA_Msk target/stm32f103xb.h /^#define SPI_CR1_CPHA_Msk /;" d +SPI_CR1_CPHA_Pos target/stm32f103xb.h /^#define SPI_CR1_CPHA_Pos /;" d +SPI_CR1_CPHA target/stm32f103xb.h /^#define SPI_CR1_CPHA /;" d +SPI_CR1_CPOL_Msk target/stm32f103xb.h /^#define SPI_CR1_CPOL_Msk /;" d +SPI_CR1_CPOL_Pos target/stm32f103xb.h /^#define SPI_CR1_CPOL_Pos /;" d +SPI_CR1_CPOL target/stm32f103xb.h /^#define SPI_CR1_CPOL /;" d +SPI_CR1_CRCEN_Msk target/stm32f103xb.h /^#define SPI_CR1_CRCEN_Msk /;" d +SPI_CR1_CRCEN_Pos target/stm32f103xb.h /^#define SPI_CR1_CRCEN_Pos /;" d +SPI_CR1_CRCEN target/stm32f103xb.h /^#define SPI_CR1_CRCEN /;" d +SPI_CR1_CRCNEXT_Msk target/stm32f103xb.h /^#define SPI_CR1_CRCNEXT_Msk /;" d +SPI_CR1_CRCNEXT_Pos target/stm32f103xb.h /^#define SPI_CR1_CRCNEXT_Pos /;" d +SPI_CR1_CRCNEXT target/stm32f103xb.h /^#define SPI_CR1_CRCNEXT /;" d +SPI_CR1_DFF_Msk target/stm32f103xb.h /^#define SPI_CR1_DFF_Msk /;" d +SPI_CR1_DFF_Pos target/stm32f103xb.h /^#define SPI_CR1_DFF_Pos /;" d +SPI_CR1_DFF target/stm32f103xb.h /^#define SPI_CR1_DFF /;" d +SPI_CR1_LSBFIRST_Msk target/stm32f103xb.h /^#define SPI_CR1_LSBFIRST_Msk /;" d +SPI_CR1_LSBFIRST_Pos target/stm32f103xb.h /^#define SPI_CR1_LSBFIRST_Pos /;" d +SPI_CR1_LSBFIRST target/stm32f103xb.h /^#define SPI_CR1_LSBFIRST /;" d +SPI_CR1_MSTR_Msk target/stm32f103xb.h /^#define SPI_CR1_MSTR_Msk /;" d +SPI_CR1_MSTR_Pos target/stm32f103xb.h /^#define SPI_CR1_MSTR_Pos /;" d +SPI_CR1_MSTR target/stm32f103xb.h /^#define SPI_CR1_MSTR /;" d +SPI_CR1_RXONLY_Msk target/stm32f103xb.h /^#define SPI_CR1_RXONLY_Msk /;" d +SPI_CR1_RXONLY_Pos target/stm32f103xb.h /^#define SPI_CR1_RXONLY_Pos /;" d +SPI_CR1_RXONLY target/stm32f103xb.h /^#define SPI_CR1_RXONLY /;" d +SPI_CR1_SPE_Msk target/stm32f103xb.h /^#define SPI_CR1_SPE_Msk /;" d +SPI_CR1_SPE_Pos target/stm32f103xb.h /^#define SPI_CR1_SPE_Pos /;" d +SPI_CR1_SPE target/stm32f103xb.h /^#define SPI_CR1_SPE /;" d +SPI_CR1_SSI_Msk target/stm32f103xb.h /^#define SPI_CR1_SSI_Msk /;" d +SPI_CR1_SSI_Pos target/stm32f103xb.h /^#define SPI_CR1_SSI_Pos /;" d +SPI_CR1_SSI target/stm32f103xb.h /^#define SPI_CR1_SSI /;" d +SPI_CR1_SSM_Msk target/stm32f103xb.h /^#define SPI_CR1_SSM_Msk /;" d +SPI_CR1_SSM_Pos target/stm32f103xb.h /^#define SPI_CR1_SSM_Pos /;" d +SPI_CR1_SSM target/stm32f103xb.h /^#define SPI_CR1_SSM /;" d +SPI_CR2_ERRIE_Msk target/stm32f103xb.h /^#define SPI_CR2_ERRIE_Msk /;" d +SPI_CR2_ERRIE_Pos target/stm32f103xb.h /^#define SPI_CR2_ERRIE_Pos /;" d +SPI_CR2_ERRIE target/stm32f103xb.h /^#define SPI_CR2_ERRIE /;" d +SPI_CR2_RXDMAEN_Msk target/stm32f103xb.h /^#define SPI_CR2_RXDMAEN_Msk /;" d +SPI_CR2_RXDMAEN_Pos target/stm32f103xb.h /^#define SPI_CR2_RXDMAEN_Pos /;" d +SPI_CR2_RXDMAEN target/stm32f103xb.h /^#define SPI_CR2_RXDMAEN /;" d +SPI_CR2_RXNEIE_Msk target/stm32f103xb.h /^#define SPI_CR2_RXNEIE_Msk /;" d +SPI_CR2_RXNEIE_Pos target/stm32f103xb.h /^#define SPI_CR2_RXNEIE_Pos /;" d +SPI_CR2_RXNEIE target/stm32f103xb.h /^#define SPI_CR2_RXNEIE /;" d +SPI_CR2_SSOE_Msk target/stm32f103xb.h /^#define SPI_CR2_SSOE_Msk /;" d +SPI_CR2_SSOE_Pos target/stm32f103xb.h /^#define SPI_CR2_SSOE_Pos /;" d +SPI_CR2_SSOE target/stm32f103xb.h /^#define SPI_CR2_SSOE /;" d +SPI_CR2_TXDMAEN_Msk target/stm32f103xb.h /^#define SPI_CR2_TXDMAEN_Msk /;" d +SPI_CR2_TXDMAEN_Pos target/stm32f103xb.h /^#define SPI_CR2_TXDMAEN_Pos /;" d +SPI_CR2_TXDMAEN target/stm32f103xb.h /^#define SPI_CR2_TXDMAEN /;" d +SPI_CR2_TXEIE_Msk target/stm32f103xb.h /^#define SPI_CR2_TXEIE_Msk /;" d +SPI_CR2_TXEIE_Pos target/stm32f103xb.h /^#define SPI_CR2_TXEIE_Pos /;" d +SPI_CR2_TXEIE target/stm32f103xb.h /^#define SPI_CR2_TXEIE /;" d +SPI_CRCPR_CRCPOLY_Msk target/stm32f103xb.h /^#define SPI_CRCPR_CRCPOLY_Msk /;" d +SPI_CRCPR_CRCPOLY_Pos target/stm32f103xb.h /^#define SPI_CRCPR_CRCPOLY_Pos /;" d +SPI_CRCPR_CRCPOLY target/stm32f103xb.h /^#define SPI_CRCPR_CRCPOLY /;" d +SPI_DR_DR_Msk target/stm32f103xb.h /^#define SPI_DR_DR_Msk /;" d +SPI_DR_DR_Pos target/stm32f103xb.h /^#define SPI_DR_DR_Pos /;" d +SPI_DR_DR target/stm32f103xb.h /^#define SPI_DR_DR /;" d +SPI_I2SCFGR_I2SMOD_Msk target/stm32f103xb.h /^#define SPI_I2SCFGR_I2SMOD_Msk /;" d +SPI_I2SCFGR_I2SMOD_Pos target/stm32f103xb.h /^#define SPI_I2SCFGR_I2SMOD_Pos /;" d +SPI_I2SCFGR_I2SMOD target/stm32f103xb.h /^#define SPI_I2SCFGR_I2SMOD /;" d +SPI_RXCRCR_RXCRC_Msk target/stm32f103xb.h /^#define SPI_RXCRCR_RXCRC_Msk /;" d +SPI_RXCRCR_RXCRC_Pos target/stm32f103xb.h /^#define SPI_RXCRCR_RXCRC_Pos /;" d +SPI_RXCRCR_RXCRC target/stm32f103xb.h /^#define SPI_RXCRCR_RXCRC /;" d +SPI_SR_BSY_Msk target/stm32f103xb.h /^#define SPI_SR_BSY_Msk /;" d +SPI_SR_BSY_Pos target/stm32f103xb.h /^#define SPI_SR_BSY_Pos /;" d +SPI_SR_BSY target/stm32f103xb.h /^#define SPI_SR_BSY /;" d +SPI_SR_CHSIDE_Msk target/stm32f103xb.h /^#define SPI_SR_CHSIDE_Msk /;" d +SPI_SR_CHSIDE_Pos target/stm32f103xb.h /^#define SPI_SR_CHSIDE_Pos /;" d +SPI_SR_CHSIDE target/stm32f103xb.h /^#define SPI_SR_CHSIDE /;" d +SPI_SR_CRCERR_Msk target/stm32f103xb.h /^#define SPI_SR_CRCERR_Msk /;" d +SPI_SR_CRCERR_Pos target/stm32f103xb.h /^#define SPI_SR_CRCERR_Pos /;" d +SPI_SR_CRCERR target/stm32f103xb.h /^#define SPI_SR_CRCERR /;" d +SPI_SR_MODF_Msk target/stm32f103xb.h /^#define SPI_SR_MODF_Msk /;" d +SPI_SR_MODF_Pos target/stm32f103xb.h /^#define SPI_SR_MODF_Pos /;" d +SPI_SR_MODF target/stm32f103xb.h /^#define SPI_SR_MODF /;" d +SPI_SR_OVR_Msk target/stm32f103xb.h /^#define SPI_SR_OVR_Msk /;" d +SPI_SR_OVR_Pos target/stm32f103xb.h /^#define SPI_SR_OVR_Pos /;" d +SPI_SR_OVR target/stm32f103xb.h /^#define SPI_SR_OVR /;" d +SPI_SR_RXNE_Msk target/stm32f103xb.h /^#define SPI_SR_RXNE_Msk /;" d +SPI_SR_RXNE_Pos target/stm32f103xb.h /^#define SPI_SR_RXNE_Pos /;" d +SPI_SR_RXNE target/stm32f103xb.h /^#define SPI_SR_RXNE /;" d +SPI_SR_TXE_Msk target/stm32f103xb.h /^#define SPI_SR_TXE_Msk /;" d +SPI_SR_TXE_Pos target/stm32f103xb.h /^#define SPI_SR_TXE_Pos /;" d +SPI_SR_TXE target/stm32f103xb.h /^#define SPI_SR_TXE /;" d +SPI_SR_UDR_Msk target/stm32f103xb.h /^#define SPI_SR_UDR_Msk /;" d +SPI_SR_UDR_Pos target/stm32f103xb.h /^#define SPI_SR_UDR_Pos /;" d +SPI_SR_UDR target/stm32f103xb.h /^#define SPI_SR_UDR /;" d +SPI_TXCRCR_TXCRC_Msk target/stm32f103xb.h /^#define SPI_TXCRCR_TXCRC_Msk /;" d +SPI_TXCRCR_TXCRC_Pos target/stm32f103xb.h /^#define SPI_TXCRCR_TXCRC_Pos /;" d +SPI_TXCRCR_TXCRC target/stm32f103xb.h /^#define SPI_TXCRCR_TXCRC /;" d +SPI_TypeDef target/stm32f103xb.h /^} SPI_TypeDef;$/;" t typeref:struct:__anon72c4c37e1808 +SQR1 target/stm32f103xb.h /^ __IO uint32_t SQR1;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SQR2 target/stm32f103xb.h /^ __IO uint32_t SQR2;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SQR3 target/stm32f103xb.h /^ __IO uint32_t SQR3;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SR1 target/stm32f103xb.h /^ __IO uint32_t SR1;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +SR2 target/stm32f103xb.h /^ __IO uint32_t SR2;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +SRAM_BASE target/stm32f103xb.h /^#define SRAM_BASE /;" d +SRAM_BB_BASE target/stm32f103xb.h /^#define SRAM_BB_BASE /;" d +SR target/stm32f103xb.h /^ __IO uint32_t SR; \/*!< ADC status register, used for ADC multimode (bits com/;" m struct:__anon72c4c37e0308 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR; \/*!< TIM status register, Address offs/;" m struct:__anon72c4c37e1908 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR; \/*!< Status register, Address offset:/;" m struct:__anon72c4c37e1308 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR; \/*!< USART Status register, Address offset: 0x00 /;" m struct:__anon72c4c37e1a08 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR; \/*!< WWDG Status register, Address offset: 0x08 *\/$/;" m struct:__anon72c4c37e1c08 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR;$/;" m struct:__anon72c4c37e0208 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +SR target/stm32f103xb.h /^ __IO uint32_t SR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +STA target/stm32f103xb.h /^ __I uint32_t STA;$/;" m struct:__anon72c4c37e1708 typeref:typename:__I uint32_t +STM32F103xB target/stm32f1xx.h /^#define STM32F103xB /;" d +STM32F1 target/stm32f1xx.h /^#define STM32F1$/;" d +SUCCESS target/stm32f1xx.h /^ SUCCESS = !ERROR$/;" e enum:__anonbccbea710303 +SVC_Handler Untitled Folder/sys_handlers.c /^void SVC_Handler(void)$/;" f typeref:typename:void +SVCall_IRQn target/stm32f103xb.h /^ SVCall_IRQn = -5, \/*!< 11 Cortex-M3 SV Call Interrupt /;" e enum:__anon72c4c37e0103 +SWIER target/stm32f103xb.h /^ __IO uint32_t SWIER;$/;" m struct:__anon72c4c37e0d08 typeref:typename:__IO uint32_t +SYSCFG_EXTI_PA_MASK drivers/io.c /^#define SYSCFG_EXTI_PA_MASK /;" d file: +SYSCFG_EXTI_PB_MASK drivers/io.c /^#define SYSCFG_EXTI_PB_MASK /;" d file: +SYSCFG_EXTI_PC_MASK drivers/io.c /^#define SYSCFG_EXTI_PC_MASK /;" d file: +SYSCFG_EXTI_PD_MASK drivers/io.c /^#define SYSCFG_EXTI_PD_MASK /;" d file: +SYSCFG_EXTI_PE_MASK drivers/io.c /^#define SYSCFG_EXTI_PE_MASK /;" d file: +SYSCFG_EXTI_PH_MASK drivers/io.c /^#define SYSCFG_EXTI_PH_MASK /;" d file: +SysTick_Handler Untitled Folder/sys_handlers.c /^void SysTick_Handler(void)$/;" f typeref:typename:void +SysTick_IRQn target/stm32f103xb.h /^ SysTick_IRQn = -1, \/*!< 15 Cortex-M3 System Tick Interrupt /;" e enum:__anon72c4c37e0103 +SystemInit target/system_clock.c /^void SystemInit (void)$/;" f typeref:typename:void +TAMPER_IRQn target/stm32f103xb.h /^ TAMPER_IRQn = 2, \/*!< Tamper Interrupt /;" e enum:__anon72c4c37e0103 +TDHR target/stm32f103xb.h /^ __IO uint32_t TDHR;$/;" m struct:__anon72c4c37e0508 typeref:typename:__IO uint32_t +TDLR target/stm32f103xb.h /^ __IO uint32_t TDLR;$/;" m struct:__anon72c4c37e0508 typeref:typename:__IO uint32_t +TDTR target/stm32f103xb.h /^ __IO uint32_t TDTR;$/;" m struct:__anon72c4c37e0508 typeref:typename:__IO uint32_t +TIM10_IRQHandler target/stm32f103xb.h /^#define TIM10_IRQHandler /;" d +TIM10_IRQn target/stm32f103xb.h /^#define TIM10_IRQn /;" d +TIM11_IRQHandler target/stm32f103xb.h /^#define TIM11_IRQHandler /;" d +TIM11_IRQn target/stm32f103xb.h /^#define TIM11_IRQn /;" d +TIM1_BASE target/stm32f103xb.h /^#define TIM1_BASE /;" d +TIM1_BRK_IRQn target/stm32f103xb.h /^ TIM1_BRK_IRQn = 24, \/*!< TIM1 Break Interrupt /;" e enum:__anon72c4c37e0103 +TIM1_BRK_TIM15_IRQHandler target/stm32f103xb.h /^#define TIM1_BRK_TIM15_IRQHandler /;" d +TIM1_BRK_TIM15_IRQn target/stm32f103xb.h /^#define TIM1_BRK_TIM15_IRQn /;" d +TIM1_BRK_TIM9_IRQHandler target/stm32f103xb.h /^#define TIM1_BRK_TIM9_IRQHandler /;" d +TIM1_BRK_TIM9_IRQn target/stm32f103xb.h /^#define TIM1_BRK_TIM9_IRQn /;" d +TIM1_CC_IRQn target/stm32f103xb.h /^ TIM1_CC_IRQn = 27, \/*!< TIM1 Capture Compare Interrupt /;" e enum:__anon72c4c37e0103 +TIM1_TRG_COM_IRQn target/stm32f103xb.h /^ TIM1_TRG_COM_IRQn = 26, \/*!< TIM1 Trigger and Commutation Interrupt /;" e enum:__anon72c4c37e0103 +TIM1_TRG_COM_TIM11_IRQHandler target/stm32f103xb.h /^#define TIM1_TRG_COM_TIM11_IRQHandler /;" d +TIM1_TRG_COM_TIM11_IRQn target/stm32f103xb.h /^#define TIM1_TRG_COM_TIM11_IRQn /;" d +TIM1_TRG_COM_TIM17_IRQHandler target/stm32f103xb.h /^#define TIM1_TRG_COM_TIM17_IRQHandler /;" d +TIM1_TRG_COM_TIM17_IRQn target/stm32f103xb.h /^#define TIM1_TRG_COM_TIM17_IRQn /;" d +TIM1_UP_IRQn target/stm32f103xb.h /^ TIM1_UP_IRQn = 25, \/*!< TIM1 Update Interrupt /;" e enum:__anon72c4c37e0103 +TIM1_UP_TIM10_IRQHandler target/stm32f103xb.h /^#define TIM1_UP_TIM10_IRQHandler /;" d +TIM1_UP_TIM10_IRQn target/stm32f103xb.h /^#define TIM1_UP_TIM10_IRQn /;" d +TIM1_UP_TIM16_IRQHandler target/stm32f103xb.h /^#define TIM1_UP_TIM16_IRQHandler /;" d +TIM1_UP_TIM16_IRQn target/stm32f103xb.h /^#define TIM1_UP_TIM16_IRQn /;" d +TIM1 target/stm32f103xb.h /^#define TIM1 /;" d +TIM2_BASE target/stm32f103xb.h /^#define TIM2_BASE /;" d +TIM2_IRQHandler drivers/timer.c /^void TIM2_IRQHandler() {$/;" f typeref:typename:void +TIM2_IRQ_PRIORITY Untitled Folder/config.h /^#define TIM2_IRQ_PRIORITY /;" d +TIM2_IRQ_PRIORITY config.h /^#define TIM2_IRQ_PRIORITY /;" d +TIM2_IRQn target/stm32f103xb.h /^ TIM2_IRQn = 28, \/*!< TIM2 global Interrupt /;" e enum:__anon72c4c37e0103 +TIM2 target/stm32f103xb.h /^#define TIM2 /;" d +TIM3_BASE target/stm32f103xb.h /^#define TIM3_BASE /;" d +TIM3_IRQHandler drivers/timer.c /^void TIM3_IRQHandler() {$/;" f typeref:typename:void +TIM3_IRQ_PRIORITY Untitled Folder/config.h /^#define TIM3_IRQ_PRIORITY /;" d +TIM3_IRQ_PRIORITY config.h /^#define TIM3_IRQ_PRIORITY /;" d +TIM3_IRQn target/stm32f103xb.h /^ TIM3_IRQn = 29, \/*!< TIM3 global Interrupt /;" e enum:__anon72c4c37e0103 +TIM3 target/stm32f103xb.h /^#define TIM3 /;" d +TIM4_BASE target/stm32f103xb.h /^#define TIM4_BASE /;" d +TIM4_IRQHandler drivers/timer.c /^void TIM4_IRQHandler() {$/;" f typeref:typename:void +TIM4_IRQ_PRIORITY Untitled Folder/config.h /^#define TIM4_IRQ_PRIORITY /;" d +TIM4_IRQ_PRIORITY config.h /^#define TIM4_IRQ_PRIORITY /;" d +TIM4_IRQn target/stm32f103xb.h /^ TIM4_IRQn = 30, \/*!< TIM4 global Interrupt /;" e enum:__anon72c4c37e0103 +TIM4 target/stm32f103xb.h /^#define TIM4 /;" d +TIM5_IRQ_PRIORITY Untitled Folder/config.h /^#define TIM5_IRQ_PRIORITY /;" d +TIM9_IRQHandler target/stm32f103xb.h /^#define TIM9_IRQHandler /;" d +TIM9_IRQn target/stm32f103xb.h /^#define TIM9_IRQn /;" d +TIM_ARR_ARR_Msk target/stm32f103xb.h /^#define TIM_ARR_ARR_Msk /;" d +TIM_ARR_ARR_Pos target/stm32f103xb.h /^#define TIM_ARR_ARR_Pos /;" d +TIM_ARR_ARR target/stm32f103xb.h /^#define TIM_ARR_ARR /;" d +TIM_BDTR_AOE_Msk target/stm32f103xb.h /^#define TIM_BDTR_AOE_Msk /;" d +TIM_BDTR_AOE_Pos target/stm32f103xb.h /^#define TIM_BDTR_AOE_Pos /;" d +TIM_BDTR_AOE target/stm32f103xb.h /^#define TIM_BDTR_AOE /;" d +TIM_BDTR_BKE_Msk target/stm32f103xb.h /^#define TIM_BDTR_BKE_Msk /;" d +TIM_BDTR_BKE_Pos target/stm32f103xb.h /^#define TIM_BDTR_BKE_Pos /;" d +TIM_BDTR_BKE target/stm32f103xb.h /^#define TIM_BDTR_BKE /;" d +TIM_BDTR_BKP_Msk target/stm32f103xb.h /^#define TIM_BDTR_BKP_Msk /;" d +TIM_BDTR_BKP_Pos target/stm32f103xb.h /^#define TIM_BDTR_BKP_Pos /;" d +TIM_BDTR_BKP target/stm32f103xb.h /^#define TIM_BDTR_BKP /;" d +TIM_BDTR_DTG_0 target/stm32f103xb.h /^#define TIM_BDTR_DTG_0 /;" d +TIM_BDTR_DTG_1 target/stm32f103xb.h /^#define TIM_BDTR_DTG_1 /;" d +TIM_BDTR_DTG_2 target/stm32f103xb.h /^#define TIM_BDTR_DTG_2 /;" d +TIM_BDTR_DTG_3 target/stm32f103xb.h /^#define TIM_BDTR_DTG_3 /;" d +TIM_BDTR_DTG_4 target/stm32f103xb.h /^#define TIM_BDTR_DTG_4 /;" d +TIM_BDTR_DTG_5 target/stm32f103xb.h /^#define TIM_BDTR_DTG_5 /;" d +TIM_BDTR_DTG_6 target/stm32f103xb.h /^#define TIM_BDTR_DTG_6 /;" d +TIM_BDTR_DTG_7 target/stm32f103xb.h /^#define TIM_BDTR_DTG_7 /;" d +TIM_BDTR_DTG_Msk target/stm32f103xb.h /^#define TIM_BDTR_DTG_Msk /;" d +TIM_BDTR_DTG_Pos target/stm32f103xb.h /^#define TIM_BDTR_DTG_Pos /;" d +TIM_BDTR_DTG target/stm32f103xb.h /^#define TIM_BDTR_DTG /;" d +TIM_BDTR_LOCK_0 target/stm32f103xb.h /^#define TIM_BDTR_LOCK_0 /;" d +TIM_BDTR_LOCK_1 target/stm32f103xb.h /^#define TIM_BDTR_LOCK_1 /;" d +TIM_BDTR_LOCK_Msk target/stm32f103xb.h /^#define TIM_BDTR_LOCK_Msk /;" d +TIM_BDTR_LOCK_Pos target/stm32f103xb.h /^#define TIM_BDTR_LOCK_Pos /;" d +TIM_BDTR_LOCK target/stm32f103xb.h /^#define TIM_BDTR_LOCK /;" d +TIM_BDTR_MOE_Msk target/stm32f103xb.h /^#define TIM_BDTR_MOE_Msk /;" d +TIM_BDTR_MOE_Pos target/stm32f103xb.h /^#define TIM_BDTR_MOE_Pos /;" d +TIM_BDTR_MOE target/stm32f103xb.h /^#define TIM_BDTR_MOE /;" d +TIM_BDTR_OSSI_Msk target/stm32f103xb.h /^#define TIM_BDTR_OSSI_Msk /;" d +TIM_BDTR_OSSI_Pos target/stm32f103xb.h /^#define TIM_BDTR_OSSI_Pos /;" d +TIM_BDTR_OSSI target/stm32f103xb.h /^#define TIM_BDTR_OSSI /;" d +TIM_BDTR_OSSR_Msk target/stm32f103xb.h /^#define TIM_BDTR_OSSR_Msk /;" d +TIM_BDTR_OSSR_Pos target/stm32f103xb.h /^#define TIM_BDTR_OSSR_Pos /;" d +TIM_BDTR_OSSR target/stm32f103xb.h /^#define TIM_BDTR_OSSR /;" d +TIM_CCER_CC1E_Msk target/stm32f103xb.h /^#define TIM_CCER_CC1E_Msk /;" d +TIM_CCER_CC1E_Pos target/stm32f103xb.h /^#define TIM_CCER_CC1E_Pos /;" d +TIM_CCER_CC1E target/stm32f103xb.h /^#define TIM_CCER_CC1E /;" d +TIM_CCER_CC1NE_Msk target/stm32f103xb.h /^#define TIM_CCER_CC1NE_Msk /;" d +TIM_CCER_CC1NE_Pos target/stm32f103xb.h /^#define TIM_CCER_CC1NE_Pos /;" d +TIM_CCER_CC1NE target/stm32f103xb.h /^#define TIM_CCER_CC1NE /;" d +TIM_CCER_CC1NP_Msk target/stm32f103xb.h /^#define TIM_CCER_CC1NP_Msk /;" d +TIM_CCER_CC1NP_Pos target/stm32f103xb.h /^#define TIM_CCER_CC1NP_Pos /;" d +TIM_CCER_CC1NP target/stm32f103xb.h /^#define TIM_CCER_CC1NP /;" d +TIM_CCER_CC1P_Msk target/stm32f103xb.h /^#define TIM_CCER_CC1P_Msk /;" d +TIM_CCER_CC1P_Pos target/stm32f103xb.h /^#define TIM_CCER_CC1P_Pos /;" d +TIM_CCER_CC1P target/stm32f103xb.h /^#define TIM_CCER_CC1P /;" d +TIM_CCER_CC2E_Msk target/stm32f103xb.h /^#define TIM_CCER_CC2E_Msk /;" d +TIM_CCER_CC2E_Pos target/stm32f103xb.h /^#define TIM_CCER_CC2E_Pos /;" d +TIM_CCER_CC2E target/stm32f103xb.h /^#define TIM_CCER_CC2E /;" d +TIM_CCER_CC2NE_Msk target/stm32f103xb.h /^#define TIM_CCER_CC2NE_Msk /;" d +TIM_CCER_CC2NE_Pos target/stm32f103xb.h /^#define TIM_CCER_CC2NE_Pos /;" d +TIM_CCER_CC2NE target/stm32f103xb.h /^#define TIM_CCER_CC2NE /;" d +TIM_CCER_CC2NP_Msk target/stm32f103xb.h /^#define TIM_CCER_CC2NP_Msk /;" d +TIM_CCER_CC2NP_Pos target/stm32f103xb.h /^#define TIM_CCER_CC2NP_Pos /;" d +TIM_CCER_CC2NP target/stm32f103xb.h /^#define TIM_CCER_CC2NP /;" d +TIM_CCER_CC2P_Msk target/stm32f103xb.h /^#define TIM_CCER_CC2P_Msk /;" d +TIM_CCER_CC2P_Pos target/stm32f103xb.h /^#define TIM_CCER_CC2P_Pos /;" d +TIM_CCER_CC2P target/stm32f103xb.h /^#define TIM_CCER_CC2P /;" d +TIM_CCER_CC3E_Msk target/stm32f103xb.h /^#define TIM_CCER_CC3E_Msk /;" d +TIM_CCER_CC3E_Pos target/stm32f103xb.h /^#define TIM_CCER_CC3E_Pos /;" d +TIM_CCER_CC3E target/stm32f103xb.h /^#define TIM_CCER_CC3E /;" d +TIM_CCER_CC3NE_Msk target/stm32f103xb.h /^#define TIM_CCER_CC3NE_Msk /;" d +TIM_CCER_CC3NE_Pos target/stm32f103xb.h /^#define TIM_CCER_CC3NE_Pos /;" d +TIM_CCER_CC3NE target/stm32f103xb.h /^#define TIM_CCER_CC3NE /;" d +TIM_CCER_CC3NP_Msk target/stm32f103xb.h /^#define TIM_CCER_CC3NP_Msk /;" d +TIM_CCER_CC3NP_Pos target/stm32f103xb.h /^#define TIM_CCER_CC3NP_Pos /;" d +TIM_CCER_CC3NP target/stm32f103xb.h /^#define TIM_CCER_CC3NP /;" d +TIM_CCER_CC3P_Msk target/stm32f103xb.h /^#define TIM_CCER_CC3P_Msk /;" d +TIM_CCER_CC3P_Pos target/stm32f103xb.h /^#define TIM_CCER_CC3P_Pos /;" d +TIM_CCER_CC3P target/stm32f103xb.h /^#define TIM_CCER_CC3P /;" d +TIM_CCER_CC4E_Msk target/stm32f103xb.h /^#define TIM_CCER_CC4E_Msk /;" d +TIM_CCER_CC4E_Pos target/stm32f103xb.h /^#define TIM_CCER_CC4E_Pos /;" d +TIM_CCER_CC4E target/stm32f103xb.h /^#define TIM_CCER_CC4E /;" d +TIM_CCER_CC4P_Msk target/stm32f103xb.h /^#define TIM_CCER_CC4P_Msk /;" d +TIM_CCER_CC4P_Pos target/stm32f103xb.h /^#define TIM_CCER_CC4P_Pos /;" d +TIM_CCER_CC4P target/stm32f103xb.h /^#define TIM_CCER_CC4P /;" d +TIM_CCMR1_CC1S_0 target/stm32f103xb.h /^#define TIM_CCMR1_CC1S_0 /;" d +TIM_CCMR1_CC1S_1 target/stm32f103xb.h /^#define TIM_CCMR1_CC1S_1 /;" d +TIM_CCMR1_CC1S_Msk target/stm32f103xb.h /^#define TIM_CCMR1_CC1S_Msk /;" d +TIM_CCMR1_CC1S_Pos target/stm32f103xb.h /^#define TIM_CCMR1_CC1S_Pos /;" d +TIM_CCMR1_CC1S target/stm32f103xb.h /^#define TIM_CCMR1_CC1S /;" d +TIM_CCMR1_CC2S_0 target/stm32f103xb.h /^#define TIM_CCMR1_CC2S_0 /;" d +TIM_CCMR1_CC2S_1 target/stm32f103xb.h /^#define TIM_CCMR1_CC2S_1 /;" d +TIM_CCMR1_CC2S_Msk target/stm32f103xb.h /^#define TIM_CCMR1_CC2S_Msk /;" d +TIM_CCMR1_CC2S_Pos target/stm32f103xb.h /^#define TIM_CCMR1_CC2S_Pos /;" d +TIM_CCMR1_CC2S target/stm32f103xb.h /^#define TIM_CCMR1_CC2S /;" d +TIM_CCMR1_IC1F_0 target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_0 /;" d +TIM_CCMR1_IC1F_1 target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_1 /;" d +TIM_CCMR1_IC1F_2 target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_2 /;" d +TIM_CCMR1_IC1F_3 target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_3 /;" d +TIM_CCMR1_IC1F_Msk target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_Msk /;" d +TIM_CCMR1_IC1F_Pos target/stm32f103xb.h /^#define TIM_CCMR1_IC1F_Pos /;" d +TIM_CCMR1_IC1F target/stm32f103xb.h /^#define TIM_CCMR1_IC1F /;" d +TIM_CCMR1_IC1PSC_0 target/stm32f103xb.h /^#define TIM_CCMR1_IC1PSC_0 /;" d +TIM_CCMR1_IC1PSC_1 target/stm32f103xb.h /^#define TIM_CCMR1_IC1PSC_1 /;" d +TIM_CCMR1_IC1PSC_Msk target/stm32f103xb.h /^#define TIM_CCMR1_IC1PSC_Msk /;" d +TIM_CCMR1_IC1PSC_Pos target/stm32f103xb.h /^#define TIM_CCMR1_IC1PSC_Pos /;" d +TIM_CCMR1_IC1PSC target/stm32f103xb.h /^#define TIM_CCMR1_IC1PSC /;" d +TIM_CCMR1_IC2F_0 target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_0 /;" d +TIM_CCMR1_IC2F_1 target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_1 /;" d +TIM_CCMR1_IC2F_2 target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_2 /;" d +TIM_CCMR1_IC2F_3 target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_3 /;" d +TIM_CCMR1_IC2F_Msk target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_Msk /;" d +TIM_CCMR1_IC2F_Pos target/stm32f103xb.h /^#define TIM_CCMR1_IC2F_Pos /;" d +TIM_CCMR1_IC2F target/stm32f103xb.h /^#define TIM_CCMR1_IC2F /;" d +TIM_CCMR1_IC2PSC_0 target/stm32f103xb.h /^#define TIM_CCMR1_IC2PSC_0 /;" d +TIM_CCMR1_IC2PSC_1 target/stm32f103xb.h /^#define TIM_CCMR1_IC2PSC_1 /;" d +TIM_CCMR1_IC2PSC_Msk target/stm32f103xb.h /^#define TIM_CCMR1_IC2PSC_Msk /;" d +TIM_CCMR1_IC2PSC_Pos target/stm32f103xb.h /^#define TIM_CCMR1_IC2PSC_Pos /;" d +TIM_CCMR1_IC2PSC target/stm32f103xb.h /^#define TIM_CCMR1_IC2PSC /;" d +TIM_CCMR1_OC1CE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC1CE_Msk /;" d +TIM_CCMR1_OC1CE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC1CE_Pos /;" d +TIM_CCMR1_OC1CE target/stm32f103xb.h /^#define TIM_CCMR1_OC1CE /;" d +TIM_CCMR1_OC1FE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC1FE_Msk /;" d +TIM_CCMR1_OC1FE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC1FE_Pos /;" d +TIM_CCMR1_OC1FE target/stm32f103xb.h /^#define TIM_CCMR1_OC1FE /;" d +TIM_CCMR1_OC1M_0 target/stm32f103xb.h /^#define TIM_CCMR1_OC1M_0 /;" d +TIM_CCMR1_OC1M_1 target/stm32f103xb.h /^#define TIM_CCMR1_OC1M_1 /;" d +TIM_CCMR1_OC1M_2 target/stm32f103xb.h /^#define TIM_CCMR1_OC1M_2 /;" d +TIM_CCMR1_OC1M_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC1M_Msk /;" d +TIM_CCMR1_OC1M_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC1M_Pos /;" d +TIM_CCMR1_OC1M target/stm32f103xb.h /^#define TIM_CCMR1_OC1M /;" d +TIM_CCMR1_OC1PE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC1PE_Msk /;" d +TIM_CCMR1_OC1PE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC1PE_Pos /;" d +TIM_CCMR1_OC1PE target/stm32f103xb.h /^#define TIM_CCMR1_OC1PE /;" d +TIM_CCMR1_OC2CE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC2CE_Msk /;" d +TIM_CCMR1_OC2CE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC2CE_Pos /;" d +TIM_CCMR1_OC2CE target/stm32f103xb.h /^#define TIM_CCMR1_OC2CE /;" d +TIM_CCMR1_OC2FE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC2FE_Msk /;" d +TIM_CCMR1_OC2FE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC2FE_Pos /;" d +TIM_CCMR1_OC2FE target/stm32f103xb.h /^#define TIM_CCMR1_OC2FE /;" d +TIM_CCMR1_OC2M_0 target/stm32f103xb.h /^#define TIM_CCMR1_OC2M_0 /;" d +TIM_CCMR1_OC2M_1 target/stm32f103xb.h /^#define TIM_CCMR1_OC2M_1 /;" d +TIM_CCMR1_OC2M_2 target/stm32f103xb.h /^#define TIM_CCMR1_OC2M_2 /;" d +TIM_CCMR1_OC2M_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC2M_Msk /;" d +TIM_CCMR1_OC2M_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC2M_Pos /;" d +TIM_CCMR1_OC2M target/stm32f103xb.h /^#define TIM_CCMR1_OC2M /;" d +TIM_CCMR1_OC2PE_Msk target/stm32f103xb.h /^#define TIM_CCMR1_OC2PE_Msk /;" d +TIM_CCMR1_OC2PE_Pos target/stm32f103xb.h /^#define TIM_CCMR1_OC2PE_Pos /;" d +TIM_CCMR1_OC2PE target/stm32f103xb.h /^#define TIM_CCMR1_OC2PE /;" d +TIM_CCMR2_CC3S_0 target/stm32f103xb.h /^#define TIM_CCMR2_CC3S_0 /;" d +TIM_CCMR2_CC3S_1 target/stm32f103xb.h /^#define TIM_CCMR2_CC3S_1 /;" d +TIM_CCMR2_CC3S_Msk target/stm32f103xb.h /^#define TIM_CCMR2_CC3S_Msk /;" d +TIM_CCMR2_CC3S_Pos target/stm32f103xb.h /^#define TIM_CCMR2_CC3S_Pos /;" d +TIM_CCMR2_CC3S target/stm32f103xb.h /^#define TIM_CCMR2_CC3S /;" d +TIM_CCMR2_CC4S_0 target/stm32f103xb.h /^#define TIM_CCMR2_CC4S_0 /;" d +TIM_CCMR2_CC4S_1 target/stm32f103xb.h /^#define TIM_CCMR2_CC4S_1 /;" d +TIM_CCMR2_CC4S_Msk target/stm32f103xb.h /^#define TIM_CCMR2_CC4S_Msk /;" d +TIM_CCMR2_CC4S_Pos target/stm32f103xb.h /^#define TIM_CCMR2_CC4S_Pos /;" d +TIM_CCMR2_CC4S target/stm32f103xb.h /^#define TIM_CCMR2_CC4S /;" d +TIM_CCMR2_IC3F_0 target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_0 /;" d +TIM_CCMR2_IC3F_1 target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_1 /;" d +TIM_CCMR2_IC3F_2 target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_2 /;" d +TIM_CCMR2_IC3F_3 target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_3 /;" d +TIM_CCMR2_IC3F_Msk target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_Msk /;" d +TIM_CCMR2_IC3F_Pos target/stm32f103xb.h /^#define TIM_CCMR2_IC3F_Pos /;" d +TIM_CCMR2_IC3F target/stm32f103xb.h /^#define TIM_CCMR2_IC3F /;" d +TIM_CCMR2_IC3PSC_0 target/stm32f103xb.h /^#define TIM_CCMR2_IC3PSC_0 /;" d +TIM_CCMR2_IC3PSC_1 target/stm32f103xb.h /^#define TIM_CCMR2_IC3PSC_1 /;" d +TIM_CCMR2_IC3PSC_Msk target/stm32f103xb.h /^#define TIM_CCMR2_IC3PSC_Msk /;" d +TIM_CCMR2_IC3PSC_Pos target/stm32f103xb.h /^#define TIM_CCMR2_IC3PSC_Pos /;" d +TIM_CCMR2_IC3PSC target/stm32f103xb.h /^#define TIM_CCMR2_IC3PSC /;" d +TIM_CCMR2_IC4F_0 target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_0 /;" d +TIM_CCMR2_IC4F_1 target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_1 /;" d +TIM_CCMR2_IC4F_2 target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_2 /;" d +TIM_CCMR2_IC4F_3 target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_3 /;" d +TIM_CCMR2_IC4F_Msk target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_Msk /;" d +TIM_CCMR2_IC4F_Pos target/stm32f103xb.h /^#define TIM_CCMR2_IC4F_Pos /;" d +TIM_CCMR2_IC4F target/stm32f103xb.h /^#define TIM_CCMR2_IC4F /;" d +TIM_CCMR2_IC4PSC_0 target/stm32f103xb.h /^#define TIM_CCMR2_IC4PSC_0 /;" d +TIM_CCMR2_IC4PSC_1 target/stm32f103xb.h /^#define TIM_CCMR2_IC4PSC_1 /;" d +TIM_CCMR2_IC4PSC_Msk target/stm32f103xb.h /^#define TIM_CCMR2_IC4PSC_Msk /;" d +TIM_CCMR2_IC4PSC_Pos target/stm32f103xb.h /^#define TIM_CCMR2_IC4PSC_Pos /;" d +TIM_CCMR2_IC4PSC target/stm32f103xb.h /^#define TIM_CCMR2_IC4PSC /;" d +TIM_CCMR2_OC3CE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC3CE_Msk /;" d +TIM_CCMR2_OC3CE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC3CE_Pos /;" d +TIM_CCMR2_OC3CE target/stm32f103xb.h /^#define TIM_CCMR2_OC3CE /;" d +TIM_CCMR2_OC3FE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC3FE_Msk /;" d +TIM_CCMR2_OC3FE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC3FE_Pos /;" d +TIM_CCMR2_OC3FE target/stm32f103xb.h /^#define TIM_CCMR2_OC3FE /;" d +TIM_CCMR2_OC3M_0 target/stm32f103xb.h /^#define TIM_CCMR2_OC3M_0 /;" d +TIM_CCMR2_OC3M_1 target/stm32f103xb.h /^#define TIM_CCMR2_OC3M_1 /;" d +TIM_CCMR2_OC3M_2 target/stm32f103xb.h /^#define TIM_CCMR2_OC3M_2 /;" d +TIM_CCMR2_OC3M_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC3M_Msk /;" d +TIM_CCMR2_OC3M_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC3M_Pos /;" d +TIM_CCMR2_OC3M target/stm32f103xb.h /^#define TIM_CCMR2_OC3M /;" d +TIM_CCMR2_OC3PE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC3PE_Msk /;" d +TIM_CCMR2_OC3PE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC3PE_Pos /;" d +TIM_CCMR2_OC3PE target/stm32f103xb.h /^#define TIM_CCMR2_OC3PE /;" d +TIM_CCMR2_OC4CE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC4CE_Msk /;" d +TIM_CCMR2_OC4CE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC4CE_Pos /;" d +TIM_CCMR2_OC4CE target/stm32f103xb.h /^#define TIM_CCMR2_OC4CE /;" d +TIM_CCMR2_OC4FE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC4FE_Msk /;" d +TIM_CCMR2_OC4FE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC4FE_Pos /;" d +TIM_CCMR2_OC4FE target/stm32f103xb.h /^#define TIM_CCMR2_OC4FE /;" d +TIM_CCMR2_OC4M_0 target/stm32f103xb.h /^#define TIM_CCMR2_OC4M_0 /;" d +TIM_CCMR2_OC4M_1 target/stm32f103xb.h /^#define TIM_CCMR2_OC4M_1 /;" d +TIM_CCMR2_OC4M_2 target/stm32f103xb.h /^#define TIM_CCMR2_OC4M_2 /;" d +TIM_CCMR2_OC4M_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC4M_Msk /;" d +TIM_CCMR2_OC4M_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC4M_Pos /;" d +TIM_CCMR2_OC4M target/stm32f103xb.h /^#define TIM_CCMR2_OC4M /;" d +TIM_CCMR2_OC4PE_Msk target/stm32f103xb.h /^#define TIM_CCMR2_OC4PE_Msk /;" d +TIM_CCMR2_OC4PE_Pos target/stm32f103xb.h /^#define TIM_CCMR2_OC4PE_Pos /;" d +TIM_CCMR2_OC4PE target/stm32f103xb.h /^#define TIM_CCMR2_OC4PE /;" d +TIM_CCR1_CCR1_Msk target/stm32f103xb.h /^#define TIM_CCR1_CCR1_Msk /;" d +TIM_CCR1_CCR1_Pos target/stm32f103xb.h /^#define TIM_CCR1_CCR1_Pos /;" d +TIM_CCR1_CCR1 target/stm32f103xb.h /^#define TIM_CCR1_CCR1 /;" d +TIM_CCR2_CCR2_Msk target/stm32f103xb.h /^#define TIM_CCR2_CCR2_Msk /;" d +TIM_CCR2_CCR2_Pos target/stm32f103xb.h /^#define TIM_CCR2_CCR2_Pos /;" d +TIM_CCR2_CCR2 target/stm32f103xb.h /^#define TIM_CCR2_CCR2 /;" d +TIM_CCR3_CCR3_Msk target/stm32f103xb.h /^#define TIM_CCR3_CCR3_Msk /;" d +TIM_CCR3_CCR3_Pos target/stm32f103xb.h /^#define TIM_CCR3_CCR3_Pos /;" d +TIM_CCR3_CCR3 target/stm32f103xb.h /^#define TIM_CCR3_CCR3 /;" d +TIM_CCR4_CCR4_Msk target/stm32f103xb.h /^#define TIM_CCR4_CCR4_Msk /;" d +TIM_CCR4_CCR4_Pos target/stm32f103xb.h /^#define TIM_CCR4_CCR4_Pos /;" d +TIM_CCR4_CCR4 target/stm32f103xb.h /^#define TIM_CCR4_CCR4 /;" d +TIM_CNT_CNT_Msk target/stm32f103xb.h /^#define TIM_CNT_CNT_Msk /;" d +TIM_CNT_CNT_Pos target/stm32f103xb.h /^#define TIM_CNT_CNT_Pos /;" d +TIM_CNT_CNT target/stm32f103xb.h /^#define TIM_CNT_CNT /;" d +TIM_CR1_ARPE_Msk target/stm32f103xb.h /^#define TIM_CR1_ARPE_Msk /;" d +TIM_CR1_ARPE_Pos target/stm32f103xb.h /^#define TIM_CR1_ARPE_Pos /;" d +TIM_CR1_ARPE target/stm32f103xb.h /^#define TIM_CR1_ARPE /;" d +TIM_CR1_CEN_Msk target/stm32f103xb.h /^#define TIM_CR1_CEN_Msk /;" d +TIM_CR1_CEN_Pos target/stm32f103xb.h /^#define TIM_CR1_CEN_Pos /;" d +TIM_CR1_CEN target/stm32f103xb.h /^#define TIM_CR1_CEN /;" d +TIM_CR1_CKD_0 target/stm32f103xb.h /^#define TIM_CR1_CKD_0 /;" d +TIM_CR1_CKD_1 target/stm32f103xb.h /^#define TIM_CR1_CKD_1 /;" d +TIM_CR1_CKD_Msk target/stm32f103xb.h /^#define TIM_CR1_CKD_Msk /;" d +TIM_CR1_CKD_Pos target/stm32f103xb.h /^#define TIM_CR1_CKD_Pos /;" d +TIM_CR1_CKD target/stm32f103xb.h /^#define TIM_CR1_CKD /;" d +TIM_CR1_CMS_0 target/stm32f103xb.h /^#define TIM_CR1_CMS_0 /;" d +TIM_CR1_CMS_1 target/stm32f103xb.h /^#define TIM_CR1_CMS_1 /;" d +TIM_CR1_CMS_Msk target/stm32f103xb.h /^#define TIM_CR1_CMS_Msk /;" d +TIM_CR1_CMS_Pos target/stm32f103xb.h /^#define TIM_CR1_CMS_Pos /;" d +TIM_CR1_CMS target/stm32f103xb.h /^#define TIM_CR1_CMS /;" d +TIM_CR1_DIR_Msk target/stm32f103xb.h /^#define TIM_CR1_DIR_Msk /;" d +TIM_CR1_DIR_Pos target/stm32f103xb.h /^#define TIM_CR1_DIR_Pos /;" d +TIM_CR1_DIR target/stm32f103xb.h /^#define TIM_CR1_DIR /;" d +TIM_CR1_OPM_Msk target/stm32f103xb.h /^#define TIM_CR1_OPM_Msk /;" d +TIM_CR1_OPM_Pos target/stm32f103xb.h /^#define TIM_CR1_OPM_Pos /;" d +TIM_CR1_OPM target/stm32f103xb.h /^#define TIM_CR1_OPM /;" d +TIM_CR1_UDIS_Msk target/stm32f103xb.h /^#define TIM_CR1_UDIS_Msk /;" d +TIM_CR1_UDIS_Pos target/stm32f103xb.h /^#define TIM_CR1_UDIS_Pos /;" d +TIM_CR1_UDIS target/stm32f103xb.h /^#define TIM_CR1_UDIS /;" d +TIM_CR1_URS_Msk target/stm32f103xb.h /^#define TIM_CR1_URS_Msk /;" d +TIM_CR1_URS_Pos target/stm32f103xb.h /^#define TIM_CR1_URS_Pos /;" d +TIM_CR1_URS target/stm32f103xb.h /^#define TIM_CR1_URS /;" d +TIM_CR2_CCDS_Msk target/stm32f103xb.h /^#define TIM_CR2_CCDS_Msk /;" d +TIM_CR2_CCDS_Pos target/stm32f103xb.h /^#define TIM_CR2_CCDS_Pos /;" d +TIM_CR2_CCDS target/stm32f103xb.h /^#define TIM_CR2_CCDS /;" d +TIM_CR2_CCPC_Msk target/stm32f103xb.h /^#define TIM_CR2_CCPC_Msk /;" d +TIM_CR2_CCPC_Pos target/stm32f103xb.h /^#define TIM_CR2_CCPC_Pos /;" d +TIM_CR2_CCPC target/stm32f103xb.h /^#define TIM_CR2_CCPC /;" d +TIM_CR2_CCUS_Msk target/stm32f103xb.h /^#define TIM_CR2_CCUS_Msk /;" d +TIM_CR2_CCUS_Pos target/stm32f103xb.h /^#define TIM_CR2_CCUS_Pos /;" d +TIM_CR2_CCUS target/stm32f103xb.h /^#define TIM_CR2_CCUS /;" d +TIM_CR2_MMS_0 target/stm32f103xb.h /^#define TIM_CR2_MMS_0 /;" d +TIM_CR2_MMS_1 target/stm32f103xb.h /^#define TIM_CR2_MMS_1 /;" d +TIM_CR2_MMS_2 target/stm32f103xb.h /^#define TIM_CR2_MMS_2 /;" d +TIM_CR2_MMS_Msk target/stm32f103xb.h /^#define TIM_CR2_MMS_Msk /;" d +TIM_CR2_MMS_Pos target/stm32f103xb.h /^#define TIM_CR2_MMS_Pos /;" d +TIM_CR2_MMS target/stm32f103xb.h /^#define TIM_CR2_MMS /;" d +TIM_CR2_OIS1N_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS1N_Msk /;" d +TIM_CR2_OIS1N_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS1N_Pos /;" d +TIM_CR2_OIS1N target/stm32f103xb.h /^#define TIM_CR2_OIS1N /;" d +TIM_CR2_OIS1_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS1_Msk /;" d +TIM_CR2_OIS1_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS1_Pos /;" d +TIM_CR2_OIS1 target/stm32f103xb.h /^#define TIM_CR2_OIS1 /;" d +TIM_CR2_OIS2N_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS2N_Msk /;" d +TIM_CR2_OIS2N_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS2N_Pos /;" d +TIM_CR2_OIS2N target/stm32f103xb.h /^#define TIM_CR2_OIS2N /;" d +TIM_CR2_OIS2_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS2_Msk /;" d +TIM_CR2_OIS2_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS2_Pos /;" d +TIM_CR2_OIS2 target/stm32f103xb.h /^#define TIM_CR2_OIS2 /;" d +TIM_CR2_OIS3N_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS3N_Msk /;" d +TIM_CR2_OIS3N_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS3N_Pos /;" d +TIM_CR2_OIS3N target/stm32f103xb.h /^#define TIM_CR2_OIS3N /;" d +TIM_CR2_OIS3_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS3_Msk /;" d +TIM_CR2_OIS3_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS3_Pos /;" d +TIM_CR2_OIS3 target/stm32f103xb.h /^#define TIM_CR2_OIS3 /;" d +TIM_CR2_OIS4_Msk target/stm32f103xb.h /^#define TIM_CR2_OIS4_Msk /;" d +TIM_CR2_OIS4_Pos target/stm32f103xb.h /^#define TIM_CR2_OIS4_Pos /;" d +TIM_CR2_OIS4 target/stm32f103xb.h /^#define TIM_CR2_OIS4 /;" d +TIM_CR2_TI1S_Msk target/stm32f103xb.h /^#define TIM_CR2_TI1S_Msk /;" d +TIM_CR2_TI1S_Pos target/stm32f103xb.h /^#define TIM_CR2_TI1S_Pos /;" d +TIM_CR2_TI1S target/stm32f103xb.h /^#define TIM_CR2_TI1S /;" d +TIM_DCR_DBA_0 target/stm32f103xb.h /^#define TIM_DCR_DBA_0 /;" d +TIM_DCR_DBA_1 target/stm32f103xb.h /^#define TIM_DCR_DBA_1 /;" d +TIM_DCR_DBA_2 target/stm32f103xb.h /^#define TIM_DCR_DBA_2 /;" d +TIM_DCR_DBA_3 target/stm32f103xb.h /^#define TIM_DCR_DBA_3 /;" d +TIM_DCR_DBA_4 target/stm32f103xb.h /^#define TIM_DCR_DBA_4 /;" d +TIM_DCR_DBA_Msk target/stm32f103xb.h /^#define TIM_DCR_DBA_Msk /;" d +TIM_DCR_DBA_Pos target/stm32f103xb.h /^#define TIM_DCR_DBA_Pos /;" d +TIM_DCR_DBA target/stm32f103xb.h /^#define TIM_DCR_DBA /;" d +TIM_DCR_DBL_0 target/stm32f103xb.h /^#define TIM_DCR_DBL_0 /;" d +TIM_DCR_DBL_1 target/stm32f103xb.h /^#define TIM_DCR_DBL_1 /;" d +TIM_DCR_DBL_2 target/stm32f103xb.h /^#define TIM_DCR_DBL_2 /;" d +TIM_DCR_DBL_3 target/stm32f103xb.h /^#define TIM_DCR_DBL_3 /;" d +TIM_DCR_DBL_4 target/stm32f103xb.h /^#define TIM_DCR_DBL_4 /;" d +TIM_DCR_DBL_Msk target/stm32f103xb.h /^#define TIM_DCR_DBL_Msk /;" d +TIM_DCR_DBL_Pos target/stm32f103xb.h /^#define TIM_DCR_DBL_Pos /;" d +TIM_DCR_DBL target/stm32f103xb.h /^#define TIM_DCR_DBL /;" d +TIM_DIER_BIE_Msk target/stm32f103xb.h /^#define TIM_DIER_BIE_Msk /;" d +TIM_DIER_BIE_Pos target/stm32f103xb.h /^#define TIM_DIER_BIE_Pos /;" d +TIM_DIER_BIE target/stm32f103xb.h /^#define TIM_DIER_BIE /;" d +TIM_DIER_CC1DE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC1DE_Msk /;" d +TIM_DIER_CC1DE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC1DE_Pos /;" d +TIM_DIER_CC1DE target/stm32f103xb.h /^#define TIM_DIER_CC1DE /;" d +TIM_DIER_CC1IE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC1IE_Msk /;" d +TIM_DIER_CC1IE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC1IE_Pos /;" d +TIM_DIER_CC1IE target/stm32f103xb.h /^#define TIM_DIER_CC1IE /;" d +TIM_DIER_CC2DE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC2DE_Msk /;" d +TIM_DIER_CC2DE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC2DE_Pos /;" d +TIM_DIER_CC2DE target/stm32f103xb.h /^#define TIM_DIER_CC2DE /;" d +TIM_DIER_CC2IE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC2IE_Msk /;" d +TIM_DIER_CC2IE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC2IE_Pos /;" d +TIM_DIER_CC2IE target/stm32f103xb.h /^#define TIM_DIER_CC2IE /;" d +TIM_DIER_CC3DE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC3DE_Msk /;" d +TIM_DIER_CC3DE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC3DE_Pos /;" d +TIM_DIER_CC3DE target/stm32f103xb.h /^#define TIM_DIER_CC3DE /;" d +TIM_DIER_CC3IE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC3IE_Msk /;" d +TIM_DIER_CC3IE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC3IE_Pos /;" d +TIM_DIER_CC3IE target/stm32f103xb.h /^#define TIM_DIER_CC3IE /;" d +TIM_DIER_CC4DE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC4DE_Msk /;" d +TIM_DIER_CC4DE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC4DE_Pos /;" d +TIM_DIER_CC4DE target/stm32f103xb.h /^#define TIM_DIER_CC4DE /;" d +TIM_DIER_CC4IE_Msk target/stm32f103xb.h /^#define TIM_DIER_CC4IE_Msk /;" d +TIM_DIER_CC4IE_Pos target/stm32f103xb.h /^#define TIM_DIER_CC4IE_Pos /;" d +TIM_DIER_CC4IE target/stm32f103xb.h /^#define TIM_DIER_CC4IE /;" d +TIM_DIER_COMDE_Msk target/stm32f103xb.h /^#define TIM_DIER_COMDE_Msk /;" d +TIM_DIER_COMDE_Pos target/stm32f103xb.h /^#define TIM_DIER_COMDE_Pos /;" d +TIM_DIER_COMDE target/stm32f103xb.h /^#define TIM_DIER_COMDE /;" d +TIM_DIER_COMIE_Msk target/stm32f103xb.h /^#define TIM_DIER_COMIE_Msk /;" d +TIM_DIER_COMIE_Pos target/stm32f103xb.h /^#define TIM_DIER_COMIE_Pos /;" d +TIM_DIER_COMIE target/stm32f103xb.h /^#define TIM_DIER_COMIE /;" d +TIM_DIER_TDE_Msk target/stm32f103xb.h /^#define TIM_DIER_TDE_Msk /;" d +TIM_DIER_TDE_Pos target/stm32f103xb.h /^#define TIM_DIER_TDE_Pos /;" d +TIM_DIER_TDE target/stm32f103xb.h /^#define TIM_DIER_TDE /;" d +TIM_DIER_TIE_Msk target/stm32f103xb.h /^#define TIM_DIER_TIE_Msk /;" d +TIM_DIER_TIE_Pos target/stm32f103xb.h /^#define TIM_DIER_TIE_Pos /;" d +TIM_DIER_TIE target/stm32f103xb.h /^#define TIM_DIER_TIE /;" d +TIM_DIER_UDE_Msk target/stm32f103xb.h /^#define TIM_DIER_UDE_Msk /;" d +TIM_DIER_UDE_Pos target/stm32f103xb.h /^#define TIM_DIER_UDE_Pos /;" d +TIM_DIER_UDE target/stm32f103xb.h /^#define TIM_DIER_UDE /;" d +TIM_DIER_UIE_Msk target/stm32f103xb.h /^#define TIM_DIER_UIE_Msk /;" d +TIM_DIER_UIE_Pos target/stm32f103xb.h /^#define TIM_DIER_UIE_Pos /;" d +TIM_DIER_UIE target/stm32f103xb.h /^#define TIM_DIER_UIE /;" d +TIM_DMAR_DMAB_Msk target/stm32f103xb.h /^#define TIM_DMAR_DMAB_Msk /;" d +TIM_DMAR_DMAB_Pos target/stm32f103xb.h /^#define TIM_DMAR_DMAB_Pos /;" d +TIM_DMAR_DMAB target/stm32f103xb.h /^#define TIM_DMAR_DMAB /;" d +TIM_EGR_BG_Msk target/stm32f103xb.h /^#define TIM_EGR_BG_Msk /;" d +TIM_EGR_BG_Pos target/stm32f103xb.h /^#define TIM_EGR_BG_Pos /;" d +TIM_EGR_BG target/stm32f103xb.h /^#define TIM_EGR_BG /;" d +TIM_EGR_CC1G_Msk target/stm32f103xb.h /^#define TIM_EGR_CC1G_Msk /;" d +TIM_EGR_CC1G_Pos target/stm32f103xb.h /^#define TIM_EGR_CC1G_Pos /;" d +TIM_EGR_CC1G target/stm32f103xb.h /^#define TIM_EGR_CC1G /;" d +TIM_EGR_CC2G_Msk target/stm32f103xb.h /^#define TIM_EGR_CC2G_Msk /;" d +TIM_EGR_CC2G_Pos target/stm32f103xb.h /^#define TIM_EGR_CC2G_Pos /;" d +TIM_EGR_CC2G target/stm32f103xb.h /^#define TIM_EGR_CC2G /;" d +TIM_EGR_CC3G_Msk target/stm32f103xb.h /^#define TIM_EGR_CC3G_Msk /;" d +TIM_EGR_CC3G_Pos target/stm32f103xb.h /^#define TIM_EGR_CC3G_Pos /;" d +TIM_EGR_CC3G target/stm32f103xb.h /^#define TIM_EGR_CC3G /;" d +TIM_EGR_CC4G_Msk target/stm32f103xb.h /^#define TIM_EGR_CC4G_Msk /;" d +TIM_EGR_CC4G_Pos target/stm32f103xb.h /^#define TIM_EGR_CC4G_Pos /;" d +TIM_EGR_CC4G target/stm32f103xb.h /^#define TIM_EGR_CC4G /;" d +TIM_EGR_COMG_Msk target/stm32f103xb.h /^#define TIM_EGR_COMG_Msk /;" d +TIM_EGR_COMG_Pos target/stm32f103xb.h /^#define TIM_EGR_COMG_Pos /;" d +TIM_EGR_COMG target/stm32f103xb.h /^#define TIM_EGR_COMG /;" d +TIM_EGR_TG_Msk target/stm32f103xb.h /^#define TIM_EGR_TG_Msk /;" d +TIM_EGR_TG_Pos target/stm32f103xb.h /^#define TIM_EGR_TG_Pos /;" d +TIM_EGR_TG target/stm32f103xb.h /^#define TIM_EGR_TG /;" d +TIM_EGR_UG_Msk target/stm32f103xb.h /^#define TIM_EGR_UG_Msk /;" d +TIM_EGR_UG_Pos target/stm32f103xb.h /^#define TIM_EGR_UG_Pos /;" d +TIM_EGR_UG target/stm32f103xb.h /^#define TIM_EGR_UG /;" d +TIM_PSC_PSC_Msk target/stm32f103xb.h /^#define TIM_PSC_PSC_Msk /;" d +TIM_PSC_PSC_Pos target/stm32f103xb.h /^#define TIM_PSC_PSC_Pos /;" d +TIM_PSC_PSC target/stm32f103xb.h /^#define TIM_PSC_PSC /;" d +TIM_RCR_REP_Msk target/stm32f103xb.h /^#define TIM_RCR_REP_Msk /;" d +TIM_RCR_REP_Pos target/stm32f103xb.h /^#define TIM_RCR_REP_Pos /;" d +TIM_RCR_REP target/stm32f103xb.h /^#define TIM_RCR_REP /;" d +TIM_SMCR_ECE_Msk target/stm32f103xb.h /^#define TIM_SMCR_ECE_Msk /;" d +TIM_SMCR_ECE_Pos target/stm32f103xb.h /^#define TIM_SMCR_ECE_Pos /;" d +TIM_SMCR_ECE target/stm32f103xb.h /^#define TIM_SMCR_ECE /;" d +TIM_SMCR_ETF_0 target/stm32f103xb.h /^#define TIM_SMCR_ETF_0 /;" d +TIM_SMCR_ETF_1 target/stm32f103xb.h /^#define TIM_SMCR_ETF_1 /;" d +TIM_SMCR_ETF_2 target/stm32f103xb.h /^#define TIM_SMCR_ETF_2 /;" d +TIM_SMCR_ETF_3 target/stm32f103xb.h /^#define TIM_SMCR_ETF_3 /;" d +TIM_SMCR_ETF_Msk target/stm32f103xb.h /^#define TIM_SMCR_ETF_Msk /;" d +TIM_SMCR_ETF_Pos target/stm32f103xb.h /^#define TIM_SMCR_ETF_Pos /;" d +TIM_SMCR_ETF target/stm32f103xb.h /^#define TIM_SMCR_ETF /;" d +TIM_SMCR_ETPS_0 target/stm32f103xb.h /^#define TIM_SMCR_ETPS_0 /;" d +TIM_SMCR_ETPS_1 target/stm32f103xb.h /^#define TIM_SMCR_ETPS_1 /;" d +TIM_SMCR_ETPS_Msk target/stm32f103xb.h /^#define TIM_SMCR_ETPS_Msk /;" d +TIM_SMCR_ETPS_Pos target/stm32f103xb.h /^#define TIM_SMCR_ETPS_Pos /;" d +TIM_SMCR_ETPS target/stm32f103xb.h /^#define TIM_SMCR_ETPS /;" d +TIM_SMCR_ETP_Msk target/stm32f103xb.h /^#define TIM_SMCR_ETP_Msk /;" d +TIM_SMCR_ETP_Pos target/stm32f103xb.h /^#define TIM_SMCR_ETP_Pos /;" d +TIM_SMCR_ETP target/stm32f103xb.h /^#define TIM_SMCR_ETP /;" d +TIM_SMCR_MSM_Msk target/stm32f103xb.h /^#define TIM_SMCR_MSM_Msk /;" d +TIM_SMCR_MSM_Pos target/stm32f103xb.h /^#define TIM_SMCR_MSM_Pos /;" d +TIM_SMCR_MSM target/stm32f103xb.h /^#define TIM_SMCR_MSM /;" d +TIM_SMCR_SMS_0 target/stm32f103xb.h /^#define TIM_SMCR_SMS_0 /;" d +TIM_SMCR_SMS_1 target/stm32f103xb.h /^#define TIM_SMCR_SMS_1 /;" d +TIM_SMCR_SMS_2 target/stm32f103xb.h /^#define TIM_SMCR_SMS_2 /;" d +TIM_SMCR_SMS_Msk target/stm32f103xb.h /^#define TIM_SMCR_SMS_Msk /;" d +TIM_SMCR_SMS_Pos target/stm32f103xb.h /^#define TIM_SMCR_SMS_Pos /;" d +TIM_SMCR_SMS target/stm32f103xb.h /^#define TIM_SMCR_SMS /;" d +TIM_SMCR_TS_0 target/stm32f103xb.h /^#define TIM_SMCR_TS_0 /;" d +TIM_SMCR_TS_1 target/stm32f103xb.h /^#define TIM_SMCR_TS_1 /;" d +TIM_SMCR_TS_2 target/stm32f103xb.h /^#define TIM_SMCR_TS_2 /;" d +TIM_SMCR_TS_Msk target/stm32f103xb.h /^#define TIM_SMCR_TS_Msk /;" d +TIM_SMCR_TS_Pos target/stm32f103xb.h /^#define TIM_SMCR_TS_Pos /;" d +TIM_SMCR_TS target/stm32f103xb.h /^#define TIM_SMCR_TS /;" d +TIM_SR_BIF_Msk target/stm32f103xb.h /^#define TIM_SR_BIF_Msk /;" d +TIM_SR_BIF_Pos target/stm32f103xb.h /^#define TIM_SR_BIF_Pos /;" d +TIM_SR_BIF target/stm32f103xb.h /^#define TIM_SR_BIF /;" d +TIM_SR_CC1IF_Msk target/stm32f103xb.h /^#define TIM_SR_CC1IF_Msk /;" d +TIM_SR_CC1IF_Pos target/stm32f103xb.h /^#define TIM_SR_CC1IF_Pos /;" d +TIM_SR_CC1IF target/stm32f103xb.h /^#define TIM_SR_CC1IF /;" d +TIM_SR_CC1OF_Msk target/stm32f103xb.h /^#define TIM_SR_CC1OF_Msk /;" d +TIM_SR_CC1OF_Pos target/stm32f103xb.h /^#define TIM_SR_CC1OF_Pos /;" d +TIM_SR_CC1OF target/stm32f103xb.h /^#define TIM_SR_CC1OF /;" d +TIM_SR_CC2IF_Msk target/stm32f103xb.h /^#define TIM_SR_CC2IF_Msk /;" d +TIM_SR_CC2IF_Pos target/stm32f103xb.h /^#define TIM_SR_CC2IF_Pos /;" d +TIM_SR_CC2IF target/stm32f103xb.h /^#define TIM_SR_CC2IF /;" d +TIM_SR_CC2OF_Msk target/stm32f103xb.h /^#define TIM_SR_CC2OF_Msk /;" d +TIM_SR_CC2OF_Pos target/stm32f103xb.h /^#define TIM_SR_CC2OF_Pos /;" d +TIM_SR_CC2OF target/stm32f103xb.h /^#define TIM_SR_CC2OF /;" d +TIM_SR_CC3IF_Msk target/stm32f103xb.h /^#define TIM_SR_CC3IF_Msk /;" d +TIM_SR_CC3IF_Pos target/stm32f103xb.h /^#define TIM_SR_CC3IF_Pos /;" d +TIM_SR_CC3IF target/stm32f103xb.h /^#define TIM_SR_CC3IF /;" d +TIM_SR_CC3OF_Msk target/stm32f103xb.h /^#define TIM_SR_CC3OF_Msk /;" d +TIM_SR_CC3OF_Pos target/stm32f103xb.h /^#define TIM_SR_CC3OF_Pos /;" d +TIM_SR_CC3OF target/stm32f103xb.h /^#define TIM_SR_CC3OF /;" d +TIM_SR_CC4IF_Msk target/stm32f103xb.h /^#define TIM_SR_CC4IF_Msk /;" d +TIM_SR_CC4IF_Pos target/stm32f103xb.h /^#define TIM_SR_CC4IF_Pos /;" d +TIM_SR_CC4IF target/stm32f103xb.h /^#define TIM_SR_CC4IF /;" d +TIM_SR_CC4OF_Msk target/stm32f103xb.h /^#define TIM_SR_CC4OF_Msk /;" d +TIM_SR_CC4OF_Pos target/stm32f103xb.h /^#define TIM_SR_CC4OF_Pos /;" d +TIM_SR_CC4OF target/stm32f103xb.h /^#define TIM_SR_CC4OF /;" d +TIM_SR_COMIF_Msk target/stm32f103xb.h /^#define TIM_SR_COMIF_Msk /;" d +TIM_SR_COMIF_Pos target/stm32f103xb.h /^#define TIM_SR_COMIF_Pos /;" d +TIM_SR_COMIF target/stm32f103xb.h /^#define TIM_SR_COMIF /;" d +TIM_SR_TIF_Msk target/stm32f103xb.h /^#define TIM_SR_TIF_Msk /;" d +TIM_SR_TIF_Pos target/stm32f103xb.h /^#define TIM_SR_TIF_Pos /;" d +TIM_SR_TIF target/stm32f103xb.h /^#define TIM_SR_TIF /;" d +TIM_SR_UIF_Msk target/stm32f103xb.h /^#define TIM_SR_UIF_Msk /;" d +TIM_SR_UIF_Pos target/stm32f103xb.h /^#define TIM_SR_UIF_Pos /;" d +TIM_SR_UIF target/stm32f103xb.h /^#define TIM_SR_UIF /;" d +TIM_TypeDef target/stm32f103xb.h /^}TIM_TypeDef;$/;" t typeref:struct:__anon72c4c37e1908 +TIR target/stm32f103xb.h /^ __IO uint32_t TIR;$/;" m struct:__anon72c4c37e0508 typeref:typename:__IO uint32_t +TRISE target/stm32f103xb.h /^ __IO uint32_t TRISE;$/;" m struct:__anon72c4c37e1208 typeref:typename:__IO uint32_t +TSR target/stm32f103xb.h /^ __IO uint32_t TSR;$/;" m struct:__anon72c4c37e0808 typeref:typename:__IO uint32_t +TXCRCR target/stm32f103xb.h /^ __IO uint32_t TXCRCR;$/;" m struct:__anon72c4c37e1808 typeref:typename:__IO uint32_t +UID_BASE target/stm32f103xb.h /^#define UID_BASE /;" d +USART1_BASE target/stm32f103xb.h /^#define USART1_BASE /;" d +USART1_IRQ_PRIORITY Untitled Folder/config.h /^#define USART1_IRQ_PRIORITY /;" d +USART1_IRQ_PRIORITY config.h /^#define USART1_IRQ_PRIORITY /;" d +USART1_IRQn target/stm32f103xb.h /^ USART1_IRQn = 37, \/*!< USART1 global Interrupt /;" e enum:__anon72c4c37e0103 +USART1 target/stm32f103xb.h /^#define USART1 /;" d +USART2_BASE target/stm32f103xb.h /^#define USART2_BASE /;" d +USART2_IRQ_PRIORITY Untitled Folder/config.h /^#define USART2_IRQ_PRIORITY /;" d +USART2_IRQ_PRIORITY config.h /^#define USART2_IRQ_PRIORITY /;" d +USART2_IRQn target/stm32f103xb.h /^ USART2_IRQn = 38, \/*!< USART2 global Interrupt /;" e enum:__anon72c4c37e0103 +USART2 target/stm32f103xb.h /^#define USART2 /;" d +USART3_BASE target/stm32f103xb.h /^#define USART3_BASE /;" d +USART3_IRQn target/stm32f103xb.h /^ USART3_IRQn = 39, \/*!< USART3 global Interrupt /;" e enum:__anon72c4c37e0103 +USART3 target/stm32f103xb.h /^#define USART3 /;" d +USART6_IRQ_PRIORITY Untitled Folder/config.h /^#define USART6_IRQ_PRIORITY /;" d +USART6_IRQ_PRIORITY config.h /^#define USART6_IRQ_PRIORITY /;" d +USART_BRR_DIV_Fraction_Msk target/stm32f103xb.h /^#define USART_BRR_DIV_Fraction_Msk /;" d +USART_BRR_DIV_Fraction_Pos target/stm32f103xb.h /^#define USART_BRR_DIV_Fraction_Pos /;" d +USART_BRR_DIV_Fraction target/stm32f103xb.h /^#define USART_BRR_DIV_Fraction /;" d +USART_BRR_DIV_Mantissa_Msk target/stm32f103xb.h /^#define USART_BRR_DIV_Mantissa_Msk /;" d +USART_BRR_DIV_Mantissa_Pos target/stm32f103xb.h /^#define USART_BRR_DIV_Mantissa_Pos /;" d +USART_BRR_DIV_Mantissa target/stm32f103xb.h /^#define USART_BRR_DIV_Mantissa /;" d +USART_CR1_IDLEIE_Msk target/stm32f103xb.h /^#define USART_CR1_IDLEIE_Msk /;" d +USART_CR1_IDLEIE_Pos target/stm32f103xb.h /^#define USART_CR1_IDLEIE_Pos /;" d +USART_CR1_IDLEIE target/stm32f103xb.h /^#define USART_CR1_IDLEIE /;" d +USART_CR1_M_Msk target/stm32f103xb.h /^#define USART_CR1_M_Msk /;" d +USART_CR1_M_Pos target/stm32f103xb.h /^#define USART_CR1_M_Pos /;" d +USART_CR1_M target/stm32f103xb.h /^#define USART_CR1_M /;" d +USART_CR1_PCE_Msk target/stm32f103xb.h /^#define USART_CR1_PCE_Msk /;" d +USART_CR1_PCE_Pos target/stm32f103xb.h /^#define USART_CR1_PCE_Pos /;" d +USART_CR1_PCE target/stm32f103xb.h /^#define USART_CR1_PCE /;" d +USART_CR1_PEIE_Msk target/stm32f103xb.h /^#define USART_CR1_PEIE_Msk /;" d +USART_CR1_PEIE_Pos target/stm32f103xb.h /^#define USART_CR1_PEIE_Pos /;" d +USART_CR1_PEIE target/stm32f103xb.h /^#define USART_CR1_PEIE /;" d +USART_CR1_PS_Msk target/stm32f103xb.h /^#define USART_CR1_PS_Msk /;" d +USART_CR1_PS_Pos target/stm32f103xb.h /^#define USART_CR1_PS_Pos /;" d +USART_CR1_PS target/stm32f103xb.h /^#define USART_CR1_PS /;" d +USART_CR1_RE_Msk target/stm32f103xb.h /^#define USART_CR1_RE_Msk /;" d +USART_CR1_RE_Pos target/stm32f103xb.h /^#define USART_CR1_RE_Pos /;" d +USART_CR1_RE target/stm32f103xb.h /^#define USART_CR1_RE /;" d +USART_CR1_RWU_Msk target/stm32f103xb.h /^#define USART_CR1_RWU_Msk /;" d +USART_CR1_RWU_Pos target/stm32f103xb.h /^#define USART_CR1_RWU_Pos /;" d +USART_CR1_RWU target/stm32f103xb.h /^#define USART_CR1_RWU /;" d +USART_CR1_RXNEIE_Msk target/stm32f103xb.h /^#define USART_CR1_RXNEIE_Msk /;" d +USART_CR1_RXNEIE_Pos target/stm32f103xb.h /^#define USART_CR1_RXNEIE_Pos /;" d +USART_CR1_RXNEIE target/stm32f103xb.h /^#define USART_CR1_RXNEIE /;" d +USART_CR1_SBK_Msk target/stm32f103xb.h /^#define USART_CR1_SBK_Msk /;" d +USART_CR1_SBK_Pos target/stm32f103xb.h /^#define USART_CR1_SBK_Pos /;" d +USART_CR1_SBK target/stm32f103xb.h /^#define USART_CR1_SBK /;" d +USART_CR1_TCIE_Msk target/stm32f103xb.h /^#define USART_CR1_TCIE_Msk /;" d +USART_CR1_TCIE_Pos target/stm32f103xb.h /^#define USART_CR1_TCIE_Pos /;" d +USART_CR1_TCIE target/stm32f103xb.h /^#define USART_CR1_TCIE /;" d +USART_CR1_TE_Msk target/stm32f103xb.h /^#define USART_CR1_TE_Msk /;" d +USART_CR1_TE_Pos target/stm32f103xb.h /^#define USART_CR1_TE_Pos /;" d +USART_CR1_TE target/stm32f103xb.h /^#define USART_CR1_TE /;" d +USART_CR1_TXEIE_Msk target/stm32f103xb.h /^#define USART_CR1_TXEIE_Msk /;" d +USART_CR1_TXEIE_Pos target/stm32f103xb.h /^#define USART_CR1_TXEIE_Pos /;" d +USART_CR1_TXEIE target/stm32f103xb.h /^#define USART_CR1_TXEIE /;" d +USART_CR1_UE_Msk target/stm32f103xb.h /^#define USART_CR1_UE_Msk /;" d +USART_CR1_UE_Pos target/stm32f103xb.h /^#define USART_CR1_UE_Pos /;" d +USART_CR1_UE target/stm32f103xb.h /^#define USART_CR1_UE /;" d +USART_CR1_WAKE_Msk target/stm32f103xb.h /^#define USART_CR1_WAKE_Msk /;" d +USART_CR1_WAKE_Pos target/stm32f103xb.h /^#define USART_CR1_WAKE_Pos /;" d +USART_CR1_WAKE target/stm32f103xb.h /^#define USART_CR1_WAKE /;" d +USART_CR2_ADD_Msk target/stm32f103xb.h /^#define USART_CR2_ADD_Msk /;" d +USART_CR2_ADD_Pos target/stm32f103xb.h /^#define USART_CR2_ADD_Pos /;" d +USART_CR2_ADD target/stm32f103xb.h /^#define USART_CR2_ADD /;" d +USART_CR2_CLKEN_Msk target/stm32f103xb.h /^#define USART_CR2_CLKEN_Msk /;" d +USART_CR2_CLKEN_Pos target/stm32f103xb.h /^#define USART_CR2_CLKEN_Pos /;" d +USART_CR2_CLKEN target/stm32f103xb.h /^#define USART_CR2_CLKEN /;" d +USART_CR2_CPHA_Msk target/stm32f103xb.h /^#define USART_CR2_CPHA_Msk /;" d +USART_CR2_CPHA_Pos target/stm32f103xb.h /^#define USART_CR2_CPHA_Pos /;" d +USART_CR2_CPHA target/stm32f103xb.h /^#define USART_CR2_CPHA /;" d +USART_CR2_CPOL_Msk target/stm32f103xb.h /^#define USART_CR2_CPOL_Msk /;" d +USART_CR2_CPOL_Pos target/stm32f103xb.h /^#define USART_CR2_CPOL_Pos /;" d +USART_CR2_CPOL target/stm32f103xb.h /^#define USART_CR2_CPOL /;" d +USART_CR2_LBCL_Msk target/stm32f103xb.h /^#define USART_CR2_LBCL_Msk /;" d +USART_CR2_LBCL_Pos target/stm32f103xb.h /^#define USART_CR2_LBCL_Pos /;" d +USART_CR2_LBCL target/stm32f103xb.h /^#define USART_CR2_LBCL /;" d +USART_CR2_LBDIE_Msk target/stm32f103xb.h /^#define USART_CR2_LBDIE_Msk /;" d +USART_CR2_LBDIE_Pos target/stm32f103xb.h /^#define USART_CR2_LBDIE_Pos /;" d +USART_CR2_LBDIE target/stm32f103xb.h /^#define USART_CR2_LBDIE /;" d +USART_CR2_LBDL_Msk target/stm32f103xb.h /^#define USART_CR2_LBDL_Msk /;" d +USART_CR2_LBDL_Pos target/stm32f103xb.h /^#define USART_CR2_LBDL_Pos /;" d +USART_CR2_LBDL target/stm32f103xb.h /^#define USART_CR2_LBDL /;" d +USART_CR2_LINEN_Msk target/stm32f103xb.h /^#define USART_CR2_LINEN_Msk /;" d +USART_CR2_LINEN_Pos target/stm32f103xb.h /^#define USART_CR2_LINEN_Pos /;" d +USART_CR2_LINEN target/stm32f103xb.h /^#define USART_CR2_LINEN /;" d +USART_CR2_STOP_0 target/stm32f103xb.h /^#define USART_CR2_STOP_0 /;" d +USART_CR2_STOP_1 target/stm32f103xb.h /^#define USART_CR2_STOP_1 /;" d +USART_CR2_STOP_Msk target/stm32f103xb.h /^#define USART_CR2_STOP_Msk /;" d +USART_CR2_STOP_Pos target/stm32f103xb.h /^#define USART_CR2_STOP_Pos /;" d +USART_CR2_STOP target/stm32f103xb.h /^#define USART_CR2_STOP /;" d +USART_CR3_CTSE_Msk target/stm32f103xb.h /^#define USART_CR3_CTSE_Msk /;" d +USART_CR3_CTSE_Pos target/stm32f103xb.h /^#define USART_CR3_CTSE_Pos /;" d +USART_CR3_CTSE target/stm32f103xb.h /^#define USART_CR3_CTSE /;" d +USART_CR3_CTSIE_Msk target/stm32f103xb.h /^#define USART_CR3_CTSIE_Msk /;" d +USART_CR3_CTSIE_Pos target/stm32f103xb.h /^#define USART_CR3_CTSIE_Pos /;" d +USART_CR3_CTSIE target/stm32f103xb.h /^#define USART_CR3_CTSIE /;" d +USART_CR3_DMAR_Msk target/stm32f103xb.h /^#define USART_CR3_DMAR_Msk /;" d +USART_CR3_DMAR_Pos target/stm32f103xb.h /^#define USART_CR3_DMAR_Pos /;" d +USART_CR3_DMAR target/stm32f103xb.h /^#define USART_CR3_DMAR /;" d +USART_CR3_DMAT_Msk target/stm32f103xb.h /^#define USART_CR3_DMAT_Msk /;" d +USART_CR3_DMAT_Pos target/stm32f103xb.h /^#define USART_CR3_DMAT_Pos /;" d +USART_CR3_DMAT target/stm32f103xb.h /^#define USART_CR3_DMAT /;" d +USART_CR3_EIE_Msk target/stm32f103xb.h /^#define USART_CR3_EIE_Msk /;" d +USART_CR3_EIE_Pos target/stm32f103xb.h /^#define USART_CR3_EIE_Pos /;" d +USART_CR3_EIE target/stm32f103xb.h /^#define USART_CR3_EIE /;" d +USART_CR3_HDSEL_Msk target/stm32f103xb.h /^#define USART_CR3_HDSEL_Msk /;" d +USART_CR3_HDSEL_Pos target/stm32f103xb.h /^#define USART_CR3_HDSEL_Pos /;" d +USART_CR3_HDSEL target/stm32f103xb.h /^#define USART_CR3_HDSEL /;" d +USART_CR3_IREN_Msk target/stm32f103xb.h /^#define USART_CR3_IREN_Msk /;" d +USART_CR3_IREN_Pos target/stm32f103xb.h /^#define USART_CR3_IREN_Pos /;" d +USART_CR3_IREN target/stm32f103xb.h /^#define USART_CR3_IREN /;" d +USART_CR3_IRLP_Msk target/stm32f103xb.h /^#define USART_CR3_IRLP_Msk /;" d +USART_CR3_IRLP_Pos target/stm32f103xb.h /^#define USART_CR3_IRLP_Pos /;" d +USART_CR3_IRLP target/stm32f103xb.h /^#define USART_CR3_IRLP /;" d +USART_CR3_NACK_Msk target/stm32f103xb.h /^#define USART_CR3_NACK_Msk /;" d +USART_CR3_NACK_Pos target/stm32f103xb.h /^#define USART_CR3_NACK_Pos /;" d +USART_CR3_NACK target/stm32f103xb.h /^#define USART_CR3_NACK /;" d +USART_CR3_RTSE_Msk target/stm32f103xb.h /^#define USART_CR3_RTSE_Msk /;" d +USART_CR3_RTSE_Pos target/stm32f103xb.h /^#define USART_CR3_RTSE_Pos /;" d +USART_CR3_RTSE target/stm32f103xb.h /^#define USART_CR3_RTSE /;" d +USART_CR3_SCEN_Msk target/stm32f103xb.h /^#define USART_CR3_SCEN_Msk /;" d +USART_CR3_SCEN_Pos target/stm32f103xb.h /^#define USART_CR3_SCEN_Pos /;" d +USART_CR3_SCEN target/stm32f103xb.h /^#define USART_CR3_SCEN /;" d +USART_DR_DR_Msk target/stm32f103xb.h /^#define USART_DR_DR_Msk /;" d +USART_DR_DR_Pos target/stm32f103xb.h /^#define USART_DR_DR_Pos /;" d +USART_DR_DR target/stm32f103xb.h /^#define USART_DR_DR /;" d +USART_GTPR_GT_Msk target/stm32f103xb.h /^#define USART_GTPR_GT_Msk /;" d +USART_GTPR_GT_Pos target/stm32f103xb.h /^#define USART_GTPR_GT_Pos /;" d +USART_GTPR_GT target/stm32f103xb.h /^#define USART_GTPR_GT /;" d +USART_GTPR_PSC_0 target/stm32f103xb.h /^#define USART_GTPR_PSC_0 /;" d +USART_GTPR_PSC_1 target/stm32f103xb.h /^#define USART_GTPR_PSC_1 /;" d +USART_GTPR_PSC_2 target/stm32f103xb.h /^#define USART_GTPR_PSC_2 /;" d +USART_GTPR_PSC_3 target/stm32f103xb.h /^#define USART_GTPR_PSC_3 /;" d +USART_GTPR_PSC_4 target/stm32f103xb.h /^#define USART_GTPR_PSC_4 /;" d +USART_GTPR_PSC_5 target/stm32f103xb.h /^#define USART_GTPR_PSC_5 /;" d +USART_GTPR_PSC_6 target/stm32f103xb.h /^#define USART_GTPR_PSC_6 /;" d +USART_GTPR_PSC_7 target/stm32f103xb.h /^#define USART_GTPR_PSC_7 /;" d +USART_GTPR_PSC_Msk target/stm32f103xb.h /^#define USART_GTPR_PSC_Msk /;" d +USART_GTPR_PSC_Pos target/stm32f103xb.h /^#define USART_GTPR_PSC_Pos /;" d +USART_GTPR_PSC target/stm32f103xb.h /^#define USART_GTPR_PSC /;" d +USART_SR_CTS_Msk target/stm32f103xb.h /^#define USART_SR_CTS_Msk /;" d +USART_SR_CTS_Pos target/stm32f103xb.h /^#define USART_SR_CTS_Pos /;" d +USART_SR_CTS target/stm32f103xb.h /^#define USART_SR_CTS /;" d +USART_SR_FE_Msk target/stm32f103xb.h /^#define USART_SR_FE_Msk /;" d +USART_SR_FE_Pos target/stm32f103xb.h /^#define USART_SR_FE_Pos /;" d +USART_SR_FE target/stm32f103xb.h /^#define USART_SR_FE /;" d +USART_SR_IDLE_Msk target/stm32f103xb.h /^#define USART_SR_IDLE_Msk /;" d +USART_SR_IDLE_Pos target/stm32f103xb.h /^#define USART_SR_IDLE_Pos /;" d +USART_SR_IDLE target/stm32f103xb.h /^#define USART_SR_IDLE /;" d +USART_SR_LBD_Msk target/stm32f103xb.h /^#define USART_SR_LBD_Msk /;" d +USART_SR_LBD_Pos target/stm32f103xb.h /^#define USART_SR_LBD_Pos /;" d +USART_SR_LBD target/stm32f103xb.h /^#define USART_SR_LBD /;" d +USART_SR_NE_Msk target/stm32f103xb.h /^#define USART_SR_NE_Msk /;" d +USART_SR_NE_Pos target/stm32f103xb.h /^#define USART_SR_NE_Pos /;" d +USART_SR_NE target/stm32f103xb.h /^#define USART_SR_NE /;" d +USART_SR_ORE_Msk target/stm32f103xb.h /^#define USART_SR_ORE_Msk /;" d +USART_SR_ORE_Pos target/stm32f103xb.h /^#define USART_SR_ORE_Pos /;" d +USART_SR_ORE target/stm32f103xb.h /^#define USART_SR_ORE /;" d +USART_SR_PE_Msk target/stm32f103xb.h /^#define USART_SR_PE_Msk /;" d +USART_SR_PE_Pos target/stm32f103xb.h /^#define USART_SR_PE_Pos /;" d +USART_SR_PE target/stm32f103xb.h /^#define USART_SR_PE /;" d +USART_SR_RXNE_Msk target/stm32f103xb.h /^#define USART_SR_RXNE_Msk /;" d +USART_SR_RXNE_Pos target/stm32f103xb.h /^#define USART_SR_RXNE_Pos /;" d +USART_SR_RXNE target/stm32f103xb.h /^#define USART_SR_RXNE /;" d +USART_SR_TC_Msk target/stm32f103xb.h /^#define USART_SR_TC_Msk /;" d +USART_SR_TC_Pos target/stm32f103xb.h /^#define USART_SR_TC_Pos /;" d +USART_SR_TC target/stm32f103xb.h /^#define USART_SR_TC /;" d +USART_SR_TXE_Msk target/stm32f103xb.h /^#define USART_SR_TXE_Msk /;" d +USART_SR_TXE_Pos target/stm32f103xb.h /^#define USART_SR_TXE_Pos /;" d +USART_SR_TXE target/stm32f103xb.h /^#define USART_SR_TXE /;" d +USART_TypeDef target/stm32f103xb.h /^} USART_TypeDef;$/;" t typeref:struct:__anon72c4c37e1a08 +USBWakeUp_IRQn target/stm32f103xb.h /^ USBWakeUp_IRQn = 42, \/*!< USB Device WakeUp from suspend through EXTI Line I/;" e enum:__anon72c4c37e0103 +USB_ADDR0_RX_ADDR0_RX_Msk target/stm32f103xb.h /^#define USB_ADDR0_RX_ADDR0_RX_Msk /;" d +USB_ADDR0_RX_ADDR0_RX_Pos target/stm32f103xb.h /^#define USB_ADDR0_RX_ADDR0_RX_Pos /;" d +USB_ADDR0_RX_ADDR0_RX target/stm32f103xb.h /^#define USB_ADDR0_RX_ADDR0_RX /;" d +USB_ADDR0_TX_ADDR0_TX_Msk target/stm32f103xb.h /^#define USB_ADDR0_TX_ADDR0_TX_Msk /;" d +USB_ADDR0_TX_ADDR0_TX_Pos target/stm32f103xb.h /^#define USB_ADDR0_TX_ADDR0_TX_Pos /;" d +USB_ADDR0_TX_ADDR0_TX target/stm32f103xb.h /^#define USB_ADDR0_TX_ADDR0_TX /;" d +USB_ADDR1_RX_ADDR1_RX_Msk target/stm32f103xb.h /^#define USB_ADDR1_RX_ADDR1_RX_Msk /;" d +USB_ADDR1_RX_ADDR1_RX_Pos target/stm32f103xb.h /^#define USB_ADDR1_RX_ADDR1_RX_Pos /;" d +USB_ADDR1_RX_ADDR1_RX target/stm32f103xb.h /^#define USB_ADDR1_RX_ADDR1_RX /;" d +USB_ADDR1_TX_ADDR1_TX_Msk target/stm32f103xb.h /^#define USB_ADDR1_TX_ADDR1_TX_Msk /;" d +USB_ADDR1_TX_ADDR1_TX_Pos target/stm32f103xb.h /^#define USB_ADDR1_TX_ADDR1_TX_Pos /;" d +USB_ADDR1_TX_ADDR1_TX target/stm32f103xb.h /^#define USB_ADDR1_TX_ADDR1_TX /;" d +USB_ADDR2_RX_ADDR2_RX_Msk target/stm32f103xb.h /^#define USB_ADDR2_RX_ADDR2_RX_Msk /;" d +USB_ADDR2_RX_ADDR2_RX_Pos target/stm32f103xb.h /^#define USB_ADDR2_RX_ADDR2_RX_Pos /;" d +USB_ADDR2_RX_ADDR2_RX target/stm32f103xb.h /^#define USB_ADDR2_RX_ADDR2_RX /;" d +USB_ADDR2_TX_ADDR2_TX_Msk target/stm32f103xb.h /^#define USB_ADDR2_TX_ADDR2_TX_Msk /;" d +USB_ADDR2_TX_ADDR2_TX_Pos target/stm32f103xb.h /^#define USB_ADDR2_TX_ADDR2_TX_Pos /;" d +USB_ADDR2_TX_ADDR2_TX target/stm32f103xb.h /^#define USB_ADDR2_TX_ADDR2_TX /;" d +USB_ADDR3_RX_ADDR3_RX_Msk target/stm32f103xb.h /^#define USB_ADDR3_RX_ADDR3_RX_Msk /;" d +USB_ADDR3_RX_ADDR3_RX_Pos target/stm32f103xb.h /^#define USB_ADDR3_RX_ADDR3_RX_Pos /;" d +USB_ADDR3_RX_ADDR3_RX target/stm32f103xb.h /^#define USB_ADDR3_RX_ADDR3_RX /;" d +USB_ADDR3_TX_ADDR3_TX_Msk target/stm32f103xb.h /^#define USB_ADDR3_TX_ADDR3_TX_Msk /;" d +USB_ADDR3_TX_ADDR3_TX_Pos target/stm32f103xb.h /^#define USB_ADDR3_TX_ADDR3_TX_Pos /;" d +USB_ADDR3_TX_ADDR3_TX target/stm32f103xb.h /^#define USB_ADDR3_TX_ADDR3_TX /;" d +USB_ADDR4_RX_ADDR4_RX_Msk target/stm32f103xb.h /^#define USB_ADDR4_RX_ADDR4_RX_Msk /;" d +USB_ADDR4_RX_ADDR4_RX_Pos target/stm32f103xb.h /^#define USB_ADDR4_RX_ADDR4_RX_Pos /;" d +USB_ADDR4_RX_ADDR4_RX target/stm32f103xb.h /^#define USB_ADDR4_RX_ADDR4_RX /;" d +USB_ADDR4_TX_ADDR4_TX_Msk target/stm32f103xb.h /^#define USB_ADDR4_TX_ADDR4_TX_Msk /;" d +USB_ADDR4_TX_ADDR4_TX_Pos target/stm32f103xb.h /^#define USB_ADDR4_TX_ADDR4_TX_Pos /;" d +USB_ADDR4_TX_ADDR4_TX target/stm32f103xb.h /^#define USB_ADDR4_TX_ADDR4_TX /;" d +USB_ADDR5_RX_ADDR5_RX_Msk target/stm32f103xb.h /^#define USB_ADDR5_RX_ADDR5_RX_Msk /;" d +USB_ADDR5_RX_ADDR5_RX_Pos target/stm32f103xb.h /^#define USB_ADDR5_RX_ADDR5_RX_Pos /;" d +USB_ADDR5_RX_ADDR5_RX target/stm32f103xb.h /^#define USB_ADDR5_RX_ADDR5_RX /;" d +USB_ADDR5_TX_ADDR5_TX_Msk target/stm32f103xb.h /^#define USB_ADDR5_TX_ADDR5_TX_Msk /;" d +USB_ADDR5_TX_ADDR5_TX_Pos target/stm32f103xb.h /^#define USB_ADDR5_TX_ADDR5_TX_Pos /;" d +USB_ADDR5_TX_ADDR5_TX target/stm32f103xb.h /^#define USB_ADDR5_TX_ADDR5_TX /;" d +USB_ADDR6_RX_ADDR6_RX_Msk target/stm32f103xb.h /^#define USB_ADDR6_RX_ADDR6_RX_Msk /;" d +USB_ADDR6_RX_ADDR6_RX_Pos target/stm32f103xb.h /^#define USB_ADDR6_RX_ADDR6_RX_Pos /;" d +USB_ADDR6_RX_ADDR6_RX target/stm32f103xb.h /^#define USB_ADDR6_RX_ADDR6_RX /;" d +USB_ADDR6_TX_ADDR6_TX_Msk target/stm32f103xb.h /^#define USB_ADDR6_TX_ADDR6_TX_Msk /;" d +USB_ADDR6_TX_ADDR6_TX_Pos target/stm32f103xb.h /^#define USB_ADDR6_TX_ADDR6_TX_Pos /;" d +USB_ADDR6_TX_ADDR6_TX target/stm32f103xb.h /^#define USB_ADDR6_TX_ADDR6_TX /;" d +USB_ADDR7_RX_ADDR7_RX_Msk target/stm32f103xb.h /^#define USB_ADDR7_RX_ADDR7_RX_Msk /;" d +USB_ADDR7_RX_ADDR7_RX_Pos target/stm32f103xb.h /^#define USB_ADDR7_RX_ADDR7_RX_Pos /;" d +USB_ADDR7_RX_ADDR7_RX target/stm32f103xb.h /^#define USB_ADDR7_RX_ADDR7_RX /;" d +USB_ADDR7_TX_ADDR7_TX_Msk target/stm32f103xb.h /^#define USB_ADDR7_TX_ADDR7_TX_Msk /;" d +USB_ADDR7_TX_ADDR7_TX_Pos target/stm32f103xb.h /^#define USB_ADDR7_TX_ADDR7_TX_Pos /;" d +USB_ADDR7_TX_ADDR7_TX target/stm32f103xb.h /^#define USB_ADDR7_TX_ADDR7_TX /;" d +USB_BASE target/stm32f103xb.h /^#define USB_BASE /;" d +USB_BTABLE_BTABLE_Msk target/stm32f103xb.h /^#define USB_BTABLE_BTABLE_Msk /;" d +USB_BTABLE_BTABLE_Pos target/stm32f103xb.h /^#define USB_BTABLE_BTABLE_Pos /;" d +USB_BTABLE_BTABLE target/stm32f103xb.h /^#define USB_BTABLE_BTABLE /;" d +USB_CNTR_CTRM_Msk target/stm32f103xb.h /^#define USB_CNTR_CTRM_Msk /;" d +USB_CNTR_CTRM_Pos target/stm32f103xb.h /^#define USB_CNTR_CTRM_Pos /;" d +USB_CNTR_CTRM target/stm32f103xb.h /^#define USB_CNTR_CTRM /;" d +USB_CNTR_ERRM_Msk target/stm32f103xb.h /^#define USB_CNTR_ERRM_Msk /;" d +USB_CNTR_ERRM_Pos target/stm32f103xb.h /^#define USB_CNTR_ERRM_Pos /;" d +USB_CNTR_ERRM target/stm32f103xb.h /^#define USB_CNTR_ERRM /;" d +USB_CNTR_ESOFM_Msk target/stm32f103xb.h /^#define USB_CNTR_ESOFM_Msk /;" d +USB_CNTR_ESOFM_Pos target/stm32f103xb.h /^#define USB_CNTR_ESOFM_Pos /;" d +USB_CNTR_ESOFM target/stm32f103xb.h /^#define USB_CNTR_ESOFM /;" d +USB_CNTR_FRES_Msk target/stm32f103xb.h /^#define USB_CNTR_FRES_Msk /;" d +USB_CNTR_FRES_Pos target/stm32f103xb.h /^#define USB_CNTR_FRES_Pos /;" d +USB_CNTR_FRES target/stm32f103xb.h /^#define USB_CNTR_FRES /;" d +USB_CNTR_FSUSP_Msk target/stm32f103xb.h /^#define USB_CNTR_FSUSP_Msk /;" d +USB_CNTR_FSUSP_Pos target/stm32f103xb.h /^#define USB_CNTR_FSUSP_Pos /;" d +USB_CNTR_FSUSP target/stm32f103xb.h /^#define USB_CNTR_FSUSP /;" d +USB_CNTR_LP_MODE_Msk target/stm32f103xb.h /^#define USB_CNTR_LP_MODE_Msk /;" d +USB_CNTR_LP_MODE_Pos target/stm32f103xb.h /^#define USB_CNTR_LP_MODE_Pos /;" d +USB_CNTR_LP_MODE target/stm32f103xb.h /^#define USB_CNTR_LP_MODE /;" d +USB_CNTR_PDWN_Msk target/stm32f103xb.h /^#define USB_CNTR_PDWN_Msk /;" d +USB_CNTR_PDWN_Pos target/stm32f103xb.h /^#define USB_CNTR_PDWN_Pos /;" d +USB_CNTR_PDWN target/stm32f103xb.h /^#define USB_CNTR_PDWN /;" d +USB_CNTR_PMAOVRM_Msk target/stm32f103xb.h /^#define USB_CNTR_PMAOVRM_Msk /;" d +USB_CNTR_PMAOVRM_Pos target/stm32f103xb.h /^#define USB_CNTR_PMAOVRM_Pos /;" d +USB_CNTR_PMAOVRM target/stm32f103xb.h /^#define USB_CNTR_PMAOVRM /;" d +USB_CNTR_RESETM_Msk target/stm32f103xb.h /^#define USB_CNTR_RESETM_Msk /;" d +USB_CNTR_RESETM_Pos target/stm32f103xb.h /^#define USB_CNTR_RESETM_Pos /;" d +USB_CNTR_RESETM target/stm32f103xb.h /^#define USB_CNTR_RESETM /;" d +USB_CNTR_RESUME_Msk target/stm32f103xb.h /^#define USB_CNTR_RESUME_Msk /;" d +USB_CNTR_RESUME_Pos target/stm32f103xb.h /^#define USB_CNTR_RESUME_Pos /;" d +USB_CNTR_RESUME target/stm32f103xb.h /^#define USB_CNTR_RESUME /;" d +USB_CNTR_SOFM_Msk target/stm32f103xb.h /^#define USB_CNTR_SOFM_Msk /;" d +USB_CNTR_SOFM_Pos target/stm32f103xb.h /^#define USB_CNTR_SOFM_Pos /;" d +USB_CNTR_SOFM target/stm32f103xb.h /^#define USB_CNTR_SOFM /;" d +USB_CNTR_SUSPM_Msk target/stm32f103xb.h /^#define USB_CNTR_SUSPM_Msk /;" d +USB_CNTR_SUSPM_Pos target/stm32f103xb.h /^#define USB_CNTR_SUSPM_Pos /;" d +USB_CNTR_SUSPM target/stm32f103xb.h /^#define USB_CNTR_SUSPM /;" d +USB_CNTR_WKUPM_Msk target/stm32f103xb.h /^#define USB_CNTR_WKUPM_Msk /;" d +USB_CNTR_WKUPM_Pos target/stm32f103xb.h /^#define USB_CNTR_WKUPM_Pos /;" d +USB_CNTR_WKUPM target/stm32f103xb.h /^#define USB_CNTR_WKUPM /;" d +USB_COUNT0_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_BLSIZE_0 /;" d +USB_COUNT0_RX_0_COUNT0_RX_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_COUNT0_RX_0 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT0_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT0_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_BLSIZE_1 /;" d +USB_COUNT0_RX_1_COUNT0_RX_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_COUNT0_RX_1 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT0_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT0_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT0_RX_BLSIZE_Msk /;" d +USB_COUNT0_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT0_RX_BLSIZE_Pos /;" d +USB_COUNT0_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT0_RX_BLSIZE /;" d +USB_COUNT0_RX_COUNT0_RX_Msk target/stm32f103xb.h /^#define USB_COUNT0_RX_COUNT0_RX_Msk /;" d +USB_COUNT0_RX_COUNT0_RX_Pos target/stm32f103xb.h /^#define USB_COUNT0_RX_COUNT0_RX_Pos /;" d +USB_COUNT0_RX_COUNT0_RX target/stm32f103xb.h /^#define USB_COUNT0_RX_COUNT0_RX /;" d +USB_COUNT0_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_0 /;" d +USB_COUNT0_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_1 /;" d +USB_COUNT0_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_2 /;" d +USB_COUNT0_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_3 /;" d +USB_COUNT0_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_4 /;" d +USB_COUNT0_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_Msk /;" d +USB_COUNT0_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK_Pos /;" d +USB_COUNT0_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT0_RX_NUM_BLOCK /;" d +USB_COUNT0_TX_0_COUNT0_TX_0 target/stm32f103xb.h /^#define USB_COUNT0_TX_0_COUNT0_TX_0 /;" d +USB_COUNT0_TX_1_COUNT0_TX_1 target/stm32f103xb.h /^#define USB_COUNT0_TX_1_COUNT0_TX_1 /;" d +USB_COUNT0_TX_COUNT0_TX_Msk target/stm32f103xb.h /^#define USB_COUNT0_TX_COUNT0_TX_Msk /;" d +USB_COUNT0_TX_COUNT0_TX_Pos target/stm32f103xb.h /^#define USB_COUNT0_TX_COUNT0_TX_Pos /;" d +USB_COUNT0_TX_COUNT0_TX target/stm32f103xb.h /^#define USB_COUNT0_TX_COUNT0_TX /;" d +USB_COUNT1_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_BLSIZE_0 /;" d +USB_COUNT1_RX_0_COUNT1_RX_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_COUNT1_RX_0 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT1_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT1_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_BLSIZE_1 /;" d +USB_COUNT1_RX_1_COUNT1_RX_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_COUNT1_RX_1 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT1_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT1_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT1_RX_BLSIZE_Msk /;" d +USB_COUNT1_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT1_RX_BLSIZE_Pos /;" d +USB_COUNT1_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT1_RX_BLSIZE /;" d +USB_COUNT1_RX_COUNT1_RX_Msk target/stm32f103xb.h /^#define USB_COUNT1_RX_COUNT1_RX_Msk /;" d +USB_COUNT1_RX_COUNT1_RX_Pos target/stm32f103xb.h /^#define USB_COUNT1_RX_COUNT1_RX_Pos /;" d +USB_COUNT1_RX_COUNT1_RX target/stm32f103xb.h /^#define USB_COUNT1_RX_COUNT1_RX /;" d +USB_COUNT1_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_0 /;" d +USB_COUNT1_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_1 /;" d +USB_COUNT1_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_2 /;" d +USB_COUNT1_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_3 /;" d +USB_COUNT1_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_4 /;" d +USB_COUNT1_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_Msk /;" d +USB_COUNT1_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK_Pos /;" d +USB_COUNT1_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT1_RX_NUM_BLOCK /;" d +USB_COUNT1_TX_0_COUNT1_TX_0 target/stm32f103xb.h /^#define USB_COUNT1_TX_0_COUNT1_TX_0 /;" d +USB_COUNT1_TX_1_COUNT1_TX_1 target/stm32f103xb.h /^#define USB_COUNT1_TX_1_COUNT1_TX_1 /;" d +USB_COUNT1_TX_COUNT1_TX_Msk target/stm32f103xb.h /^#define USB_COUNT1_TX_COUNT1_TX_Msk /;" d +USB_COUNT1_TX_COUNT1_TX_Pos target/stm32f103xb.h /^#define USB_COUNT1_TX_COUNT1_TX_Pos /;" d +USB_COUNT1_TX_COUNT1_TX target/stm32f103xb.h /^#define USB_COUNT1_TX_COUNT1_TX /;" d +USB_COUNT2_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_BLSIZE_0 /;" d +USB_COUNT2_RX_0_COUNT2_RX_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_COUNT2_RX_0 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT2_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT2_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_BLSIZE_1 /;" d +USB_COUNT2_RX_1_COUNT2_RX_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_COUNT2_RX_1 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT2_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT2_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT2_RX_BLSIZE_Msk /;" d +USB_COUNT2_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT2_RX_BLSIZE_Pos /;" d +USB_COUNT2_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT2_RX_BLSIZE /;" d +USB_COUNT2_RX_COUNT2_RX_Msk target/stm32f103xb.h /^#define USB_COUNT2_RX_COUNT2_RX_Msk /;" d +USB_COUNT2_RX_COUNT2_RX_Pos target/stm32f103xb.h /^#define USB_COUNT2_RX_COUNT2_RX_Pos /;" d +USB_COUNT2_RX_COUNT2_RX target/stm32f103xb.h /^#define USB_COUNT2_RX_COUNT2_RX /;" d +USB_COUNT2_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_0 /;" d +USB_COUNT2_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_1 /;" d +USB_COUNT2_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_2 /;" d +USB_COUNT2_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_3 /;" d +USB_COUNT2_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_4 /;" d +USB_COUNT2_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_Msk /;" d +USB_COUNT2_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK_Pos /;" d +USB_COUNT2_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT2_RX_NUM_BLOCK /;" d +USB_COUNT2_TX_0_COUNT2_TX_0 target/stm32f103xb.h /^#define USB_COUNT2_TX_0_COUNT2_TX_0 /;" d +USB_COUNT2_TX_1_COUNT2_TX_1 target/stm32f103xb.h /^#define USB_COUNT2_TX_1_COUNT2_TX_1 /;" d +USB_COUNT2_TX_COUNT2_TX_Msk target/stm32f103xb.h /^#define USB_COUNT2_TX_COUNT2_TX_Msk /;" d +USB_COUNT2_TX_COUNT2_TX_Pos target/stm32f103xb.h /^#define USB_COUNT2_TX_COUNT2_TX_Pos /;" d +USB_COUNT2_TX_COUNT2_TX target/stm32f103xb.h /^#define USB_COUNT2_TX_COUNT2_TX /;" d +USB_COUNT3_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_BLSIZE_0 /;" d +USB_COUNT3_RX_0_COUNT3_RX_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_COUNT3_RX_0 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT3_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT3_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_BLSIZE_1 /;" d +USB_COUNT3_RX_1_COUNT3_RX_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_COUNT3_RX_1 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT3_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT3_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT3_RX_BLSIZE_Msk /;" d +USB_COUNT3_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT3_RX_BLSIZE_Pos /;" d +USB_COUNT3_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT3_RX_BLSIZE /;" d +USB_COUNT3_RX_COUNT3_RX_Msk target/stm32f103xb.h /^#define USB_COUNT3_RX_COUNT3_RX_Msk /;" d +USB_COUNT3_RX_COUNT3_RX_Pos target/stm32f103xb.h /^#define USB_COUNT3_RX_COUNT3_RX_Pos /;" d +USB_COUNT3_RX_COUNT3_RX target/stm32f103xb.h /^#define USB_COUNT3_RX_COUNT3_RX /;" d +USB_COUNT3_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_0 /;" d +USB_COUNT3_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_1 /;" d +USB_COUNT3_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_2 /;" d +USB_COUNT3_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_3 /;" d +USB_COUNT3_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_4 /;" d +USB_COUNT3_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_Msk /;" d +USB_COUNT3_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK_Pos /;" d +USB_COUNT3_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT3_RX_NUM_BLOCK /;" d +USB_COUNT3_TX_0_COUNT3_TX_0 target/stm32f103xb.h /^#define USB_COUNT3_TX_0_COUNT3_TX_0 /;" d +USB_COUNT3_TX_1_COUNT3_TX_1 target/stm32f103xb.h /^#define USB_COUNT3_TX_1_COUNT3_TX_1 /;" d +USB_COUNT3_TX_COUNT3_TX_Msk target/stm32f103xb.h /^#define USB_COUNT3_TX_COUNT3_TX_Msk /;" d +USB_COUNT3_TX_COUNT3_TX_Pos target/stm32f103xb.h /^#define USB_COUNT3_TX_COUNT3_TX_Pos /;" d +USB_COUNT3_TX_COUNT3_TX target/stm32f103xb.h /^#define USB_COUNT3_TX_COUNT3_TX /;" d +USB_COUNT4_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_BLSIZE_0 /;" d +USB_COUNT4_RX_0_COUNT4_RX_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_COUNT4_RX_0 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT4_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT4_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_BLSIZE_1 /;" d +USB_COUNT4_RX_1_COUNT4_RX_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_COUNT4_RX_1 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT4_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT4_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT4_RX_BLSIZE_Msk /;" d +USB_COUNT4_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT4_RX_BLSIZE_Pos /;" d +USB_COUNT4_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT4_RX_BLSIZE /;" d +USB_COUNT4_RX_COUNT4_RX_Msk target/stm32f103xb.h /^#define USB_COUNT4_RX_COUNT4_RX_Msk /;" d +USB_COUNT4_RX_COUNT4_RX_Pos target/stm32f103xb.h /^#define USB_COUNT4_RX_COUNT4_RX_Pos /;" d +USB_COUNT4_RX_COUNT4_RX target/stm32f103xb.h /^#define USB_COUNT4_RX_COUNT4_RX /;" d +USB_COUNT4_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_0 /;" d +USB_COUNT4_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_1 /;" d +USB_COUNT4_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_2 /;" d +USB_COUNT4_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_3 /;" d +USB_COUNT4_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_4 /;" d +USB_COUNT4_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_Msk /;" d +USB_COUNT4_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK_Pos /;" d +USB_COUNT4_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT4_RX_NUM_BLOCK /;" d +USB_COUNT4_TX_0_COUNT4_TX_0 target/stm32f103xb.h /^#define USB_COUNT4_TX_0_COUNT4_TX_0 /;" d +USB_COUNT4_TX_1_COUNT4_TX_1 target/stm32f103xb.h /^#define USB_COUNT4_TX_1_COUNT4_TX_1 /;" d +USB_COUNT4_TX_COUNT4_TX_Msk target/stm32f103xb.h /^#define USB_COUNT4_TX_COUNT4_TX_Msk /;" d +USB_COUNT4_TX_COUNT4_TX_Pos target/stm32f103xb.h /^#define USB_COUNT4_TX_COUNT4_TX_Pos /;" d +USB_COUNT4_TX_COUNT4_TX target/stm32f103xb.h /^#define USB_COUNT4_TX_COUNT4_TX /;" d +USB_COUNT5_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_BLSIZE_0 /;" d +USB_COUNT5_RX_0_COUNT5_RX_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_COUNT5_RX_0 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT5_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT5_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_BLSIZE_1 /;" d +USB_COUNT5_RX_1_COUNT5_RX_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_COUNT5_RX_1 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT5_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT5_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT5_RX_BLSIZE_Msk /;" d +USB_COUNT5_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT5_RX_BLSIZE_Pos /;" d +USB_COUNT5_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT5_RX_BLSIZE /;" d +USB_COUNT5_RX_COUNT5_RX_Msk target/stm32f103xb.h /^#define USB_COUNT5_RX_COUNT5_RX_Msk /;" d +USB_COUNT5_RX_COUNT5_RX_Pos target/stm32f103xb.h /^#define USB_COUNT5_RX_COUNT5_RX_Pos /;" d +USB_COUNT5_RX_COUNT5_RX target/stm32f103xb.h /^#define USB_COUNT5_RX_COUNT5_RX /;" d +USB_COUNT5_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_0 /;" d +USB_COUNT5_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_1 /;" d +USB_COUNT5_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_2 /;" d +USB_COUNT5_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_3 /;" d +USB_COUNT5_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_4 /;" d +USB_COUNT5_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_Msk /;" d +USB_COUNT5_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK_Pos /;" d +USB_COUNT5_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT5_RX_NUM_BLOCK /;" d +USB_COUNT5_TX_0_COUNT5_TX_0 target/stm32f103xb.h /^#define USB_COUNT5_TX_0_COUNT5_TX_0 /;" d +USB_COUNT5_TX_1_COUNT5_TX_1 target/stm32f103xb.h /^#define USB_COUNT5_TX_1_COUNT5_TX_1 /;" d +USB_COUNT5_TX_COUNT5_TX_Msk target/stm32f103xb.h /^#define USB_COUNT5_TX_COUNT5_TX_Msk /;" d +USB_COUNT5_TX_COUNT5_TX_Pos target/stm32f103xb.h /^#define USB_COUNT5_TX_COUNT5_TX_Pos /;" d +USB_COUNT5_TX_COUNT5_TX target/stm32f103xb.h /^#define USB_COUNT5_TX_COUNT5_TX /;" d +USB_COUNT6_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_BLSIZE_0 /;" d +USB_COUNT6_RX_0_COUNT6_RX_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_COUNT6_RX_0 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT6_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT6_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_BLSIZE_1 /;" d +USB_COUNT6_RX_1_COUNT6_RX_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_COUNT6_RX_1 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT6_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT6_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT6_RX_BLSIZE_Msk /;" d +USB_COUNT6_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT6_RX_BLSIZE_Pos /;" d +USB_COUNT6_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT6_RX_BLSIZE /;" d +USB_COUNT6_RX_COUNT6_RX_Msk target/stm32f103xb.h /^#define USB_COUNT6_RX_COUNT6_RX_Msk /;" d +USB_COUNT6_RX_COUNT6_RX_Pos target/stm32f103xb.h /^#define USB_COUNT6_RX_COUNT6_RX_Pos /;" d +USB_COUNT6_RX_COUNT6_RX target/stm32f103xb.h /^#define USB_COUNT6_RX_COUNT6_RX /;" d +USB_COUNT6_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_0 /;" d +USB_COUNT6_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_1 /;" d +USB_COUNT6_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_2 /;" d +USB_COUNT6_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_3 /;" d +USB_COUNT6_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_4 /;" d +USB_COUNT6_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_Msk /;" d +USB_COUNT6_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK_Pos /;" d +USB_COUNT6_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT6_RX_NUM_BLOCK /;" d +USB_COUNT6_TX_0_COUNT6_TX_0 target/stm32f103xb.h /^#define USB_COUNT6_TX_0_COUNT6_TX_0 /;" d +USB_COUNT6_TX_1_COUNT6_TX_1 target/stm32f103xb.h /^#define USB_COUNT6_TX_1_COUNT6_TX_1 /;" d +USB_COUNT6_TX_COUNT6_TX_Msk target/stm32f103xb.h /^#define USB_COUNT6_TX_COUNT6_TX_Msk /;" d +USB_COUNT6_TX_COUNT6_TX_Pos target/stm32f103xb.h /^#define USB_COUNT6_TX_COUNT6_TX_Pos /;" d +USB_COUNT6_TX_COUNT6_TX target/stm32f103xb.h /^#define USB_COUNT6_TX_COUNT6_TX /;" d +USB_COUNT7_RX_0_BLSIZE_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_BLSIZE_0 /;" d +USB_COUNT7_RX_0_COUNT7_RX_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_COUNT7_RX_0 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0_2 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0_3 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0_4 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 /;" d +USB_COUNT7_RX_0_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_0_NUM_BLOCK_0 /;" d +USB_COUNT7_RX_1_BLSIZE_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_BLSIZE_1 /;" d +USB_COUNT7_RX_1_COUNT7_RX_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_COUNT7_RX_1 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1_2 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1_3 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1_4 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 /;" d +USB_COUNT7_RX_1_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_1_NUM_BLOCK_1 /;" d +USB_COUNT7_RX_BLSIZE_Msk target/stm32f103xb.h /^#define USB_COUNT7_RX_BLSIZE_Msk /;" d +USB_COUNT7_RX_BLSIZE_Pos target/stm32f103xb.h /^#define USB_COUNT7_RX_BLSIZE_Pos /;" d +USB_COUNT7_RX_BLSIZE target/stm32f103xb.h /^#define USB_COUNT7_RX_BLSIZE /;" d +USB_COUNT7_RX_COUNT7_RX_Msk target/stm32f103xb.h /^#define USB_COUNT7_RX_COUNT7_RX_Msk /;" d +USB_COUNT7_RX_COUNT7_RX_Pos target/stm32f103xb.h /^#define USB_COUNT7_RX_COUNT7_RX_Pos /;" d +USB_COUNT7_RX_COUNT7_RX target/stm32f103xb.h /^#define USB_COUNT7_RX_COUNT7_RX /;" d +USB_COUNT7_RX_NUM_BLOCK_0 target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_0 /;" d +USB_COUNT7_RX_NUM_BLOCK_1 target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_1 /;" d +USB_COUNT7_RX_NUM_BLOCK_2 target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_2 /;" d +USB_COUNT7_RX_NUM_BLOCK_3 target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_3 /;" d +USB_COUNT7_RX_NUM_BLOCK_4 target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_4 /;" d +USB_COUNT7_RX_NUM_BLOCK_Msk target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_Msk /;" d +USB_COUNT7_RX_NUM_BLOCK_Pos target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK_Pos /;" d +USB_COUNT7_RX_NUM_BLOCK target/stm32f103xb.h /^#define USB_COUNT7_RX_NUM_BLOCK /;" d +USB_COUNT7_TX_0_COUNT7_TX_0 target/stm32f103xb.h /^#define USB_COUNT7_TX_0_COUNT7_TX_0 /;" d +USB_COUNT7_TX_1_COUNT7_TX_1 target/stm32f103xb.h /^#define USB_COUNT7_TX_1_COUNT7_TX_1 /;" d +USB_COUNT7_TX_COUNT7_TX_Msk target/stm32f103xb.h /^#define USB_COUNT7_TX_COUNT7_TX_Msk /;" d +USB_COUNT7_TX_COUNT7_TX_Pos target/stm32f103xb.h /^#define USB_COUNT7_TX_COUNT7_TX_Pos /;" d +USB_COUNT7_TX_COUNT7_TX target/stm32f103xb.h /^#define USB_COUNT7_TX_COUNT7_TX /;" d +USB_DADDR_ADD0_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD0_Msk /;" d +USB_DADDR_ADD0_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD0_Pos /;" d +USB_DADDR_ADD0 target/stm32f103xb.h /^#define USB_DADDR_ADD0 /;" d +USB_DADDR_ADD1_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD1_Msk /;" d +USB_DADDR_ADD1_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD1_Pos /;" d +USB_DADDR_ADD1 target/stm32f103xb.h /^#define USB_DADDR_ADD1 /;" d +USB_DADDR_ADD2_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD2_Msk /;" d +USB_DADDR_ADD2_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD2_Pos /;" d +USB_DADDR_ADD2 target/stm32f103xb.h /^#define USB_DADDR_ADD2 /;" d +USB_DADDR_ADD3_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD3_Msk /;" d +USB_DADDR_ADD3_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD3_Pos /;" d +USB_DADDR_ADD3 target/stm32f103xb.h /^#define USB_DADDR_ADD3 /;" d +USB_DADDR_ADD4_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD4_Msk /;" d +USB_DADDR_ADD4_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD4_Pos /;" d +USB_DADDR_ADD4 target/stm32f103xb.h /^#define USB_DADDR_ADD4 /;" d +USB_DADDR_ADD5_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD5_Msk /;" d +USB_DADDR_ADD5_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD5_Pos /;" d +USB_DADDR_ADD5 target/stm32f103xb.h /^#define USB_DADDR_ADD5 /;" d +USB_DADDR_ADD6_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD6_Msk /;" d +USB_DADDR_ADD6_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD6_Pos /;" d +USB_DADDR_ADD6 target/stm32f103xb.h /^#define USB_DADDR_ADD6 /;" d +USB_DADDR_ADD_Msk target/stm32f103xb.h /^#define USB_DADDR_ADD_Msk /;" d +USB_DADDR_ADD_Pos target/stm32f103xb.h /^#define USB_DADDR_ADD_Pos /;" d +USB_DADDR_ADD target/stm32f103xb.h /^#define USB_DADDR_ADD /;" d +USB_DADDR_EF_Msk target/stm32f103xb.h /^#define USB_DADDR_EF_Msk /;" d +USB_DADDR_EF_Pos target/stm32f103xb.h /^#define USB_DADDR_EF_Pos /;" d +USB_DADDR_EF target/stm32f103xb.h /^#define USB_DADDR_EF /;" d +USB_EP0R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP0R_CTR_RX_Msk /;" d +USB_EP0R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP0R_CTR_RX_Pos /;" d +USB_EP0R_CTR_RX target/stm32f103xb.h /^#define USB_EP0R_CTR_RX /;" d +USB_EP0R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP0R_CTR_TX_Msk /;" d +USB_EP0R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP0R_CTR_TX_Pos /;" d +USB_EP0R_CTR_TX target/stm32f103xb.h /^#define USB_EP0R_CTR_TX /;" d +USB_EP0R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP0R_DTOG_RX_Msk /;" d +USB_EP0R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP0R_DTOG_RX_Pos /;" d +USB_EP0R_DTOG_RX target/stm32f103xb.h /^#define USB_EP0R_DTOG_RX /;" d +USB_EP0R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP0R_DTOG_TX_Msk /;" d +USB_EP0R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP0R_DTOG_TX_Pos /;" d +USB_EP0R_DTOG_TX target/stm32f103xb.h /^#define USB_EP0R_DTOG_TX /;" d +USB_EP0R_EA_Msk target/stm32f103xb.h /^#define USB_EP0R_EA_Msk /;" d +USB_EP0R_EA_Pos target/stm32f103xb.h /^#define USB_EP0R_EA_Pos /;" d +USB_EP0R_EA target/stm32f103xb.h /^#define USB_EP0R_EA /;" d +USB_EP0R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP0R_EP_KIND_Msk /;" d +USB_EP0R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP0R_EP_KIND_Pos /;" d +USB_EP0R_EP_KIND target/stm32f103xb.h /^#define USB_EP0R_EP_KIND /;" d +USB_EP0R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP0R_EP_TYPE_0 /;" d +USB_EP0R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP0R_EP_TYPE_1 /;" d +USB_EP0R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP0R_EP_TYPE_Msk /;" d +USB_EP0R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP0R_EP_TYPE_Pos /;" d +USB_EP0R_EP_TYPE target/stm32f103xb.h /^#define USB_EP0R_EP_TYPE /;" d +USB_EP0R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP0R_SETUP_Msk /;" d +USB_EP0R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP0R_SETUP_Pos /;" d +USB_EP0R_SETUP target/stm32f103xb.h /^#define USB_EP0R_SETUP /;" d +USB_EP0R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP0R_STAT_RX_0 /;" d +USB_EP0R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP0R_STAT_RX_1 /;" d +USB_EP0R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP0R_STAT_RX_Msk /;" d +USB_EP0R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP0R_STAT_RX_Pos /;" d +USB_EP0R_STAT_RX target/stm32f103xb.h /^#define USB_EP0R_STAT_RX /;" d +USB_EP0R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP0R_STAT_TX_0 /;" d +USB_EP0R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP0R_STAT_TX_1 /;" d +USB_EP0R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP0R_STAT_TX_Msk /;" d +USB_EP0R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP0R_STAT_TX_Pos /;" d +USB_EP0R_STAT_TX target/stm32f103xb.h /^#define USB_EP0R_STAT_TX /;" d +USB_EP0R target/stm32f103xb.h /^#define USB_EP0R /;" d +USB_EP1R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP1R_CTR_RX_Msk /;" d +USB_EP1R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP1R_CTR_RX_Pos /;" d +USB_EP1R_CTR_RX target/stm32f103xb.h /^#define USB_EP1R_CTR_RX /;" d +USB_EP1R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP1R_CTR_TX_Msk /;" d +USB_EP1R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP1R_CTR_TX_Pos /;" d +USB_EP1R_CTR_TX target/stm32f103xb.h /^#define USB_EP1R_CTR_TX /;" d +USB_EP1R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP1R_DTOG_RX_Msk /;" d +USB_EP1R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP1R_DTOG_RX_Pos /;" d +USB_EP1R_DTOG_RX target/stm32f103xb.h /^#define USB_EP1R_DTOG_RX /;" d +USB_EP1R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP1R_DTOG_TX_Msk /;" d +USB_EP1R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP1R_DTOG_TX_Pos /;" d +USB_EP1R_DTOG_TX target/stm32f103xb.h /^#define USB_EP1R_DTOG_TX /;" d +USB_EP1R_EA_Msk target/stm32f103xb.h /^#define USB_EP1R_EA_Msk /;" d +USB_EP1R_EA_Pos target/stm32f103xb.h /^#define USB_EP1R_EA_Pos /;" d +USB_EP1R_EA target/stm32f103xb.h /^#define USB_EP1R_EA /;" d +USB_EP1R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP1R_EP_KIND_Msk /;" d +USB_EP1R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP1R_EP_KIND_Pos /;" d +USB_EP1R_EP_KIND target/stm32f103xb.h /^#define USB_EP1R_EP_KIND /;" d +USB_EP1R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP1R_EP_TYPE_0 /;" d +USB_EP1R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP1R_EP_TYPE_1 /;" d +USB_EP1R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP1R_EP_TYPE_Msk /;" d +USB_EP1R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP1R_EP_TYPE_Pos /;" d +USB_EP1R_EP_TYPE target/stm32f103xb.h /^#define USB_EP1R_EP_TYPE /;" d +USB_EP1R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP1R_SETUP_Msk /;" d +USB_EP1R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP1R_SETUP_Pos /;" d +USB_EP1R_SETUP target/stm32f103xb.h /^#define USB_EP1R_SETUP /;" d +USB_EP1R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP1R_STAT_RX_0 /;" d +USB_EP1R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP1R_STAT_RX_1 /;" d +USB_EP1R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP1R_STAT_RX_Msk /;" d +USB_EP1R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP1R_STAT_RX_Pos /;" d +USB_EP1R_STAT_RX target/stm32f103xb.h /^#define USB_EP1R_STAT_RX /;" d +USB_EP1R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP1R_STAT_TX_0 /;" d +USB_EP1R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP1R_STAT_TX_1 /;" d +USB_EP1R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP1R_STAT_TX_Msk /;" d +USB_EP1R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP1R_STAT_TX_Pos /;" d +USB_EP1R_STAT_TX target/stm32f103xb.h /^#define USB_EP1R_STAT_TX /;" d +USB_EP1R target/stm32f103xb.h /^#define USB_EP1R /;" d +USB_EP2R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP2R_CTR_RX_Msk /;" d +USB_EP2R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP2R_CTR_RX_Pos /;" d +USB_EP2R_CTR_RX target/stm32f103xb.h /^#define USB_EP2R_CTR_RX /;" d +USB_EP2R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP2R_CTR_TX_Msk /;" d +USB_EP2R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP2R_CTR_TX_Pos /;" d +USB_EP2R_CTR_TX target/stm32f103xb.h /^#define USB_EP2R_CTR_TX /;" d +USB_EP2R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP2R_DTOG_RX_Msk /;" d +USB_EP2R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP2R_DTOG_RX_Pos /;" d +USB_EP2R_DTOG_RX target/stm32f103xb.h /^#define USB_EP2R_DTOG_RX /;" d +USB_EP2R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP2R_DTOG_TX_Msk /;" d +USB_EP2R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP2R_DTOG_TX_Pos /;" d +USB_EP2R_DTOG_TX target/stm32f103xb.h /^#define USB_EP2R_DTOG_TX /;" d +USB_EP2R_EA_Msk target/stm32f103xb.h /^#define USB_EP2R_EA_Msk /;" d +USB_EP2R_EA_Pos target/stm32f103xb.h /^#define USB_EP2R_EA_Pos /;" d +USB_EP2R_EA target/stm32f103xb.h /^#define USB_EP2R_EA /;" d +USB_EP2R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP2R_EP_KIND_Msk /;" d +USB_EP2R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP2R_EP_KIND_Pos /;" d +USB_EP2R_EP_KIND target/stm32f103xb.h /^#define USB_EP2R_EP_KIND /;" d +USB_EP2R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP2R_EP_TYPE_0 /;" d +USB_EP2R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP2R_EP_TYPE_1 /;" d +USB_EP2R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP2R_EP_TYPE_Msk /;" d +USB_EP2R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP2R_EP_TYPE_Pos /;" d +USB_EP2R_EP_TYPE target/stm32f103xb.h /^#define USB_EP2R_EP_TYPE /;" d +USB_EP2R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP2R_SETUP_Msk /;" d +USB_EP2R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP2R_SETUP_Pos /;" d +USB_EP2R_SETUP target/stm32f103xb.h /^#define USB_EP2R_SETUP /;" d +USB_EP2R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP2R_STAT_RX_0 /;" d +USB_EP2R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP2R_STAT_RX_1 /;" d +USB_EP2R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP2R_STAT_RX_Msk /;" d +USB_EP2R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP2R_STAT_RX_Pos /;" d +USB_EP2R_STAT_RX target/stm32f103xb.h /^#define USB_EP2R_STAT_RX /;" d +USB_EP2R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP2R_STAT_TX_0 /;" d +USB_EP2R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP2R_STAT_TX_1 /;" d +USB_EP2R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP2R_STAT_TX_Msk /;" d +USB_EP2R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP2R_STAT_TX_Pos /;" d +USB_EP2R_STAT_TX target/stm32f103xb.h /^#define USB_EP2R_STAT_TX /;" d +USB_EP2R target/stm32f103xb.h /^#define USB_EP2R /;" d +USB_EP3R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP3R_CTR_RX_Msk /;" d +USB_EP3R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP3R_CTR_RX_Pos /;" d +USB_EP3R_CTR_RX target/stm32f103xb.h /^#define USB_EP3R_CTR_RX /;" d +USB_EP3R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP3R_CTR_TX_Msk /;" d +USB_EP3R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP3R_CTR_TX_Pos /;" d +USB_EP3R_CTR_TX target/stm32f103xb.h /^#define USB_EP3R_CTR_TX /;" d +USB_EP3R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP3R_DTOG_RX_Msk /;" d +USB_EP3R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP3R_DTOG_RX_Pos /;" d +USB_EP3R_DTOG_RX target/stm32f103xb.h /^#define USB_EP3R_DTOG_RX /;" d +USB_EP3R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP3R_DTOG_TX_Msk /;" d +USB_EP3R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP3R_DTOG_TX_Pos /;" d +USB_EP3R_DTOG_TX target/stm32f103xb.h /^#define USB_EP3R_DTOG_TX /;" d +USB_EP3R_EA_Msk target/stm32f103xb.h /^#define USB_EP3R_EA_Msk /;" d +USB_EP3R_EA_Pos target/stm32f103xb.h /^#define USB_EP3R_EA_Pos /;" d +USB_EP3R_EA target/stm32f103xb.h /^#define USB_EP3R_EA /;" d +USB_EP3R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP3R_EP_KIND_Msk /;" d +USB_EP3R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP3R_EP_KIND_Pos /;" d +USB_EP3R_EP_KIND target/stm32f103xb.h /^#define USB_EP3R_EP_KIND /;" d +USB_EP3R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP3R_EP_TYPE_0 /;" d +USB_EP3R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP3R_EP_TYPE_1 /;" d +USB_EP3R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP3R_EP_TYPE_Msk /;" d +USB_EP3R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP3R_EP_TYPE_Pos /;" d +USB_EP3R_EP_TYPE target/stm32f103xb.h /^#define USB_EP3R_EP_TYPE /;" d +USB_EP3R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP3R_SETUP_Msk /;" d +USB_EP3R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP3R_SETUP_Pos /;" d +USB_EP3R_SETUP target/stm32f103xb.h /^#define USB_EP3R_SETUP /;" d +USB_EP3R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP3R_STAT_RX_0 /;" d +USB_EP3R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP3R_STAT_RX_1 /;" d +USB_EP3R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP3R_STAT_RX_Msk /;" d +USB_EP3R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP3R_STAT_RX_Pos /;" d +USB_EP3R_STAT_RX target/stm32f103xb.h /^#define USB_EP3R_STAT_RX /;" d +USB_EP3R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP3R_STAT_TX_0 /;" d +USB_EP3R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP3R_STAT_TX_1 /;" d +USB_EP3R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP3R_STAT_TX_Msk /;" d +USB_EP3R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP3R_STAT_TX_Pos /;" d +USB_EP3R_STAT_TX target/stm32f103xb.h /^#define USB_EP3R_STAT_TX /;" d +USB_EP3R target/stm32f103xb.h /^#define USB_EP3R /;" d +USB_EP4R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP4R_CTR_RX_Msk /;" d +USB_EP4R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP4R_CTR_RX_Pos /;" d +USB_EP4R_CTR_RX target/stm32f103xb.h /^#define USB_EP4R_CTR_RX /;" d +USB_EP4R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP4R_CTR_TX_Msk /;" d +USB_EP4R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP4R_CTR_TX_Pos /;" d +USB_EP4R_CTR_TX target/stm32f103xb.h /^#define USB_EP4R_CTR_TX /;" d +USB_EP4R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP4R_DTOG_RX_Msk /;" d +USB_EP4R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP4R_DTOG_RX_Pos /;" d +USB_EP4R_DTOG_RX target/stm32f103xb.h /^#define USB_EP4R_DTOG_RX /;" d +USB_EP4R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP4R_DTOG_TX_Msk /;" d +USB_EP4R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP4R_DTOG_TX_Pos /;" d +USB_EP4R_DTOG_TX target/stm32f103xb.h /^#define USB_EP4R_DTOG_TX /;" d +USB_EP4R_EA_Msk target/stm32f103xb.h /^#define USB_EP4R_EA_Msk /;" d +USB_EP4R_EA_Pos target/stm32f103xb.h /^#define USB_EP4R_EA_Pos /;" d +USB_EP4R_EA target/stm32f103xb.h /^#define USB_EP4R_EA /;" d +USB_EP4R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP4R_EP_KIND_Msk /;" d +USB_EP4R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP4R_EP_KIND_Pos /;" d +USB_EP4R_EP_KIND target/stm32f103xb.h /^#define USB_EP4R_EP_KIND /;" d +USB_EP4R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP4R_EP_TYPE_0 /;" d +USB_EP4R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP4R_EP_TYPE_1 /;" d +USB_EP4R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP4R_EP_TYPE_Msk /;" d +USB_EP4R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP4R_EP_TYPE_Pos /;" d +USB_EP4R_EP_TYPE target/stm32f103xb.h /^#define USB_EP4R_EP_TYPE /;" d +USB_EP4R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP4R_SETUP_Msk /;" d +USB_EP4R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP4R_SETUP_Pos /;" d +USB_EP4R_SETUP target/stm32f103xb.h /^#define USB_EP4R_SETUP /;" d +USB_EP4R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP4R_STAT_RX_0 /;" d +USB_EP4R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP4R_STAT_RX_1 /;" d +USB_EP4R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP4R_STAT_RX_Msk /;" d +USB_EP4R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP4R_STAT_RX_Pos /;" d +USB_EP4R_STAT_RX target/stm32f103xb.h /^#define USB_EP4R_STAT_RX /;" d +USB_EP4R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP4R_STAT_TX_0 /;" d +USB_EP4R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP4R_STAT_TX_1 /;" d +USB_EP4R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP4R_STAT_TX_Msk /;" d +USB_EP4R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP4R_STAT_TX_Pos /;" d +USB_EP4R_STAT_TX target/stm32f103xb.h /^#define USB_EP4R_STAT_TX /;" d +USB_EP4R target/stm32f103xb.h /^#define USB_EP4R /;" d +USB_EP5R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP5R_CTR_RX_Msk /;" d +USB_EP5R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP5R_CTR_RX_Pos /;" d +USB_EP5R_CTR_RX target/stm32f103xb.h /^#define USB_EP5R_CTR_RX /;" d +USB_EP5R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP5R_CTR_TX_Msk /;" d +USB_EP5R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP5R_CTR_TX_Pos /;" d +USB_EP5R_CTR_TX target/stm32f103xb.h /^#define USB_EP5R_CTR_TX /;" d +USB_EP5R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP5R_DTOG_RX_Msk /;" d +USB_EP5R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP5R_DTOG_RX_Pos /;" d +USB_EP5R_DTOG_RX target/stm32f103xb.h /^#define USB_EP5R_DTOG_RX /;" d +USB_EP5R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP5R_DTOG_TX_Msk /;" d +USB_EP5R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP5R_DTOG_TX_Pos /;" d +USB_EP5R_DTOG_TX target/stm32f103xb.h /^#define USB_EP5R_DTOG_TX /;" d +USB_EP5R_EA_Msk target/stm32f103xb.h /^#define USB_EP5R_EA_Msk /;" d +USB_EP5R_EA_Pos target/stm32f103xb.h /^#define USB_EP5R_EA_Pos /;" d +USB_EP5R_EA target/stm32f103xb.h /^#define USB_EP5R_EA /;" d +USB_EP5R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP5R_EP_KIND_Msk /;" d +USB_EP5R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP5R_EP_KIND_Pos /;" d +USB_EP5R_EP_KIND target/stm32f103xb.h /^#define USB_EP5R_EP_KIND /;" d +USB_EP5R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP5R_EP_TYPE_0 /;" d +USB_EP5R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP5R_EP_TYPE_1 /;" d +USB_EP5R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP5R_EP_TYPE_Msk /;" d +USB_EP5R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP5R_EP_TYPE_Pos /;" d +USB_EP5R_EP_TYPE target/stm32f103xb.h /^#define USB_EP5R_EP_TYPE /;" d +USB_EP5R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP5R_SETUP_Msk /;" d +USB_EP5R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP5R_SETUP_Pos /;" d +USB_EP5R_SETUP target/stm32f103xb.h /^#define USB_EP5R_SETUP /;" d +USB_EP5R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP5R_STAT_RX_0 /;" d +USB_EP5R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP5R_STAT_RX_1 /;" d +USB_EP5R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP5R_STAT_RX_Msk /;" d +USB_EP5R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP5R_STAT_RX_Pos /;" d +USB_EP5R_STAT_RX target/stm32f103xb.h /^#define USB_EP5R_STAT_RX /;" d +USB_EP5R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP5R_STAT_TX_0 /;" d +USB_EP5R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP5R_STAT_TX_1 /;" d +USB_EP5R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP5R_STAT_TX_Msk /;" d +USB_EP5R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP5R_STAT_TX_Pos /;" d +USB_EP5R_STAT_TX target/stm32f103xb.h /^#define USB_EP5R_STAT_TX /;" d +USB_EP5R target/stm32f103xb.h /^#define USB_EP5R /;" d +USB_EP6R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP6R_CTR_RX_Msk /;" d +USB_EP6R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP6R_CTR_RX_Pos /;" d +USB_EP6R_CTR_RX target/stm32f103xb.h /^#define USB_EP6R_CTR_RX /;" d +USB_EP6R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP6R_CTR_TX_Msk /;" d +USB_EP6R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP6R_CTR_TX_Pos /;" d +USB_EP6R_CTR_TX target/stm32f103xb.h /^#define USB_EP6R_CTR_TX /;" d +USB_EP6R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP6R_DTOG_RX_Msk /;" d +USB_EP6R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP6R_DTOG_RX_Pos /;" d +USB_EP6R_DTOG_RX target/stm32f103xb.h /^#define USB_EP6R_DTOG_RX /;" d +USB_EP6R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP6R_DTOG_TX_Msk /;" d +USB_EP6R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP6R_DTOG_TX_Pos /;" d +USB_EP6R_DTOG_TX target/stm32f103xb.h /^#define USB_EP6R_DTOG_TX /;" d +USB_EP6R_EA_Msk target/stm32f103xb.h /^#define USB_EP6R_EA_Msk /;" d +USB_EP6R_EA_Pos target/stm32f103xb.h /^#define USB_EP6R_EA_Pos /;" d +USB_EP6R_EA target/stm32f103xb.h /^#define USB_EP6R_EA /;" d +USB_EP6R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP6R_EP_KIND_Msk /;" d +USB_EP6R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP6R_EP_KIND_Pos /;" d +USB_EP6R_EP_KIND target/stm32f103xb.h /^#define USB_EP6R_EP_KIND /;" d +USB_EP6R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP6R_EP_TYPE_0 /;" d +USB_EP6R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP6R_EP_TYPE_1 /;" d +USB_EP6R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP6R_EP_TYPE_Msk /;" d +USB_EP6R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP6R_EP_TYPE_Pos /;" d +USB_EP6R_EP_TYPE target/stm32f103xb.h /^#define USB_EP6R_EP_TYPE /;" d +USB_EP6R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP6R_SETUP_Msk /;" d +USB_EP6R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP6R_SETUP_Pos /;" d +USB_EP6R_SETUP target/stm32f103xb.h /^#define USB_EP6R_SETUP /;" d +USB_EP6R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP6R_STAT_RX_0 /;" d +USB_EP6R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP6R_STAT_RX_1 /;" d +USB_EP6R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP6R_STAT_RX_Msk /;" d +USB_EP6R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP6R_STAT_RX_Pos /;" d +USB_EP6R_STAT_RX target/stm32f103xb.h /^#define USB_EP6R_STAT_RX /;" d +USB_EP6R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP6R_STAT_TX_0 /;" d +USB_EP6R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP6R_STAT_TX_1 /;" d +USB_EP6R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP6R_STAT_TX_Msk /;" d +USB_EP6R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP6R_STAT_TX_Pos /;" d +USB_EP6R_STAT_TX target/stm32f103xb.h /^#define USB_EP6R_STAT_TX /;" d +USB_EP6R target/stm32f103xb.h /^#define USB_EP6R /;" d +USB_EP7R_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP7R_CTR_RX_Msk /;" d +USB_EP7R_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP7R_CTR_RX_Pos /;" d +USB_EP7R_CTR_RX target/stm32f103xb.h /^#define USB_EP7R_CTR_RX /;" d +USB_EP7R_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP7R_CTR_TX_Msk /;" d +USB_EP7R_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP7R_CTR_TX_Pos /;" d +USB_EP7R_CTR_TX target/stm32f103xb.h /^#define USB_EP7R_CTR_TX /;" d +USB_EP7R_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP7R_DTOG_RX_Msk /;" d +USB_EP7R_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP7R_DTOG_RX_Pos /;" d +USB_EP7R_DTOG_RX target/stm32f103xb.h /^#define USB_EP7R_DTOG_RX /;" d +USB_EP7R_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP7R_DTOG_TX_Msk /;" d +USB_EP7R_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP7R_DTOG_TX_Pos /;" d +USB_EP7R_DTOG_TX target/stm32f103xb.h /^#define USB_EP7R_DTOG_TX /;" d +USB_EP7R_EA_Msk target/stm32f103xb.h /^#define USB_EP7R_EA_Msk /;" d +USB_EP7R_EA_Pos target/stm32f103xb.h /^#define USB_EP7R_EA_Pos /;" d +USB_EP7R_EA target/stm32f103xb.h /^#define USB_EP7R_EA /;" d +USB_EP7R_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP7R_EP_KIND_Msk /;" d +USB_EP7R_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP7R_EP_KIND_Pos /;" d +USB_EP7R_EP_KIND target/stm32f103xb.h /^#define USB_EP7R_EP_KIND /;" d +USB_EP7R_EP_TYPE_0 target/stm32f103xb.h /^#define USB_EP7R_EP_TYPE_0 /;" d +USB_EP7R_EP_TYPE_1 target/stm32f103xb.h /^#define USB_EP7R_EP_TYPE_1 /;" d +USB_EP7R_EP_TYPE_Msk target/stm32f103xb.h /^#define USB_EP7R_EP_TYPE_Msk /;" d +USB_EP7R_EP_TYPE_Pos target/stm32f103xb.h /^#define USB_EP7R_EP_TYPE_Pos /;" d +USB_EP7R_EP_TYPE target/stm32f103xb.h /^#define USB_EP7R_EP_TYPE /;" d +USB_EP7R_SETUP_Msk target/stm32f103xb.h /^#define USB_EP7R_SETUP_Msk /;" d +USB_EP7R_SETUP_Pos target/stm32f103xb.h /^#define USB_EP7R_SETUP_Pos /;" d +USB_EP7R_SETUP target/stm32f103xb.h /^#define USB_EP7R_SETUP /;" d +USB_EP7R_STAT_RX_0 target/stm32f103xb.h /^#define USB_EP7R_STAT_RX_0 /;" d +USB_EP7R_STAT_RX_1 target/stm32f103xb.h /^#define USB_EP7R_STAT_RX_1 /;" d +USB_EP7R_STAT_RX_Msk target/stm32f103xb.h /^#define USB_EP7R_STAT_RX_Msk /;" d +USB_EP7R_STAT_RX_Pos target/stm32f103xb.h /^#define USB_EP7R_STAT_RX_Pos /;" d +USB_EP7R_STAT_RX target/stm32f103xb.h /^#define USB_EP7R_STAT_RX /;" d +USB_EP7R_STAT_TX_0 target/stm32f103xb.h /^#define USB_EP7R_STAT_TX_0 /;" d +USB_EP7R_STAT_TX_1 target/stm32f103xb.h /^#define USB_EP7R_STAT_TX_1 /;" d +USB_EP7R_STAT_TX_Msk target/stm32f103xb.h /^#define USB_EP7R_STAT_TX_Msk /;" d +USB_EP7R_STAT_TX_Pos target/stm32f103xb.h /^#define USB_EP7R_STAT_TX_Pos /;" d +USB_EP7R_STAT_TX target/stm32f103xb.h /^#define USB_EP7R_STAT_TX /;" d +USB_EP7R target/stm32f103xb.h /^#define USB_EP7R /;" d +USB_EPADDR_FIELD_Msk target/stm32f103xb.h /^#define USB_EPADDR_FIELD_Msk /;" d +USB_EPADDR_FIELD_Pos target/stm32f103xb.h /^#define USB_EPADDR_FIELD_Pos /;" d +USB_EPADDR_FIELD target/stm32f103xb.h /^#define USB_EPADDR_FIELD /;" d +USB_EPKIND_MASK target/stm32f103xb.h /^#define USB_EPKIND_MASK /;" d +USB_EPREG_MASK target/stm32f103xb.h /^#define USB_EPREG_MASK /;" d +USB_EPRX_DTOG1 target/stm32f103xb.h /^#define USB_EPRX_DTOG1 /;" d +USB_EPRX_DTOG2 target/stm32f103xb.h /^#define USB_EPRX_DTOG2 /;" d +USB_EPRX_DTOGMASK target/stm32f103xb.h /^#define USB_EPRX_DTOGMASK /;" d +USB_EPRX_STAT_Msk target/stm32f103xb.h /^#define USB_EPRX_STAT_Msk /;" d +USB_EPRX_STAT_Pos target/stm32f103xb.h /^#define USB_EPRX_STAT_Pos /;" d +USB_EPRX_STAT target/stm32f103xb.h /^#define USB_EPRX_STAT /;" d +USB_EPTX_DTOG1 target/stm32f103xb.h /^#define USB_EPTX_DTOG1 /;" d +USB_EPTX_DTOG2 target/stm32f103xb.h /^#define USB_EPTX_DTOG2 /;" d +USB_EPTX_DTOGMASK target/stm32f103xb.h /^#define USB_EPTX_DTOGMASK /;" d +USB_EPTX_STAT_Msk target/stm32f103xb.h /^#define USB_EPTX_STAT_Msk /;" d +USB_EPTX_STAT_Pos target/stm32f103xb.h /^#define USB_EPTX_STAT_Pos /;" d +USB_EPTX_STAT target/stm32f103xb.h /^#define USB_EPTX_STAT /;" d +USB_EP_BULK target/stm32f103xb.h /^#define USB_EP_BULK /;" d +USB_EP_CONTROL target/stm32f103xb.h /^#define USB_EP_CONTROL /;" d +USB_EP_CTR_RX_Msk target/stm32f103xb.h /^#define USB_EP_CTR_RX_Msk /;" d +USB_EP_CTR_RX_Pos target/stm32f103xb.h /^#define USB_EP_CTR_RX_Pos /;" d +USB_EP_CTR_RX target/stm32f103xb.h /^#define USB_EP_CTR_RX /;" d +USB_EP_CTR_TX_Msk target/stm32f103xb.h /^#define USB_EP_CTR_TX_Msk /;" d +USB_EP_CTR_TX_Pos target/stm32f103xb.h /^#define USB_EP_CTR_TX_Pos /;" d +USB_EP_CTR_TX target/stm32f103xb.h /^#define USB_EP_CTR_TX /;" d +USB_EP_DTOG_RX_Msk target/stm32f103xb.h /^#define USB_EP_DTOG_RX_Msk /;" d +USB_EP_DTOG_RX_Pos target/stm32f103xb.h /^#define USB_EP_DTOG_RX_Pos /;" d +USB_EP_DTOG_RX target/stm32f103xb.h /^#define USB_EP_DTOG_RX /;" d +USB_EP_DTOG_TX_Msk target/stm32f103xb.h /^#define USB_EP_DTOG_TX_Msk /;" d +USB_EP_DTOG_TX_Pos target/stm32f103xb.h /^#define USB_EP_DTOG_TX_Pos /;" d +USB_EP_DTOG_TX target/stm32f103xb.h /^#define USB_EP_DTOG_TX /;" d +USB_EP_INTERRUPT target/stm32f103xb.h /^#define USB_EP_INTERRUPT /;" d +USB_EP_ISOCHRONOUS target/stm32f103xb.h /^#define USB_EP_ISOCHRONOUS /;" d +USB_EP_KIND_Msk target/stm32f103xb.h /^#define USB_EP_KIND_Msk /;" d +USB_EP_KIND_Pos target/stm32f103xb.h /^#define USB_EP_KIND_Pos /;" d +USB_EP_KIND target/stm32f103xb.h /^#define USB_EP_KIND /;" d +USB_EP_RX_DIS target/stm32f103xb.h /^#define USB_EP_RX_DIS /;" d +USB_EP_RX_NAK target/stm32f103xb.h /^#define USB_EP_RX_NAK /;" d +USB_EP_RX_STALL target/stm32f103xb.h /^#define USB_EP_RX_STALL /;" d +USB_EP_RX_VALID target/stm32f103xb.h /^#define USB_EP_RX_VALID /;" d +USB_EP_SETUP_Msk target/stm32f103xb.h /^#define USB_EP_SETUP_Msk /;" d +USB_EP_SETUP_Pos target/stm32f103xb.h /^#define USB_EP_SETUP_Pos /;" d +USB_EP_SETUP target/stm32f103xb.h /^#define USB_EP_SETUP /;" d +USB_EP_TX_DIS target/stm32f103xb.h /^#define USB_EP_TX_DIS /;" d +USB_EP_TX_NAK target/stm32f103xb.h /^#define USB_EP_TX_NAK /;" d +USB_EP_TX_STALL target/stm32f103xb.h /^#define USB_EP_TX_STALL /;" d +USB_EP_TX_VALID target/stm32f103xb.h /^#define USB_EP_TX_VALID /;" d +USB_EP_TYPE_MASK_Msk target/stm32f103xb.h /^#define USB_EP_TYPE_MASK_Msk /;" d +USB_EP_TYPE_MASK_Pos target/stm32f103xb.h /^#define USB_EP_TYPE_MASK_Pos /;" d +USB_EP_TYPE_MASK target/stm32f103xb.h /^#define USB_EP_TYPE_MASK /;" d +USB_EP_T_FIELD_Msk target/stm32f103xb.h /^#define USB_EP_T_FIELD_Msk /;" d +USB_EP_T_FIELD_Pos target/stm32f103xb.h /^#define USB_EP_T_FIELD_Pos /;" d +USB_EP_T_FIELD target/stm32f103xb.h /^#define USB_EP_T_FIELD /;" d +USB_EP_T_MASK target/stm32f103xb.h /^#define USB_EP_T_MASK /;" d +USB_FNR_FN_Msk target/stm32f103xb.h /^#define USB_FNR_FN_Msk /;" d +USB_FNR_FN_Pos target/stm32f103xb.h /^#define USB_FNR_FN_Pos /;" d +USB_FNR_FN target/stm32f103xb.h /^#define USB_FNR_FN /;" d +USB_FNR_LCK_Msk target/stm32f103xb.h /^#define USB_FNR_LCK_Msk /;" d +USB_FNR_LCK_Pos target/stm32f103xb.h /^#define USB_FNR_LCK_Pos /;" d +USB_FNR_LCK target/stm32f103xb.h /^#define USB_FNR_LCK /;" d +USB_FNR_LSOF_Msk target/stm32f103xb.h /^#define USB_FNR_LSOF_Msk /;" d +USB_FNR_LSOF_Pos target/stm32f103xb.h /^#define USB_FNR_LSOF_Pos /;" d +USB_FNR_LSOF target/stm32f103xb.h /^#define USB_FNR_LSOF /;" d +USB_FNR_RXDM_Msk target/stm32f103xb.h /^#define USB_FNR_RXDM_Msk /;" d +USB_FNR_RXDM_Pos target/stm32f103xb.h /^#define USB_FNR_RXDM_Pos /;" d +USB_FNR_RXDM target/stm32f103xb.h /^#define USB_FNR_RXDM /;" d +USB_FNR_RXDP_Msk target/stm32f103xb.h /^#define USB_FNR_RXDP_Msk /;" d +USB_FNR_RXDP_Pos target/stm32f103xb.h /^#define USB_FNR_RXDP_Pos /;" d +USB_FNR_RXDP target/stm32f103xb.h /^#define USB_FNR_RXDP /;" d +USB_HP_CAN1_TX_IRQn target/stm32f103xb.h /^ USB_HP_CAN1_TX_IRQn = 19, \/*!< USB Device High Priority or CAN1 TX Interrupts /;" e enum:__anon72c4c37e0103 +USB_HP_IRQHandler target/stm32f103xb.h /^#define USB_HP_IRQHandler /;" d +USB_HP_IRQn target/stm32f103xb.h /^#define USB_HP_IRQn /;" d +USB_ISTR_CTR_Msk target/stm32f103xb.h /^#define USB_ISTR_CTR_Msk /;" d +USB_ISTR_CTR_Pos target/stm32f103xb.h /^#define USB_ISTR_CTR_Pos /;" d +USB_ISTR_CTR target/stm32f103xb.h /^#define USB_ISTR_CTR /;" d +USB_ISTR_DIR_Msk target/stm32f103xb.h /^#define USB_ISTR_DIR_Msk /;" d +USB_ISTR_DIR_Pos target/stm32f103xb.h /^#define USB_ISTR_DIR_Pos /;" d +USB_ISTR_DIR target/stm32f103xb.h /^#define USB_ISTR_DIR /;" d +USB_ISTR_EP_ID_Msk target/stm32f103xb.h /^#define USB_ISTR_EP_ID_Msk /;" d +USB_ISTR_EP_ID_Pos target/stm32f103xb.h /^#define USB_ISTR_EP_ID_Pos /;" d +USB_ISTR_EP_ID target/stm32f103xb.h /^#define USB_ISTR_EP_ID /;" d +USB_ISTR_ERR_Msk target/stm32f103xb.h /^#define USB_ISTR_ERR_Msk /;" d +USB_ISTR_ERR_Pos target/stm32f103xb.h /^#define USB_ISTR_ERR_Pos /;" d +USB_ISTR_ERR target/stm32f103xb.h /^#define USB_ISTR_ERR /;" d +USB_ISTR_ESOF_Msk target/stm32f103xb.h /^#define USB_ISTR_ESOF_Msk /;" d +USB_ISTR_ESOF_Pos target/stm32f103xb.h /^#define USB_ISTR_ESOF_Pos /;" d +USB_ISTR_ESOF target/stm32f103xb.h /^#define USB_ISTR_ESOF /;" d +USB_ISTR_PMAOVR_Msk target/stm32f103xb.h /^#define USB_ISTR_PMAOVR_Msk /;" d +USB_ISTR_PMAOVR_Pos target/stm32f103xb.h /^#define USB_ISTR_PMAOVR_Pos /;" d +USB_ISTR_PMAOVR target/stm32f103xb.h /^#define USB_ISTR_PMAOVR /;" d +USB_ISTR_RESET_Msk target/stm32f103xb.h /^#define USB_ISTR_RESET_Msk /;" d +USB_ISTR_RESET_Pos target/stm32f103xb.h /^#define USB_ISTR_RESET_Pos /;" d +USB_ISTR_RESET target/stm32f103xb.h /^#define USB_ISTR_RESET /;" d +USB_ISTR_SOF_Msk target/stm32f103xb.h /^#define USB_ISTR_SOF_Msk /;" d +USB_ISTR_SOF_Pos target/stm32f103xb.h /^#define USB_ISTR_SOF_Pos /;" d +USB_ISTR_SOF target/stm32f103xb.h /^#define USB_ISTR_SOF /;" d +USB_ISTR_SUSP_Msk target/stm32f103xb.h /^#define USB_ISTR_SUSP_Msk /;" d +USB_ISTR_SUSP_Pos target/stm32f103xb.h /^#define USB_ISTR_SUSP_Pos /;" d +USB_ISTR_SUSP target/stm32f103xb.h /^#define USB_ISTR_SUSP /;" d +USB_ISTR_WKUP_Msk target/stm32f103xb.h /^#define USB_ISTR_WKUP_Msk /;" d +USB_ISTR_WKUP_Pos target/stm32f103xb.h /^#define USB_ISTR_WKUP_Pos /;" d +USB_ISTR_WKUP target/stm32f103xb.h /^#define USB_ISTR_WKUP /;" d +USB_LP_CAN1_RX0_IRQn target/stm32f103xb.h /^ USB_LP_CAN1_RX0_IRQn = 20, \/*!< USB Device Low Priority or CAN1 RX0 Interrupts /;" e enum:__anon72c4c37e0103 +USB_LP_IRQHandler target/stm32f103xb.h /^#define USB_LP_IRQHandler /;" d +USB_LP_IRQn target/stm32f103xb.h /^#define USB_LP_IRQn /;" d +USB_PMAADDR target/stm32f103xb.h /^#define USB_PMAADDR /;" d +USB_TypeDef target/stm32f103xb.h /^} USB_TypeDef;$/;" t typeref:struct:__anon72c4c37e1b08 +USB target/stm32f103xb.h /^#define USB /;" d +USER target/stm32f103xb.h /^ __IO uint16_t USER;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +UsageFault_Handler Untitled Folder/sys_handlers.c /^void UsageFault_Handler(void)$/;" f typeref:typename:void +UsageFault_IRQn target/stm32f103xb.h /^ UsageFault_IRQn = -10, \/*!< 6 Cortex-M3 Usage Fault Interrupt /;" e enum:__anon72c4c37e0103 +VECT_TAB_OFFSET target/system_clock.c /^#define VECT_TAB_OFFSET /;" d file: +WRITE_REG target/stm32f1xx.h /^#define WRITE_REG(/;" d +WRP0 target/stm32f103xb.h /^ __IO uint16_t WRP0;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +WRP1 target/stm32f103xb.h /^ __IO uint16_t WRP1;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +WRP2 target/stm32f103xb.h /^ __IO uint16_t WRP2;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +WRP3 target/stm32f103xb.h /^ __IO uint16_t WRP3;$/;" m struct:__anon72c4c37e0f08 typeref:typename:__IO uint16_t +WRPR target/stm32f103xb.h /^ __IO uint32_t WRPR;$/;" m struct:__anon72c4c37e0e08 typeref:typename:__IO uint32_t +WWDG_BASE target/stm32f103xb.h /^#define WWDG_BASE /;" d +WWDG_CFR_EWI_Msk target/stm32f103xb.h /^#define WWDG_CFR_EWI_Msk /;" d +WWDG_CFR_EWI_Pos target/stm32f103xb.h /^#define WWDG_CFR_EWI_Pos /;" d +WWDG_CFR_EWI target/stm32f103xb.h /^#define WWDG_CFR_EWI /;" d +WWDG_CFR_W0 target/stm32f103xb.h /^#define WWDG_CFR_W0 /;" d +WWDG_CFR_W1 target/stm32f103xb.h /^#define WWDG_CFR_W1 /;" d +WWDG_CFR_W2 target/stm32f103xb.h /^#define WWDG_CFR_W2 /;" d +WWDG_CFR_W3 target/stm32f103xb.h /^#define WWDG_CFR_W3 /;" d +WWDG_CFR_W4 target/stm32f103xb.h /^#define WWDG_CFR_W4 /;" d +WWDG_CFR_W5 target/stm32f103xb.h /^#define WWDG_CFR_W5 /;" d +WWDG_CFR_W6 target/stm32f103xb.h /^#define WWDG_CFR_W6 /;" d +WWDG_CFR_WDGTB0 target/stm32f103xb.h /^#define WWDG_CFR_WDGTB0 /;" d +WWDG_CFR_WDGTB1 target/stm32f103xb.h /^#define WWDG_CFR_WDGTB1 /;" d +WWDG_CFR_WDGTB_0 target/stm32f103xb.h /^#define WWDG_CFR_WDGTB_0 /;" d +WWDG_CFR_WDGTB_1 target/stm32f103xb.h /^#define WWDG_CFR_WDGTB_1 /;" d +WWDG_CFR_WDGTB_Msk target/stm32f103xb.h /^#define WWDG_CFR_WDGTB_Msk /;" d +WWDG_CFR_WDGTB_Pos target/stm32f103xb.h /^#define WWDG_CFR_WDGTB_Pos /;" d +WWDG_CFR_WDGTB target/stm32f103xb.h /^#define WWDG_CFR_WDGTB /;" d +WWDG_CFR_W_0 target/stm32f103xb.h /^#define WWDG_CFR_W_0 /;" d +WWDG_CFR_W_1 target/stm32f103xb.h /^#define WWDG_CFR_W_1 /;" d +WWDG_CFR_W_2 target/stm32f103xb.h /^#define WWDG_CFR_W_2 /;" d +WWDG_CFR_W_3 target/stm32f103xb.h /^#define WWDG_CFR_W_3 /;" d +WWDG_CFR_W_4 target/stm32f103xb.h /^#define WWDG_CFR_W_4 /;" d +WWDG_CFR_W_5 target/stm32f103xb.h /^#define WWDG_CFR_W_5 /;" d +WWDG_CFR_W_6 target/stm32f103xb.h /^#define WWDG_CFR_W_6 /;" d +WWDG_CFR_W_Msk target/stm32f103xb.h /^#define WWDG_CFR_W_Msk /;" d +WWDG_CFR_W_Pos target/stm32f103xb.h /^#define WWDG_CFR_W_Pos /;" d +WWDG_CFR_W target/stm32f103xb.h /^#define WWDG_CFR_W /;" d +WWDG_CR_T0 target/stm32f103xb.h /^#define WWDG_CR_T0 /;" d +WWDG_CR_T1 target/stm32f103xb.h /^#define WWDG_CR_T1 /;" d +WWDG_CR_T2 target/stm32f103xb.h /^#define WWDG_CR_T2 /;" d +WWDG_CR_T3 target/stm32f103xb.h /^#define WWDG_CR_T3 /;" d +WWDG_CR_T4 target/stm32f103xb.h /^#define WWDG_CR_T4 /;" d +WWDG_CR_T5 target/stm32f103xb.h /^#define WWDG_CR_T5 /;" d +WWDG_CR_T6 target/stm32f103xb.h /^#define WWDG_CR_T6 /;" d +WWDG_CR_T_0 target/stm32f103xb.h /^#define WWDG_CR_T_0 /;" d +WWDG_CR_T_1 target/stm32f103xb.h /^#define WWDG_CR_T_1 /;" d +WWDG_CR_T_2 target/stm32f103xb.h /^#define WWDG_CR_T_2 /;" d +WWDG_CR_T_3 target/stm32f103xb.h /^#define WWDG_CR_T_3 /;" d +WWDG_CR_T_4 target/stm32f103xb.h /^#define WWDG_CR_T_4 /;" d +WWDG_CR_T_5 target/stm32f103xb.h /^#define WWDG_CR_T_5 /;" d +WWDG_CR_T_6 target/stm32f103xb.h /^#define WWDG_CR_T_6 /;" d +WWDG_CR_T_Msk target/stm32f103xb.h /^#define WWDG_CR_T_Msk /;" d +WWDG_CR_T_Pos target/stm32f103xb.h /^#define WWDG_CR_T_Pos /;" d +WWDG_CR_T target/stm32f103xb.h /^#define WWDG_CR_T /;" d +WWDG_CR_WDGA_Msk target/stm32f103xb.h /^#define WWDG_CR_WDGA_Msk /;" d +WWDG_CR_WDGA_Pos target/stm32f103xb.h /^#define WWDG_CR_WDGA_Pos /;" d +WWDG_CR_WDGA target/stm32f103xb.h /^#define WWDG_CR_WDGA /;" d +WWDG_IRQn target/stm32f103xb.h /^ WWDG_IRQn = 0, \/*!< Window WatchDog Interrupt /;" e enum:__anon72c4c37e0103 +WWDG_SR_EWIF_Msk target/stm32f103xb.h /^#define WWDG_SR_EWIF_Msk /;" d +WWDG_SR_EWIF_Pos target/stm32f103xb.h /^#define WWDG_SR_EWIF_Pos /;" d +WWDG_SR_EWIF target/stm32f103xb.h /^#define WWDG_SR_EWIF /;" d +WWDG_TypeDef target/stm32f103xb.h /^} WWDG_TypeDef;$/;" t typeref:struct:__anon72c4c37e1c08 +WWDG target/stm32f103xb.h /^#define WWDG /;" d +_Clock_t Untitled Folder/rcc.h /^typedef struct _Clock_t {$/;" s +_Clock_t drivers/rcc.h /^typedef struct _Clock_t {$/;" s +_IO_H_ drivers/io.h /^#define _IO_H_$/;" d +_RCC_H_ Untitled Folder/rcc.h /^#define _RCC_H_$/;" d +_RCC_H_ drivers/rcc.h /^#define _RCC_H_$/;" d +_TIMER_H_ drivers/timer.h /^#define _TIMER_H_$/;" d +__CM3_REV target/stm32f103xb.h /^#define __CM3_REV /;" d +__MPU_PRESENT target/stm32f103xb.h /^#define __MPU_PRESENT /;" d +__NVIC_PRIO_BITS target/stm32f103xb.h /^#define __NVIC_PRIO_BITS /;" d +__STM32F103xB_H target/stm32f103xb.h /^#define __STM32F103xB_H$/;" d +__STM32F1XX_H target/stm32f1xx.h /^#define __STM32F1XX_H$/;" d +__STM32F1_CMSIS_VERSION_MAIN target/stm32f1xx.h /^#define __STM32F1_CMSIS_VERSION_MAIN /;" d +__STM32F1_CMSIS_VERSION_RC target/stm32f1xx.h /^#define __STM32F1_CMSIS_VERSION_RC /;" d +__STM32F1_CMSIS_VERSION_SUB1 target/stm32f1xx.h /^#define __STM32F1_CMSIS_VERSION_SUB1 /;" d +__STM32F1_CMSIS_VERSION_SUB2 target/stm32f1xx.h /^#define __STM32F1_CMSIS_VERSION_SUB2 /;" d +__STM32F1_CMSIS_VERSION target/stm32f1xx.h /^#define __STM32F1_CMSIS_VERSION /;" d +__SYSTEM_STM32F10X_H target/system_stm32f1xx.h /^#define __SYSTEM_STM32F10X_H$/;" d +__SYS_HANDLERS_H_ Untitled Folder/sys_handlers.h /^#define __SYS_HANDLERS_H_$/;" d +__Vendor_SysTickConfig target/stm32f103xb.h /^#define __Vendor_SysTickConfig /;" d +__anon571959e70103 Untitled Folder/rcc.h /^enum {$/;" g +__anon72c4c37e0103 target/stm32f103xb.h /^{$/;" g +__anon72c4c37e0208 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0308 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0408 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0508 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0608 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0708 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0808 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0908 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0a08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0b08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0c08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0d08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0e08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e0f08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1008 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1108 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1208 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1308 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1408 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1508 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1608 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1708 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1808 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1908 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1a08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1b08 target/stm32f103xb.h /^{$/;" s +__anon72c4c37e1c08 target/stm32f103xb.h /^{$/;" s +__anonbccbea710103 target/stm32f1xx.h /^{$/;" g +__anonbccbea710203 target/stm32f1xx.h /^{$/;" g +__anonbccbea710303 target/stm32f1xx.h /^{$/;" g +_clock_config Untitled Folder/rcc.c /^static struct ClockConfig_t _clock_config[] = {$/;" v typeref:struct:ClockConfig_t[] file: +_clock_config drivers/rcc.c /^static struct ClockConfig_t _clock_config[] = {$/;" v typeref:struct:ClockConfig_t[] file: +ahb_freq Untitled Folder/rcc.c /^ uint32_t ahb_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +ahb_freq Untitled Folder/rcc.h /^ uint32_t ahb_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +ahb_freq drivers/rcc.c /^ uint32_t ahb_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +ahb_freq drivers/rcc.h /^ uint32_t ahb_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb1_freq Untitled Folder/rcc.c /^ uint32_t apb1_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +apb1_freq Untitled Folder/rcc.h /^ uint32_t apb1_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb1_freq drivers/rcc.c /^ uint32_t apb1_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +apb1_freq drivers/rcc.h /^ uint32_t apb1_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb1_timer_freq Untitled Folder/rcc.h /^ uint32_t apb1_timer_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb1_timer_freq drivers/rcc.h /^ uint32_t apb1_timer_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb2_freq Untitled Folder/rcc.c /^ uint32_t apb2_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +apb2_freq Untitled Folder/rcc.h /^ uint32_t apb2_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb2_freq drivers/rcc.c /^ uint32_t apb2_freq;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +apb2_freq drivers/rcc.h /^ uint32_t apb2_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb2_timer_freq Untitled Folder/rcc.h /^ uint32_t apb2_timer_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +apb2_timer_freq drivers/rcc.h /^ uint32_t apb2_timer_freq;$/;" m struct:_Clock_t typeref:typename:uint32_t +callback2 drivers/timer.c /^static OnTick callback2 = 0;$/;" v typeref:typename:OnTick file: +callback3 drivers/timer.c /^static OnTick callback3 = 0;$/;" v typeref:typename:OnTick file: +callback4 drivers/timer.c /^static OnTick callback4 = 0;$/;" v typeref:typename:OnTick file: +flash_cfg Untitled Folder/rcc.c /^ uint32_t flash_cfg;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +flash_cfg drivers/rcc.c /^ uint32_t flash_cfg;$/;" m struct:ClockConfig_t typeref:typename:uint32_t file: +hpre Untitled Folder/rcc.c /^ uint8_t hpre;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +hpre drivers/rcc.c /^ uint8_t hpre;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +io_cb drivers/io.c /^static OnIO io_cb[16]={$/;" v typeref:typename:OnIO[16] file: +io_clear drivers/io.c /^void io_clear(GPIO_TypeDef *gpio, uint16_t mask)$/;" f typeref:typename:void +io_configure drivers/io.c /^int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint32_t pin_cfg, $/;" f typeref:typename:int +io_read drivers/io.c /^uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask)$/;" f typeref:typename:uint32_t +io_set drivers/io.c /^void io_set(GPIO_TypeDef *gpio, uint16_t mask)$/;" f typeref:typename:void +io_write_n drivers/io.c /^void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask)$/;" f typeref:typename:void +io_write drivers/io.c /^void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask)$/;" f typeref:typename:void +main main.c /^int main(void) {$/;" f typeref:typename:int +pll_src Untitled Folder/rcc.c /^ uint8_t pll_src;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pll_src drivers/rcc.c /^ uint8_t pll_src;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pllm Untitled Folder/rcc.c /^ uint8_t pllm;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pllmul drivers/rcc.c /^ uint8_t pllmul;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +plln Untitled Folder/rcc.c /^ uint16_t plln;$/;" m struct:ClockConfig_t typeref:typename:uint16_t file: +pllp Untitled Folder/rcc.c /^ uint8_t pllp;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pllq Untitled Folder/rcc.c /^ uint8_t pllq;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pllr Untitled Folder/rcc.c /^ uint8_t pllr;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +power_save Untitled Folder/rcc.c /^ uint8_t power_save;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +ppre1 Untitled Folder/rcc.c /^ uint8_t ppre1;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +ppre1 drivers/rcc.c /^ uint8_t ppre1;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +ppre2 Untitled Folder/rcc.c /^ uint8_t ppre2;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +ppre2 drivers/rcc.c /^ uint8_t ppre2;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +pwm_start drivers/timer.h /^#define pwm_start(/;" d +pwm_stop drivers/timer.h /^#define pwm_stop(/;" d +rcc_config_clock Untitled Folder/rcc.c /^void rcc_config_clock(uint32_t config, Clock_t *sysclks)$/;" f typeref:typename:void +rcc_config_clock drivers/rcc.c /^void rcc_config_clock(uint32_t config, Clock_t *sysclks)$/;" f typeref:typename:void +rcc_osc_off Untitled Folder/rcc.c /^static void rcc_osc_off(enum rcc_osc osc)$/;" f typeref:typename:void file: +rcc_osc_off drivers/rcc.c /^static void rcc_osc_off(enum rcc_osc osc)$/;" f typeref:typename:void file: +rcc_osc_on Untitled Folder/rcc.c /^static void rcc_osc_on(enum rcc_osc osc)$/;" f typeref:typename:void file: +rcc_osc_on drivers/rcc.c /^static void rcc_osc_on(enum rcc_osc osc)$/;" f typeref:typename:void file: +rcc_osc Untitled Folder/rcc.c /^enum rcc_osc {$/;" g file: +rcc_osc drivers/rcc.c /^enum rcc_osc {$/;" g file: +rcc_set_sysclk Untitled Folder/rcc.c /^static void rcc_set_sysclk(enum rcc_osc osc)$/;" f typeref:typename:void file: +rcc_set_sysclk drivers/rcc.c /^static void rcc_set_sysclk(enum rcc_osc osc)$/;" f typeref:typename:void file: +sFIFOMailBox target/stm32f103xb.h /^ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];$/;" m struct:__anon72c4c37e0808 typeref:typename:CAN_FIFOMailBox_TypeDef[2] +sFilterRegister target/stm32f103xb.h /^ CAN_FilterRegister_TypeDef sFilterRegister[14];$/;" m struct:__anon72c4c37e0808 typeref:typename:CAN_FilterRegister_TypeDef[14] +sTxMailBox target/stm32f103xb.h /^ CAN_TxMailBox_TypeDef sTxMailBox[3];$/;" m struct:__anon72c4c37e0808 typeref:typename:CAN_TxMailBox_TypeDef[3] +sysclks main.c /^Clock_t sysclks;$/;" v typeref:typename:Clock_t +timeout_cb main.c /^static void timeout_cb(void) {$/;" f typeref:typename:void file: +timer_start drivers/timer.c /^void timer_start(TIM_TypeDef *tmr) {$/;" f typeref:typename:void +timer_stop drivers/timer.c /^void timer_stop(TIM_TypeDef *tmr) {$/;" f typeref:typename:void +timer_tick_init drivers/timer.c /^int timer_tick_init(TIM_TypeDef *tmr, uint32_t tick_ms, OnTick cb) {$/;" f typeref:typename:int +timer_tick_period drivers/timer.c /^int timer_tick_period(TIM_TypeDef *tmr, uint32_t tick_ms) {$/;" f typeref:typename:int +type Untitled Folder/rcc.c /^ uint8_t type;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +type drivers/rcc.c /^ uint8_t type;$/;" m struct:ClockConfig_t typeref:typename:uint8_t file: +val main.c /^int val = 0;$/;" v typeref:typename:int diff --git a/src/target/STM32F103XB.ld b/src/target/STM32F103XB.ld new file mode 100644 index 0000000..9d1604b --- /dev/null +++ b/src/target/STM32F103XB.ld @@ -0,0 +1,160 @@ +/* Linker script to configure memory regions. */ +/* 0xEC reserved for vectors - 8byte aligned = 0xF0 */ + + +STACK_SIZE = 0x400; + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K + RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4) +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/src/target/startup_stm32f103xb.s b/src/target/startup_stm32f103xb.s new file mode 100644 index 0000000..e429ded --- /dev/null +++ b/src/target/startup_stm32f103xb.s @@ -0,0 +1,371 @@ +/** + *************** (C) COPYRIGHT 2016 STMicroelectronics ************************ + * @file startup_stm32f103xb.s + * @author MCD Application Team + * @version V4.1.0 + * @date 29-April-2016 + * @brief STM32F103xB Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ +// bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + bl main + //bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/target/stm32f103xb.h b/src/target/stm32f103xb.h new file mode 100644 index 0000000..5bf8aa0 --- /dev/null +++ b/src/target/stm32f103xb.h @@ -0,0 +1,10642 @@ +/** + ****************************************************************************** + * @file stm32f103xb.h + * @author MCD Application Team + * @version V4.2.0 + * @date 31-March-2017 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f103xb + * @{ + */ + +#ifndef __STM32F103xB_H +#define __STM32F103xB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ +#define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "cmsis/core_cm3.h" +#include "system_stm32f1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + uint32_t RESERVED[16]; + __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ +} ADC_Common_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; + __IO uint32_t I2SCFGR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ + +#define RTC_BKP_NUMBER 10 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ +#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ +#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ +#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ +#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ +#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ +#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ +#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ +#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ +#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ +#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ +#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ +#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ +#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ +#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ +#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ +#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ +#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ +#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ +#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ +#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ +#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ +#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ +#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ +#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ +#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ +#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ +#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ + +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ + + /* Reference defines */ + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ + +#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ + +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ + + +#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ + + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ + +#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ + +#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ + +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ + + + + + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ +#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ + + + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ +#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ + +#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ +#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ + +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ + + +#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ + + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ + +#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ + +#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ + +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ + + + + + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ + +#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ +#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ +#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ + +#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ +#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ +#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ + +#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ +#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ +#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ + +#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ +#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ +#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ + +#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ +#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ +#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ + +#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ +#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ +#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ + +#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ +#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ +#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ + +#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ +#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ +#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ + +#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ +#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ +#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ + +#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ +#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ +#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ + +#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ +#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ +#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ + +#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ +#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ +#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ + +#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ +#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ +#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ + +#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ +#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ +#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ + +#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ +#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ +#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ +#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ +#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ + +#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ +#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ +#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ + +#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ +#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ +#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ + +#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ +#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ +#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ + +#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ +#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ +#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ + +#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ +#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ +#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ + +#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ +#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ +#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ + +#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ +#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ +#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ + +#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ +#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ +#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ + +#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ +#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ +#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ + +#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ +#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ +#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ + +#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ +#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ +#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ + +#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ +#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ +#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ + +#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ +#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ +#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ + +#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ +#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ +#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ + +#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ +#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ +#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ +#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ +#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ +#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ +#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ +#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ +#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ +#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ +#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ +#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ +#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ +#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ +#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ + +#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ +#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ +#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ +#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ +#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ +#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ +#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ +#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ +#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ +#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ + +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ +#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF18 EXTI_PR_PR18 + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOS) +#define ADC_SR_JEOC (ADC_SR_JEOS) + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ +#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ +#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ +#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ +#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ + +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ + +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ + + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) + /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ +#define STM32F103xB /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +//#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V4.2.0 + */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F1_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/target/system_clock.c b/src/target/system_clock.c new file mode 100644 index 0000000..cb0916b --- /dev/null +++ b/src/target/system_clock.c @@ -0,0 +1,109 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 8 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 36 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + */ + +#include "stm32f1xx.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= 0x00000001U; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#if !defined(STM32F105xC) && !defined(STM32F107xC) + RCC->CFGR &= 0xF8FF0000U; +#else + RCC->CFGR &= 0xF0FF0000U; +#endif /* STM32F105xC */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= 0xFF80FFFFU; + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEBFFFFFFU; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000U; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000U; +#elif defined(STM32F100xB) || defined(STM32F100xE) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000U; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000U; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000U; +#endif /* STM32F105xC */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ +#endif + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif + +} + diff --git a/src/target/system_stm32f1xx.h b/src/target/system_stm32f1xx.h new file mode 100644 index 0000000..f2557fa --- /dev/null +++ b/src/target/system_stm32f1xx.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V4.2.0 + * @date 31-March-2017 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/types_c.taghl b/src/types_c.taghl new file mode 100644 index 0000000..ab87ecc --- /dev/null +++ b/src/types_c.taghl @@ -0,0 +1,343 @@ +syn keyword CTagsStructure ClockConfig_t __anon72c4c37e0c08 __anon72c4c37e0708 __anon72c4c37e0608 __anon72c4c37e0408 __anon72c4c37e0308 __anon72c4c37e0a08 __anon72c4c37e1508 _Clock_t __anon72c4c37e0908 __anon72c4c37e1a08 __anon72c4c37e1008 __anon72c4c37e1608 __anon72c4c37e1308 __anon72c4c37e1708 __anon72c4c37e0e08 __anon72c4c37e0208 __anon72c4c37e0f08 __anon72c4c37e1408 __anon72c4c37e0d08 __anon72c4c37e1908 __anon72c4c37e0508 __anon72c4c37e0808 __anon72c4c37e0b08 __anon72c4c37e1c08 __anon72c4c37e1808 +syn keyword CTagsStructure __anon72c4c37e1208 __anon72c4c37e1b08 __anon72c4c37e1108 +syn keyword CTagsMember JDR2 plln FMR JDR4 CRL SMPR1 CRCPR pll_src pllmul WRP0 Data1 PSC apb1_freq RESP2 JDR3 RF0R sTxMailBox DR RESP3 CCER I2SCFGR AHBENR GTPR RDTR MCR CCR MSR IDR DCTRL JDR1 PRLH ISR CFR OBR BSRR PR RESERVED8 RDP EP4R CNTL CRH EVCR CMAR ppre1 BTABLE FA1R JOFR4 RESERVED3 EP1R JOFR3 LTR FIFOCNT SMCR FIFO type CR RESERVEDC DR10 JOFR1 SQR3 JOFR2 RESP1 CPAR CCR1 FFA1R WRP2 FTSR RIR EP0R CNTH CR1 RESP4 RESERVED2 power_save RESERVED0 SQR2 DCR FR2 BRR RDHR RTSR DCOUNT TRISE CR2 DR7 RCR FS1R TIR +syn keyword CTagsMember SR1 DIVL APB2ENR CCR3 AR CNT ARR EP7R RESERVED7 pllq SQR1 EXTICR apb2_freq HTR CCMR2 DLEN IER CMD DTIMER CCR2 CFGR ISTR RESERVED5 RESPCMD pllr OAR2 CCMR1 KR RF1R pllm EP2R OR SMPR2 STA TXCRCR FNR RTCCR TSR DR5 SR sFilterRegister SR2 IMR FR1 DR8 DR6 TDLR ESR WRPR CR3 ARG WRP3 BDTR DIER OPTKEYR RESERVEDA EP3R IFCR LCKR DMAR RESERVED1 RXCRCR IDCODE CIR EP6R FM1R sFIFOMailBox RESERVED6 DR2 JSQR DADDR apb2_timer_freq ppre2 WRP1 DIVH ODR DR4 USER DR3 POWER ICR OAR1 CCR4 RESERVED4 EMR CNTR +syn keyword CTagsMember DR1 BTR ALRL RESERVEDB KEYR RLR Data0 RDLR SWIER ahb_freq MAPR flash_cfg APB2RSTR EP5R ACR CSR BDCR CNDTR APB1ENR DR9 EGR hpre RESERVED9 APB1RSTR MASK TDTR CLKCR apb1_timer_freq RESERVED TDHR MAPR2 ALRH pllp PRLL +syn keyword CTagsGlobalVariable callback4 callback3 io_cb callback2 _clock_config val sysclks +syn keyword CTagsEnumeratorName __anon571959e70103 __anonbccbea710203 __anonbccbea710303 __anonbccbea710103 rcc_osc __anon72c4c37e0103 Clock_config +syn keyword CTagsEnumerationValue ADC1_2_IRQn EXTI15_10_IRQn PendSV_IRQn RTC_IRQn SVCall_IRQn CLOCK_CONFIG_PERFORMANCE TAMPER_IRQn I2C1_ER_IRQn USBWakeUp_IRQn USART2_IRQn TIM1_CC_IRQn TIM2_IRQn EXTI9_5_IRQn USB_LP_CAN1_RX0_IRQn TIM1_UP_IRQn DMA1_Channel2_IRQn ENABLE I2C1_EV_IRQn TIM4_IRQn CLOCK_CONFIG_POWERSAVE CLOCK_CONFIG_HSE_96MHz EXTI1_IRQn HardFault_IRQn MemoryManagement_IRQn RCC_IRQn DebugMonitor_IRQn USART1_IRQn USART3_IRQn BusFault_IRQn NonMaskableInt_IRQn I2C2_EV_IRQn RCC_PLL DMA1_Channel6_IRQn +syn keyword CTagsEnumerationValue TIM1_BRK_IRQn CAN1_RX1_IRQn CLOCK_CONFIG_HSI_16MHz RTC_Alarm_IRQn RCC_LSI CLOCK_CONFIG_HSE_84MHz PVD_IRQn CLOCK_CONFIG_HSI_48MHz RCC_LSE USB_HP_CAN1_TX_IRQn CLOCK_CONFIG_HSE_48MHz RCC_HSI SPI2_IRQn EXTI4_IRQn TIM1_TRG_COM_IRQn UsageFault_IRQn FLASH_IRQn ERROR I2C2_ER_IRQn DISABLE SysTick_IRQn SPI1_IRQn CLOCK_CONFIG_HSE_8MHz RCC_HSE SUCCESS CLOCK_CONFIG_HSI_96MHz RESET CAN1_SCE_IRQn CLOCK_CONFIG_END DMA1_Channel1_IRQn EXTI3_IRQn RCC_PLLI2S CLOCK_CONFIG_HSI_84MHz WWDG_IRQn +syn keyword CTagsEnumerationValue SET DMA1_Channel4_IRQn DMA1_Channel5_IRQn EXTI0_IRQn EXTI2_IRQn DMA1_Channel3_IRQn TIM3_IRQn DMA1_Channel7_IRQn +syn keyword CTagsFunction SVC_Handler EXTI15_10_IRQHandler TIM3_IRQHandler io_write EXTI3_IRQHandler DebugMon_Handler EXTI4_IRQHandler TIM2_IRQHandler rcc_set_sysclk timer_start io_set SystemInit EXTI2_IRQHandler io_read timer_stop SysTick_Handler rcc_config_clock MemManage_Handler EXTI0_IRQHandler io_configure timer_tick_period PendSV_Handler timer_tick_init HardFault_Handler main io_clear BusFault_Handler UsageFault_Handler timeout_cb TIM4_IRQHandler EXTI1_IRQHandler EXTI9_5_IRQHandler io_write_n +syn keyword CTagsFunction rcc_osc_on rcc_osc_off NMI_Handler +syn keyword CTagsType FunctionalState ADC_TypeDef CAN_TypeDef IWDG_TypeDef EXTI_TypeDef CAN_FIFOMailBox_TypeDef RTC_TypeDef SDIO_TypeDef I2C_TypeDef IRQn_Type DBGMCU_TypeDef CAN_TxMailBox_TypeDef Clock_t ITStatus FlagStatus DMA_TypeDef TIM_TypeDef USART_TypeDef OnTick WWDG_TypeDef USB_TypeDef GPIO_TypeDef CAN_FilterRegister_TypeDef CRC_TypeDef BKP_TypeDef DMA_Channel_TypeDef ErrorStatus RCC_TypeDef SPI_TypeDef AFIO_TypeDef PWR_TypeDef ADC_Common_TypeDef FLASH_TypeDef OB_TypeDef OnIO +syn keyword CTagsDefinedName CAN_F6R1_FB13 TIM_CCMR2_OC3PE CAN_F0R2_FB5_Pos CAN_TI0R_TXRQ_Pos CAN_F12R1_FB25 CAN_F13R1_FB7 I2C_CR1_START_Pos GPIO_LCKR_LCK6 GPIO_LCKR_LCK1_Pos ADC_SQR3_SQ4_Msk I2C_CR2_FREQ_3 CAN_TDL2R_DATA2_Msk AFIO_EVCR_PIN_PX11 CAN_F5R1_FB3_Pos CAN_F12R2_FB17 EXTI_EMR_EM14 ADC_DR_ADC2DATA RCC_APB2ENR_IOPDEN_Pos CAN_F3R1_FB18_Msk CAN_F10R2_FB10_Pos CAN_RDT1R_TIME_Msk USB_EP4R_EA_Msk EXTI_RTSR_TR10_Pos ADC_SQR2_SQ7_2 BKP_CSR_TIF_Msk TIM_CCMR1_IC1F_Pos USB_EPADDR_FIELD_Msk CAN_F1R2_FB30_Pos +syn keyword CTagsDefinedName CAN_F8R1_FB0_Msk CAN_F5R2_FB15_Msk CAN_TDH2R_DATA4_Msk ADC_SQR2_SQ8_3 SPI2_BASE CAN_ESR_BOFF_Pos CAN_TDH2R_DATA5_Pos EXTI_RTSR_TR2_Msk SPI_CR1_CRCNEXT_Pos DBGMCU_CR_DBG_STOP_Pos ADC_JSQR_JSQ3_3 RCC_CIR_HSERDYC ADC_JDR3_JDATA_Msk CAN_F3R1_FB15 CAN_F8R1_FB27 DMA_IFCR_CTCIF4_Msk CAN_F3R1_FB11 CAN_F5R1_FB12 AFIO_EVCR_PORT_PD CAN_F11R1_FB10 RTC_CRL_SECF_Pos EXTI_PR_PR0_Msk CAN_F11R2_FB10 CAN_F1R1_FB24_Pos I2C_CR1_PE_Pos CAN_F6R2_FB2 I2C_CR1_SMBTYPE CAN_F8R2_FB20_Msk GPIO_LCKR_LCK10 +syn keyword CTagsDefinedName CAN_F4R1_FB0_Pos CAN_F10R1_FB1 USART_CR1_UE_Pos SPI_SR_OVR_Pos SDIO_STA_TXFIFOF_Pos CAN_F0R1_FB20 ADC_LTR_LT CAN_F7R1_FB3_Msk EXTI_SWIER_SWIER12_Msk CAN_F11R2_FB2_Pos GPIO_CRL_CNF4_0 RCC_CSR_WWDGRSTF_Msk SDIO_MASK_CMDACTIE_Msk RTC_CRL_CNF_Pos CAN_RI0R_IDE SDIO_STA_RXOVERR CAN_F2R1_FB31_Msk CAN_RDT1R_FMI CAN_F9R1_FB19 AFIO_EXTICR4_EXTI13_PE_Msk TIM_SR_UIF CAN_F5R2_FB30 CAN_TDH1R_DATA7_Msk CAN_F12R1_FB12_Msk CAN_F7R2_FB21 SDIO_CMD_WAITRESP CAN_F10R2_FB29_Pos FLASH_BASE +syn keyword CTagsDefinedName USB_COUNT6_RX_1_NUM_BLOCK_1_1 CAN_F12R2_FB30_Pos CAN_FFA1R_FFA13_Pos CAN_F5R2_FB19 CAN_F4R1_FB7 SPI_SR_UDR_Msk EXTI_RTSR_TR4 AFIO_EXTICR4_EXTI13_PB_Msk AFIO_EXTICR2_EXTI5_PB_Pos CAN_FA1R_FACT8_Msk CAN_F12R1_FB20_Msk CAN_TDT2R_DLC USB_ADDR1_RX_ADDR1_RX EXTI_SWIER_SWIER4 EXTI_FTSR_FT12 EXTI_SWIER_SWIER11 IS_TIM_ETR_INSTANCE RCC_CFGR_PLLMULL7_Msk USB_COUNT3_TX_COUNT3_TX_Msk USB_COUNT4_RX_0_NUM_BLOCK_0_1 CAN_F1R2_FB27_Pos CAN_F5R1_FB25_Msk CAN_RDL1R_DATA2_Pos GPIO_CRH_CNF10_Pos +syn keyword CTagsDefinedName CAN_F2R1_FB11 USB_COUNT1_RX_BLSIZE CAN_F5R1_FB7_Pos ADC2 USB_FNR_LSOF CAN_F8R1_FB3 SDIO_MASK_TXFIFOHEIE_Msk CAN_F2R2_FB13 TIM_CCER_CC3NP_Pos USB_COUNT4_RX_NUM_BLOCK_Pos RCC_APB2ENR_IOPDEN USB_COUNT3_RX_COUNT3_RX_Pos CAN_F5R1_FB26_Pos RCC_CFGR_MCO_Msk CAN_F5R2_FB30_Msk I2C_SR2_BUSY_Msk RCC_CSR_RMVF_Pos CAN_F5R1_FB2 __NVIC_PRIO_BITS CAN_F5R1_FB31_Pos CAN_F9R1_FB14_Pos USB_COUNT1_RX_1_BLSIZE_1 CAN_F11R2_FB7_Msk USB_FNR_LCK_Msk GPIO_CRL_CNF2 USB_COUNT4_RX_NUM_BLOCK_0 CAN_F10R1_FB22 +syn keyword CTagsDefinedName CAN_F9R2_FB10 CAN_F12R2_FB25 CAN_F0R1_FB1 FLASH_WRP0_WRP0_Msk ADC_HTR_HT_Msk TIM_CR1_DIR_Pos PWR_CR_CSBF_Msk DBGMCU_CR_DBG_TIM1_STOP_Msk ADC_SQR1_SQ13_4 CAN_TDT1R_DLC RCC_APB1ENR_TIM2EN_Msk CAN_F9R1_FB0_Msk TIM_EGR_CC2G_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_0 USB_EP2R_CTR_RX_Msk GPIO_BSRR_BR12_Pos CAN_F12R1_FB5_Msk RCC_APB1ENR_TIM3EN_Msk CAN_F8R2_FB5 DMA1_Channel4 CAN_TDL1R_DATA0_Msk EXTI_RTSR_TR11_Pos CAN_F13R1_FB7_Pos PIN_OPT_AF14 TIM_EGR_CC2G_Msk CAN_F8R2_FB21 CAN_F12R1_FB17 +syn keyword CTagsDefinedName RCC_APB1ENR_I2C1EN_Msk PWR_CR_PLS_LEV0 RCC_APB1RSTR_I2C2RST_Pos CAN_F3R2_FB15 EXTI_SWIER_SWIER0_Msk CAN_F11R1_FB18 CAN_F8R1_FB21 CAN_MCR_RESET_Msk FLASH_RDP_RDP_Pos USB_ISTR_SUSP_Msk CAN_F0R1_FB24_Pos TIM_CCMR1_OC1M_2 AFIO_EVCR_PIN_PX3_Pos DMA_ISR_TEIF3_Pos USB_COUNT4_RX_NUM_BLOCK_1 DMA_ISR_GIF5_Msk CAN_F2R1_FB0_Pos SDIO_MASK_RXOVERRIE CAN_F10R2_FB14 CAN_F10R2_FB0 EXTI_SWIER_SWIER16_Msk I2C_TRISE_TRISE_Pos CAN_F11R1_FB0_Pos EXTI_SWIER_SWIER17_Msk CAN_RI0R_STID TIM_CCER_CC1E_Pos +syn keyword CTagsDefinedName CAN_F9R2_FB28 GPIO_CRL_CNF3_Msk BKP_CSR_TPIE_Pos CAN_F13R2_FB7_Msk CAN_F9R2_FB1_Msk CAN_F9R1_FB11_Pos CAN_F5R2_FB11_Pos RCC_CFGR_PLLMULL8 CAN_F2R1_FB15 CAN_F13R2_FB28 CAN_ESR_LEC_2 AFIO_EXTICR4_EXTI14_PE_Pos I2C3_IRQ_PRIORITY CAN_F1R1_FB7 CAN_F2R1_FB6 CAN_F4R1_FB15_Msk TIM_SMCR_ETF_3 RCC_CIR_LSERDYIE_Msk SPI_DR_DR_Msk BKP_DR3_D_Pos SDIO_CLKCR_WIDBUS_1 AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk CAN_F3R1_FB12_Msk USB_EP1R_SETUP_Pos SDIO_CMD_WAITINT_Msk GPIO_CRH_CNF_Pos +syn keyword CTagsDefinedName CAN_F0R1_FB5_Pos CAN_F7R1_FB18_Pos CAN_F13R2_FB27_Pos ADC_JSQR_JSQ1_3 SDIO_CMD_SDIOSUSPEND_Pos GPIO_ODR_ODR1_Pos SDIO_MASK_DTIMEOUTIE_Msk EXTI_RTSR_TR11_Msk AFIO_EXTICR4_EXTI14_PA CAN_FFA1R_FFA9_Pos CAN_F11R2_FB13_Msk CAN_RDH0R_DATA7 CAN_F0R2_FB12_Pos TIM_DIER_COMIE_Msk USB_EP0R_EA_Pos AFIO_EXTICR4_EXTI13 GPIO_IDR_IDR15_Msk AFIO_MAPR_TIM2_REMAP DMA_ISR_TCIF6_Pos SDIO_CMD_CMDINDEX_Pos CAN_F3R2_FB4_Pos TIM_SMCR_ETF_1 ADC_CR2_EXTSEL CAN_F8R2_FB30 USB_EP7R_CTR_RX_Pos +syn keyword CTagsDefinedName RCC_APB1RSTR_USART3RST_Pos RCC_CIR_LSIRDYF CAN_FS1R_FSC9 DMA_CCR_PSIZE CAN_F1R2_FB25_Msk CAN_F3R2_FB18_Pos RCC_CFGR_PLLMULL11_Msk ADC_CR2_EXTSEL_2 PWR_CR_PDDS SPI_CR1_SSI_Msk I2C_CR1_SWRST_Msk SPI_CR1_BR_Msk GPIO_BSRR_BS10_Msk I2C_CR1_ENPEC_Msk I2C_OAR1_ADDMODE_Pos TIM_CCR4_CCR4 APB1PERIPH_BASE DMA_ISR_GIF1 CAN_F1R1_FB6 DMA_ISR_HTIF6 GPIO_ODR_ODR11_Msk CAN_TDL0R_DATA1_Pos GPIOA_BASE CAN_F12R1_FB27_Msk CAN_FS1R_FSC5 EXTI_PR_PR2 PWR_CSR_WUF_Pos TIM_CCMR1_OC2CE_Msk EXTI_PR_PR8 +syn keyword CTagsDefinedName WWDG_SR_EWIF_Msk USB_COUNT5_RX_NUM_BLOCK_3 CAN1_RX0_IRQHandler CAN_F10R1_FB18_Pos CAN_F11R1_FB6 SDIO_STA_CMDSENT USB_EP_TYPE_MASK_Pos CAN_F12R2_FB7_Msk TIM_SR_CC1IF_Pos DMA_ISR_HTIF6_Pos RCC_CSR_PINRSTF_Msk SDIO_MASK_CCRCFAILIE EXTI_PR_PR11_Pos TIM_CCER_CC4P RCC_APB1ENR_USART3EN_Msk CAN_F5R1_FB5_Pos USB_COUNT4_RX_COUNT4_RX_Pos USB_COUNT6_RX_COUNT6_RX_Msk EXTI_SWIER_SWI10 TIM_BDTR_MOE_Msk TIM11_IRQHandler SDIO_ARG_CMDARG_Pos CAN_F12R1_FB23_Msk GPIO_CRL_CNF7_Pos +syn keyword CTagsDefinedName AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk FLASH_ACR_LATENCY_0 RCC_APB1RSTR_CAN1RST_Pos IS_GPIO_ALL_INSTANCE CAN_F10R2_FB21_Pos GPIO_CRL_CNF7_Msk CAN_F5R1_FB9_Pos CAN_F7R2_FB19_Msk RCC_APB1ENR_I2C2EN_Msk CRC_CR_RESET EXTI_EMR_MR8_Msk WWDG_BASE ADC_SMPR1_SMP11_1 CAN_F10R2_FB3 CAN_F3R2_FB12 PIN_OPT_IRQ_EDGE_RISE GPIO_BSRR_BR3_Pos RCC_CFGR_SW_Pos CAN_F13R1_FB13_Msk CAN_F7R1_FB12_Msk RCC_CFGR_HPRE_1 ADC_CR1_JEOSIE EXTI_FTSR_TR5_Pos RCC_CIR_HSIRDYC_Pos DBGMCU_CR_DBG_WWDG_STOP_Msk +syn keyword CTagsDefinedName USB_CNTR_FSUSP_Pos SDIO_ICR_DBCKENDC_Pos CAN_F10R2_FB10_Msk TIM_CCR2_CCR2_Msk USB_COUNT7_RX_NUM_BLOCK_1 USART_GTPR_PSC_6 CAN_F4R2_FB25_Pos CAN_RDH1R_DATA5_Msk USB_FNR_RXDP_Pos USB_EP4R_EP_KIND_Msk ADC_SMPR1_SMP10_Pos CAN_F2R1_FB16_Pos USART_SR_IDLE_Pos TIM_DIER_COMDE_Pos SDIO_MASK_CMDSENTIE_Pos CAN_F0R2_FB8 SDIO_MASK_SDIOITIE_Pos SDIO_CLKCR_CLKDIV_Msk EXTI_FTSR_FT0 AFIO_EXTICR4_EXTI12_PD EXTI_RTSR_TR10_Msk CAN_F1R1_FB26_Pos USART_SR_IDLE_Msk CAN_F5R1_FB16_Msk +syn keyword CTagsDefinedName RCC_APB1RSTR_PWRRST_Pos RCC_CFGR_PLLMULL8_Pos CAN_F11R2_FB18 USB_EP2R_STAT_RX_Pos CAN_F7R1_FB25 EXTI_PR_PR9 TIM_BDTR_BKE CAN_F10R1_FB13_Pos FLASH_OBR_USER_Pos RCC_APB1RSTR_USBRST_Pos GPIO_BRR_BR12_Msk GPIO_CRH_CNF14_Pos CAN_F8R2_FB10_Msk PIN_OPT_AF7 IS_DMA_ALL_INSTANCE GPIO_CRH_CNF14_0 ADC_SMPR1_SMP17_1 SDIO_STA_TXFIFOF_Msk CAN_F13R2_FB18 CAN_F6R1_FB23_Pos TIM_CCMR2_OC3CE CAN_BTR_TS1_2 DMA_ISR_TCIF1_Pos TIM_CR2_OIS4 EXTI_PR_PR1 I2C_CR1_ACK_Msk RCC_APB2ENR_USART1EN_Msk +syn keyword CTagsDefinedName TIM_DCR_DBL_1 RCC_CFGR_PPRE_DIV_2 CAN_F13R1_FB11_Pos RCC_CFGR_MCO_Pos CAN_F3R2_FB31_Pos TIM_SR_CC1OF_Msk USB_ADDR2_TX_ADDR2_TX_Pos USART_CR2_STOP ADC_SQR2_SQ7_Msk I2C_CR1_SWRST_Pos CAN_TI2R_RTR AFIO_EXTICR4_EXTI15_Pos CAN_F6R1_FB14_Pos EXTI_PR_PR3 USB_COUNT7_RX_0_COUNT7_RX_0 USART_CR3_DMAT_Msk CAN_FMR_FINIT_Msk CAN_F5R1_FB17_Msk CAN_F13R1_FB22_Pos CAN_F5R1_FB19 USART_CR1_TE_Pos BKP_DR5_D_Msk CAN_F8R1_FB22_Pos RCC_APB2RSTR_IOPCRST_Pos RCC_CFGR_PPRE_DIV_4 CAN_F8R2_FB22_Msk +syn keyword CTagsDefinedName GPIO_CRH_CNF12_0 CAN_F5R1_FB22_Msk AFIO_EXTICR4_EXTI15_PB_Msk I2C_SR2_PEC_Pos SDIO_STA_CCRCFAIL_Msk ADC_SQR1_SQ16_1 CAN_F13R1_FB10_Msk USB_EP1R_STAT_RX CAN_F4R2_FB18 EXTI_SWIER_SWIER18 RCC_CFGR_PLLMULL3 USB_EP6R_SETUP AFIO_MAPR_SWJ_CFG_0 CAN_F5R2_FB1_Pos AFIO_MAPR_SPI1_REMAP_Pos CAN_F11R2_FB3_Pos CAN_F12R1_FB11_Pos USB_EP_INTERRUPT SDIO_CLKCR_PWRSAV_Pos CAN_F12R2_FB23 CAN_F2R2_FB14_Msk BKP_RTCCR_ASOE CAN_F0R2_FB28_Msk TIM_SR_TIF_Pos CAN_MSR_SAMP_Msk USB_COUNT3_RX_NUM_BLOCK_Msk +syn keyword CTagsDefinedName CAN_F9R2_FB6 TIM_CCR1_CCR1_Pos IS_UART_HWFLOW_INSTANCE USB_EP5R_SETUP_Pos GPIO_CRH_MODE9_Pos CAN_F12R2_FB18 CAN_F13R1_FB21_Pos EXTI_FTSR_TR0_Pos BKP_RTCCR_ASOS_Msk CAN_F1R2_FB14_Pos AFIO_MAPR_PD01_REMAP RCC_CFGR_MCO_HSI DMA_ISR_HTIF4_Pos CAN_F10R2_FB24_Msk CAN_F9R1_FB30_Msk GPIO_BSRR_BR8_Pos CAN_F3R1_FB30_Pos CAN_IER_ERRIE_Msk CAN_RDL0R_DATA2_Msk DMA_ISR_TEIF5_Pos EXTI_FTSR_TR0 CAN_F9R1_FB31_Pos RCC_CSR_WWDGRSTF CAN_F1R1_FB2 CAN_FS1R_FSC0_Msk USB_EP0R_EP_TYPE_Pos +syn keyword CTagsDefinedName DMA_IFCR_CTEIF2_Msk CAN_F7R1_FB6_Pos USB_COUNT0_RX_NUM_BLOCK CAN_F10R1_FB13 GPIO_BSRR_BS14_Pos SPI_SR_UDR_Pos CAN_F2R1_FB13_Msk RCC_CFGR_PLLMULL10_Msk USB_EP5R_STAT_RX_1 USB_EP2R_DTOG_RX_Msk CAN_F4R1_FB20_Pos SDIO_CLKCR_BYPASS_Msk ADC_JSQR_JSQ2_Pos AFIO_EXTICR4_EXTI12_PD_Pos CAN_F12R1_FB21_Pos USB_COUNT7_RX_0_NUM_BLOCK_0 CAN_F3R2_FB29_Pos GPIO_LCKR_LCK14 ADC_SQR3_SQ2 GPIO_CRH_MODE10_Pos GPIO_ODR_ODR0_Pos CAN_F4R2_FB4_Pos GPIO_BSRR_BS0_Msk RCC_CR_PLLON_Pos USB_EP6R CAN_FS1R_FSC2 +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI15_PC_Msk CAN_F7R2_FB10_Msk TIM_CR1_UDIS_Pos USB_COUNT6_RX_NUM_BLOCK_2 CAN_F6R2_FB24_Pos CAN_TSR_ABRQ0_Msk USB_EP4R USB_EP5R_EP_TYPE CAN_F12R2_FB23_Msk CAN_MSR_SLAKI_Msk CAN_F7R2_FB7 SDIO_MASK_RXFIFOEIE_Msk USART_CR3_IREN_Msk AFIO_EXTICR1_EXTI0_PC_Msk SDIO_DCTRL_DTMODE RCC_APB2ENR_ADC1EN_Pos SPI_CR2_RXNEIE_Pos TIM_CR1_CKD_Msk ADC_JSQR_JSQ3 CAN_FMR_FINIT CAN_F6R2_FB25_Pos EXTI_RTSR_TR4_Pos CAN_F11R1_FB5_Pos RCC_CFGR_HPRE_DIV_NONE EXTI_EMR_MR10 +syn keyword CTagsDefinedName EXTI_SWIER_SWIER9_Msk USB_BTABLE_BTABLE_Pos CAN_F6R2_FB12_Msk CAN_F1R1_FB8_Pos TIM_DCR_DBA_Pos FLASH_SR_WRPRTERR ADC_CR2_JEXTSEL_Msk EXTI_SWIER_SWIER1_Pos CAN_F13R2_FB13 EXTI_EMR_MR14 TIM_SMCR_SMS ADC_JSQR_JSQ3_Msk USB_COUNT2_TX_COUNT2_TX_Msk USB_EP1R_STAT_RX_1 CAN_F10R2_FB28_Pos RTC_CRL_RTOFF_Msk TIM_CCMR1_IC2F_2 RCC_CFGR_PLLMULL8_Msk RCC_APB1ENR_USART3EN RCC_CFGR_SWS_Pos FLASH_KEYR_FKEYR_Pos I2C_OAR1_ADD8 CAN_F10R2_FB16 DMA_IFCR_CGIF1_Msk SDIO_STA_RXFIFOF EXTI_IMR_MR9_Pos +syn keyword CTagsDefinedName USB_EP0R_SETUP_Msk TIM_CCER_CC2NP TIM_CCER_CC1NP_Pos CAN_FM1R_FBM8_Msk CAN_FA1R_FACT3_Pos CAN_F9R1_FB28_Pos CAN_F7R1_FB22_Pos RCC_CFGR_MCOSEL_PLL_DIV2 CAN_F9R1_FB21_Pos DMA_IFCR_CGIF3_Pos AFIO_EXTICR1_EXTI2_PC_Msk SDIO_BASE CAN_F5R1_FB16 RCC_APB1ENR_BKPEN_Pos CAN_F5R1_FB6 CAN_F8R1_FB26 USB_COUNT7_RX_COUNT7_RX_Pos TIM10_IRQHandler SDIO_MASK_TXDAVLIE BKP_RTCCR_CCO CAN_F6R1_FB28_Pos AFIO_EVCR_PIN_PX3_Msk GPIO_BRR_BR9_Msk CAN_F9R2_FB2_Msk CAN_TSR_LOW0_Msk AFIO_EXTICR3_EXTI10_PC_Pos +syn keyword CTagsDefinedName I2C_SR2_PEC USART_BRR_DIV_Mantissa_Msk CAN_F11R1_FB8 CAN_F3R1_FB20 USB_DADDR_ADD1_Pos RCC_CR_HSEBYP_Pos AFIO_EXTICR1_EXTI1_PC_Pos EXTI_SWIER_SWI15 CAN_F9R2_FB14 CAN_F2R1_FB7 CAN_FA1R_FACT4_Msk RCC_AHBENR_DMA1EN_Msk AFIO_EXTICR1_EXTI3_PB CAN_F1R1_FB22_Msk CAN_F1R1_FB13_Pos ADC_CR2_JEXTTRIG_Msk USB_EP2R_CTR_RX_Pos CAN_F12R2_FB1 TIM_CCMR2_IC4PSC_0 AFIO_MAPR_SWJ_CFG_DISABLE_Msk AFIO_EXTICR1_EXTI3_PF_Pos CAN_TI1R_STID_Msk RCC_APB2RSTR_IOPERST DMA_ISR_TEIF7_Pos CAN_F7R1_FB20_Pos +syn keyword CTagsDefinedName USB_EP3R_CTR_RX_Msk CAN_F4R2_FB18_Pos CAN_F1R1_FB17_Msk CAN_FM1R_FBM12 CAN_F5R2_FB28 CAN_F6R1_FB13_Msk SDIO_ICR_CCRCFAILC ADC_SMPR2_SMP2_Pos USB_COUNT1_RX_BLSIZE_Pos CAN_F12R1_FB6_Pos USB_DADDR_ADD0_Msk CAN_FS1R_FSC1_Msk DMA_CCR_HTIE_Msk AFIO_EXTICR4_EXTI13_PF_Pos CAN_F8R2_FB16_Msk CAN_F13R1_FB15_Msk GPIO_CRH_MODE12_1 CAN_F12R1_FB2_Msk CAN_F9R1_FB22 CAN_F4R1_FB17_Msk EXTI_IMR_MR16 CAN_F5R2_FB2_Pos CAN_F6R1_FB0_Msk DBGMCU_CR_DBG_TIM3_STOP_Pos GPIO_IDR_IDR9_Pos CAN_F13R2_FB14_Msk +syn keyword CTagsDefinedName CAN_F3R1_FB14 RCC_CR_HSITRIM_Msk CAN_FA1R_FACT0_Pos EXTI_PR_PR8_Pos CAN_RF0R_FOVR0 CAN_F5R2_FB21_Msk RCC_CFGR_PLLMULL_Msk CAN_F4R2_FB10 CAN_F5R1_FB13_Msk IS_TIM_CC1_INSTANCE RCC_CSR_LPWRRSTF_Msk CAN_TI2R_EXID USART_CR1_IDLEIE_Pos AFIO_EXTICR4_EXTI14_PC CAN_F9R1_FB6 TIM_CCER_CC3P CAN_F9R1_FB18_Pos AFIO_EXTICR1_EXTI2_PD_Msk SDIO_STA_CMDACT CAN_RF0R_FMP0_Msk CAN_F13R2_FB12 CAN_F6R2_FB29 USB_CNTR_PDWN RCC_APB2RSTR_IOPBRST_Pos SDIO_ICR_DATAENDC_Pos AFIO_EXTICR1_EXTI3_PF_Msk +syn keyword CTagsDefinedName CAN_F9R2_FB20 RCC_APB1ENR_I2C1EN CAN_F8R1_FB12_Pos EXTI_RTSR_TR14 GPIO_BRR_BR9 CAN_TSR_TXOK0 ADC_JDR4_JDATA_Msk ADC_SMPR2_SMP2_1 ADC_SR_EOS WWDG_CR_T_Pos CAN_F10R1_FB25_Pos EXTI_IMR_MR3_Pos SDIO_STA_RXACT FLASH_KEY1 CAN_F2R1_FB2_Msk DMA1_Channel2 CAN_F2R1_FB13 USB_EP6R_EP_KIND CAN_F3R1_FB29 CAN_TDH0R_DATA4 ADC_SQR1_SQ13_2 CAN_F12R1_FB30_Pos RTC_CNTH_RTC_CNT_Msk USB_COUNT3_RX_NUM_BLOCK_0 USB_ADDR7_RX_ADDR7_RX_Pos RCC_CFGR_PLLMULL3_Msk CAN_F7R1_FB10 DBGMCU_CR_DBG_TIM1_STOP_Pos +syn keyword CTagsDefinedName ADC_SMPR1_SMP15 ADC_JOFR2_JOFFSET2 CAN_F1R1_FB10_Msk FLASH_SR_PGERR_Msk ADC_CR2_JSWSTART CAN_F0R1_FB8_Pos CAN_F8R1_FB10_Pos IS_TIM_SLAVE_INSTANCE AFIO_EVCR_PIN_PX5_Msk EXTI_IMR_IM3 SDIO_MASK_CMDRENDIE EXTI_SWIER_SWIER6_Msk CAN_F11R2_FB11_Msk DBGMCU_IDCODE_REV_ID_9 CAN_F13R2_FB17_Pos EXTI_RTSR_TR12_Pos CAN_F8R1_FB14 CAN_F7R1_FB21_Msk I2C_SR1_OVR_Pos CAN_FFA1R_FFA0_Msk IS_IWDG_ALL_INSTANCE EXTI_RTSR_TR0 USART_SR_RXNE_Msk ADC_JSQR_JSQ2_3 CAN_F7R1_FB0_Msk CAN_F1R1_FB2_Msk +syn keyword CTagsDefinedName EXTI_EMR_MR10_Pos RTC_ALRH_RTC_ALR CAN_F1R2_FB1_Msk TIM_SMCR_ETPS_0 USB_EP6R_STAT_RX_1 EXTI_SWIER_SWIER10 USART_CR2_LBDIE_Pos AFIO_MAPR_USART3_REMAP_Msk CAN_F7R1_FB27 DMA_ISR_TEIF2_Msk IWDG_PR_PR_2 DMA_ISR_HTIF5 CAN_RF0R_FULL0_Msk TIM_CR2_OIS1_Pos CAN_F9R1_FB10_Pos GPIO_CRH_CNF15_Msk GPIO_BRR_BR10_Pos CAN_F5R2_FB6_Pos TIM_CCER_CC2P_Pos CAN_F1R2_FB18 CAN_F4R1_FB23 RCC_APB1RSTR_TIM2RST_Msk I2C_SR2_TRA_Pos FLASH_CR_STRT_Msk CAN_F11R1_FB15_Msk CAN_FM1R_FBM11_Pos ADC_JSQR_JSQ4_Pos +syn keyword CTagsDefinedName GPIO_IDR_IDR10_Msk AFIO_EXTICR1_EXTI3_PG_Pos SDIO_RESP1_CARDSTATUS1_Msk SPI_CR1_CRCNEXT RCC_BDCR_BDRST DMA_ISR_TEIF4_Msk CAN_F12R2_FB29 DMA_ISR_HTIF7_Pos CAN_FS1R_FSC7 PIN_OPT_OUTPUT_SPEED_MEDIUM I2C_SR1_AF_Msk CAN_F10R2_FB11_Msk CAN_F4R1_FB4 CAN_F13R1_FB2_Msk AFIO_EXTICR3_EXTI9_PA GPIO_CRL_MODE5_0 TIM_EGR_CC4G_Pos USB_CNTR_CTRM SDIO_DCOUNT_DATACOUNT SPI_SR_CRCERR_Msk CAN_F2R2_FB1_Pos USB_EP5R_STAT_TX_Msk DMA_IFCR_CTEIF4 EXTI_EMR_EM9 CAN_F5R1_FB6_Msk FLASH_WRP3_WRP3_Pos +syn keyword CTagsDefinedName CAN_F4R2_FB31 RCC_APB1ENR_BKPEN ADC_SQR1_SQ16_0 CAN_F7R2_FB24_Pos CAN_F12R1_FB25_Msk CAN_F12R1_FB5_Pos CAN_F8R1_FB8_Msk AFIO_EXTICR1_EXTI1_PE_Pos CAN_F0R2_FB9_Pos USB_DADDR_ADD5 CAN_F9R1_FB31 EXTI_IMR_MR7_Msk CAN_F5R1_FB11_Pos TIM_BDTR_DTG_4 CAN_F4R1_FB7_Pos CAN_F7R1_FB16_Msk ADC_JSQR_JSQ4_Msk CAN_F8R1_FB15_Pos CAN_F9R1_FB8_Pos SPI_SR_OVR_Msk RCC_CIR_CSSC TIM_BDTR_DTG_Msk CAN_TDL2R_DATA2 AFIO_EVCR_PORT_PE CAN_F8R1_FB18 GPIO_BRR_BR6_Msk CAN_F12R2_FB15_Msk CAN_F2R2_FB16_Pos +syn keyword CTagsDefinedName SPI_CR1_LSBFIRST_Msk CAN_F9R1_FB30_Pos EXTI_SWIER_SWI17 SDIO_MASK_CMDACTIE SDIO_FIFO_FIFODATA_Pos CAN_F8R1_FB10_Msk USB_ADDR2_TX_ADDR2_TX_Msk AFIO_EXTICR3_EXTI8_PA USB_EP5R_CTR_RX_Pos USB_COUNT6_RX_COUNT6_RX_Pos TIM_CCMR2_IC3PSC_Pos CAN_F10R2_FB7_Pos CAN_F4R1_FB27 I2C_CR1_NOSTRETCH_Msk CAN_FM1R_FBM9 CAN_TDT2R_TGT_Msk CAN_F8R2_FB15 CAN_F12R1_FB7 CAN_F4R1_FB23_Pos GPIO_CRL_CNF2_Pos USB_ISTR_PMAOVR_Pos FLASH_ACR_PRFTBS DMA_ISR_HTIF1_Pos CAN_F5R2_FB23_Msk CAN_F1R2_FB9_Pos +syn keyword CTagsDefinedName CAN_F6R1_FB24_Msk USB_ISTR_RESET_Pos CAN_BTR_TS2 RCC_APB1ENR_BKPEN_Msk I2C_SR1_AF_Pos CAN_F5R2_FB3_Msk AFIO_EXTICR4_EXTI12_Msk CAN_F6R1_FB5_Msk USB_EP5R_STAT_TX_0 CAN_F12R1_FB26_Pos CAN_IER_FFIE0 RCC_CFGR_PLLMULL5 RCC_APB2RSTR_IOPERST_Msk EXTI_IMR_IM1 TIM_CR2_OIS3_Pos RCC_CFGR_PLLMULL13 CAN_F9R1_FB0 SDIO_MASK_TXFIFOEIE WWDG_CR_T TIM1_TRG_COM_TIM11_IRQHandler IS_TIM_CLOCK_DIVISION_INSTANCE USB_COUNT7_RX_0_BLSIZE_0 SDIO_FIFOCNT_FIFOCOUNT CAN_F8R1_FB1_Msk GPIO_IDR_IDR2_Msk +syn keyword CTagsDefinedName SDIO_RESPCMD_RESPCMD_Msk CAN_F12R1_FB28_Msk CAN_RDH1R_DATA4_Msk CAN_F9R1_FB17_Msk IS_TIM_XOR_INSTANCE USB_EP6R_SETUP_Msk CAN_TDL0R_DATA3_Msk CAN_F2R2_FB4_Msk RCC_APB2ENR_IOPEEN_Msk USB_COUNT0_RX_BLSIZE_Msk DMA1_Channel7 RCC_CIR_CSSC_Msk EXTI_IMR_MR11 RTC_CRL_RSF_Msk CAN_F7R2_FB22_Msk RCC_CFGR_PLLMULL_0 TIM_CCMR2_OC4FE __STM32F1_CMSIS_VERSION_SUB1 IS_IRDA_INSTANCE CAN_F7R1_FB2_Pos ADC_SQR2_SQ9_Msk CAN_RDH1R_DATA5 CAN_F3R2_FB24_Pos EXTI_IMR_MR8_Pos CAN_F3R1_FB20_Msk +syn keyword CTagsDefinedName TIM_CR2_OIS3N_Msk CAN_F6R2_FB22 USB_CNTR_ERRM_Pos AFIO_EXTICR4_EXTI15_PC_Pos AFIO_MAPR_TIM1_REMAP_0 USB_EP_CTR_RX_Msk SET_BIT GPIO_CRH_MODE8_Pos TIM_DIER_UIE PWR_CR_PLS_2V8 USART_BRR_DIV_Fraction_Pos TIM_CCER_CC3NP CAN_F2R2_FB6_Msk CAN_F6R1_FB6_Pos EXTI_EMR_MR17 CAN_F7R2_FB29_Msk USB_DADDR_EF_Pos CAN_F8R2_FB8 RCC_CFGR_PPRE1_DIV2 GPIO_CRL_MODE5_Msk CAN_F3R2_FB0_Pos CAN_F12R2_FB10_Msk CAN_F0R2_FB13_Pos CAN_F12R1_FB7_Msk USART_SR_ORE_Msk TIM_CCMR2_OC3CE_Pos TIM_CCMR2_OC3M +syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI2_PE_Msk CAN_F3R1_FB20_Pos SYSCFG_EXTI_PH_MASK SPI_CR1_SSM_Pos EXTI_PR_PR14 RTC_CRL_ALRF_Pos CAN_F0R2_FB1_Msk SDIO_ICR_CTIMEOUTC_Msk CAN_F7R2_FB21_Msk CAN_FA1R_FACT9 CAN_F9R2_FB14_Pos SDIO_ICR_CEATAENDC_Msk USB_COUNT0_RX_NUM_BLOCK_3 I2C_SR1_SB_Pos TIM_DIER_CC2DE_Msk RCC_APB2ENR_IOPBEN EXTI_IMR_MR13_Msk CAN_TDL1R_DATA0 SDIO_CLKCR_WIDBUS_Msk ADC_SMPR2_SMP2_Msk CAN_F3R2_FB22_Msk CAN_F4R2_FB12 EXTI_IMR_MR12 FLASH_CR_ERRIE CAN_F7R2_FB28_Msk BKP_DR7_D_Pos +syn keyword CTagsDefinedName DMA_IFCR_CHTIF2_Pos CAN_F9R1_FB27 CAN_F9R2_FB27_Msk DMA_ISR_TCIF3_Msk CAN_F12R2_FB14 ADC_SQR2_SQ10_Pos CAN_F3R1_FB7 CAN_FM1R_FBM0_Pos RCC_CFGR_SW_HSE CAN_F0R1_FB12 USB_EP_T_FIELD_Msk CAN_F5R2_FB22_Msk CAN_F3R2_FB27 AFIO_EXTICR3_EXTI11_PD_Msk I2C_CR1_ALERT_Pos IS_TIM_MASTER_INSTANCE CAN_F1R1_FB29 USB_EP1R ADC_CR1_AWDCH_2 CAN_F3R1_FB4_Pos CAN_F12R1_FB17_Pos ADC_JDR1_JDATA EXTI_IMR_IM17 GPIO_LCKR_LCK2_Pos AFIO_EXTICR4_EXTI13_PD_Pos DMA_CCR_MEM2MEM_Msk TIM_DMAR_DMAB_Msk +syn keyword CTagsDefinedName CAN_F9R1_FB28_Msk USART_CR1_RE_Msk SDIO_MASK_RXDAVLIE_Pos CAN_F7R1_FB23 CAN_F10R2_FB23_Msk CAN_F0R2_FB9 ADC_JOFR4_JOFFSET4_Pos EXTI_RTSR_RT8 CAN_F9R1_FB19_Msk FLASH_WRP2_WRP2_Pos USB_EP1R_CTR_RX_Pos I2C_OAR1_ADD6 EXTI_RTSR_RT15 GPIO_CRL_MODE4_Pos TIM_CCER_CC3P_Msk CAN_F9R2_FB8_Msk CAN_F8R2_FB17_Pos CAN_F12R1_FB11_Msk SDIO_CMD_CPSMEN_Pos RCC_BDCR_LSEBYP_Msk CAN_F2R1_FB19_Msk GPIO_CRH_CNF13_Msk BKP_RTCCR_CAL I2C_OAR1_ADD0_Pos TIM_DCR_DBA_0 TIM1_BRK_TIM15_IRQHandler +syn keyword CTagsDefinedName USB_EP7R_DTOG_RX_Pos RCC_APB1RSTR_USART2RST_Pos CAN_F13R2_FB8_Pos TIM_CCER_CC2P I2C_SR1_TXE_Msk I2C_OAR2_ENDUAL_Msk CAN_F5R2_FB8_Pos CAN_F10R1_FB24_Msk FLASH_CR_OPTPG_Msk USART_DR_DR_Pos CAN_F11R2_FB25_Pos CAN_F6R2_FB29_Pos TIM_CCMR1_CC2S_1 GPIO_CRH_MODE13_1 CAN_MCR_TTCM ADC_SQR2_SQ12_Msk CAN_FFA1R_FFA5_Pos CAN_F4R2_FB15 I2C_CR1_SWRST CAN_ESR_EWGF_Pos PIN_8 USB_EP5R_EA USB_COUNT5_RX_NUM_BLOCK_1 TIM_CCMR1_IC1F_2 CAN_F12R1_FB27_Pos EXTI_IMR_MR6_Msk SPI_SR_RXNE_Pos BKP_CSR_CTE_Msk +syn keyword CTagsDefinedName ADC_SMPR1_SMP14_2 CAN_F9R2_FB25_Pos CAN_TI0R_STID_Msk ADC_SQR3_SQ1_0 CAN_F5R1_FB8_Msk CAN_F3R2_FB1 TIM_CCR4_CCR4_Msk CAN_F12R1_FB19_Pos USART_GTPR_PSC CAN_RDH1R_DATA6_Pos TIM_CCMR2_OC4M_2 ADC_SQR3_SQ2_0 CAN_F3R1_FB18 DMA_IFCR_CHTIF6_Pos AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos CAN_F3R2_FB15_Pos CAN_TDH2R_DATA4_Pos USART_BRR_DIV_Fraction_Msk CAN_F11R2_FB12_Msk CAN_F0R1_FB9_Pos EXTI_RTSR_TR18_Msk I2C_CR2_FREQ_Pos GPIO_CRL_MODE6 SPI_CR2_ERRIE_Msk ADC_SR_EOC AFIO_EVCR_PORT_0 +syn keyword CTagsDefinedName CAN_F9R2_FB31_Msk CAN_F5R2_FB0 CAN_F11R1_FB4 CAN_F13R2_FB2_Pos CAN_F2R2_FB18 CAN_BTR_SJW_Msk GPIO_BSRR_BS13_Msk CAN_F7R1_FB15_Msk DMA_CCR_DIR_Msk EXTI_SWIER_SWIER10_Msk TIM_CCMR2_CC4S GPIO_CRL_MODE0_Msk CAN_F8R1_FB13_Msk CAN_F4R1_FB19_Pos PIN_OPT_RESISTOR_NONE TIM_CCMR2_OC3PE_Msk CAN_TI0R_EXID_Pos USB_CNTR_WKUPM_Msk CAN_F12R1_FB13 CAN_F12R1_FB26 GPIO_ODR_ODR1_Msk CAN_RI0R_RTR_Msk USB_ADDR3_TX_ADDR3_TX EXTI_SWIER_SWI12 ADC_JSQR_JSQ4_1 CAN_F0R2_FB28_Pos I2C_SR1_ADD10_Pos +syn keyword CTagsDefinedName EXTI_EMR_MR7 ADC_CR1_JAWDEN_Msk FLASH_DATA1_nDATA1_Pos PERIPH_BB_BASE RTC_PRLL_PRL_Msk USB_DADDR_ADD5_Pos CAN_F4R2_FB2_Msk TIM_PSC_PSC_Pos EXTI_IMR_MR8_Msk CAN_F5R1_FB25 CAN_ESR_LEC_1 CAN_F11R1_FB20_Pos CAN_F6R2_FB14_Pos CAN_F0R1_FB31_Msk USB_ISTR_ESOF CAN_F12R1_FB14_Msk CAN_F2R1_FB9_Msk SDIO_ICR_RXOVERRC_Msk CAN_F8R1_FB17 EXTI_FTSR_TR1 GPIO_CRL_MODE2_Msk SDIO_MASK_STBITERRIE_Pos CAN_F13R2_FB19 USB_COUNT6_RX_NUM_BLOCK_4 CAN_F1R2_FB7_Msk CAN_F4R1_FB3_Pos GPIO_BRR_BR1_Pos +syn keyword CTagsDefinedName EXTI_PR_PIF5 CAN_F2R1_FB3_Pos GPIO_BRR_BR3_Msk CAN_F1R2_FB28 CAN_F10R1_FB27_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_0 CAN_F6R1_FB26_Msk DMA_ISR_TCIF7_Pos RCC_CFGR_PPRE1_DIV8 CAN_F13R2_FB4_Pos USB_EP6R_EP_TYPE_Pos AFIO_EXTICR1_EXTI3_PG FLASH_CR_PG_Pos I2C_SR1_OVR EXTI_EMR_MR17_Pos CAN_F4R1_FB20 CAN_F0R2_FB26 ADC_SQR3_SQ5_Msk CAN_F2R1_FB15_Msk GPIO_LCKR_LCK1_Msk ADC_CR2_JEXTSEL AFIO_EXTICR2_EXTI5_PF_Pos EXTI_EMR_EM5 IS_GPIO_AF_INSTANCE RCC_CR_PLLRDY_Msk RTC_CRL_SECF_Msk +syn keyword CTagsDefinedName USB_EP6R_DTOG_RX_Msk GPIO_ODR_ODR3_Msk CAN_F9R2_FB15_Pos CAN_F3R2_FB26_Pos EXTI_PR_PR16 SDIO_ICR_DATAENDC USB_DADDR_EF USB_COUNT5_RX_COUNT5_RX GPIO_CRL_CNF2_0 ADC_JOFR1_JOFFSET1_Msk CAN_FFA1R_FFA6_Msk CAN_IER_FOVIE0_Pos CAN_F2R2_FB2 CAN_F10R2_FB8 TIM_RCR_REP_Pos GPIO_LCKR_LCK0 GPIO_IDR_IDR0_Pos DMA_CCR_CIRC_Pos GPIO_BRR_BR3_Pos GPIO_CRL_CNF6_Msk PIN_OPT_AF4 AFIO_EXTICR4_EXTI13_PB EXTI_EMR_MR3 SDIO_CMD_ENCMDCOMPL_Msk USB_EPTX_DTOG1 ADC_CR1_JAUTO TIM_DCR_DBA_3 USB_DADDR_ADD3 +syn keyword CTagsDefinedName USB_COUNT7_RX_NUM_BLOCK_3 USB_COUNT4_RX_BLSIZE USB_ADDR5_TX_ADDR5_TX USB_EP6R_CTR_TX_Pos CAN_F4R2_FB17 AFIO_EXTICR3_EXTI10_Msk TIM_DIER_CC4IE CAN_F8R2_FB28_Msk SDIO_DCTRL_DBLOCKSIZE_Msk TIM_DIER_TIE_Pos SPI_CRCPR_CRCPOLY_Pos TIM_DIER_CC4DE_Msk CAN_F9R2_FB13_Msk SDIO_STA_RXFIFOF_Pos CAN_F6R2_FB27_Pos PIN_OPT_AF1 SRAM_BASE CAN_F13R1_FB4_Msk CAN_F5R2_FB13 DMA_IFCR_CTCIF1_Msk BKP_DR7_D_Msk CAN_FM1R_FBM5_Pos I2C1_IRQERR_PRIORITY RCC_CR_HSEBYP FLASH_RDP_nRDP_Msk SDIO_STA_RXFIFOE_Msk +syn keyword CTagsDefinedName CAN_TDT1R_TGT_Pos WWDG_SR_EWIF RCC_APB1RSTR_SPI2RST AFIO_EVCR_PORT CAN_F8R2_FB30_Pos TIM_CCMR1_IC1F_0 CAN_F2R1_FB3_Msk CAN_F6R2_FB28 CAN_F10R1_FB23 I2C_SR1_ADDR_Msk CAN_F8R1_FB0_Pos CAN_F9R1_FB8 DMA_IFCR_CHTIF7 CAN_F8R1_FB31_Msk TIM3_IRQ_PRIORITY CAN_F1R1_FB1_Pos SDIO_MASK_DATAENDIE_Pos RCC_APB1RSTR_PWRRST CAN_FS1R_FSC9_Pos CAN_F9R2_FB11_Pos CAN_F8R2_FB26 GPIO_CRH_MODE13_Pos CAN_RDT0R_TIME_Pos USB_EP2R_EP_KIND CAN_FMR_CAN2SB DMA_IFCR_CTEIF5 CAN_RDT1R_DLC_Msk CAN_F6R1_FB15_Msk +syn keyword CTagsDefinedName TIM_DIER_CC3IE_Pos CAN_F1R1_FB15_Pos TIM2 DMA_ISR_HTIF2_Pos AFIO_MAPR_CAN_REMAP_Pos CAN_F4R2_FB21_Msk CAN_IER_ERRIE BKP_DR8_D_Pos CAN_F2R2_FB21 USB_HP_IRQn TIM_CCER_CC4P_Pos CAN_MSR_RX TIM_SR_BIF_Pos CAN_F3R2_FB11 I2C_CCR_DUTY EXTI_FTSR_TR4_Pos GPIO_CRH_CNF9_1 TIM_CCMR1_CC1S GPIO_IDR_IDR7_Pos USB_ADDR4_RX_ADDR4_RX CAN_F13R1_FB9 RTC_CRL_CNF_Msk CAN_F4R1_FB10_Msk RCC_CIR_HSERDYIE_Msk USB_CNTR_SOFM_Pos ADC_CR2_SWSTART AFIO_EXTICR2_EXTI6_PF_Pos SPI_CR1_BIDIOE_Pos +syn keyword CTagsDefinedName USB_EP4R_STAT_TX_Msk FLASH_ACR_HLFCYA_Pos TIM_SR_CC2OF_Pos ADC_SMPR2_SMP3 CAN_F9R1_FB30 CAN_F5R1_FB1_Msk CAN_FFA1R_FFA7 CAN_F1R2_FB7 USART_CR1_PCE_Pos CAN_F3R2_FB20 CAN_F12R2_FB15_Pos CAN_F13R1_FB14 SDIO_CLKCR_NEGEDGE CAN_TDH0R_DATA7_Pos AFIO_MAPR_SWJ_CFG_1 FLASH_OBR_DATA0 CAN_FA1R_FACT_Pos CAN_TDH0R_DATA7_Msk CAN_F13R2_FB20 USART_GTPR_PSC_5 CAN_F4R2_FB2 GPIO_CRH_CNF_Msk CAN_F1R1_FB29_Pos CAN_F9R2_FB31_Pos CAN_F10R2_FB22_Pos CAN_F0R1_FB4_Msk EXTI_FTSR_TR18 CAN_F4R2_FB23_Pos +syn keyword CTagsDefinedName TIM_CCMR1_OC2M_0 GPIO_BSRR_BS7_Pos RCC_APB2ENR_IOPEEN TIM_CCMR1_OC1FE_Pos CAN_F9R1_FB15 ADC_CR1_AWDEN_Pos AFIO_EXTICR1_EXTI2_PF_Msk TIM_CCMR1_IC1F USART_SR_CTS_Pos CAN_F0R2_FB17_Pos CAN_F10R2_FB16_Msk PWR_CR_PLS_2V6 RCC_APB2ENR_AFIOEN_Msk CAN_TSR_TME_Pos CAN_F0R1_FB22_Msk CAN_F0R2_FB7_Pos ADC_SMPR2_SMP9_0 EXTI_RTSR_RT5 GPIO_BSRR_BS5_Msk USB_EP4R_CTR_RX_Pos CAN_FS1R_FSC13 TIM_CR1_CMS_Msk RCC_APB1RSTR_TIM3RST AFIO_EXTICR3_EXTI10_PA EXTI_PR_PR11 CAN_F7R1_FB22 CAN_MSR_RXM +syn keyword CTagsDefinedName DMA_IFCR_CTEIF5_Msk AFIO_EXTICR2_EXTI7_PE_Pos AFIO_MAPR_CAN_REMAP_REMAP2 CAN_F4R1_FB5 RCC_APB1RSTR_USART3RST CAN_FS1R_FSC4 CAN_F6R1_FB19_Pos GPIO_BSRR_BS12 IS_FUNCTIONAL_STATE CAN_F7R1_FB2 USB_COUNT7_RX_NUM_BLOCK_4 ADC1_IRQ_PRIORITY AFIO_EXTICR1_EXTI2_PF RCC_CIR_HSIRDYIE_Msk USB_COUNT7_RX_1_NUM_BLOCK_1 CLEAR_REG CAN_F1R1_FB3_Pos EXTI_EMR_EM13 USB_COUNT6_RX_COUNT6_RX SPI_SR_RXNE EXTI_RTSR_TR4_Msk I2C_SR1_SMBALERT_Msk SDIO_MASK_RXACTIE_Msk CAN_F0R2_FB20 CAN_F10R2_FB20 +syn keyword CTagsDefinedName GPIO_BSRR_BS1_Msk I2C_CR1_START_Msk CAN_F13R2_FB13_Msk TIM_ARR_ARR RCC_CFGR_MCOSEL_0 USB_EP2R_STAT_TX_0 CAN_F6R2_FB12 IS_UART_HALFDUPLEX_INSTANCE CAN_F0R2_FB10 AFIO_EXTICR4_EXTI15_PE CAN_F1R1_FB15 ADC_SMPR1_SMP14 TIM_SMCR_ECE_Pos USART_CR1_PEIE_Pos BKP_RTCCR_ASOE_Pos DMA_ISR_TCIF6 CAN_F5R2_FB0_Pos CAN_F4R2_FB21_Pos CAN_F9R2_FB14_Msk RCC_APB2RSTR_ADC2RST_Pos SDIO_CMD_WAITRESP_Msk ADC_SQR1_SQ14_Pos AFIO_EXTICR3_EXTI11_PF_Msk BKP_DR9_D_Pos CAN_F0R2_FB15_Pos CAN_F2R2_FB17_Msk +syn keyword CTagsDefinedName USB_EP1R_SETUP_Msk CAN_MSR_WKUI_Msk GPIO_CRH_CNF13_0 CAN_F9R2_FB12_Msk FLASH_DATA1_DATA1_Msk SDIO_MASK_DATAENDIE USB_EP4R_CTR_TX_Pos CAN_F13R1_FB29_Pos CAN_FA1R_FACT13_Pos CAN_IER_FMPIE1 CAN_F6R1_FB22 RCC_CSR_SFTRSTF_Msk CAN_F12R1_FB2_Pos I2C_CR1_PEC EXTI_IMR_MR1_Pos CAN_FA1R_FACT0_Msk CAN_F4R2_FB13 CAN_F8R2_FB27_Pos AFIO_EXTICR4_EXTI14_PC_Pos ADC_SQR2_SQ10_0 EXTI_SWIER_SWIER2_Pos CAN_F0R2_FB16_Msk CAN_FM1R_FBM10_Pos CAN_F9R1_FB5_Msk CAN_F11R1_FB29_Msk CAN_F4R2_FB29_Msk +syn keyword CTagsDefinedName TIM_SR_CC2OF_Msk CAN_F11R2_FB21 DMA_IFCR_CGIF2_Pos CAN_F13R2_FB24 USB_COUNT2_RX_0_COUNT2_RX_0 TIM_DIER_CC1IE_Pos USART_CR2_ADD_Msk CAN_F8R1_FB29 ADC_SMPR1_SMP17_Msk TIM2_BASE CAN_RI1R_STID BKP_DR9_D_Msk CAN_F0R1_FB26_Pos CAN_F11R2_FB17 TIM_BDTR_LOCK_Msk FLASH_CR_EOPIE_Pos GPIO_CRL_CNF1_0 CAN_TDT2R_TIME_Pos CAN_F8R1_FB7_Pos CAN_F2R1_FB26_Pos ADC_CR2_JSWSTART_Msk CAN_F10R2_FB23_Pos CAN_F11R2_FB15_Pos USB_EP_KIND_Pos BKP_CR_TPE_Msk CAN_F1R1_FB25_Msk RTC_CRL_CNF ADC_CR2_ADON_Pos +syn keyword CTagsDefinedName USB_ADDR2_RX_ADDR2_RX_Pos EXTI_IMR_IM11 RCC_CIR_LSERDYC CAN_F9R1_FB26_Msk RCC_CFGR_MCO_1 AFIO_EXTICR1_EXTI2_Pos USB_ISTR_SUSP_Pos DMA_IFCR_CTEIF6_Msk ADC_SQR1_SQ14_3 AFIO_EVCR_PIN_PX5_Pos I2C_CR1_ALERT_Msk TIM_BDTR_DTG_3 CAN_F11R1_FB28 CAN_F3R2_FB23 PIN_OPT_AF13 GPIO_IDR_IDR10_Pos RCC_CFGR_PLLMULL9_Msk CAN_F4R1_FB0_Msk RTC_CNTH_RTC_CNT_Pos CAN_F7R2_FB20 CAN_BTR_LBKM USB_CNTR_RESUME_Pos CAN_F11R1_FB20 PIN_7 CAN_F11R1_FB7 ADC_SQR3_SQ6_3 USB_EP_CONTROL PWR_CSR_EWUP_Pos +syn keyword CTagsDefinedName RCC_APB1ENR_CAN1EN_Pos CAN_F11R2_FB14_Pos CAN_F5R1_FB13 IS_TIM_CLOCKSOURCE_TIX_INSTANCE USB_COUNT1_TX_0_COUNT1_TX_0 DMA_IFCR_CGIF3_Msk EXTI_RTSR_TR7_Pos USB_ISTR_ERR CAN_F2R1_FB6_Msk USB_ISTR_ERR_Pos CAN_TDT2R_DLC_Msk CAN_F7R2_FB23_Msk USB_CNTR_FRES CAN_TSR_LOW1 CAN_F10R1_FB7_Msk CAN_TDT0R_TGT_Pos CAN_F13R1_FB16_Msk RCC_CFGR_HPRE_DIV8 CAN_F2R2_FB10 CAN_F6R1_FB31_Msk RCC_CR_HSERDY_Msk ADC_SMPR2_SMP5_Pos ADC_SR_AWD SDIO_ICR_DTIMEOUTC_Msk RCC_CFGR_SWS_PLL USART_SR_IDLE +syn keyword CTagsDefinedName CAN_FA1R_FACT6_Pos CAN_F11R2_FB21_Msk CAN_F3R1_FB1 WWDG CAN_F4R2_FB31_Pos AFIO_MAPR_CAN_REMAP_REMAP1 CAN_F9R1_FB18_Msk AFIO_EVCR_PIN_PX12_Msk I2C_SR1_BERR_Msk USB_COUNT6_RX_1_NUM_BLOCK_1_4 GPIO_BSRR_BS4_Pos CAN_F9R1_FB12_Msk CAN_F13R2_FB5_Pos USB_COUNT4_RX_COUNT4_RX_Msk CAN_F10R2_FB4_Msk USB_EP1R_DTOG_RX AFIO_EXTICR3_EXTI9_PD_Pos CAN_F13R1_FB9_Msk RCC_APB1ENR_CAN1EN_Msk CAN_FM1R_FBM10_Msk OB CAN_F0R1_FB0_Msk WWDG_CFR_W_1 RDP_KEY_Msk CAN_MSR_SLAKI CAN_MCR_RESET CAN_F5R1_FB12_Pos +syn keyword CTagsDefinedName CAN_F2R2_FB31_Pos CAN_F10R2_FB1_Pos CAN_TSR_CODE USB_COUNT3_RX_0_NUM_BLOCK_0_3 CAN_F11R2_FB22_Pos CAN_F13R2_FB3_Msk GPIO_ODR_ODR13 ADC_SMPR2_SMP8_Pos CAN_F11R2_FB27 EXTI_IMR_MR7 CAN_F8R2_FB16_Pos RCC_CFGR_MCOSEL_NOCLOCK USB_EP_CTR_RX_Pos GPIO_LCKR_LCK4 DMA_IFCR_CHTIF3 CAN_FFA1R_FFA5_Msk USB_COUNT0_RX_1_NUM_BLOCK_1_0 CAN_F7R2_FB24_Msk CAN_F8R1_FB2 CAN_F1R2_FB20_Msk CAN_F7R2_FB3_Pos CAN_RF1R_FMP1_Pos CAN_F3R1_FB29_Msk AFIO_EVCR_PIN_Pos CAN_BTR_BRP_Msk GPIO_ODR_ODR7_Msk +syn keyword CTagsDefinedName USART_CR3_DMAR_Msk AFIO_EXTICR4_EXTI13_PF CAN_F2R2_FB16_Msk CAN_FA1R_FACT7_Msk USB_COUNT5_RX_BLSIZE_Msk SPI_SR_OVR GPIO_BSRR_BR7 CAN_F1R1_FB19_Msk CAN_F0R1_FB19_Msk CAN_F13R1_FB10_Pos CAN_FM1R_FBM4 CAN_F1R1_FB9 USB_COUNT5_RX_0_NUM_BLOCK_0_2 DMA_IFCR_CGIF4 I2C_SR1_TXE CAN_TDT2R_TIME OB_BASE USB_ADDR5_TX_ADDR5_TX_Pos TIM_DCR_DBL_4 EXTI_RTSR_RT0 CAN_F8R2_FB20_Pos I2C_DR_DR_Msk SDIO_CLKCR_PWRSAV_Msk CAN_F8R2_FB8_Msk ADC_JOFR1_JOFFSET1_Pos CAN_F7R2_FB15_Pos PWR_CR_PLS CAN_FS1R_FSC12 +syn keyword CTagsDefinedName GPIO_CRH_MODE8 AFIO_EXTICR1_EXTI2_PD USB_CNTR_PMAOVRM USB_EP3R_STAT_RX_Pos CAN_F9R1_FB14 CAN_F11R2_FB6_Pos CAN_FS1R_FSC0 CAN_FS1R_FSC11_Msk BKP_RTCCR_ASOS_Pos USB_EP5R_DTOG_TX_Msk AFIO_EXTICR4_EXTI13_PE EXTI_SWIER_SWIER14_Msk RCC_APB2ENR_IOPCEN __STM32F1_CMSIS_VERSION_MAIN CAN_TDH1R_DATA6 CAN_F5R1_FB21 GPIO_CRH_MODE10 DMA_ISR_TEIF7 USB_COUNT0_TX_0_COUNT0_TX_0 ADC_SMPR2_SMP8_Msk TIM_CR2_CCPC_Pos CAN_F13R1_FB28 CAN_F5R2_FB21_Pos CAN_F10R2_FB29_Msk RTC_CRL_OWF_Pos USART3_BASE +syn keyword CTagsDefinedName USB_EP6R_STAT_RX_0 USB_COUNT6_RX_1_NUM_BLOCK_1_0 BKP_BASE CAN_F4R2_FB3_Msk CAN_F2R2_FB26_Pos CAN_F7R2_FB2_Pos CAN_F3R2_FB6_Msk CAN_F12R1_FB26_Msk DMA_ISR_GIF2_Msk CAN_F3R1_FB26_Msk CAN_FS1R_FSC8_Msk RTC_ALRL_RTC_ALR USB_CNTR_CTRM_Pos USB_COUNT6_RX_NUM_BLOCK_3 TIM_CCMR1_IC2F_Msk USART_SR_TXE_Msk DBGMCU_CR_DBG_IWDG_STOP_Msk TIM_DIER_CC2IE_Msk CAN_F0R1_FB11 CAN_F3R1_FB13 TIM_CR2_OIS1N_Pos RCC_CSR_SFTRSTF_Pos DMA_ISR_TCIF3_Pos CAN_F5R2_FB17_Pos RCC_APB2RSTR_IOPARST_Msk +syn keyword CTagsDefinedName USB_EP3R_CTR_TX_Msk CAN_F11R1_FB2 CAN_F2R1_FB8_Pos CAN_F3R1_FB28_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_1 ADC_JSQR_JL SPI_CR2_TXDMAEN_Pos CAN_FFA1R_FFA4_Pos DMA_IFCR_CTEIF3_Msk DMA_CCR_PL_1 GPIO_LCKR_LCK9_Msk ADC_SQR2_SQ11_0 TIM4 TIM_EGR_TG CAN_RDH1R_DATA7_Msk CAN_F11R1_FB2_Msk TIM_CCMR1_OC1FE_Msk RCC_APB2RSTR_SPI1RST AFIO_EXTICR1_EXTI0_Pos CAN_F7R1_FB3_Pos USB_COUNT2_RX_0_NUM_BLOCK_0_0 FLASH_SR_WRPRTERR_Pos CAN_F2R1_FB1_Msk USB_ADDR7_RX_ADDR7_RX CAN_F4R1_FB22_Pos FLASH_CR_PER +syn keyword CTagsDefinedName USB_COUNT4_TX_COUNT4_TX CAN1_TX_IRQn CAN_F2R1_FB5 CAN_F9R1_FB3 ADC_SMPR1_SMP16 CAN_TDH0R_DATA6_Pos RTC_DIVH_RTC_DIV CAN_F13R2_FB24_Msk AFIO_EVCR_PIN_PX12_Pos USB_EP_TX_STALL CAN_F4R1_FB11_Pos CAN_F8R1_FB19_Pos CAN_F1R1_FB21 CAN_F1R1_FB1_Msk SDIO_DCTRL_RWSTART_Pos CAN_F0R2_FB24_Msk GPIO_BSRR_BR14_Pos CAN_F12R2_FB23_Pos USB_EP7R_DTOG_RX_Msk WWDG_CR_T_4 RCC_CFGR_ADCPRE_0 USART_CR1_PCE_Msk CAN_F3R1_FB4 CAN_F3R1_FB31_Msk AFIO_EXTICR3_EXTI11_PE_Msk USART_CR2_ADD TIM_CCMR1_IC1F_Msk +syn keyword CTagsDefinedName USART_CR1_PS_Msk SDIO_STA_DBCKEND_Pos RCC_APB1RSTR_WWDGRST ADC_SQR3_SQ6_2 GPIO_BSRR_BR3 CAN_F0R1_FB21_Msk USART_CR3_HDSEL CAN_F7R1_FB4_Msk CAN_F13R2_FB15_Msk WWDG_CR_T3 CAN_F3R1_FB28 SDIO_CLKCR_PWRSAV AFIO_EXTICR2_EXTI4_Pos CAN_F3R2_FB7_Pos USB_COUNT5_RX_NUM_BLOCK_0 AFIO_EXTICR1_EXTI2_PF_Pos CAN_TSR_RQCP1_Msk CAN_F3R1_FB27 CAN_F7R2_FB2 CAN_F10R1_FB10 SDIO_MASK_DTIMEOUTIE GPIO_CRL_MODE2_0 USB_ADDR7_TX_ADDR7_TX CAN_F12R1_FB0 CAN_F10R2_FB26 USB_EP2R_STAT_RX_1 AFIO_EXTICR2_EXTI4_PG +syn keyword CTagsDefinedName CAN_F10R2_FB31_Pos PIN_1 GPIO_ODR_ODR4 CAN_F5R1_FB21_Pos USART_CR3_NACK_Msk FLASH_KEY1_Pos CAN_F12R1_FB10_Msk GPIO_IDR_IDR11 USB_EP2R_EA CAN_F12R2_FB6 I2C_SR1_STOPF DMA_ISR_HTIF7 USB_COUNT2_RX_COUNT2_RX_Msk USB_COUNT1_RX_BLSIZE_Msk CAN_F12R1_FB22_Pos CAN_F8R1_FB21_Msk AFIO_MAPR_CAN_REMAP_REMAP3_Pos TIM_CCMR1_OC1M_Pos SPI_SR_MODF_Msk FLASH_CR_PG_Msk CAN_TDL2R_DATA0_Msk TIM_BDTR_DTG_7 USB_ISTR_RESET AFIO_EXTICR1_EXTI1_PD_Pos CAN_BTR_SILM_Msk USB_EP5R_CTR_TX_Pos CAN_F9R2_FB15 +syn keyword CTagsDefinedName GPIO_BSRR_BS14 CAN_RI0R_IDE_Msk CAN_F7R1_FB2_Msk GPIO_LCKR_LCK7_Msk SPI_I2SCFGR_I2SMOD_Pos TIM_SR_TIF_Msk RCC_CFGR_PLLSRC_Pos CAN_MSR_ERRI_Msk CAN_F4R1_FB11 DBGMCU_IDCODE_REV_ID_0 CAN_F9R2_FB17 CAN_F5R1_FB19_Pos BKP_DR2_D PWR_CR_PLS_LEV1 I2C_SR2_MSL EXTI_FTSR_FT11 USART_CR1_TXEIE GPIO_LCKR_LCK12_Msk CAN_F9R2_FB19_Msk CAN_RF0R_RFOM0_Msk CAN_F4R1_FB9_Msk CAN_F3R2_FB14_Msk CAN_F3R1_FB12 PIN_OPT_OUTPUT_PUSHPULL RCC_APB2RSTR_AFIORST SDIO_CMD_CEATACMD_Msk CAN_F11R2_FB10_Msk +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5 CAN_RDT1R_TIME_Pos TIM_CCMR1_CC1S_1 TIM_CCMR1_OC2PE_Msk IS_UART_INSTANCE AFIO_MAPR_USART3_REMAP_Pos AFIO_EXTICR2_EXTI7_PC_Pos CAN_F12R1_FB14_Pos USART_DR_DR_Msk CAN_F3R2_FB25 AFIO_EXTICR3_EXTI9_PF_Msk CAN_F4R2_FB5_Msk EXTI_RTSR_TR14_Msk TIM_DCR_DBA_2 RCC_APB2ENR_AFIOEN_Pos GPIO_CRH_MODE_Msk ADC_SMPR2_SMP1_2 CAN_MCR_ABOM I2C_SR2_DUALF CAN_F3R1_FB0 TIM_CR1_URS_Pos RTC_CNTL_RTC_CNT_Msk GPIO_BSRR_BS7_Msk CAN_MCR_RESET_Pos CAN_F5R1_FB27_Pos CAN_F7R1_FB8_Msk +syn keyword CTagsDefinedName CAN_FS1R_FSC1 TIM_CCMR1_IC2F_0 EXTI_FTSR_TR11 SDIO_STA_SDIOIT_Pos GPIO_ODR_ODR3 SDIO_DCTRL_RWSTART DMA_CMAR_MA_Msk AFIO_EVCR_PORT_PD_Msk USB_CNTR_PMAOVRM_Pos GPIO_BRR_BR5_Msk USART6_IRQ_PRIORITY AFIO_EXTICR2_EXTI7_PD_Pos FLASH_ACR_HLFCYA TIM_CCMR2_OC3CE_Msk GPIO_BSRR_BR1_Pos WWDG_CFR_W_4 CAN_F7R2_FB20_Pos CAN_F4R1_FB7_Msk CAN_F9R2_FB4_Pos CAN_F9R1_FB16_Msk ADC_SQR2_SQ12_3 RCC_CFGR_SW_1 ADC_JSQR_JSQ1_1 CAN_F13R2_FB18_Pos CAN_F9R1_FB15_Pos AFIO_EXTICR2_EXTI6_PB_Pos +syn keyword CTagsDefinedName CAN_F3R1_FB15_Msk RCC_CFGR_MCO_HSE DMA_CCR_TCIE_Pos CAN_F10R1_FB3 ADC_SQR1_SQ14_1 USB_EP4R_EP_KIND USB_EP3R_STAT_RX_0 CAN_FA1R_FACT0 CAN_MCR_NART GPIO_CRL_MODE4_1 EXTI_IMR_IM9 TIM_CR1_URS_Msk GPIO_ODR_ODR9 AFIO_EXTICR3_EXTI8_PE USB_EP1R_STAT_TX_0 USART_CR1_RXNEIE_Pos AFIO_EXTICR2_EXTI4_PD_Pos USB_COUNT3_RX_1_NUM_BLOCK_1_4 AFIO_EXTICR3_EXTI9_PE_Pos TIM_CR2_OIS3 GPIO_ODR_ODR12_Msk USB_EP4R_CTR_TX CAN_F12R2_FB12 CAN_F7R1_FB12_Pos CAN_F13R2_FB9 AFIO_EXTICR1_EXTI2_PG_Pos +syn keyword CTagsDefinedName ADC_SMPR2_SMP3_0 USB_EP0R_EP_KIND USB_EP4R_SETUP_Pos SDIO_STA_DTIMEOUT_Msk CAN_F11R1_FB11_Msk ADC_JSQR_JL_0 CAN_F3R1_FB7_Pos CAN_F3R1_FB11_Msk RCC_CFGR_PPRE2_DIV8 USB_EP0R_EP_TYPE_Msk ADC_SMPR1_SMP15_Msk USB_COUNT4_RX_1_COUNT4_RX_1 CAN_TDT2R_DLC_Pos TIM_CCER_CC1P TIM_CCMR1_IC1PSC_Pos SPI_CR1_CPOL_Msk EXTI_PR_PR6_Pos CAN_F1R2_FB3_Pos EXTI_RTSR_RT12 I2C2_BASE TIM4_BASE GPIO_BRR_BR11_Msk SPI_CR2_RXNEIE ADC_CR2_DMA_Msk DBGMCU_IDCODE_REV_ID_14 CAN_TSR_ABRQ0_Pos DMA_IFCR_CTCIF2_Msk +syn keyword CTagsDefinedName AFIO_EXTICR3_EXTI9_PD_Msk EXTI_PR_PIF4 I2C_OAR1_ADD7 CAN_F1R2_FB14_Msk SPI_CR1_CRCEN_Msk AFIO_EXTICR4_EXTI14_PF CAN_F4R2_FB25_Msk CAN_F12R2_FB9_Pos CAN_F11R1_FB6_Msk ADC_SQR3_SQ2_1 CAN_TI0R_IDE_Msk USB_EP7R_STAT_RX_1 CAN_IER_FFIE1_Msk SPI_CR1_MSTR_Msk ADC_SMPR1_SMP13_1 EXTI_SWIER_SWIER13_Pos TIM1_BRK_TIM9_IRQHandler CAN_F9R1_FB25_Pos GPIO_LCKR_LCK9_Pos CAN_F2R2_FB2_Pos I2C_CR1_ACK SPI_DR_DR_Pos CAN_F3R2_FB28 CAN_MCR_INRQ CAN_F7R2_FB17_Pos FLASH_DATA1_nDATA1 CAN_F1R1_FB20_Pos +syn keyword CTagsDefinedName GPIO_LCKR_LCK4_Msk CAN_F4R1_FB18_Msk CAN_F9R1_FB4_Pos RCC_CFGR_PLLMULL5_Msk CAN_F5R1_FB10 TIM_DIER_CC2DE USB_FNR_RXDM GPIO_IDR_IDR2_Pos AFIO_EXTICR1_EXTI1_PB CAN_F2R2_FB7 AFIO_MAPR_TIM3_REMAP_Pos CAN_F2R1_FB31 PWR_CSR_EWUP DMA_CPAR_PA_Msk CAN_TI2R_RTR_Pos I2C_CR1_SMBUS USB_COUNT6_RX_1_NUM_BLOCK_1_3 CAN_F11R2_FB22 CAN_TSR_RQCP2_Msk EXTI_EMR_MR11_Msk AFIO_EXTICR3_EXTI10_PD_Pos CAN_F1R1_FB13 AFIO_EXTICR1_EXTI3_PE RTC_CNTH_RTC_CNT CAN_F9R2_FB6_Pos TIM_CR1_CMS_Pos USART_CR3_IRLP_Msk +syn keyword CTagsDefinedName CAN_F11R1_FB25_Pos CAN_TDL2R_DATA1_Msk CAN_F7R2_FB16_Pos CAN_F2R1_FB30_Msk AFIO_EXTICR3_EXTI9_PC_Pos USART_SR_LBD_Pos WWDG_CFR_W_Pos CAN_F7R1_FB11 CAN_F5R1_FB20_Pos CAN_F8R1_FB25_Pos CAN_F6R2_FB15_Pos CAN_F12R1_FB4_Pos CAN_FM1R_FBM12_Pos CAN_F3R1_FB27_Msk USART_CR2_CPHA AFIO_EVCR_PORT_PB_Pos AFIO_MAPR_SWJ_CFG_2 CAN_F13R1_FB24 GPIO_ODR_ODR8 CAN_F7R1_FB17_Pos SDIO_POWER_PWRCTRL_0 CAN_F2R1_FB17_Msk CAN_F1R1_FB3 ADC_CR1_AWDEN_Msk AFIO_EVCR_PIN_PX6 CAN_F4R2_FB14 RCC_CFGR_HPRE_DIV512 +syn keyword CTagsDefinedName USB_EP7R_DTOG_TX_Msk CAN_F8R1_FB1 EXTI_PR_PIF10 CAN_TDH0R_DATA5 CAN_F9R2_FB7_Msk pwm_stop RCC_APB1RSTR_USBRST_Msk CAN_FS1R_FSC2_Pos SDIO_ICR_RXOVERRC_Pos TIM_DIER_TIE SDIO_ICR_CMDRENDC CAN_F7R2_FB29_Pos ADC_SMPR2_SMP1_1 DMA_ISR_GIF6_Msk I2C_OAR1_ADD2_Msk CAN_TI2R_TXRQ_Pos USB_EP0R_STAT_RX_0 ADC_JDR3_JDATA FLASH_CR_OPTER_Msk CAN_F10R2_FB3_Pos CAN_TSR_TME DMA1_Channel3 CAN_F6R1_FB20_Msk USART_SR_ORE_Pos CAN_F4R2_FB24_Pos TIM9_IRQHandler CAN_RI0R_RTR SPI_SR_BSY_Msk BKP_CR_TPAL_Pos +syn keyword CTagsDefinedName CAN_F5R2_FB29_Pos CAN_F8R2_FB31_Msk CAN_F6R2_FB13 IWDG_RLR_RL CAN_F10R1_FB11_Pos CAN_F5R1_FB2_Msk BKP_CSR_TPIE SPI_SR_UDR USB_EP6R_CTR_TX EXTI_IMR_MR0_Pos AFIO_BASE CAN_TDL2R_DATA3_Pos USB_EP3R_EP_KIND_Pos CAN_TI1R_IDE_Pos CAN_F2R2_FB14 CAN_F10R2_FB26_Pos I2C_CR1_ALERT EXTI_PR_PR15_Pos CAN_F7R2_FB21_Pos GPIO_BSRR_BR6_Msk ADC_CR2_ADON_Msk DMA_IFCR_CHTIF7_Pos CAN_F4R1_FB0 DBGMCU_CR_DBG_TIM4_STOP_Msk CAN_TSR_LOW0 USB_ADDR0_TX_ADDR0_TX_Pos FLASH_OPTKEYR_OPTKEYR_Pos TIM_EGR_BG +syn keyword CTagsDefinedName CAN_F9R2_FB21_Pos CAN_TDH2R_DATA4 DMA1_Channel5 EXTI_IMR_IM0 SDIO_ICR_CCRCFAILC_Msk EXTI_BASE DMA_CCR_HTIE_Pos SYSCFG_EXTI_PB_MASK CAN_F1R2_FB20_Pos CAN_F13R2_FB1_Pos CAN_F6R1_FB8_Pos CAN_F11R1_FB26_Pos CAN_FS1R_FSC3 GPIO_BSRR_BS11_Msk CAN_FFA1R_FFA7_Msk CAN_F3R1_FB19 ADC_SQR3_SQ4_2 AFIO_MAPR_SWJ_CFG_NOJNTRST TIM_CCMR2_IC3PSC_0 USB_COUNT4_RX_1_NUM_BLOCK_1_3 EXTI_FTSR_TR16 CAN_F0R2_FB7 CAN_F2R1_FB27_Msk CAN_F2R2_FB26_Msk EXTI9_5_IRQ_PRIORITY CAN_F5R2_FB30_Pos CAN_F3R2_FB13_Pos +syn keyword CTagsDefinedName EXTI_FTSR_FT10 EXTI_FTSR_TR12_Pos TIM_CCMR1_OC1FE CAN_TDL2R_DATA3 CAN_F2R2_FB19_Msk CAN_FM1R_FBM7_Pos CAN_TSR_TME1_Pos CAN_F3R2_FB5_Msk CAN_F6R1_FB25 CAN_F10R1_FB6_Msk USART_CR3_DMAR_Pos CAN_F9R1_FB7_Msk CAN_FFA1R_FFA13_Msk CAN_FFA1R_FFA13 CAN_BTR_TS2_2 CAN_F3R1_FB3_Pos USART_SR_TC_Msk CAN_F0R1_FB23 CAN_F11R1_FB23 CAN_F5R1_FB17 AFIO_EVCR_PIN_PX6_Pos GPIO_CRH_CNF8_1 RCC_APB2RSTR_ADC2RST_Msk PWR_CR_CSBF TIM_CCER_CC2NP_Pos ADC_SQR1_SQ14_Msk CAN_F1R2_FB18_Pos AFIO_EVCR_PIN_PX1 +syn keyword CTagsDefinedName USART_SR_TXE ADC_SQR3_SQ6_4 FLASH_OPTKEYR_OPTKEYR CAN_F8R1_FB9 DBGMCU_CR_DBG_IWDG_STOP RTC_ALRL_RTC_ALR_Msk CAN_F12R2_FB3 TIM_CCMR1_IC1PSC_1 CAN_F11R1_FB9_Msk AFIO_EXTICR3_EXTI8_PD_Pos I2C_OAR2_ADD2 CAN_F3R2_FB14 AFIO_EXTICR2_EXTI6_PD_Msk CAN_F2R1_FB31_Pos CAN_MCR_AWUM USB_EP6R_EP_KIND_Msk TIM_EGR_CC3G_Msk CAN_F8R1_FB25_Msk SDIO_CLKCR_NEGEDGE_Msk CAN_F5R2_FB10_Pos CAN_F4R2_FB28_Msk CAN_F3R2_FB16 BKP_CSR_CTI DBGMCU_CR_DBG_TIM1_STOP CAN_F1R1_FB14_Pos CAN_F11R1_FB19_Pos +syn keyword CTagsDefinedName CAN_F11R1_FB11_Pos CAN_F12R2_FB16_Msk RCC_CIR_LSIRDYIE_Msk TIM_CCMR2_OC3M_2 EXTI_RTSR_TR1_Msk SDIO_STA_TXUNDERR_Pos CAN_TI0R_TXRQ_Msk CAN_F8R1_FB22 CAN_F13R1_FB30_Pos RCC_APB1RSTR_I2C2RST CAN_F11R1_FB24_Msk RCC_CFGR_HPRE_Msk AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos AFIO_EXTICR3_EXTI11_PF_Pos CAN_F4R2_FB20_Msk RCC_APB2RSTR_ADC1RST_Msk ADC_SQR2_SQ11_Msk USB_ISTR_ESOF_Pos BKP_DR5_D_Pos USB_COUNT4_TX_0_COUNT4_TX_0 TIM_EGR_CC1G_Pos I2C_SR1_STOPF_Pos CAN_F7R2_FB24 EXTI_SWIER_SWIER3_Msk +syn keyword CTagsDefinedName USB_EP1R_EP_TYPE_Pos USB_EP6R_EA_Msk FLASH_OBR_IWDG_SW GPIO_BSRR_BS6_Msk GPIO_IDR_IDR6_Msk SPI1_BASE DMA_ISR_TEIF4_Pos EXTI_SWIER_SWIER18_Msk CAN_F5R1_FB23 WWDG_CFR_WDGTB_Msk GPIO_ODR_ODR13_Pos CAN_F3R2_FB25_Pos GPIO_BSRR_BS1 GPIO_BSRR_BS10 CAN_F0R2_FB4_Pos GPIO_CRH_CNF15_0 CAN_F8R1_FB6 RCC_APB2RSTR_AFIORST_Msk CAN_F13R2_FB11_Pos I2C_CR1_POS_Pos CAN_F12R2_FB0 EXTI_RTSR_TR12_Msk CAN_F6R1_FB17 CAN_F10R1_FB21_Msk IS_TIM_DMABURST_INSTANCE CAN_F5R1_FB12_Msk CAN_F13R1_FB20_Pos +syn keyword CTagsDefinedName AFIO_EVCR_PORT_PD_Pos CAN_TSR_RQCP0_Msk CAN_F10R2_FB17_Msk EXTI_RTSR_TR17_Pos SPI_TXCRCR_TXCRC_Pos EXTI_IMR_MR17 AFIO_EXTICR2_EXTI5_PD_Msk UID_BASE TIM_CCMR1_IC2F_1 USB_ISTR_EP_ID_Pos TIM_EGR_BG_Pos DMA_ISR_TEIF6 CRC_DR_DR_Pos SDIO_STA_CMDSENT_Pos AFIO_EXTICR3_EXTI9_PC_Msk CAN_F3R2_FB30 SDIO_DCTRL_DBLOCKSIZE_0 USB_EPKIND_MASK CAN_MSR_TXM CAN_F6R1_FB8_Msk CAN_FA1R_FACT5 CAN_F11R1_FB9_Pos CAN_FA1R_FACT7_Pos ADC_SQR2_SQ8_4 CAN_F0R1_FB7 CAN_F2R1_FB15_Pos GPIO_LCKR_LCK4_Pos +syn keyword CTagsDefinedName EXTI_SWIER_SWI18 TIM5_IRQ_PRIORITY SDIO_MASK_CTIMEOUTIE_Msk CAN_F2R1_FB8 ADC_SQR3_SQ6 CAN_MSR_WKUI_Pos CAN_F1R1_FB18 AFIO_EXTICR2_EXTI5_PB CAN_F11R2_FB19_Msk CAN_F5R2_FB9_Msk DMA_CCR_DIR_Pos CAN_F9R1_FB24_Msk AFIO_EXTICR4_EXTI13_PD CAN_F7R2_FB31_Msk CAN_F3R1_FB13_Pos EXTI2_IRQ_PRIORITY AFIO_EXTICR1_EXTI3_PG_Msk CAN_F8R2_FB8_Pos USB_EP6R_STAT_RX_Msk CAN_TI1R_TXRQ_Msk USB_EPREG_MASK AFIO_EXTICR3_EXTI8_PG_Msk EXTI_IMR_MR3 SDIO_STA_DTIMEOUT_Pos AFIO_EXTICR4_EXTI12 CAN_F9R1_FB6_Msk +syn keyword CTagsDefinedName CAN_F7R2_FB16_Msk IS_ADC_DMA_CAPABILITY_INSTANCE CAN_F8R2_FB3_Pos WWDG_SR_EWIF_Pos CAN_RDL1R_DATA1_Msk I2C_DR_DR RCC_CSR_LPWRRSTF_Pos CAN_F13R2_FB22 CAN_F3R2_FB3_Pos TIM_SR_CC1IF USB_ADDR5_TX_ADDR5_TX_Msk CAN_F12R1_FB13_Msk ADC_SMPR1_SMP16_2 SDIO_RESP2_CARDSTATUS2_Msk TIM_BDTR_LOCK CAN_F6R1_FB2_Msk AFIO_EXTICR1_EXTI0_PG SPI_CR1_SPE_Pos ADC_CR2_ALIGN_Msk CAN_IER_EPVIE_Msk TIM_CCMR2_OC4FE_Pos CAN_F0R2_FB12_Msk DMA_IFCR_CGIF6_Pos CAN_F11R1_FB19_Msk DMA_CCR_CIRC_Msk +syn keyword CTagsDefinedName AFIO_MAPR_SPI1_REMAP_Msk CAN_TSR_RQCP0_Pos CAN_F7R1_FB1 USART_SR_FE CAN_TI1R_STID CAN_F9R2_FB12 CAN_F6R2_FB28_Pos SPI_RXCRCR_RXCRC_Pos USB_EP5R_EP_TYPE_Msk I2C_OAR1_ADD3_Pos CAN_F12R1_FB9_Msk SDIO_CLKCR_HWFC_EN CAN_F2R1_FB5_Msk GPIO_BRR_BR13_Pos EXTI_EMR_MR16 USART_SR_NE_Msk AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk USB_EP2R_STAT_TX_Msk DMA_CCR_MINC CAN_F9R1_FB29_Msk CAN_F10R1_FB4_Pos TIM_SMCR_ETF_2 USART_SR_PE_Pos WWDG_CR_T_6 CAN_RDL1R_DATA1 CAN_F10R1_FB27 CAN_F10R2_FB2 +syn keyword CTagsDefinedName USART_CR3_EIE_Pos CAN_F1R2_FB27 DMA_IFCR_CHTIF3_Msk RCC_APB2ENR_SPI1EN_Pos CAN_F7R2_FB26_Pos RCC_CFGR_ADCPRE_1 GPIO_CRL_MODE_Msk IS_ADC_ALL_INSTANCE RCC_APB1RSTR_PWRRST_Msk CAN_F9R1_FB24 GPIO_LCKR_LCK7 CAN_F3R2_FB19_Msk CAN_F1R1_FB20_Msk USB_CNTR_LP_MODE_Msk TIM_CR1_CKD_Pos USB_DADDR_ADD6 I2C_SR1_PECERR CAN_F2R1_FB28_Pos ADC_SQR3_SQ3_1 CAN_F4R2_FB27 CAN_F9R2_FB25 USB_EP7R_EP_KIND_Pos CAN_F9R2_FB31 CAN_F12R2_FB4_Msk EXTI_PR_PR12_Pos AFIO_EXTICR1_EXTI3_PC_Msk IWDG_PR_PR +syn keyword CTagsDefinedName DMA_ISR_GIF4_Pos USART_CR1_WAKE_Msk RCC_CFGR_PPRE1_0 I2C_CCR_FS_Pos USB_COUNT7_RX_NUM_BLOCK RCC_CFGR_PPRE2_2 GPIO_BSRR_BR12 AFIO_EXTICR4_EXTI14_PE_Msk RCC_CFGR_PLLMULL6_Pos TIM_CCMR2_OC4M_0 USB_EP3R_EA_Pos PIN_OPT_OUTPUT_SPEED_LOW RTC_BASE GPIO_LCKR_LCK8_Msk CAN_FFA1R_FFA8_Msk DMA_IFCR_CTCIF7 EXTI_SWIER_SWI0 ADC_CR1_JDISCEN IS_TIM_CC3_INSTANCE EXTI_RTSR_TR2_Pos EXTI_SWIER_SWI14 USB_EP0R_STAT_RX_1 USB_EP6R_EA_Pos CAN_TDL1R_DATA3_Msk CAN_F9R2_FB3_Msk CAN_MSR_INAK_Pos +syn keyword CTagsDefinedName CAN_F10R1_FB12 CAN_F10R1_FB19_Pos CAN_F3R2_FB14_Pos CAN_F8R1_FB25 ADC_SR_EOS_Msk CAN_F1R2_FB18_Msk CAN_RDH1R_DATA4 CAN_F11R1_FB17_Msk USB_CNTR_ESOFM_Msk BKP_DR1_D_Msk USB_COUNT5_RX_1_NUM_BLOCK_1_2 DMA1_Channel7_BASE PWR_CR_PVDE GPIO_CRH_MODE I2C_CR2_FREQ_4 TIM_SMCR_TS_0 CAN_F2R1_FB12_Msk CAN_F11R2_FB4_Msk TIM_CCMR1_CC2S_Msk PWR_CR_PDDS_Pos WWDG_CFR_W5 USB_COUNT1_RX_0_BLSIZE_0 GPIO_LCKR_LCK10_Msk RCC_APB1ENR_SPI2EN_Msk CAN_TDL1R_DATA3 USART_CR1_TXEIE_Pos CAN_F5R2_FB23 +syn keyword CTagsDefinedName ADC_JSQR_JSQ3_1 GPIO_CRH_MODE11_Msk CAN_F1R1_FB30_Pos CAN_F0R2_FB24 CAN_F11R1_FB17 CAN_F13R2_FB11 CAN_IER_FMPIE0_Msk USB_EPTX_STAT_Pos RCC_BDCR_RTCSEL_NOCLOCK AFIO_EXTICR4_EXTI13_Msk AFIO_EVCR_PIN_PX14 AFIO_EXTICR2_EXTI4_PB CAN_F3R2_FB11_Pos SYSCFG_EXTI_PE_MASK USB_COUNT4_RX_1_NUM_BLOCK_1 CAN_FFA1R_FFA4 CAN_F12R1_FB20_Pos GPIO_BRR_BR1_Msk CAN_F12R1_FB0_Msk DMA_CCR_PINC USB_COUNT5_TX_COUNT5_TX AFIO_EVCR_PIN_PX8 I2C_CR1_SMBUS_Msk CAN_FS1R_FSC10 ADC_SMPR2_SMP2 ADC_CR2_CONT_Msk +syn keyword CTagsDefinedName EXTI_RTSR_RT4 SDIO_CLKCR_WIDBUS_0 FLASH_ACR_PRFTBE SDIO_MASK_DCRCFAILIE_Msk EXTI_SWIER_SWI11 PWR_CR_PLS_1 CAN_F10R2_FB23 EXTI0_IRQ_PRIORITY USART_GTPR_PSC_2 ADC_SMPR1_SMP11 CAN_F13R2_FB28_Msk CAN_F6R1_FB28 TIM_DIER_CC1IE_Msk RCC_CFGR_PPRE2_DIV4 GPIO_LCKR_LCK9 CAN_F9R1_FB26_Pos GPIO_ODR_ODR2_Pos CAN_F11R2_FB19 AFIO_EXTICR1_EXTI2_PG_Msk GPIO_CRH_MODE_Pos PWR_CR_DBP_Pos SDIO_CMD_SDIOSUSPEND TIM_CCMR1_CC2S_Pos USB_EP0R_EP_TYPE SDIO_RESP4_CARDSTATUS4_Pos CAN_F6R1_FB8 +syn keyword CTagsDefinedName ADC_SMPR1_SMP17_Pos AFIO_EVCR_PIN_PX7_Pos CAN_F4R1_FB28_Pos CAN_F8R1_FB23_Pos SPI1_IRQ_PRIORITY CAN_F0R2_FB15_Msk ADC_SQR3_SQ3_3 CAN_F12R2_FB26_Pos CAN_F10R1_FB20_Msk CAN_FS1R_FSC12_Msk CAN_F0R2_FB18 CAN_F9R2_FB30_Msk USB_COUNT6_TX_0_COUNT6_TX_0 EXTI_EMR_MR5_Pos CAN_F2R2_FB18_Msk CAN_F4R1_FB21 CAN_TSR_LOW1_Msk USB_COUNT5_RX_1_COUNT5_RX_1 EXTI_PR_PR5_Msk CAN_F12R1_FB6 AFIO_EXTICR2_EXTI6_PG GPIO_CRH_CNF10 CAN_F6R1_FB19 CAN_TSR_RQCP2 IS_RTC_ALL_INSTANCE CAN_F12R2_FB24_Pos +syn keyword CTagsDefinedName USART_CR3_DMAT_Pos AFIO_EXTICR1_EXTI0_PC SDIO_STA_TXDAVL_Msk CAN_F3R2_FB10_Msk CAN_F7R2_FB6 CAN_F5R2_FB0_Msk USB_HP_IRQHandler ADC_CR1_EOSIE_Msk CAN_F11R1_FB10_Msk CAN_F11R2_FB27_Pos CAN_RDT1R_DLC_Pos CAN_F11R1_FB31_Pos RCC_CFGR_PPRE2_DIV16 CAN_F3R2_FB13 CAN_F8R1_FB10 FLASH_DATA0_nDATA0_Pos CAN_F8R2_FB5_Msk CAN_F4R1_FB27_Pos CAN_F12R1_FB19_Msk ADC_CR1_AWDIE USB_COUNT7_RX_BLSIZE_Msk I2C1_BASE CAN_F4R2_FB31_Msk CAN_FA1R_FACT1 CAN_F2R1_FB12_Pos CAN_F8R1_FB24_Msk CAN_F12R2_FB29_Pos +syn keyword CTagsDefinedName I2C_OAR1_ADD4 CAN_F0R2_FB15 IWDG_RLR_RL_Pos USART_CR3_NACK USB_COUNT5_TX_0_COUNT5_TX_0 CAN_F6R1_FB4 RCC_CR_HSEON_Pos RCC_CFGR_HPRE_Pos CAN_TDL1R_DATA1_Msk USB_EP_RX_DIS EXTI_EMR_MR17_Msk CAN_F1R2_FB13_Msk USB_EP2R_CTR_TX_Msk ADC_SMPR1_SMP10 EXTI_IMR_IM12 USB_ADDR5_RX_ADDR5_RX USB_DADDR_ADD0 CAN_F12R1_FB10 CAN_F8R2_FB9 AFIO_EXTICR3_EXTI8_PE_Msk USB_EP2R_EP_TYPE_0 CAN_F4R1_FB17 CAN_F4R1_FB30_Msk CAN_F9R2_FB15_Msk CAN_F8R1_FB2_Pos CAN_F13R1_FB3_Pos READ_BIT BKP_DR3_D +syn keyword CTagsDefinedName WWDG_CFR_WDGTB_1 CAN_F12R1_FB16 SDIO_DCTRL_RWSTOP_Pos CAN_F8R2_FB11 CAN_F13R1_FB7_Msk FLASH_OBR_nRST_STDBY_Pos USB_EPTX_STAT_Msk SDIO_DCTRL_RWMOD RCC_CFGR_SWS_Msk USB_EP0R_STAT_RX CAN_TDH2R_DATA7_Pos RCC_CR_HSION_Pos RCC_APB1RSTR_WWDGRST_Pos CAN_F0R2_FB11_Pos RCC_APB2ENR_IOPCEN_Pos CAN_F9R2_FB22_Msk I2C_CR1_ENGC_Msk CAN_F4R1_FB18_Pos EXTI_RTSR_TR3_Msk GPIO_CRH_CNF14_1 GPIO_BRR_BR4_Pos CAN_TDT1R_TIME_Msk CAN_F2R2_FB28 CAN_F10R2_FB6 CAN_F0R1_FB6_Msk CAN_F11R2_FB8_Pos +syn keyword CTagsDefinedName USB_DADDR_ADD6_Pos ADC_SQR1_SQ14 USB_EP5R_STAT_RX_Pos CAN_TDH0R_DATA4_Pos CAN_F8R2_FB25_Msk AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos CAN_F12R2_FB10_Pos RCC_APB1RSTR_TIM4RST_Msk CAN_FFA1R_FFA_Msk CAN_F11R1_FB4_Pos CAN_F8R1_FB11_Msk RCC_MAX_FREQUENCY EXTI_RTSR_TR5 CAN_F10R2_FB18_Pos USB_EP_DTOG_RX FLASH_RDP_nRDP CAN_F9R1_FB23_Pos SDIO_MASK_CMDACTIE_Pos EXTI_FTSR_FT6 RCC_CIR_PLLRDYF DBGMCU_CR_DBG_TIM4_STOP FLASH_OBR_OPTERR DMA_IFCR_CTCIF2_Pos ADC_CR2_JSWSTART_Pos CAN_FMR_CAN2SB_Msk +syn keyword CTagsDefinedName DMA_IFCR_CTCIF3 RCC_CFGR_PLLXTPRE_HSE USB_EP2R_CTR_TX_Pos ADC_SQR3_SQ4_0 EXTI_PR_PR18 USART_SR_PE AFIO_EXTICR3_EXTI9_Msk SDIO_CMD_CMDINDEX_Msk ADC_SMPR1_SMP16_Pos FLASH_RDP_RDP_Msk CAN_F1R1_FB16 RCC_CR_CSSON_Msk USB_COUNT7_RX_1_COUNT7_RX_1 TIM_CCMR1_CC2S OTG_FS_WKUP_IRQn CAN_TDL0R_DATA0 USB_EP7R_DTOG_TX CAN_F5R2_FB20_Pos CAN_TI2R_EXID_Pos ADC_JDR4_JDATA CAN_F10R2_FB16_Pos CAN_F7R1_FB12 DBGMCU ADC_DR_ADC2DATA_Pos CAN_F12R2_FB12_Msk USB_EP0R_STAT_RX_Pos CAN_F13R2_FB5 +syn keyword CTagsDefinedName I2C_CCR_DUTY_Msk TIM_BDTR_AOE CAN_F12R2_FB5_Msk CAN_FM1R_FBM9_Pos CAN_F2R2_FB11_Msk USB_ADDR4_TX_ADDR4_TX_Msk PIN_OPT_AF6 USART_SR_RXNE CAN_F7R2_FB10 GPIO_CRL_MODE3_Msk GPIO_CRL_CNF0_0 CAN_F7R2_FB2_Msk AFIO_EVCR_PIN_PX8_Pos CAN_F3R1_FB11_Pos CAN_F8R2_FB1 EXTI_SWIER_SWIER4_Pos CAN_F9R1_FB22_Msk AFIO_EXTICR3_EXTI11_PC CAN_F8R2_FB24_Pos CAN_F4R2_FB0_Pos RCC_CSR_PINRSTF_Pos USB_EP3R_EP_TYPE DMA_CCR_DIR EXTI_SWIER_SWIER5_Msk DMA_ISR_GIF5_Pos CAN_F3R1_FB23 CAN_F7R2_FB11 +syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI1_PE SDIO_DCTRL_SDIOEN DBGMCU_CR_DBG_STANDBY_Pos USB_ADDR0_RX_ADDR0_RX_Pos RCC_APB2RSTR_ADC1RST_Pos USB_COUNT3_TX_0_COUNT3_TX_0 CAN_F13R1_FB24_Pos CAN_F2R2_FB11_Pos CAN_F11R1_FB4_Msk RTC_CRL_RTOFF_Pos USART_GTPR_GT TIM_SMCR_ETP USB_EP4R_DTOG_TX_Msk RCC_APB1ENR_USART3EN_Pos GPIO_LCKR_LCK7_Pos USB_EPRX_STAT_Pos CAN_RDT0R_FMI_Msk USB_EP3R_EP_TYPE_1 CAN_F3R2_FB3 CAN_F2R2_FB20_Msk TIM_EGR_CC1G CAN_MSR_SLAK_Msk CAN_F0R2_FB16_Pos DBGMCU_CR_TRACE_MODE_1 +syn keyword CTagsDefinedName CAN_F2R2_FB1_Msk AFIO_EXTICR2_EXTI5_PB_Msk SDIO_DTIMER_DATATIME_Msk TIM_SR_CC3OF_Pos BKP_CSR_CTE EXTI_SWIER_SWIER9 ADC_JSQR_JSQ4 USB_ISTR_RESET_Msk I2C_SR2_DUALF_Msk RCC_CIR_HSERDYC_Pos USB_COUNT5_RX_NUM_BLOCK CAN_F1R1_FB15_Msk ADC_SMPR2_SMP8_1 GPIO_IDR_IDR12_Pos CAN_F13R1_FB8_Pos DMA_ISR_TEIF3 RCC_CIR_LSERDYF_Pos AFIO_EXTICR1_EXTI0_PD_Msk AFIO_EXTICR3_EXTI8_PG CAN_F13R2_FB2_Msk CAN_F3R1_FB1_Msk CAN_F2R1_FB20_Msk TIM_CCMR1_OC1M_0 CAN_F3R2_FB27_Msk AFIO_EXTICR3_EXTI8_PF +syn keyword CTagsDefinedName USART_CR1_TXEIE_Msk USB_EP3R_CTR_TX CAN_F4R1_FB2_Msk CAN_F7R1_FB27_Pos USB_EP3R_EP_TYPE_Msk AFIO_EXTICR2_EXTI5_PF TIM_CCMR2_IC3F_1 USB_EP2R_STAT_RX AFIO_EXTICR3_EXTI8_PB TIM_CR1_CMS USB_EP0R_STAT_TX CAN_F5R2_FB14_Pos GPIO_LCKR_LCK2_Msk USB_EP1R_CTR_RX RCC_APB1ENR_WWDGEN_Pos USB_EP1R_EP_KIND_Msk GPIO_IDR_IDR4_Pos USART_CR2_LBCL_Msk CAN_F11R2_FB20 TIM_DIER_CC3DE SDIO_CMD_CPSMEN_Msk EXTI_EMR_MR6_Msk SDIO_STA_RXFIFOHF_Msk DBGMCU_IDCODE_REV_ID_10 GPIO_IDR_IDR1_Msk +syn keyword CTagsDefinedName RCC_CIR_HSIRDYF_Pos USB_EP0R_CTR_TX_Pos CAN_F3R2_FB1_Msk AFIO_EXTICR4_EXTI15_PD I2C_OAR2_ADD2_Msk CAN_RI1R_EXID GPIO_CRH_MODE15 RCC_CSR_IWDGRSTF_Pos CAN_RDL0R_DATA0_Pos CAN_F4R2_FB30 CAN_F0R1_FB19_Pos CAN_F7R2_FB1_Pos CAN_F6R1_FB6_Msk AFIO_EXTICR1_EXTI0_PD USB_COUNT7_TX_COUNT7_TX_Pos EXTI_PR_PR17 ADC_SMPR1_SMP12 CAN_F2R2_FB30 CAN_TSR_TXOK1 CAN_F6R1_FB12_Msk IS_TIM_OCXREF_CLEAR_INSTANCE DBGMCU_CR_TRACE_IOEN_Pos CAN_F4R1_FB11_Msk CAN_F3R2_FB27_Pos CAN_F5R1_FB30_Pos +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PE_Pos GPIO_CRH_CNF12_Pos SDIO_STA_RXFIFOE_Pos ADC_SQR2_SQ8 USB_EP4R_DTOG_RX USB_EP7R_DTOG_TX_Pos AFIO_EXTICR3_EXTI9_PE_Msk CAN_FA1R_FACT12_Pos GPIO_ODR_ODR10 EXTI_IMR_MR15_Msk SDIO_DCTRL_DBLOCKSIZE TIM_SMCR_TS_1 CAN_F0R1_FB2_Pos DMA_CCR_PSIZE_Pos RCC_BDCR_BDRST_Msk AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PG_Pos AFIO_EXTICR3_EXTI11_PD_Pos TIM_SMCR_ETF CAN_F0R2_FB23_Msk CAN_RDL0R_DATA1_Msk EXTI_FTSR_FT13 DMA_CMAR_MA CAN_F13R1_FB4_Pos TIM_CCMR2_CC4S_Msk +syn keyword CTagsDefinedName SDIO_MASK_TXUNDERRIE_Pos EXTI_IMR_MR14_Pos USB_EP0R_EP_TYPE_1 TIM_CR1_ARPE_Pos TIM_SMCR_ECE_Msk I2C_SR1_SMBALERT USART_GTPR_PSC_Msk ADC_SQR1_SQ14_0 USB_ADDR7_TX_ADDR7_TX_Pos GPIO_LCKR_LCKK_Pos PIN_5 CAN_F13R2_FB22_Msk PIN_4 CAN_FFA1R_FFA10_Msk USB_ADDR6_TX_ADDR6_TX_Msk CAN_F11R1_FB18_Msk CAN_F6R2_FB19_Pos AFIO_EXTICR2_EXTI5_PE USB_CNTR_FRES_Pos USB_CNTR_CTRM_Msk USART2_IRQ_PRIORITY CAN_F7R1_FB31_Pos TIM_EGR_CC4G I2C_CR2_FREQ_Msk CAN_F8R1_FB27_Pos USB_EP5R_EP_KIND_Pos +syn keyword CTagsDefinedName ADC_SMPR1_SMP15_1 SDIO_ICR_CMDRENDC_Pos SDIO_STA_DBCKEND_Msk USB_FNR_RXDP SPI_CR1_BIDIMODE CAN_F2R2_FB2_Msk IS_ADC_MULTIMODE_MASTER_INSTANCE AFIO_EXTICR3_EXTI9_PF CAN_F11R1_FB8_Pos ADC_SMPR2_SMP3_Pos ADC_CR2_EXTSEL_Pos USB_COUNT3_RX_1_NUM_BLOCK_1_2 CAN_F2R2_FB5_Msk CAN_F1R1_FB13_Msk CAN_F4R1_FB29 CAN_F0R1_FB13_Pos CAN_F13R1_FB5_Msk GPIO_LCKR_LCK5_Msk CAN_F2R1_FB25_Msk USB_COUNT2_RX_NUM_BLOCK_0 CAN_F5R2_FB2 AFIO_EXTICR1_EXTI3_PE_Msk AFIO_EXTICR2_EXTI4_PD_Msk CAN_F5R1_FB0_Pos +syn keyword CTagsDefinedName CAN_F6R1_FB0_Pos CAN_FFA1R_FFA2_Msk CAN_F13R1_FB27 GPIO_IDR_IDR2 CAN_F1R1_FB29_Msk CAN_F0R2_FB6_Pos USB_FNR_LSOF_Msk CAN_F1R1_FB27_Pos CAN_TDL1R_DATA1_Pos CAN_FM1R_FBM13 CAN_F6R1_FB18_Msk CAN_FM1R_FBM10 GPIO_IDR_IDR11_Pos DMA_IFCR_CHTIF4_Pos SDIO_CMD_WAITPEND SDIO_DCTRL_SDIOEN_Msk SPI_CR2_TXEIE_Pos TIM_SMCR_TS_2 TIM_CR2_OIS2N_Pos CAN_F9R1_FB17 CRC_IDR_IDR_Pos CAN_RDL1R_DATA2_Msk IWDG_PR_PR_Pos USB_DADDR_ADD2_Msk EXTI_SWIER_SWIER12_Pos CAN_F1R1_FB24_Msk CAN_F4R2_FB15_Pos +syn keyword CTagsDefinedName CAN_F10R2_FB13_Msk FLASH_DATA0_DATA0_Pos WWDG_CFR_W_3 CAN_F8R1_FB16_Pos CAN_F2R2_FB10_Pos RCC_APB2ENR_IOPBEN_Msk ADC_SQR3_SQ5_Pos USB_EP5R_DTOG_TX CAN_F7R1_FB1_Pos FLASH_WRP1_WRP1_Msk EXTI_EMR_EM16 RCC_CFGR_HPRE_DIV_128 EXTI_FTSR_FT14 GPIO_ODR_ODR1 USB_EP7R_EP_TYPE_1 TIM_CR1_CEN_Pos CAN_F6R2_FB24_Msk CAN_RF0R_FULL0_Pos USB_COUNT7_RX_COUNT7_RX_Msk CAN_F0R1_FB2_Msk TIM_CCMR1_OC2M_2 PIN_OPT_RESISTOR_PULLDOWN CAN_F11R1_FB0 SPI_CR1_BIDIOE_Msk EXTI_RTSR_RT10 CAN_MSR_INAK SPI_CR1_DFF +syn keyword CTagsDefinedName I2C_SR1_PECERR_Msk CAN_F5R1_FB13_Pos TIM_CCMR1_CC1S_Pos FLASH_ACR_LATENCY USB_COUNT1_RX_0_NUM_BLOCK_0_4 AFIO_EXTICR1_EXTI3_PD_Msk RCC_APB1ENR_TIM2EN ADC_SR_STRT_Msk CAN_TSR_TXOK2 CAN_TSR_TXOK0_Msk GPIO_CRL_CNF3 USB_EPRX_DTOG1 CAN_F6R1_FB18_Pos CAN_F1R1_FB6_Pos CAN_F3R1_FB19_Pos SDIO_STA_STBITERR CAN_F1R2_FB26_Pos TIM10_IRQn CAN_F2R1_FB14_Pos PWR_CR_CSBF_Pos CAN_F5R2_FB26_Pos GPIO_IDR_IDR11_Msk TIM_DCR_DBL CAN_F7R1_FB31_Msk CAN_FA1R_FACT10_Pos FLASH_OBR_DATA1 CAN_F6R2_FB14_Msk +syn keyword CTagsDefinedName AFIO_EVCR_PORT_PC CAN_F0R2_FB26_Msk AFIO_EXTICR1_EXTI1_PC_Msk GPIO_LCKR_LCK15_Msk EXTI_EMR_MR4_Pos TIM_CCER_CC1E AFIO_EXTICR4_EXTI14_PC_Msk AFIO_EVCR_PIN_PX14_Msk CAN_F3R2_FB16_Pos TIM_CCMR2_IC3PSC_Msk RCC_APB1ENR_USBEN_Pos CAN_F10R1_FB12_Pos CAN_FA1R_FACT_Msk GPIO_BSRR_BR4_Msk CAN_F6R2_FB16_Pos CAN_F2R1_FB0_Msk CAN_F12R2_FB13_Pos CAN_TI2R_STID GPIO_IDR_IDR5 GPIO_BRR_BR13_Msk RCC_CFGR_MCO_2 CAN_F4R1_FB3_Msk CAN_F13R2_FB25_Pos CAN_F11R2_FB21_Pos I2C_CR1_NOSTRETCH +syn keyword CTagsDefinedName GPIO_ODR_ODR9_Pos CAN_F4R1_FB1 CAN_F11R1_FB14_Pos RCC_APB1RSTR_TIM3RST_Pos BKP_CR_TPE CAN_ESR_TEC_Msk CAN_TSR_TME0 GPIO_BRR_BR8 CAN_F13R1_FB13_Pos GPIO_BSRR_BR3_Msk IWDG_RLR_RL_Msk CAN_TI1R_EXID_Pos CAN_TSR_CODE_Msk CAN_F5R1_FB4_Pos I2C_CR2_ITERREN RCC_APB2RSTR_IOPBRST_Msk SDIO_STA_STBITERR_Msk CAN_ESR_BOFF TIM_CCER_CC2NE USB_COUNT1_RX_NUM_BLOCK_0 I2C_SR2_DUALF_Pos SPI_CR1_SSI GPIO_ODR_ODR12_Pos CAN_RI1R_RTR_Msk GPIO_BSRR_BR11_Pos CAN_F3R1_FB21_Msk CAN_F9R2_FB22 +syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP CAN_F0R2_FB19 EXTI_RTSR_TR16_Pos CAN_FFA1R_FFA3_Pos CAN_F13R2_FB15 GPIO_BRR_BR14 USB_DADDR_ADD4 CAN_F7R1_FB30_Pos AFIO_MAPR_CAN_REMAP_REMAP3 USB_EP0R_STAT_RX_Msk CAN_F8R2_FB15_Pos USB_EP6R_SETUP_Pos CAN_F11R2_FB9 USART_CR1_TCIE_Pos CAN_F12R1_FB2 CAN_TI0R_RTR_Pos SPI_I2SCFGR_I2SMOD AFIO_EXTICR1_EXTI0_PF_Pos DMA_CCR_MSIZE USB_DADDR_ADD2_Pos I2C_CR2_FREQ_1 SDIO_DCTRL_SDIOEN_Pos GPIO_CRH_CNF10_0 CAN_F11R2_FB26_Pos CAN_F3R2_FB21_Msk USB_EP3R_DTOG_TX_Msk +syn keyword CTagsDefinedName CAN_F9R1_FB29 TIM_CNT_CNT_Pos ADC_SQR2_SQ12_4 DMA_ISR_GIF6_Pos CAN_F2R2_FB25_Pos AFIO_MAPR_SPI1_REMAP ADC_CR1_AWDSGL CAN_F10R2_FB12_Msk CAN_F12R1_FB23_Pos SDIO_CMD_CEATACMD_Pos CAN_F1R2_FB28_Msk CAN_F4R2_FB4_Msk GPIO_BRR_BR12_Pos CAN_MCR_NART_Msk CAN_RDT1R_DLC CAN_F12R2_FB19_Msk BKP_CSR_TEF SDIO_MASK_CEATAENDIE_Msk CAN_F3R1_FB8 AFIO_EXTICR1_EXTI2_PB_Pos CAN_F5R1_FB19_Msk SDIO_ARG_CMDARG GPIO_IDR_IDR8_Msk CEC_IRQHandler TIM_CCMR2_CC4S_Pos USB_EP3R_DTOG_TX USB_EP7R_CTR_RX_Msk +syn keyword CTagsDefinedName FLASH_BANK1_END CAN_FS1R_FSC9_Msk DMA_CCR_PINC_Pos CAN_F7R1_FB4 RCC_CR_PLLON_Msk TIM_CCMR1_IC2PSC_1 FLASH_WRP1_WRP1_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_4 CAN_F1R2_FB1 GPIO_CRH_MODE8_1 USB_EP0R_DTOG_RX ADC_CR1_DISCEN BKP_DR9_D ADC_CR2_EXTSEL_Msk USB_CNTR_WKUPM CAN_F2R2_FB24_Msk SDIO_ICR_DCRCFAILC CAN_F1R1_FB11_Pos CAN_F0R1_FB18_Msk EXTI_PR_PR16_Msk CAN_F7R2_FB25 CAN_IER_EWGIE_Pos SPI_CR1_BIDIMODE_Msk TIM_CCMR2_OC4FE_Msk RCC_CFGR_USBPRE USB_COUNT2_RX_NUM_BLOCK_3 GPIO_CRH_CNF8_Msk +syn keyword CTagsDefinedName USB_CNTR_ERRM_Msk ADC_SQR2_SQ12_Pos DMA_IFCR_CHTIF5_Msk CAN_F0R1_FB15 AFIO_EXTICR1_EXTI0_PE_Pos USB_EPRX_STAT RCC_CSR_PINRSTF USB_EP7R_CTR_RX CAN_F6R1_FB0 TIM_CCER_CC1E_Msk USB_ADDR3_RX_ADDR3_RX_Pos CAN_TDT1R_TGT USB_EP2R_DTOG_RX_Pos CAN_F1R2_FB2_Msk AFIO_EVCR_PIN_0 GPIO_IDR_IDR7 TIM_CR2_OIS1N_Msk GPIO_CRL_MODE TIM_CCMR2_OC4PE CAN_F7R1_FB30 GPIO_CRH_MODE8_Msk CAN_F6R1_FB4_Msk CAN_F2R2_FB21_Pos CAN_F5R2_FB24 GPIO_CRL_CNF0_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_2 CAN_F9R1_FB10 +syn keyword CTagsDefinedName USB_CNTR_RESUME IWDG_PR_PR_1 CAN_RDT1R_FMI_Msk CAN_F4R2_FB27_Msk CAN_F10R2_FB3_Msk EXTI_SWIER_SWI16 CAN_F0R2_FB18_Pos EXTI_FTSR_TR10 CAN_F9R1_FB5 CAN_F11R2_FB24 CAN_F10R1_FB20 RCC_BDCR_RTCSEL_Msk CAN_F8R2_FB15_Msk CEC_IRQn CAN_F13R1_FB31_Msk FLASHSIZE_BASE CAN_F8R1_FB24_Pos SDIO_DLEN_DATALENGTH_Pos EXTI_RTSR_TR6_Pos BKP_DR10_D_Pos CAN_F12R1_FB30_Msk RCC_CSR_LSION TIM2_IRQ_PRIORITY USB_COUNT6_RX_1_COUNT6_RX_1 CAN_F1R1_FB8_Msk EXTI_EMR_MR9_Pos TIM_SR_CC3IF_Msk IS_SPI_ALL_INSTANCE +syn keyword CTagsDefinedName CAN_TDL0R_DATA0_Msk GPIO_CRL_CNF2_1 CAN_F10R2_FB8_Msk RCC_CIR_CSSF_Pos CAN_F5R1_FB6_Pos USART_CR1_M CAN_TDH1R_DATA6_Msk RCC_CIR_LSIRDYIE CAN_FFA1R_FFA9_Msk CAN_F11R2_FB5 TIM_DMAR_DMAB_Pos CAN_F12R2_FB1_Pos CAN_F0R2_FB19_Msk AFIO_EVCR_PIN_PX4_Pos CAN_F1R1_FB21_Msk CAN_F6R1_FB5_Pos AFIO_EXTICR2_EXTI7_PC_Msk FLASH_DATA0_nDATA0_Msk TIM_ARR_ARR_Pos SPI_CR2_SSOE_Msk CAN_F10R1_FB8_Msk CAN_F8R1_FB27_Msk CAN_F9R1_FB1_Msk ADC_CR1_DISCEN_Pos ADC_CR2_ADON ADC_CR2_EXTSEL_1 CAN_F1R2_FB0_Msk +syn keyword CTagsDefinedName CAN_F2R2_FB9_Pos CAN_F8R1_FB22_Msk GPIO_BSRR_BR8_Msk TIM_CCMR1_OC2CE AFIO_EXTICR2_EXTI6_PF USART_CR3_HDSEL_Msk SDIO_MASK_CMDRENDIE_Msk CAN_MSR_SLAK CAN_F8R2_FB6_Msk DMA_CCR_TCIE GPIO_LCKR_LCK12_Pos EXTI_RTSR_TR10 CAN_IER_FOVIE0_Msk I2C_SR1_BTF_Pos SDIO_STA_RXOVERR_Msk SPI_RXCRCR_RXCRC USB_EP6R_EP_TYPE USB_EP_T_MASK FLASH_WRP1_nWRP1_Msk TIM_CCMR1_CC2S_0 CAN_F0R1_FB4 DMA_ISR_HTIF5_Pos EXTI_IMR_MR16_Pos I2C_CR1_POS_Msk USB_COUNT5_RX_1_NUM_BLOCK_1_3 USB_EP2R_STAT_RX_Msk +syn keyword CTagsDefinedName I2C_CR1_SMBTYPE_Msk CAN_MCR_SLEEP_Msk CAN_F12R2_FB11 CAN_F8R1_FB3_Msk EXTI_RTSR_TR9_Pos SDIO_MASK_DBCKENDIE_Msk SPI_SR_RXNE_Msk CAN_F1R1_FB8 USB_EP7R_STAT_RX DMA_ISR_HTIF6_Msk GPIO_BSRR_BS13 CAN_F13R1_FB19_Msk GPIO_CRL_CNF3_Pos CAN_BTR_BRP CAN_F3R1_FB23_Msk GPIO_LCKR_LCK11_Msk CAN_F3R2_FB4 TIM1 I2C_OAR1_ADD1_7 RCC_CIR_PLLRDYC_Pos USART_GTPR_PSC_0 SPI_SR_BSY_Pos EXTI_IMR_MR13 FLASH_SR_PGERR FLASH_OBR_DATA1_Msk CAN_F1R2_FB10 CAN_F2R2_FB24 CAN_F8R2_FB6_Pos CAN_F11R1_FB15 +syn keyword CTagsDefinedName CAN_F3R2_FB29 CAN_F9R1_FB23_Msk CAN_F13R1_FB30 CAN_F1R1_FB5_Msk CAN_F11R2_FB13_Pos AFIO_EVCR_PIN_PX9 DMA_CCR_MEM2MEM_Pos RCC_CFGR_PLLMULL4_Msk ADC_SQR2_SQ7_1 CAN_F9R1_FB12 CAN_F2R2_FB22 CAN_F8R2_FB21_Msk CAN_RDL0R_DATA0_Msk GPIO_ODR_ODR11_Pos USB_EP6R_DTOG_TX_Msk CAN_TDL1R_DATA2_Msk GPIO_CRH_CNF9_Msk RCC_CFGR_USBPRE_Msk CAN_TSR_ALST2_Msk CAN_F2R1_FB25 CAN_F11R2_FB11_Pos EXTI_FTSR_TR7_Msk RTC_PRLH_PRL_Pos CAN_F4R1_FB30 EXTI_SWIER_SWIER2_Msk CAN_RDT0R_DLC_Msk CAN_BTR_TS1_3 +syn keyword CTagsDefinedName CAN_F13R1_FB14_Pos SDIO_POWER_PWRCTRL_Msk USB_COUNT3_RX_0_NUM_BLOCK_0_0 EXTI_SWIER_SWIER3_Pos ADC_SR_AWD_Pos USB_COUNT5_RX_NUM_BLOCK_4 CAN_F4R1_FB19_Msk CAN_F0R1_FB25_Msk TIM_CCMR1_IC1F_1 ADC_JSQR_JSQ4_2 AFIO_EXTICR4_EXTI14_PD PIN_MODE_OUTPUT CAN_F8R2_FB13 CAN_F11R2_FB31_Msk CAN_TSR_TME2 DBGMCU_IDCODE_REV_ID_8 USB_COUNT0_RX_COUNT0_RX_Msk SDIO_MASK_TXDAVLIE_Pos USART_SR_LBD DMA_ISR_TEIF1_Pos FLASH_WRP3_nWRP3_Msk USB_COUNT4_RX_NUM_BLOCK RCC_CFGR_HPRE_3 TIM_SMCR_SMS_1 +syn keyword CTagsDefinedName CAN_F1R2_FB8_Msk CAN_F8R2_FB6 TIM_BDTR_DTG_2 ADC_DR_DATA EXTI_RTSR_TR6 WWDG_CFR_EWI_Msk CAN_F10R2_FB6_Pos CAN_F9R2_FB30_Pos DMA_IFCR_CTEIF4_Msk I2C_CR1_ENPEC_Pos AFIO_EXTICR2_EXTI5_PG_Pos RCC_CIR_LSIRDYC_Msk CAN_F2R2_FB3_Msk CAN_F12R1_FB25_Pos CAN_TI0R_RTR_Msk DMA1_Channel1_BASE AFIO_EXTICR4_EXTI14_PF_Pos CAN_F1R2_FB16 CAN_F1R2_FB25_Pos GPIO_IDR_IDR13_Pos AFIO_MAPR_CAN_REMAP_Msk CAN_F9R1_FB27_Pos USB_EP5R_EP_TYPE_0 CAN_F11R2_FB20_Msk AFIO_EXTICR3_EXTI8_Msk RCC_APB1RSTR_TIM2RST +syn keyword CTagsDefinedName USB_EP2R_DTOG_RX USB_ADDR5_RX_ADDR5_RX_Msk PWR_CSR_WUF EXTI_FTSR_FT5 AFIO_EXTICR2_EXTI4_Msk CAN_F2R1_FB28_Msk RCC_APB1ENR_TIM2EN_Pos TIM_CR2_OIS2N AFIO_EXTICR1_EXTI1_PG_Msk ADC_CR1_AWDSGL_Msk CAN_TSR_TXOK2_Pos CAN_F12R2_FB7 DMA_ISR_HTIF2 GPIO_ODR_ODR5_Pos AFIO_EXTICR1_EXTI0_PB_Msk SDIO_DLEN_DATALENGTH TIM_SMCR_SMS_0 USART_CR3_EIE DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk EXTI_IMR_IM15 EXTI_SWIER_SWI3 CAN_F2R1_FB12 CAN_F13R1_FB31_Pos CAN_F0R2_FB25_Msk CAN_F7R1_FB19_Pos +syn keyword CTagsDefinedName CAN_TDL0R_DATA1 ADC_SMPR1_SMP14_Msk RCC_CFGR_SW IWDG_SR_RVU_Pos GPIO_BRR_BR7_Pos CAN_F2R1_FB20_Pos ADC_CR2_RSTCAL_Pos CAN_TSR_CODE_Pos EXTI_EMR_EM17 TIM_BDTR_MOE USB_COUNT3_RX_BLSIZE_Pos CAN_F10R2_FB30_Pos CAN_F11R1_FB3 CAN_F3R2_FB18 CAN_F13R1_FB1_Msk I2C_CCR_DUTY_Pos USB_EP3R_STAT_RX_1 RCC_BDCR_LSEON_Msk WWDG_CFR_W4 CAN_F9R2_FB18_Msk FLASH_ACR_PRFTBS_Msk CAN_F6R1_FB29 CAN_F3R1_FB25_Pos TIM_BDTR_BKE_Msk CAN_F11R1_FB31_Msk ADC_CR2_JEXTTRIG_Pos CAN_F8R1_FB23 ADC_JSQR_JSQ3_4 +syn keyword CTagsDefinedName CAN_F5R2_FB13_Pos TIM_CR2_OIS3N RCC_CFGR_MCOSEL_HSI RCC_CIR_HSIRDYIE_Pos GPIO_CRL_MODE0 ADC_CR2_RSTCAL TIM_CCMR2_IC3F_0 WWDG_CR_T_3 RTC_CRL_SECF CAN_F9R2_FB19 AFIO_EVCR_PIN_PX1_Msk RCC_CFGR_USBPRE_Pos CAN_F1R2_FB29_Pos I2C_CR2_LAST_Pos ADC_SQR2_SQ8_Pos DMA_ISR_TEIF7_Msk GPIO_CRH_MODE14_Pos TIM_CCMR2_IC4PSC_Pos USB_EP1R_DTOG_RX_Pos DMA_ISR_HTIF3_Pos CAN_F6R2_FB21_Msk CAN_F13R2_FB9_Msk RCC_APB2ENR_IOPBEN_Pos CAN_MCR_AWUM_Pos BKP_CSR_CTI_Msk CAN_F6R2_FB20 AFIO_EXTICR1_EXTI3_PF +syn keyword CTagsDefinedName USB_ISTR_SOF_Msk GPIO_CRL_MODE2 AFIO_EXTICR3_EXTI8 DBGMCU_CR_DBG_WWDG_STOP_Pos TIM1_UP_TIM10_IRQn DMA_CCR_TCIE_Msk ADC_SMPR2_SMP0_Msk AFIO_MAPR_USART3_REMAP_1 GPIO_IDR_IDR3_Msk I2C_CR2_ITEVTEN SDIO_ICR_DTIMEOUTC_Pos USB_EP_SETUP_Pos USB_ADDR1_TX_ADDR1_TX_Msk CAN_F3R1_FB22 CAN_TSR_TME0_Pos USB_COUNT1_RX_1_NUM_BLOCK_1_2 CAN_F9R1_FB9_Msk GPIO_BSRR_BS11 CAN_MSR_ERRI SPI_SR_TXE RCC_CFGR_MCO_NOCLOCK SYSCFG_EXTI_PC_MASK CAN_F11R1_FB30_Pos FLASH_CR_LOCK_Msk SDIO_RESP1_CARDSTATUS1_Pos +syn keyword CTagsDefinedName CAN_F13R2_FB30_Pos CAN_F12R2_FB31_Pos ADC_SQR3_SQ6_1 CAN_F2R1_FB30 CAN_TSR_TXOK0_Pos USB_FNR_FN CAN_F6R1_FB12_Pos CAN_F11R2_FB0_Pos CAN_F6R2_FB21_Pos CAN_F11R1_FB0_Msk USB_EP6R_STAT_TX_Pos ADC_SMPR1_SMP12_Pos CAN_MCR_RFLM_Msk USART_SR_FE_Pos CLEAR_BIT CAN_FFA1R_FFA0 EXTI_EMR_MR12_Msk CAN_F13R1_FB0 CAN_F1R1_FB18_Msk USB_EPADDR_FIELD CAN_F0R2_FB3 SDIO_STA_CMDREND_Msk CAN_F12R2_FB12_Pos ADC_CR1_AWDIE_Pos SDIO_MASK_DBCKENDIE_Pos CAN_F13R1_FB29 CAN_F9R1_FB24_Pos EXTI_FTSR_FT3 +syn keyword CTagsDefinedName GPIO_IDR_IDR9_Msk AFIO_EXTICR1_EXTI1_Pos CAN_F1R2_FB24_Pos CAN_F6R1_FB9 GPIO_ODR_ODR4_Msk CAN_F7R2_FB5 USB_EP6R_DTOG_RX_Pos GPIO_IDR_IDR4 CAN_F10R1_FB10_Pos EXTI_RTSR_TR15_Msk CAN_ESR_EPVF_Pos AFIO_EXTICR3_EXTI9_PG_Pos USB_COUNT2_RX_BLSIZE ADC_CR1_DISCNUM_0 CAN_FFA1R_FFA4_Msk CAN_F1R2_FB9 CAN_F9R2_FB18 CAN_F1R1_FB6_Msk CAN_TSR_ALST0_Pos PERIPH_BASE CAN_F12R2_FB0_Msk DMA_ISR_TCIF4_Msk FLASH_KEY2_Msk DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT RCC_CFGR_HPRE_DIV1 AFIO_EVCR_PIN_PX2_Msk +syn keyword CTagsDefinedName USB_COUNT5_RX_BLSIZE_Pos TIM_CR2_CCUS_Pos ADC_SMPR1_SMP17 CAN_F8R1_FB21_Pos GPIO_CRL_MODE2_Pos GPIO_CRL_MODE6_Pos CAN_RF1R_FOVR1_Pos GPIO_CRL_CNF6_Pos SDIO_ARG_CMDARG_Msk CAN_F2R2_FB10_Msk AFIO_EXTICR1_EXTI0_PE BKP_CSR_TEF_Msk CAN_F2R2_FB29_Msk CAN_F8R2_FB31_Pos CAN_TSR_ABRQ2_Msk CAN_F5R1_FB11 CAN_FFA1R_FFA_Pos DBGMCU_IDCODE_REV_ID_Pos CAN_F6R1_FB31 RCC_CFGR_PLLMULL14 RCC_APB2ENR_AFIOEN USB_COUNT0_RX_0_NUM_BLOCK_0_4 AFIO_EXTICR4_EXTI12_PE_Pos CAN_ESR_TEC_Pos PIN_0 +syn keyword CTagsDefinedName USB_EP1R_EP_TYPE TIM_BDTR_OSSI_Pos CAN_F13R2_FB8_Msk CAN_F1R2_FB9_Msk CAN_RDL1R_DATA0_Msk CAN_F9R1_FB1_Pos I2C_OAR1_ADD1_Pos SDIO_STA_RXACT_Msk USB_ADDR7_RX_ADDR7_RX_Msk EXTI_IMR_IM16 CAN_F0R2_FB25_Pos PWR_CR_PLS_LEV6 EXTI_FTSR_TR5_Msk CAN_F8R2_FB31 CAN_F6R2_FB18_Pos TIM_BDTR_OSSI USART_CR2_CLKEN CAN_ESR_REC_Pos USB_EP3R_STAT_TX_0 CAN_F1R2_FB0 CAN_F9R2_FB9 I2C_CR1_PEC_Pos TIM_CR2_OIS2 EXTI_FTSR_TR6_Pos TIM_DIER_CC1DE ADC_CR2_EXTTRIG_Pos CAN_F1R1_FB17_Pos EXTI_FTSR_TR14 +syn keyword CTagsDefinedName USB_COUNT2_RX_BLSIZE_Pos CAN_FA1R_FACT1_Pos CAN_F11R2_FB17_Msk CAN_F12R1_FB3 CAN_TI1R_IDE CAN_F9R1_FB9_Pos CAN_F0R1_FB13 AFIO_EXTICR2_EXTI6_Msk USB_COUNT3_RX_0_NUM_BLOCK_0_4 CAN_F11R1_FB23_Msk DMA1_Channel5_BASE TIM_SR_CC3IF USB_COUNT7_RX_1_BLSIZE_1 USB_ISTR_PMAOVR_Msk CAN_F8R2_FB25 GPIO_ODR_ODR14_Pos USB_EP6R_EA TIM_CCMR2_IC4PSC I2C_CR2_ITBUFEN_Msk USB_EP5R_DTOG_RX USB_EP3R_STAT_TX_Pos CAN_F10R2_FB22_Msk RCC_BDCR_RTCEN_Msk CAN_F0R2_FB27 USB_EP_DTOG_TX RCC_CIR_LSERDYC_Pos +syn keyword CTagsDefinedName CAN_F7R2_FB12 FLASH_KEYR_FKEYR_Msk ADC_CR2_TSVREFE_Pos EXTI_IMR_MR14_Msk DMA_IFCR_CGIF1 CAN_F4R2_FB12_Msk BKP_CSR_CTI_Pos GPIO_BSRR_BR11_Msk TIM_CCR3_CCR3_Pos USB_EP3R_SETUP_Pos CAN_F9R1_FB4 EXTI_IMR_MR5_Pos USB_CNTR_FRES_Msk RCC_APB1ENR_USART2EN I2C_CR1_ENGC_Pos TIM_SMCR_ETP_Msk CAN_F0R2_FB21_Pos BKP_RTCCR_ASOS FLASH_WRP3_nWRP3_Pos USB_EP2R_SETUP_Pos CAN_F6R2_FB0_Msk CAN_F5R2_FB22_Pos CAN_FFA1R_FFA6 USB_EP0R_STAT_TX_Msk GPIO_LCKR_LCK15_Pos CAN_F9R1_FB3_Msk +syn keyword CTagsDefinedName SDIO_RESP3_CARDSTATUS3_Pos CAN_TI2R_IDE_Pos CAN_FA1R_FACT8_Pos CAN_FS1R_FSC10_Msk RCC_APB1RSTR_USART2RST IWDG CAN_F0R2_FB2_Pos SDIO_MASK_CEATAENDIE AFIO_EVCR_PIN_PX4 BKP_DR2_D_Msk GPIO_BSRR_BR5 TIM_CNT_CNT_Msk CAN_F13R1_FB5_Pos GPIO_CRH_MODE11 GPIO_BRR_BR8_Msk GPIO_CRH_MODE15_1 USB_CNTR_RESETM EXTI_PR_PIF17 USB_EP6R_STAT_TX_1 CAN_F5R1_FB31_Msk TIM_CCR4_CCR4_Pos EXTI_PR_PR7 CAN_F11R1_FB19 CAN_F10R2_FB29 USART1 USART_SR_TXE_Pos USB_EPTX_DTOGMASK TIM_CCMR1_IC2PSC +syn keyword CTagsDefinedName CAN_F11R1_FB13_Pos AFIO_EXTICR4_EXTI13_PB_Pos ADC_SQR1_L_1 CAN_F11R2_FB8 CAN_F11R2_FB16_Msk CAN_F11R2_FB6_Msk ADC_CR1_AWDCH_Pos GPIO_BSRR_BR2_Pos CAN_MSR_RXM_Pos USB_COUNT7_RX_0_NUM_BLOCK_0_1 RCC_CFGR_PPRE1_Pos ADC_SR_AWD_Msk CAN_F10R1_FB17 CAN_F12R2_FB24_Msk AFIO_EVCR_PIN_PX4_Msk USB_COUNT6_RX_NUM_BLOCK_Pos CAN_F2R2_FB0_Pos CAN_F3R2_FB8_Pos SDIO_RESP0_CARDSTATUS0_Msk CAN_F1R2_FB19 PIN_14 ADC_SMPR2_SMP6_Msk SDIO_RESP2_CARDSTATUS2_Pos I2C_CR2_ITEVTEN_Msk ADC_CR2_JEXTSEL_Pos +syn keyword CTagsDefinedName AFIO_EXTICR3_EXTI10_PF_Pos CAN_F0R2_FB6_Msk CAN_TDH2R_DATA7 CAN_F1R2_FB25 CAN_F9R1_FB20 TIM_DIER_CC2DE_Pos AFIO_EXTICR4_EXTI12_PB_Pos CAN_F5R2_FB3 CAN_F4R2_FB23 CAN_TSR_TME0_Msk CAN_F8R1_FB4_Msk CAN_F13R2_FB1 CAN_F11R2_FB13 RCC_CFGR_SWS_HSE GPIO_LCKR_LCK14_Pos I2C_OAR1_ADD0 CAN_F12R1_FB1_Msk AFIO_EVCR_PORT_1 AFIO_EVCR_PIN_3 USB_EP_RX_STALL CAN_F5R1_FB2_Pos AFIO_EXTICR2_EXTI6_PG_Msk CAN_F12R2_FB8 SDIO_DCTRL_RWMOD_Pos CAN_FA1R_FACT11 CAN_F6R2_FB23_Pos TIM_CCER_CC4P_Msk +syn keyword CTagsDefinedName DMA_ISR_TCIF2 GPIO_CRL_MODE1 EXTI_SWIER_SWIER14_Pos USB_ADDR1_TX_ADDR1_TX AFIO_EXTICR2_EXTI6_PC TIM_EGR_CC2G CAN_F6R2_FB10_Msk RCC_BDCR_RTCSEL_Pos DMA1_Channel6 RCC_CR_HSERDY WWDG_CFR_W3 SDIO_STA_RXFIFOHF TIM_CR2_TI1S USB_EP_CTR_TX ADC_SQR3_SQ2_2 CAN_BTR_LBKM_Pos CAN_F1R2_FB15 GPIO_BSRR_BS12_Msk RCC_CFGR_PLLMULL6_Msk CAN_F11R2_FB27_Msk CAN_F12R2_FB18_Msk I2C_CR1_ACK_Pos RCC_CSR_LPWRRSTF CAN_MCR_TXFP_Pos SDIO_RESPCMD_RESPCMD_Pos CAN_FM1R_FBM3 CAN_F7R1_FB7 +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PF_Msk CAN_F5R1_FB21_Msk CAN_F7R1_FB21 CAN_F6R1_FB30_Pos FLASH_OBR_nRST_STOP_Pos PIN_2 CAN_F10R1_FB27_Pos CAN_F3R2_FB24 TIM_CCMR1_OC1CE_Msk AFIO_EXTICR3_EXTI10_PE_Pos CAN_F10R1_FB22_Pos I2C_SR1_ADD10_Msk USB_COUNT3_RX_1_NUM_BLOCK_1_1 ADC_CR1_DUALMOD_Pos CAN_F7R1_FB14 CAN_F4R2_FB20 CAN_F7R2_FB4 CAN_F9R1_FB22_Pos IS_TIM_COMMUTATION_EVENT_INSTANCE CAN_RDL0R_DATA1_Pos CAN_F6R2_FB6_Pos GPIO_CRL_CNF4 AFIO_EXTICR2_EXTI6_PE_Msk AFIO_EXTICR3_EXTI9_PC +syn keyword CTagsDefinedName RCC_APB2RSTR_SPI1RST_Msk EXTI_PR_PR3_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk EXTI_IMR_IM6 CAN_F3R1_FB26 TIM_SMCR_SMS_2 CAN_RDH0R_DATA6 IS_SMARTCARD_INSTANCE CAN_F13R2_FB1_Msk GPIO_CRH_MODE13 CAN_F12R1_FB20 USB_EP1R_EP_TYPE_0 CAN_F11R2_FB25_Msk EXTI_PR_PR13_Pos AFIO_EXTICR4_EXTI14 SDIO_CLKCR_WIDBUS GPIO_IDR_IDR1 FLASH_DATA1_DATA1 CAN_F1R1_FB4_Msk GPIO_CRH_CNF9 CAN_F7R2_FB30_Pos TIM_CCMR2_IC3F_Msk CAN_F12R2_FB2_Pos CAN_F1R2_FB16_Pos USART_CR2_LBDL CAN_MCR_INRQ_Pos +syn keyword CTagsDefinedName TIM_SR_UIF_Pos CAN_F0R1_FB30_Msk CAN_IER_FMPIE1_Pos CAN_FMR_FINIT_Pos CAN_F1R1_FB28 CAN_F10R1_FB28_Pos RCC_APB1ENR_I2C2EN BKP_DR6_D CAN_F12R2_FB28 CAN_F6R1_FB6 SDIO_DCTRL_DBLOCKSIZE_Pos SDIO_MASK_TXFIFOFIE_Pos USB_EP_CTR_TX_Msk CAN_FS1R_FSC4_Msk USB_EP1R_EA_Pos TIM_CCER_CC2E SDIO_STA_DCRCFAIL_Msk USB_COUNT7_TX_1_COUNT7_TX_1 CAN_F0R2_FB17 CAN_F10R2_FB1 __STM32F1_CMSIS_VERSION CAN_F8R2_FB3 TIM_SR_CC1IF_Msk AFIO_EXTICR3_EXTI8_PC AFIO_MAPR_SWJ_CFG_DISABLE_Pos +syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI0_PF_Msk FLASH_WRPR_WRP_Pos RCC_CIR_LSIRDYC_Pos CRC_CR_RESET_Pos CAN_RDL0R_DATA2 ADC_SQR3_SQ2_Msk CAN_BTR_SJW_Pos CAN_TSR_ALST2 EXTI_RTSR_TR11 RTC_CRL_RSF CAN_F3R1_FB0_Pos CAN_F7R1_FB9_Msk CAN_F9R1_FB16 EXTI_FTSR_FT16 DMA_IFCR_CGIF2 GPIO_ODR_ODR14_Msk SDIO_ICR_DATAENDC_Msk CAN_F5R1_FB22_Pos DMA_CCR_MINC_Msk SDIO_CMD_NIEN_Pos CAN_F7R1_FB7_Msk ADC_SMPR1_SMP12_Msk TIM_BDTR_AOE_Msk CAN_F11R1_FB25_Msk CAN_F11R2_FB9_Pos CAN_TDT2R_TIME_Msk CAN_F10R1_FB5_Msk +syn keyword CTagsDefinedName CAN_TDT2R_TGT_Pos CAN_F0R1_FB23_Msk PWR_CR_CWUF_Pos SPI_CR2_SSOE BKP_RTCCR_CAL_Pos CAN_ESR_REC_Msk CAN_F12R2_FB9_Msk SDIO_FIFOCNT_FIFOCOUNT_Pos AFIO_EVCR_PIN_PX1_Pos RCC_CIR_PLLRDYF_Msk CAN_F0R2_FB31_Pos CAN_F11R1_FB25 SDIO_STA_CTIMEOUT_Pos CAN_TDL0R_DATA1_Msk AFIO_MAPR_TIM2_REMAP_NOREMAP CAN_F1R1_FB26 CAN_F12R1_FB24 FLASH_CR_OPTER DMA_CNDTR_NDT DBGMCU_IDCODE_DEV_ID_Msk SPI_SR_CRCERR CAN_BTR_TS1_0 CAN_F7R2_FB9_Pos CAN_F2R1_FB9_Pos GPIO_CRL_CNF2_Msk TIM_CR2_OIS1_Msk WWDG_CFR_W +syn keyword CTagsDefinedName CAN_TSR_RQCP1 TIM_CCMR2_IC3F DMA_IFCR_CGIF1_Pos IS_CAN_ALL_INSTANCE TIM_CR1_CMS_0 CAN_F9R2_FB8 PWR_CSR_EWUP_Msk IS_TIM_CCX_INSTANCE CAN_F1R1_FB0 CAN_F3R1_FB10 CAN_F9R1_FB20_Pos CAN_F8R1_FB19 IS_UART_MULTIPROCESSOR_INSTANCE ADC_JOFR1_JOFFSET1 CAN_F6R2_FB0_Pos USB_COUNT4_RX_0_NUM_BLOCK_0_4 AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos SDIO_DCTRL_DBLOCKSIZE_1 USART_CR1_PS_Pos ADC_SMPR2_SMP4_Pos DMA_IFCR_CGIF5_Pos CAN_TI2R_RTR_Msk USB_EP6R_DTOG_RX CAN_F1R2_FB24 WWDG_CFR_W0 AFIO +syn keyword CTagsDefinedName USB_ISTR_WKUP_Pos RCC_CR_HSION USB_COUNT4_RX_NUM_BLOCK_Msk USB_EP0R_DTOG_RX_Msk CAN_TSR_ALST1_Pos PWR_CR_PLS_LEV5 CAN_F7R1_FB20_Msk GPIO_BSRR_BS9 BKP_RTCCR_CCO_Pos EXTI_FTSR_FT2 CAN_F8R2_FB2 CAN_F6R1_FB11_Msk AFIO_MAPR_TIM3_REMAP_1 DMA_IFCR_CHTIF6 CAN_F3R1_FB29_Pos SPI_TXCRCR_TXCRC_Msk ADC_CR2_SWSTART_Pos FLASH_ACR_HLFCYA_Msk GPIO_BSRR_BR4_Pos RCC_CFGR_PPRE1 AFIO_EXTICR3_EXTI10_PG_Msk CAN_FM1R_FBM6_Msk CAN_F4R2_FB7_Pos GPIO_LCKR_LCKK AFIO_EXTICR2_EXTI6_PC_Pos +syn keyword CTagsDefinedName FLASH_ACR_PRFTBE_Pos CAN_F11R2_FB28 USB_EP0R_STAT_TX_Pos EXTI_PR_PR0_Pos GPIO_ODR_ODR9_Msk USB_EP6R_CTR_RX_Msk CAN_F2R2_FB24_Pos CAN_F12R1_FB12 CAN_F2R1_FB4 SPI_CR1_CRCNEXT_Msk RCC_CFGR_PPRE2_DIV2 RCC_CFGR_SWS CAN_F7R2_FB22 CAN_F10R2_FB24_Pos EXTI_PR_PR12 FLASH_OBR_DATA0_Pos CAN_F7R2_FB12_Msk USART_CR2_CPOL_Pos CAN_F13R2_FB16_Msk CAN_F9R2_FB21 RCC_CFGR_PLLMULL_2 RCC_APB1RSTR_USBRST CAN_IER_FMPIE0_Pos CAN_F10R1_FB23_Msk USB_COUNT6_RX_NUM_BLOCK CAN_IER_FFIE1_Pos EXTI_IMR_MR1_Msk +syn keyword CTagsDefinedName TIM_PSC_PSC_Msk RCC_BDCR_RTCSEL_LSE USB_EP6R_STAT_TX_0 GPIOE_BASE CAN_F7R2_FB27_Pos EXTI_EMR_MR1_Pos USB_CNTR_PMAOVRM_Msk USB_COUNT7_RX_1_NUM_BLOCK_1_0 ADC_SQR1_SQ13_3 USB_EP3R_EP_KIND CAN_F0R1_FB30_Pos GPIO_BRR_BR3 USART_CR2_LINEN CAN_F10R1_FB16 AFIO_MAPR_CAN_REMAP_REMAP3_Msk CAN_F9R1_FB4_Msk CAN_F7R1_FB11_Msk DMA_IFCR_CGIF4_Msk CAN_F11R1_FB8_Msk TIM_CCMR1_OC2FE TIM_CR1_CKD USB_ADDR6_TX_ADDR6_TX SDIO_ICR_DBCKENDC AFIO_MAPR_PD01_REMAP_Pos USB_COUNT1_RX_COUNT1_RX_Msk +syn keyword CTagsDefinedName USB_EPRX_DTOGMASK GPIO_BSRR_BS15_Msk TIM_BDTR_OSSI_Msk GPIO_CRH_CNF11_Pos AFIO_MAPR_TIM4_REMAP CAN_F1R1_FB17 ADC_SMPR2_SMP7_Pos CAN_F11R1_FB18_Pos CAN_F11R2_FB20_Pos CAN_F6R1_FB17_Pos CAN_FS1R_FSC2_Msk ADC_SR_JEOS_Msk CAN_F11R2_FB15 AFIO_EXTICR2_EXTI4_PG_Pos DMA_IFCR_CTCIF3_Pos CAN_F5R1_FB4 CAN_F3R1_FB2 CAN_F8R2_FB10 CAN_F11R2_FB18_Pos CAN_FM1R_FBM_Pos USART_CR3_SCEN_Msk USB_CNTR_SOFM_Msk CAN_F5R1_FB14_Msk SDIO_CMD_WAITINT ADC_CR1_DISCNUM_Pos USB_COUNT3_TX_COUNT3_TX +syn keyword CTagsDefinedName CAN_RDH0R_DATA4_Msk CAN_F11R2_FB10_Pos SPI3_IRQ_PRIORITY EXTI_EMR_MR10_Msk CAN_F2R2_FB25 CAN_F8R1_FB15 USART_CR3_CTSIE_Pos DMA_ISR_TEIF6_Msk CAN_F5R2_FB4_Pos SPI_CR2_TXEIE CAN_F3R1_FB19_Msk CAN_F1R1_FB11 CAN_F6R1_FB27_Pos CAN_F2R1_FB10_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_3 CAN_F9R2_FB17_Msk DBGMCU_CR_DBG_WWDG_STOP SDIO_DCTRL_DTDIR CAN_F10R1_FB21 TIM_CCMR1_OC1PE AFIO_EXTICR4_EXTI12_PC_Pos EXTI_RTSR_TR5_Pos CAN_F11R2_FB16_Pos TIM_DIER_BIE_Pos USB_EP5R_DTOG_RX_Pos RCC_APB1ENR_PWREN +syn keyword CTagsDefinedName DMA_ISR_TCIF1_Msk RCC_CIR_CSSF I2C_SR1_TIMEOUT TIM1_BRK_TIM15_IRQn USB_COUNT5_RX_COUNT5_RX_Pos FLASH_ACR_LATENCY_Msk ADC_SQR3_SQ5_1 ADC_CR1_AWDSGL_Pos CAN_F13R2_FB0_Pos CAN_F2R2_FB18_Pos CAN_F12R2_FB25_Pos SDIO_MASK_RXFIFOHFIE_Msk CAN_IER_SLKIE_Msk EXTI_FTSR_FT17 RCC_CFGR_HPRE_DIV2 TIM_CCR2_CCR2_Pos USART_CR3_SCEN ADC_CR1_EOSIE ADC_SQR3_SQ2_3 USART_CR3_DMAT CAN_F2R1_FB28 DBGMCU_IDCODE_REV_ID_3 USB_COUNT2_RX_0_BLSIZE_0 AFIO_EXTICR3_EXTI10_PG CAN_F3R2_FB10 CAN_F6R1_FB28_Msk +syn keyword CTagsDefinedName EXTI_FTSR_TR3_Msk I2C_SR1_BTF CAN_F12R1_FB27 USB_EP1R_DTOG_TX_Msk ADC_SQR3_SQ4_4 DMA_IFCR_CTEIF1_Msk AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_EXTICR2_EXTI7_Msk CAN_FA1R_FACT DMA_CNDTR_NDT_Pos CAN_F6R2_FB27_Msk CAN_F1R2_FB6_Pos CAN_F6R2_FB6 EXTI_SWIER_SWIER10_Pos CAN_F1R2_FB22 CAN_F5R2_FB12_Msk GPIO_CRL_CNF0_1 CAN_FFA1R_FFA11_Pos FLASH_RDP_RDP CAN_F10R1_FB15_Pos CAN_F11R1_FB7_Msk USB_FNR_LCK_Pos EXTI_IMR_MR12_Pos CAN_FFA1R_FFA5 CAN_F11R2_FB23_Pos CAN_F8R1_FB20_Pos WWDG_CFR_EWI_Pos +syn keyword CTagsDefinedName CAN_F0R1_FB10_Pos CAN_RDH1R_DATA6 SDIO_DCOUNT_DATACOUNT_Msk CAN_F4R1_FB22 USB_EP7R_STAT_TX_1 CAN_TDL0R_DATA2_Pos AFIO_EXTICR2_EXTI4_PE CAN_F4R1_FB4_Pos AFIO_EXTICR1_EXTI1_PD_Msk EXTI_SWIER_SWIER9_Pos __SYS_HANDLERS_H_ CAN_F7R2_FB0_Msk CAN_F12R2_FB26_Msk AFIO_MAPR_USART2_REMAP RCC_APB2ENR_IOPAEN_Msk CAN_TSR_RQCP2_Pos RCC_BDCR_LSERDY CAN_F2R1_FB22 EXTI_EMR_EM15 CAN_F7R2_FB27_Msk EXTI_RTSR_TR15 CAN_FM1R_FBM0 CAN_F0R1_FB2 ADC_JSQR_JSQ2_4 EXTI_FTSR_TR14_Msk +syn keyword CTagsDefinedName USB_COUNT2_RX_1_NUM_BLOCK_1_2 CAN_RI0R_EXID_Pos CAN_F4R1_FB16_Pos AFIO_EVCR_PIN_PX13_Msk CAN_F0R1_FB28 CAN_F7R1_FB26 PIN_OPT_OUTPUT_SPEED_FAST USB_ADDR1_RX_ADDR1_RX_Pos TIM_CR1_UDIS SPI_CR2_TXEIE_Msk USB_EPTX_STAT CAN_F2R2_FB8 EXTI_SWIER_SWI2 CAN_RDH0R_DATA5 CAN_F2R2_FB7_Msk CAN_F5R1_FB7_Msk EXTI_FTSR_TR7 CAN_F8R2_FB7 TIM_CCER_CC1NP TIM_BDTR_DTG IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE CAN_TI1R_TXRQ USB_DADDR_ADD6_Msk I2C_OAR2_ENDUAL USB_EP6R_DTOG_TX CAN_IER_LECIE_Msk +syn keyword CTagsDefinedName ADC_SMPR2_SMP5_Msk ADC_SQR1_SQ15_Pos USB_EP_KIND CAN_F7R1_FB23_Msk RCC_APB2ENR_IOPDEN_Msk USB_COUNT1_RX_NUM_BLOCK_Pos RTC_CRH_SECIE CAN_IER_TMEIE CAN_F1R1_FB28_Pos EXTI_EMR_EM0 CAN_FFA1R_FFA3 RCC_CFGR_PLLMULL15 CAN_RDH0R_DATA5_Msk CAN_F10R1_FB8 CAN_F1R1_FB27 CAN_F3R2_FB19_Pos CAN_F4R2_FB29 FLASH_WRP0_WRP0_Pos ADC_JSQR_JL_1 RCC_CFGR_PLLMULL16_Msk CAN_F9R1_FB17_Pos CAN_TDL0R_DATA0_Pos CAN_RF0R_FOVR0_Pos EXTI_IMR_IM4 ADC_SMPR2_SMP8_2 ADC_SQR2_SQ12_1 SDIO_STA_CMDREND_Pos +syn keyword CTagsDefinedName CAN_F8R1_FB5_Msk RCC_BDCR_RTCEN_Pos CAN_F4R1_FB1_Pos RCC_BASE GPIO_BSRR_BS2_Msk I2C_SR1_ARLO_Pos USB_COUNT1_RX_COUNT1_RX FLASH_RDP_nRDP_Pos CAN_MSR_INAK_Msk USART_BRR_DIV_Mantissa CAN_F11R1_FB21 AFIO_EXTICR4_EXTI14_PD_Pos RCC_APB1RSTR_TIM4RST CAN_F8R2_FB2_Msk IS_TIM_DMA_CC_INSTANCE ADC_CR1_JAWDEN_Pos CAN_RF1R_FOVR1 CAN_TDH1R_DATA4_Msk CAN_FA1R_FACT5_Msk GPIOB_BASE BKP_DR5_D RCC_CIR_HSIRDYIE CAN_F0R1_FB0 AFIO_EXTICR1_EXTI1_PG_Pos USB_COUNT2_TX_COUNT2_TX_Pos CAN_F13R2_FB21_Msk +syn keyword CTagsDefinedName IS_TIM_CLOCKSOURCE_ITRX_INSTANCE AFIO_EXTICR3_EXTI9_PB CAN_F1R1_FB1 SDIO_CMD_WAITRESP_1 TIM_CCMR2_OC4CE_Pos ADC_SMPR1_SMP15_2 CAN_F5R2_FB25_Pos EXTI_EMR_MR2_Msk I2C_SR1_STOPF_Msk CAN_F13R1_FB11_Msk CAN_F3R1_FB4_Msk CAN_F12R2_FB4 CAN_F4R2_FB30_Msk CAN_F11R1_FB29_Pos AFIO_EXTICR3_EXTI9 CAN_RDH0R_DATA7_Pos CAN_F4R1_FB15 SDIO_MASK_RXDAVLIE USB_EP0R_STAT_TX_0 CAN_F5R2_FB10 EXTI_SWIER_SWIER5 AFIO_EXTICR2_EXTI4_PB_Pos CAN_F0R2_FB18_Msk TIM_SMCR_TS RCC_BDCR_LSEON DMA_CCR_EN_Msk +syn keyword CTagsDefinedName USB_COUNT6_RX_0_NUM_BLOCK_0_0 TIM_SR_COMIF GPIOB RCC_CFGR_MCO_PLLCLK_DIV2 TIM_CCER_CC2P_Msk ADC_SQR2_SQ9 CAN_TDH0R_DATA5_Pos EXTI_EMR_MR18_Pos CAN_F9R1_FB9 SDIO_CLKCR_HWFC_EN_Msk USART_SR_NE AFIO_EXTICR2_EXTI7_PG_Pos CAN_F8R2_FB3_Msk RCC_CFGR_HPRE_DIV_2 CAN_F12R2_FB22 CAN_F8R1_FB5 CAN_FM1R_FBM13_Msk RCC_CFGR_PPRE_DIV_8 DMA_ISR_HTIF1 CAN_F4R1_FB25 RCC_APB2ENR_ADC1EN_Msk SDIO_DCTRL_DTEN_Pos TIM_CCMR1_OC1M_1 TIM_CR1_UDIS_Msk FLASH_OBR_DATA0_Msk TIM_CR2_TI1S_Pos CAN_F0R1_FB14 +syn keyword CTagsDefinedName PWR_BASE TIM_CCMR2_OC3FE_Msk CAN_F2R1_FB13_Pos SDIO_STA_DATAEND_Pos CAN_F8R1_FB12 EXTI_IMR_MR4 GPIO_BRR_BR7_Msk SDIO_ICR_SDIOITC PWR_CR_PLS_LEV7 TIM_CCMR1_OC1M RCC_CIR_HSIRDYC_Msk USB_EP3R_DTOG_RX_Msk CAN_F4R2_FB16 CAN_F5R2_FB5_Msk EXTI_SWIER_SWIER6_Pos TIM_CR1_CEN_Msk CAN_RF1R_RFOM1_Msk CAN_F2R2_FB15_Msk SDIO_MASK_TXACTIE_Pos USB_ISTR_CTR_Msk DMA_CCR_PINC_Msk CAN_F0R1_FB4_Pos USART_CR3_CTSIE_Msk CAN_F6R2_FB19_Msk DMA_IFCR_CTCIF5_Msk TIM_PSC_PSC CAN_F10R2_FB2_Msk CAN_F4R1_FB14 +syn keyword CTagsDefinedName CAN_F10R1_FB18_Msk CAN_F6R1_FB29_Pos CAN_FA1R_FACT9_Msk CAN_F3R1_FB8_Msk CAN_F1R2_FB10_Msk USB_COUNT2_RX_COUNT2_RX_Pos CAN_F2R2_FB23_Pos USB_COUNT7_RX_NUM_BLOCK_2 TIM_DIER_COMDE CAN_F7R2_FB30_Msk ADC_SMPR2_SMP4_0 PWR_CR_PLS_LEV4 SDIO_ICR_STBITERRC EXTI_EMR_MR4 DBGMCU_CR_DBG_STANDBY_Msk USART_CR3_RTSE_Msk PIN_3 USB_EP3R_EA_Msk AFIO_EXTICR1_EXTI3_PC CAN_F13R1_FB1_Pos CAN_F3R1_FB25 RTC_CRH_ALRIE GPIO_BSRR_BR13 CAN_F2R1_FB2_Pos EXTI_FTSR_TR0_Msk CAN_MCR_SLEEP TIM_CR1_DIR +syn keyword CTagsDefinedName USB_EP0R_SETUP GPIO_BSRR_BS3 CAN_F2R1_FB14_Msk CAN_F7R1_FB16_Pos GPIO_BSRR_BR10_Msk CAN_F3R1_FB5_Msk AFIO_EXTICR4_EXTI12_PG_Pos TIM_SR_CC1OF CAN_F10R1_FB31 PWR_CR_PLS_2V7 TIM11_IRQn FLASH_WRP2_nWRP2 USB_COUNT2_RX_0_NUM_BLOCK_0_4 CAN_F3R2_FB9 EXTI_EMR_MR0 USB_COUNT6_RX_NUM_BLOCK_1 BKP_DR6_D_Msk CAN_F6R1_FB22_Msk USB_COUNT5_RX_1_BLSIZE_1 ADC_SQR1_SQ14_2 TIM_DCR_DBA_Msk DMA_ISR_HTIF4 AFIO_EXTICR2_EXTI7_Pos CAN_F0R1_FB9 SDIO_MASK_RXFIFOFIE TIM_CR2_OIS1 EXTI_PR_PR4 RCC_CIR_PLLRDYC +syn keyword CTagsDefinedName CAN_F12R1_FB17_Msk CAN_F2R2_FB3 CAN_F2R1_FB21_Msk CAN_F2R1_FB4_Msk USB_EP7R_CTR_TX FLASH_OPTKEY2 ADC_SMPR2_SMP8 EXTI_SWIER_SWIER13_Msk CAN_F6R2_FB7 CAN_F3R1_FB31_Pos SDIO_ICR_CTIMEOUTC EXTI_EMR_EM7 CAN_F5R2_FB11_Msk GPIO_BRR_BR2_Msk CAN_F0R1_FB3_Pos CAN_F0R1_FB28_Msk CAN_F4R1_FB28_Msk CAN_RDL0R_DATA0 CAN_F3R1_FB17 ADC_SQR2_SQ8_1 USB_COUNT4_RX_1_NUM_BLOCK_1_1 I2C_SR2_GENCALL_Msk SDIO_CMD_CEATACMD CAN_F5R1_FB9_Msk USB_EP4R_STAT_RX AFIO_EXTICR1_EXTI0_PB_Pos PIN_13 +syn keyword CTagsDefinedName CAN_F4R1_FB13_Pos CAN_F9R2_FB24 TIM_CCER_CC4E_Pos CAN_F2R1_FB7_Pos CAN_FM1R_FBM8 CAN_F7R2_FB19_Pos GPIO_IDR_IDR6 CAN_F3R1_FB6 CAN_F9R2_FB9_Msk ADC_CR2_EXTSEL_0 RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL12 CAN_FFA1R_FFA1_Msk CAN_F11R2_FB4 USART_CR3_DMAR CAN_TI2R_STID_Msk USART_CR1_RXNEIE_Msk USB_EP4R_EA_Pos AFIO_MAPR_CAN_REMAP_1 TIM_SR_BIF TIM_SR_CC2IF_Pos USB_ADDR2_RX_ADDR2_RX_Msk USB_EP0R_SETUP_Pos TIM_CR2_TI1S_Msk RCC_APB2RSTR_IOPERST_Pos CAN_F4R1_FB21_Msk EXTI_EMR_MR11 +syn keyword CTagsDefinedName CAN_FFA1R_FFA8 CAN_F5R1_FB8_Pos CAN_F3R2_FB18_Msk ADC_CR2_CAL_Pos USB_COUNT4_RX_0_COUNT4_RX_0 I2C_CR1_NOSTRETCH_Pos I2C_SR1_BERR_Pos CAN_F12R2_FB21_Pos CAN_F9R1_FB27_Msk I2C_CR1_SMBTYPE_Pos CAN_RI1R_RTR ADC_CR1_DUALMOD AFIO_EXTICR1_EXTI1 AFIO_EXTICR4_EXTI13_PF_Msk TIM_CCMR1_IC2PSC_Pos CAN_F4R1_FB14_Msk IS_TIM_CCXN_INSTANCE CAN_F0R1_FB24 CAN_F12R1_FB24_Pos CAN_F3R1_FB1_Pos SDIO_MASK_RXFIFOEIE GPIO_CRL_MODE7_Msk RCC_CFGR_HPRE_DIV16 TIM_EGR_TG_Msk CAN_F6R2_FB14 RCC_CSR_PORRSTF_Msk +syn keyword CTagsDefinedName CAN_FFA1R_FFA10 ADC_SMPR2_SMP7 RCC_CFGR_PPRE2_0 ADC_HTR_HT ADC_SQR2_SQ8_Msk GPIO_ODR_ODR10_Msk CAN_F2R2_FB17 CAN_F3R2_FB6 CAN_F9R2_FB1 TIM_CCR3_CCR3 BKP_DR6_D_Pos CAN_FS1R_FSC12_Pos ADC_SQR3_SQ4_Pos CAN_F2R2_FB15 RCC_CFGR_HPRE_0 TIM_CR2_OIS2_Msk CAN_RDL0R_DATA3 RCC AFIO_EXTICR1_EXTI1_PB_Pos CAN_F12R2_FB5_Pos GPIO_BSRR_BR10 CAN_F8R1_FB9_Pos CAN_FS1R_FSC6_Msk USART_CR1_PEIE AFIO_EXTICR3_EXTI11_PG I2C_CR1_STOP _IO_H_ AFIO_EVCR_PIN_PX9_Msk TIM_BDTR_LOCK_1 CAN_F3R2_FB15_Msk +syn keyword CTagsDefinedName ADC_SQR3_SQ6_Msk CAN_F7R1_FB5_Msk GPIO_BSRR_BS5 SDIO_STA_TXACT_Msk AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk CAN_F1R1_FB26_Msk AFIO_EXTICR3_EXTI11_PE_Pos CAN_TDH0R_DATA5_Msk READ_REG AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR1_EXTI3_PE_Pos TIM_BDTR_OSSR_Pos WWDG_CFR_W6 GPIO_BSRR_BS2 GPIO_CRL_MODE6_1 USART_CR1_WAKE GPIO_BSRR_BR5_Msk I2C1 TIM_CCMR2_OC3M_0 RTC_CRL_ALRF CAN_F10R1_FB0 CAN_F0R2_FB23_Pos CAN_RDT1R_TIME CAN_F12R2_FB30 CAN_F3R1_FB21_Pos USB_ISTR_DIR_Pos AFIO_EXTICR1_EXTI3_PB_Msk +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI7_PB_Msk USB_DADDR_ADD0_Pos CAN_F7R2_FB26_Msk DBGMCU_CR_DBG_SLEEP_Msk CAN_F5R1_FB29_Pos CAN_F6R2_FB0 USB_COUNT6_RX_BLSIZE_Pos SDIO_ICR_TXUNDERRC_Msk CAN_F9R1_FB10_Msk CAN_F4R2_FB12_Pos EXTI_PR_PIF6 USART_SR_ORE RCC_CFGR_PLLMULL_Pos CAN_F12R2_FB29_Msk I2C1_IRQ_PRIORITY CAN_BTR_SILM CAN_F5R2_FB5_Pos CAN_F11R2_FB15_Msk USB_COUNT2_RX_NUM_BLOCK_4 AFIO_EXTICR3_EXTI10_PG_Pos TIM_DIER_CC1DE_Pos PWR_CR_PLS_2V4 AFIO_EVCR_PIN_PX7 RCC_APB1ENR_WWDGEN_Msk +syn keyword CTagsDefinedName SDIO_CLKCR_NEGEDGE_Pos AFIO_EXTICR2_EXTI7_PE_Msk CAN_F9R2_FB25_Msk CAN_F2R1_FB24_Pos SPI_CR2_TXDMAEN_Msk TIM_BDTR_OSSR_Msk CAN_F13R1_FB3_Msk CAN_F6R2_FB31 USB_CNTR_WKUPM_Pos CAN_MSR_SLAKI_Pos AFIO_EXTICR4_EXTI12_PG CAN_F8R1_FB18_Msk CAN_TI2R_EXID_Msk CAN_MSR_ERRI_Pos CAN_F2R1_FB6_Pos CAN_F4R1_FB1_Msk CAN_F9R1_FB0_Pos AFIO_EXTICR2_EXTI7_PF_Msk USB_EP5R_EP_TYPE_Pos CAN_F6R2_FB4_Msk TIM1_BASE CAN_FFA1R_FFA1 AFIO_MAPR_TIM4_REMAP_Msk IS_ADC_COMMON_INSTANCE CAN_F11R1_FB20_Msk +syn keyword CTagsDefinedName CAN_F0R1_FB11_Msk PWR_CSR_SBF_Msk USB_COUNT1_RX_0_NUM_BLOCK_0_0 FLASH_WRP0_WRP0 TIM_CCER_CC3NP_Msk USB_EP2R_EA_Msk CAN_F8R2_FB27 FLASH_SR_BSY CAN_F3R1_FB5_Pos ADC_SMPR2_SMP6_2 RCC_APB2RSTR_AFIORST_Pos TIM_DIER_CC2IE AFIO_EXTICR2_EXTI4_PF_Msk CAN_F1R2_FB27_Msk WWDG_CR_T1 CAN_F3R2_FB23_Pos ADC_CR1_DUALMOD_1 USB_DADDR_ADD1_Msk CAN_FFA1R_FFA0_Pos CAN_F4R1_FB12_Msk ADC_SQR3_SQ3_Msk CAN_F7R1_FB18_Msk CAN_F3R2_FB8_Msk SDIO_ICR_SDIOITC_Msk CAN_F1R2_FB5 RTC_PRLH_PRL CAN_F10R1_FB12_Msk +syn keyword CTagsDefinedName ADC_SQR2_SQ8_0 CAN_F4R1_FB9 USB_COUNT3_TX_COUNT3_TX_Pos CAN_F7R2_FB8_Msk DMA_ISR_HTIF2_Msk AFIO_MAPR_TIM2_REMAP_Msk ADC_LTR_LT_Msk CAN_F2R2_FB5_Pos RCC_APB2RSTR_IOPDRST_Msk AFIO_MAPR_USART3_REMAP CAN_F7R1_FB15 SDIO_STA_DATAEND_Msk SPI_CR1_MSTR_Pos USB_EP5R_EA_Pos GPIO_CRH_CNF TIM_CCMR2_CC4S_0 CAN_F2R2_FB27_Msk USB_EP0R_DTOG_TX TIM_EGR_CC3G_Pos CAN_F13R1_FB15 TIM_CCER_CC1NP_Msk USB_COUNT2_RX_NUM_BLOCK_2 EXTI_EMR_MR18 CAN_F3R2_FB5 CAN_F3R2_FB20_Msk EXTI_IMR_MR15 +syn keyword CTagsDefinedName RCC_APB1ENR_TIM4EN_Msk AFIO_EXTICR3_EXTI11_PB_Pos PWR_CSR_PVDO CAN_F0R1_FB28_Pos CAN_F12R1_FB14 CAN_FFA1R_FFA12 USB_EPRX_STAT_Msk TIM_DCR_DBL_0 USB_FNR_LCK AFIO_EVCR_PIN_PX2_Pos CAN_F0R2_FB30 RCC_APB1ENR_TIM4EN CAN_F10R1_FB19 CAN_F2R1_FB23_Msk RCC_APB2RSTR_ADC1RST CAN_F5R1_FB24_Msk USB_COUNT6_RX_BLSIZE_Msk CAN_F1R2_FB4_Msk EXTI_SWIER_SWIER7_Msk CAN_F5R2_FB8_Msk TIM_CCMR2_OC3FE_Pos AFIO_EXTICR3_EXTI11_PC_Pos CAN_F7R2_FB0 ADC_CR2_CONT FLASH_CR_LOCK_Pos TIM_DCR_DBA_1 +syn keyword CTagsDefinedName DMA_ISR_GIF1_Msk CAN_F11R1_FB1_Pos CAN_F12R2_FB17_Pos I2C_OAR1_ADD1_Msk AFIO_EVCR_PIN_PX0 CAN_FA1R_FACT8 PIN_OPT_AF10 CAN_F13R2_FB10_Msk FLASH_SR_BSY_Msk CAN_F5R2_FB6 ADC_JSQR_JSQ3_2 CAN_F5R2_FB4_Msk ADC_SMPR2_SMP2_2 EXTI_FTSR_TR2 USB_COUNT1_TX_1_COUNT1_TX_1 TIM_DIER_UIE_Pos CAN_F8R1_FB20 CAN_MCR_TXFP_Msk DMA_ISR_HTIF5_Msk CAN_F1R1_FB25_Pos CAN_TDH0R_DATA6 RCC_APB1RSTR_TIM4RST_Pos CAN_F6R2_FB9 ADC_CR2_ALIGN_Pos CAN_TDL0R_DATA2 FLASH_ACR_PRFTBS_Pos RCC_CFGR_ADCPRE_Msk +syn keyword CTagsDefinedName __STM32F1_CMSIS_VERSION_SUB2 EXTI_FTSR_TR9_Msk EXTI_FTSR_TR9 CAN_TSR_ALST0 TIM_DCR_DBA_4 CAN_F1R1_FB10_Pos AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos AFIO_EXTICR2_EXTI4_PE_Pos CAN_F4R2_FB19_Msk I2C_SR2_SMBHOST_Msk RCC_APB2ENR_SPI1EN_Msk CAN_F0R1_FB6_Pos USB_EP3R_STAT_TX AFIO_EXTICR1_EXTI2 USB_EP4R_STAT_RX_Pos EXTI_RTSR_RT7 TIM_BDTR_BKP_Msk I2C_CR2_ITBUFEN CAN_F5R2_FB17_Msk CAN_F6R1_FB11 EXTI_IMR_IM18 GPIO_CRH_MODE9_1 CAN_F10R1_FB24_Pos RCC_APB2RSTR_USART1RST_Msk DMA_CCR_MINC_Pos +syn keyword CTagsDefinedName CAN_F9R1_FB21_Msk CAN_F1R2_FB26 SPI_CR1_CPOL_Pos WWDG_CFR_W1 ADC_SMPR1_SMP12_0 CAN_F13R1_FB23 RCC_CR_HSICAL_Msk AFIO_EXTICR1_EXTI2_PC RCC_CFGR_HPRE_DIV64 CAN_F12R1_FB6_Msk CAN_F12R2_FB3_Msk I2C_OAR1_ADD8_Msk I2C_CCR_FS_Msk ADC_SMPR2_SMP3_Msk CAN_F6R1_FB26_Pos CAN_TDT0R_TGT FLASH_DATA0_DATA0 SDIO_FIFO_FIFODATA_Msk SPI4_IRQ_PRIORITY USB_EP6R_DTOG_TX_Pos CAN_F2R2_FB15_Pos ADC_SQR2_SQ12_2 AFIO_EXTICR2_EXTI6_PA EXTI_EMR_MR1 TIM_DIER_CC3DE_Pos GPIO_CRL_MODE1_1 CAN_F4R2_FB8 +syn keyword CTagsDefinedName SDIO_STA_CEATAEND ADC_SQR1_L_0 GPIO_CRL_MODE1_Msk EXTI_IMR_MR6_Pos CAN_MCR_DBF CAN_F3R1_FB25_Msk EXTI_RTSR_TR16 USB_COUNT5_RX_NUM_BLOCK_Msk DMA_IFCR_CTEIF1_Pos SPI_CR1_CPOL CAN_F9R2_FB9_Pos EXTI15_10_IRQ_PRIORITY CAN_F12R2_FB25_Msk BKP_DR7_D CAN_F11R2_FB5_Pos AFIO_EXTICR3_EXTI10_PB_Pos PWR_CR_PLS_0 CAN_F7R1_FB23_Pos CAN_FA1R_FACT10_Msk CAN_F8R2_FB1_Msk EXTI_FTSR_TR13_Pos CAN_F6R2_FB2_Msk TIM_CCMR2_IC4F_1 CAN_F8R1_FB31_Pos TIM_CR1_ARPE USB_EP0R_EA_Msk USB_COUNT3_RX_NUM_BLOCK_4 +syn keyword CTagsDefinedName RCC_AHBENR_SRAMEN_Msk USB_COUNT2_RX_COUNT2_RX EXTI_FTSR_TR11_Pos GPIO_LCKR_LCK14_Msk CAN_F8R2_FB14_Msk AFIO_EXTICR2_EXTI7_PD_Msk FLASH_SR_WRPRTERR_Msk GPIO_BSRR_BR9_Msk CAN_F8R1_FB20_Msk TIM1_TRG_COM_TIM17_IRQHandler CAN_F5R2_FB16_Msk CAN_F12R2_FB15 CAN_F8R1_FB28 CAN_TDH2R_DATA6 EXTI_FTSR_TR10_Pos SDIO_MASK_RXACTIE_Pos DMA_CNDTR_NDT_Msk EXTI_RTSR_TR1 USB_FNR_LSOF_Pos CAN_F13R1_FB6_Pos EXTI_PR_PR2_Msk RCC_CFGR_PPRE2_Pos AFIO_EVCR_PIN_PX15_Pos CAN_FM1R_FBM3_Msk CAN_F2R2_FB23_Msk +syn keyword CTagsDefinedName FLASH_OBR_OPTERR_Pos GPIO_CRL_CNF4_Msk I2C_OAR2_ENDUAL_Pos USB_EP7R_EP_KIND GPIO_CRH_CNF8_0 GPIO_BSRR_BR9_Pos AFIO_EXTICR3_EXTI11_PF GPIO_BSRR_BR0 CAN_F3R2_FB28_Msk EXTI_FTSR_TR1_Msk GPIO_CRL_MODE2_1 SPI_CRCPR_CRCPOLY_Msk EXTI_IMR_MR11_Msk CAN_F11R2_FB25 TIM_CCMR2_IC4F_3 CAN_ESR_LEC_Pos CAN_F2R1_FB18 USB_COUNT5_RX_1_NUM_BLOCK_1_4 I2C_OAR1_ADD9_Msk CAN_F2R1_FB1 CAN_F3R1_FB9_Msk ADC_CR2_JEXTSEL_0 GPIO_CRH_CNF11_1 TIM_SR_CC3IF_Pos GPIO_BSRR_BR15 USB_EP_T_FIELD_Pos USB_EP6R_STAT_RX +syn keyword CTagsDefinedName USB_COUNT5_RX_0_NUM_BLOCK_0_1 USART_SR_TC_Pos CAN_F7R1_FB5 RCC_CR_HSERDY_Pos USB_COUNT3_RX_COUNT3_RX_Msk CAN_F10R1_FB0_Pos USB_COUNT0_RX_NUM_BLOCK_2 DMA_IFCR_CTEIF2 CAN_F3R2_FB13_Msk USB_EP5R_EP_TYPE_1 TIM_DIER_UDE_Pos CAN_RF1R_FOVR1_Msk CAN_F1R2_FB22_Msk USB_EP3R USART_CR2_STOP_Msk CAN_F12R1_FB28_Pos CAN_FS1R_FSC3_Pos SDIO_MASK_DTIMEOUTIE_Pos CAN_F10R1_FB22_Msk CAN_F12R2_FB18_Pos DBGMCU_IDCODE_REV_ID_13 CAN1_TX_IRQHandler EXTI_EMR_MR5 CAN_TDT1R_TIME CAN_F11R1_FB17_Pos +syn keyword CTagsDefinedName EXTI_PR_PR5 EXTI_SWIER_SWIER0 SPI_CR1_CPHA_Msk ADC_CR1_AWDCH_1 CAN_F10R2_FB9 CAN_F9R2_FB1_Pos CAN_F8R1_FB2_Msk CAN_F13R1_FB1 CAN_F5R1_FB3 CAN_MSR_RX_Msk DMA_IFCR_CGIF6_Msk AFIO_EXTICR1_EXTI1_PF_Pos I2C_CR1_ENARP CAN_F1R1_FB20 EXTI_FTSR_TR3_Pos CAN_F0R1_FB22 USB_COUNT1_RX_NUM_BLOCK_4 CAN_F10R2_FB8_Pos CAN_F8R1_FB26_Pos CAN_F11R2_FB4_Pos DMA_CCR_PL_Pos AFIO_EXTICR2_EXTI6_PE CAN_F3R1_FB17_Msk SPI_CR1_LSBFIRST_Pos AFIO_EXTICR2_EXTI5_PE_Msk DMA_IFCR_CTCIF3_Msk CAN_F8R2_FB29_Pos +syn keyword CTagsDefinedName CAN_F7R2_FB8 CAN_F2R1_FB22_Msk CAN_F11R1_FB12_Pos AFIO_MAPR_TIM3_REMAP_NOREMAP EXTI_RTSR_TR2 USB_EP1R_STAT_TX ADC_SQR2_SQ12 CAN_F1R2_FB2 TIM_CCMR1_OC2M_1 SDIO_DCTRL_DTDIR_Msk BKP_DR4_D_Pos AFIO_MAPR_TIM4_REMAP_Pos ADC1_BASE CAN_F5R2_FB25 RCC_CIR_LSERDYC_Msk RCC_CFGR_HPRE_DIV_64 CAN_FM1R_FBM5 CAN_IER_LECIE CAN_TI0R_IDE_Pos SPI_CR1_RXONLY_Msk CAN_IER_EPVIE_Pos AFIO_EXTICR4_EXTI12_PE_Msk IWDG_KR_KEY_Msk AFIO_EXTICR4_EXTI14_Msk IWDG_SR_RVU_Msk EXTI_EMR_MR8_Pos ADC_SQR3_SQ1_1 +syn keyword CTagsDefinedName ADC_SMPR2_SMP5_2 CAN_MCR_TTCM_Pos CAN_F12R2_FB5 TIM_DIER_CC3IE CAN_FFA1R_FFA CAN_F13R1_FB28_Msk DMA_CCR_EN DMA_IFCR_CTEIF5_Pos EXTI_EMR_EM8 IS_TIM_ADVANCED_INSTANCE RTC_PRLH_PRL_Msk USB_COUNT0_RX_0_COUNT0_RX_0 CAN_F9R1_FB28 ADC_SMPR2_SMP6_0 CAN_F4R1_FB18 CAN_F7R2_FB3_Msk CAN_FS1R_FSC5_Pos EXTI_FTSR_TR12 CAN_F8R2_FB20 DMA_CCR_MSIZE_Pos GPIO_CRL_MODE0_0 USB_COUNT5_RX_0_COUNT5_RX_0 CAN_TSR_TERR1_Pos CAN_F6R1_FB24_Pos PIN_OPT_AF2 CAN_F13R2_FB6 USB_EP5R_STAT_TX_Pos CAN_F5R1_FB14 +syn keyword CTagsDefinedName CAN_F11R1_FB30 USB_COUNT1_RX_0_NUM_BLOCK_0_1 USB_EP5R_DTOG_RX_Msk USB_EP1R_CTR_TX_Pos DMA_IFCR_CGIF7 GPIO_BRR_BR15_Pos USART_CR1_SBK CAN_F9R1_FB13 ADC_SMPR2_SMP1_0 CAN_F0R2_FB5_Msk RCC_APB2ENR_IOPAEN AFIO_EXTICR4_EXTI15_PB EXTI_FTSR_TR9_Pos CAN_F6R2_FB18_Msk CAN_F12R2_FB24 EXTI_IMR_MR17_Pos CAN_F4R2_FB17_Pos PWR_CSR_SBF USB_COUNT1_RX_NUM_BLOCK_Msk CAN_F6R1_FB7_Pos CAN_F12R1_FB4 USB_EP4R_EP_TYPE_Pos ADC_SQR1_SQ15 EXTI_PR_PR10_Pos ADC_LTR_LT_Pos CAN_F7R1_FB19_Msk +syn keyword CTagsDefinedName RCC_APB1ENR_USBEN ADC_CR2_CAL I2C_SR1_PECERR_Pos GPIO_CRH_MODE10_0 CAN_MCR_DBF_Pos CAN_F5R2_FB26_Msk CAN_F8R2_FB28_Pos RCC_CR_PLLRDY TIM_CCMR2_OC3M_Msk CAN_F12R2_FB14_Msk EXTI_PR_PR14_Pos RCC_APB1ENR_CAN1EN ADC_SQR2_SQ10_3 CAN_F12R2_FB21_Msk GPIO_BSRR_BS6 CAN_F2R1_FB19_Pos SDIO_STA_CEATAEND_Msk USB_EP7R_EP_TYPE_Pos CAN_F9R2_FB20_Msk STM32F103xB WWDG_CFR_WDGTB0 TIM_DIER_BIE AFIO_EXTICR2_EXTI5_PC_Msk CAN_F6R2_FB15 ADC_SQR2_SQ10_1 CAN_TSR_TERR1_Msk RCC_APB1ENR_PWREN_Msk +syn keyword CTagsDefinedName PWM_CHANNEL_4 CAN_F8R2_FB11_Msk CAN_F8R2_FB23_Msk CAN_RI0R_RTR_Pos I2C_SR2_SMBDEFAULT_Msk GPIO_CRL_MODE0_1 AFIO_EXTICR4_EXTI14_PG_Pos CAN_F11R1_FB26_Msk SDIO_RESPCMD_RESPCMD USB_EP0R_EP_KIND_Pos CAN_F3R1_FB23_Pos PWR_CR_LPDS_Pos CAN_F13R2_FB25 USB_EP1R_EP_KIND_Pos CAN_F11R1_FB14 CAN_F0R2_FB8_Pos USB_EP0R_CTR_RX CAN_F13R2_FB26 CAN_F6R2_FB5_Msk USB_EP7R_STAT_RX_0 TIM_CCER_CC2E_Msk GPIO_CRL_CNF0 GPIO_BRR_BR13 ADC_SQR3_SQ6_Pos CAN_F0R2_FB4 CAN_F0R1_FB13_Msk +syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP_Msk I2C_CR1_PE AFIO_EXTICR2_EXTI4_PC_Msk CAN_F0R2_FB2_Msk USB_ADDR1_TX_ADDR1_TX_Pos SPI2_IRQ_PRIORITY CAN_F5R2_FB9 TIM9_IRQn USB_CNTR_SOFM DBGMCU_IDCODE_REV_ID_15 CAN_F3R1_FB9_Pos USB_COUNT0_RX_1_BLSIZE_1 SPI2 CAN_F2R1_FB17 TIM_CCMR1_IC2F_Pos GPIO_CRH_MODE11_1 CAN_F1R2_FB17_Msk ADC1_IRQn ADC_SQR1_SQ13_Msk GPIO_IDR_IDR15 RCC_APB2ENR_ADC2EN_Pos CAN_F0R1_FB15_Msk AFIO_EXTICR2_EXTI5_Msk CAN_F1R1_FB30 RCC_APB2ENR_IOPEEN_Pos SPI_TXCRCR_TXCRC CAN_F1R2_FB0_Pos +syn keyword CTagsDefinedName BKP_CSR_TEF_Pos FLASH_CR_LOCK RCC_APB2RSTR_TIM1RST AFIO_EVCR_PIN_PX3 GPIO_LCKR_LCK3_Pos USART_CR3_CTSE_Pos CAN_F1R2_FB31 CAN_RF1R_FMP1_Msk USART_CR2_LBDIE_Msk GPIO_IDR_IDR5_Msk CAN_F10R2_FB20_Msk ADC_CR1_AWDCH_3 GPIO_CRL_CNF6_1 CAN_F11R1_FB13_Msk FLASH_CR_MER CAN_F3R2_FB21 CAN_IER_EWGIE_Msk CAN_FFA1R_FFA8_Pos CAN_F7R1_FB10_Msk TIM_CCMR2_IC3F_2 EXTI_IMR_MR2_Pos CAN_F9R1_FB7 CAN_F12R1_FB29_Msk GPIO_CRH_MODE12_0 AFIO_EXTICR2_EXTI5_PD I2C_SR1_BTF_Msk USB_ADDR2_RX_ADDR2_RX +syn keyword CTagsDefinedName RCC_APB1RSTR_I2C1RST CAN_F8R1_FB9_Msk USB_CNTR_ERRM EXTI_EMR_MR6_Pos CAN_F9R1_FB29_Pos CAN_F3R2_FB7 RCC_CIR_CSSF_Msk CAN_F13R1_FB25_Msk USB_COUNT4_RX_0_NUM_BLOCK_0_0 PWR_CR_CWUF_Msk TIM_CCMR1_OC1PE_Msk CAN_F9R2_FB20_Pos ADC_SMPR1_SMP13_2 CAN_F13R1_FB4 USB_EP0R_DTOG_TX_Msk CAN_F0R2_FB0_Msk CAN_F4R2_FB22_Msk CAN_F3R1_FB26_Pos EXTI_EMR_MR0_Msk I2C_SR2_MSL_Pos CAN_F7R1_FB13_Msk CAN_F5R1_FB23_Pos CAN_FS1R_FSC0_Pos CAN_F9R2_FB17_Pos RCC_CFGR_PLLXTPRE_Pos CAN_F13R2_FB10_Pos +syn keyword CTagsDefinedName CAN_F1R1_FB21_Pos DMA_IFCR_CTCIF4_Pos USB_EP7R_SETUP AFIO_EXTICR2_EXTI4_PC_Pos SDIO_CLKCR_BYPASS_Pos USB_COUNT5_RX_NUM_BLOCK_2 DMA_IFCR_CTCIF5_Pos SDIO_ICR_TXUNDERRC_Pos EXTI_PR_PIF11 CAN_FA1R_FACT9_Pos TIM_CCMR2_OC4CE GPIO_IDR_IDR8_Pos ADC_SQR2_SQ11 DMA_IFCR_CTEIF7 USB_EP1R_EP_TYPE_Msk GPIO_BSRR_BR7_Msk CAN_F9R1_FB25 SDIO_RESP2_CARDSTATUS2 EXTI_PR_PR9_Pos PWR_CR_PLS_2V5 ADC_SQR2_SQ7_3 TIM_CR2_CCUS_Msk TIM_CCMR2_OC3FE CAN_F12R1_FB15 CAN_F0R1_FB21 CAN_F6R1_FB23_Msk +syn keyword CTagsDefinedName I2C_SR2_SMBHOST CAN_F8R2_FB2_Pos CAN_F13R1_FB25_Pos AFIO_EXTICR2_EXTI6 FLASH_R_BASE CAN_F10R2_FB9_Pos CAN_F9R2_FB16_Pos RCC_CIR_LSERDYF_Msk AFIO_MAPR_TIM2_REMAP_FULLREMAP CAN_F12R1_FB3_Pos TIM_EGR_UG_Msk USB_COUNT0_RX_NUM_BLOCK_Pos USB_ADDR4_TX_ADDR4_TX USB_COUNT7_TX_COUNT7_TX_Msk CAN_F0R2_FB26_Pos SDIO_MASK_CTIMEOUTIE_Pos CAN_F13R2_FB20_Msk USART_CR3_IRLP CAN_F5R2_FB13_Msk DMA_ISR_TCIF5_Pos I2C_OAR2_ADD2_Pos USB_EP2R_CTR_RX USB_COUNT7_RX_1_NUM_BLOCK_1_4 CAN_F10R2_FB25_Pos +syn keyword CTagsDefinedName CAN_F5R2_FB18_Pos RCC_CIR_CSSC_Pos CAN_F13R1_FB25 CAN_IER_EPVIE SDIO_DCOUNT_DATACOUNT_Pos AFIO_EXTICR1_EXTI3_PD_Pos USB_ISTR_CTR_Pos USART_CR1_IDLEIE TIM_EGR_COMG_Pos CAN_TI0R_RTR CAN_F6R1_FB14 CAN_FFA1R_FFA1_Pos CAN_F13R2_FB17 RCC_APB1ENR_SPI2EN GPIO_IDR_IDR5_Pos RTC_CRL_OWF CAN_F2R2_FB30_Msk SDIO_MASK_RXACTIE FLASH_CR_OPTPG CAN_F12R2_FB13 GPIO_BSRR_BS5_Pos CAN_F12R2_FB6_Msk SDIO_STA_SDIOIT ADC_SQR3_SQ1_2 GPIO_CRH_CNF13_1 AFIO_EXTICR4_EXTI15_Msk CAN_F13R2_FB14 +syn keyword CTagsDefinedName CAN_FS1R_FSC13_Pos AFIO_EXTICR2_EXTI5_PD_Pos EXTI_IMR_MR10_Msk TIM_SMCR_ETP_Pos USB_COUNT1_TX_COUNT1_TX_Pos CAN_F11R1_FB16 WWDG_CR_T0 CAN_F5R1_FB18_Msk SPI_CR1_MSTR GPIO_CRH_CNF13 USB_COUNT3_RX_NUM_BLOCK_Pos EXTI_IMR_MR4_Msk EXTI_PR_PIF8 TIM_DIER_CC4IE_Pos RCC_AHBENR_FLITFEN DMA_ISR_TEIF5_Msk GPIO_BSRR_BR14 USART_CR1_RWU AFIO_MAPR_CAN_REMAP_REMAP2_Msk SDIO_STA_DBCKEND CAN_TI0R_IDE AFIO_EXTICR4_EXTI15_PF_Msk SDIO_DCTRL_DTMODE_Msk PWR_CR_PLS_LEV3 CAN_F10R2_FB31_Msk +syn keyword CTagsDefinedName USB_COUNT7_RX_0_NUM_BLOCK_0_4 CAN_F1R2_FB19_Msk GPIO_CRH_CNF13_Pos USB_COUNT0_RX_NUM_BLOCK_4 GPIO_BSRR_BS0 SDIO_STA_CMDACT_Msk EXTI_FTSR_TR8_Pos ADC_SMPR1_SMP10_Msk DMA_IFCR_CGIF5_Msk CAN_FFA1R_FFA9 AFIO_EXTICR1_EXTI3_PC_Pos EXTI_FTSR_TR17_Pos SDIO_MASK_CMDSENTIE USB_COUNT3_RX_1_NUM_BLOCK_1 CAN_F2R2_FB14_Pos CAN_F10R2_FB24 USART_GTPR_PSC_7 CAN_F11R1_FB22_Msk CAN_F7R1_FB21_Pos GPIO_IDR_IDR14_Pos CAN_FM1R_FBM12_Msk EXTI_PR_PIF2 CAN_F2R2_FB0 SDIO_CMD_SDIOSUSPEND_Msk +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PC_Msk CAN_FM1R_FBM1_Pos USB_ADDR6_TX_ADDR6_TX_Pos CAN_F11R1_FB22_Pos SDIO_ICR_TXUNDERRC USB_COUNT2_TX_COUNT2_TX CAN_F8R2_FB28 CAN_F8R1_FB16 AFIO_EXTICR4_EXTI13_Pos GPIO_CRL_CNF7_0 CAN_F10R1_FB9_Pos CAN_F6R2_FB25_Msk CAN_F11R2_FB16 CAN_TDT0R_DLC_Pos USB_EP0R AFIO_EXTICR3_EXTI8_PB_Msk CAN_F2R2_FB25_Msk AFIO_EXTICR1_EXTI1_PA CAN_F7R1_FB14_Msk CAN_FS1R_FSC10_Pos GPIO_CRL_CNF0_Pos I2C_TRISE_TRISE_Msk GPIO_CRH_MODE13_Msk CAN_F8R2_FB12_Msk WWDG_CR_T5 +syn keyword CTagsDefinedName GPIO_CRL_CNF3_0 AFIO_EXTICR4_EXTI15_PD_Pos CAN_F3R1_FB16_Pos CAN_FS1R_FSC11_Pos TIM_BDTR_LOCK_Pos RCC_CFGR_PPRE2_Msk CAN_FS1R_FSC4_Pos CAN_F2R2_FB4 SDIO_DCTRL_DTEN TIM_SMCR_MSM_Pos CAN_FA1R_FACT5_Pos RCC_CSR_LSIRDY_Msk CAN_F0R1_FB21_Pos CAN_F1R2_FB17 RTC_CNTL_RTC_CNT AFIO_EXTICR4_EXTI13_PC_Msk CAN_F1R2_FB13_Pos CAN_F4R1_FB12 CAN_F4R2_FB1_Pos AFIO_EVCR_PIN_1 CAN_F13R2_FB21 ADC_SMPR1_SMP17_0 TIM_BDTR_BKP CAN_RDH0R_DATA5_Pos CAN_F4R2_FB3 CAN_RF0R_RFOM0_Pos TIM_SR_CC2IF_Msk +syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI1_PF CAN_F7R1_FB27_Msk CAN_F10R2_FB4 EXTI_EMR_MR15_Msk USB_COUNT0_RX_COUNT0_RX CAN_F12R1_FB15_Pos CAN_F4R2_FB28_Pos AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos FLASH_USER_USER_Msk CAN_F12R1_FB8_Pos CAN_F13R1_FB12 CAN_F8R1_FB7_Msk GPIO_CRH_MODE9 CAN_F13R1_FB23_Pos CAN_F0R2_FB10_Pos CAN_F8R1_FB6_Msk CAN_F4R1_FB8_Msk CAN_RDH1R_DATA7 CAN_F6R2_FB11_Msk ADC_SQR1_SQ13_0 GPIO_BRR_BR14_Pos AFIO_EXTICR2_EXTI5_PC_Pos I2C_SR1_SB_Msk AFIO_EXTICR4_EXTI13_PG SDIO_MASK_TXFIFOHEIE +syn keyword CTagsDefinedName EXTI_FTSR_TR1_Pos AFIO_EXTICR4_EXTI12_PA AFIO_EXTICR1_EXTI1_PD SDIO_STA_RXFIFOHF_Pos CAN_RI0R_IDE_Pos USB_CNTR_LP_MODE CAN_F8R2_FB29_Msk CAN_RF0R_FMP0 GPIOC CAN_F10R2_FB0_Msk USART_CR1_TE_Msk CAN_F8R2_FB4_Pos AFIO_MAPR_TIM1_REMAP_1 CAN_F1R2_FB5_Pos AFIO_EXTICR2_EXTI6_PB_Msk SDIO_STA_TXUNDERR_Msk USB_EP2R_EP_KIND_Msk RCC_AHBENR_CRCEN_Msk CAN_F12R2_FB26 CAN_F13R1_FB22_Msk ADC_SMPR1_SMP13_Msk AFIO_EXTICR1_EXTI1_PE_Msk CAN_F13R2_FB8 RCC_APB1RSTR_USART2RST_Msk +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI6_PG_Pos CAN_F0R1_FB25_Pos EXTI_RTSR_TR18_Pos USB_COUNT1_RX_0_NUM_BLOCK_0_2 CRC_CR_RESET_Msk CAN_F4R1_FB6_Msk SDIO_POWER_PWRCTRL_1 ADC_CR1_SCAN_Msk CAN_F6R2_FB2_Pos CAN_F6R1_FB16 CAN_F0R1_FB1_Msk CAN_F10R2_FB2_Pos DMA_CCR_MSIZE_0 USB_EP1R_STAT_RX_Pos SDIO_STA_CCRCFAIL CAN_F3R2_FB30_Pos GPIO_LCKR_LCK15 CAN_F5R2_FB7_Msk DMA_CCR_TEIE_Pos USART_CR3_SCEN_Pos CAN_F1R1_FB10 RCC_CFGR_PPRE_DIV_16 GPIO_BRR_BR6_Pos CAN_F3R2_FB4_Msk RCC_BDCR_RTCSEL_LSI +syn keyword CTagsDefinedName RCC_AHBENR_DMA1EN_Pos CAN_F12R1_FB10_Pos SDIO_DLEN_DATALENGTH_Msk USB_COUNT7_TX_COUNT7_TX CAN_F8R2_FB18_Msk CAN_F6R2_FB23 CAN_MSR_SAMP_Pos CAN_MCR_TTCM_Msk TIM_DIER_CC4DE_Pos USART_CR2_STOP_Pos IS_WWDG_ALL_INSTANCE EXTI_IMR_MR10 CAN_F10R2_FB0_Pos I2C2_IRQERR_PRIORITY EXTI_FTSR_TR17 TIM_CR2_CCDS_Pos RCC_CR_HSITRIM_Pos CAN_F5R1_FB26 DMA_ISR_TCIF3 TIM_CCR2_CCR2 IS_GPIO_LOCK_INSTANCE EXTI_FTSR_TR2_Pos EXTI_FTSR_FT18 USB_EP0R_EP_KIND_Msk CAN_F11R1_FB5_Msk DMA_IFCR_CHTIF1_Msk +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PD_Msk GPIO_ODR_ODR10_Pos GPIO_CRH_MODE15_Pos USART_CR3_RTSE RCC_APB1ENR_WWDGEN CAN_F11R2_FB0 SDIO_FIFO_FIFODATA USB_EP4R_STAT_RX_1 USB_EP7R CAN_F10R2_FB19_Msk USB_EP7R_EP_TYPE FLASH_SR_EOP_Pos CAN_F6R2_FB17_Msk AFIO_EXTICR4_EXTI12_PC EXTI_PR_PIF16 CAN_F2R2_FB8_Msk EXTI_SWIER_SWIER18_Pos GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk RCC_APB1ENR_TIM3EN EXTI_IMR_MR1 CAN_F6R1_FB12 SDIO_ICR_STBITERRC_Msk CAN_F1R2_FB10_Pos CAN_F4R1_FB4_Msk AFIO_EVCR_PIN_PX8_Msk CAN_F5R2_FB16 +syn keyword CTagsDefinedName DMA_CCR_MSIZE_Msk USB_DADDR_ADD CAN_FA1R_FACT13 CAN_F13R1_FB8 USB_ADDR1_RX_ADDR1_RX_Msk USB_COUNT2_RX_0_NUM_BLOCK_0_1 CAN_F0R1_FB27_Pos TIM_DIER_TIE_Msk ADC_SQR2_SQ8_2 AFIO_EXTICR4_EXTI14_Pos CAN_F3R2_FB30_Msk ADC_CR1_SCAN_Pos ADC_JOFR2_JOFFSET2_Pos CAN_TSR_ALST1_Msk RCC_CFGR_PLLMULL14_Pos GPIO_CRH_CNF11_Msk CAN_F2R2_FB31_Msk GPIO_BRR_BR2_Pos CAN_F5R2_FB11 ADC_SMPR2_SMP7_0 CAN_TI2R_STID_Pos CAN_RDL1R_DATA0_Pos TIM_CCMR1_CC1S_Msk SDIO_STA_TXUNDERR CAN_F9R2_FB26 USB_ISTR_SOF +syn keyword CTagsDefinedName CAN_FM1R_FBM2_Pos CAN_F4R1_FB19 USB_EP7R_EA AFIO_EXTICR2_EXTI7_PB_Pos EXTI_SWIER_SWIER5_Pos IS_USART_INSTANCE TIM1_UP_TIM16_IRQHandler CAN_F6R1_FB16_Pos RCC_CFGR_PLLSRC_Msk USB_COUNT0_RX_0_BLSIZE_0 AFIO_EXTICR3_EXTI11_Pos BKP_CSR_TIF CAN_TDH2R_DATA5_Msk USB_CNTR_SUSPM USB_EP7R_EP_TYPE_0 BKP_DR1_D_Pos USART_CR1_SBK_Msk CAN_F3R1_FB14_Pos EXTI_IMR_MR9_Msk DMA_ISR_GIF5 EXTI RCC_CIR_LSERDYIE_Pos RCC_APB1RSTR_I2C2RST_Msk CAN_F7R2_FB12_Pos FLASH_WRP3_WRP3_Msk CAN_F13R1_FB14_Msk +syn keyword CTagsDefinedName EXTI_PR_PR6 CAN_F6R1_FB10_Msk FLASH_KEY2_Pos AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk USB_EP0R_CTR_RX_Pos CAN_F8R2_FB0_Pos USB_ISTR_WKUP_Msk SPI_CR1_CPHA CAN_F2R2_FB28_Pos USB_EP3R_EP_TYPE_0 EXTI_PR_PR14_Msk PIN_10 RCC_CFGR_HPRE_DIV_8 CAN_TSR_TERR2_Msk EXTI_RTSR_TR1_Pos CAN_F4R1_FB2 ADC_SMPR2_SMP1_Pos AFIO_EXTICR2_EXTI6_Pos CAN_F3R2_FB2 USB_COUNT5_RX_0_NUM_BLOCK_0 EXTI_SWIER_SWIER0_Pos SDIO_MASK_CTIMEOUTIE CAN_F13R2_FB19_Pos DMA1_Channel1 RCC_CFGR_PLLMULL11_Pos CAN_F6R1_FB11_Pos +syn keyword CTagsDefinedName CAN_F1R1_FB9_Pos I2C_SR1_ARLO_Msk TIM_CR2_CCUS CAN_TSR_ALST0_Msk AFIO_EXTICR3_EXTI9_PG GPIO_CRL_MODE7 USART_CR2_LBDL_Pos USB_ISTR_PMAOVR CAN_F13R2_FB31_Msk CAN_F13R2_FB4_Msk CAN_F0R1_FB27 USB_COUNT0_RX_1_NUM_BLOCK_1_4 CAN_F13R2_FB27 GPIO_IDR_IDR0 CAN1 SDIO_ICR_CMDSENTC EXTI_SWIER_SWI7 SDIO_CMD_NIEN_Msk CAN_RDH1R_DATA7_Pos GPIO_BSRR_BS3_Pos MODIFY_REG RCC_APB2ENR_IOPCEN_Msk CAN_F9R2_FB7 USART_CR1_SBK_Pos CAN_TSR_ALST2_Pos GPIO_CRL_MODE4_0 CAN_F0R1_FB24_Msk USB_EP5R_SETUP +syn keyword CTagsDefinedName CAN_F2R2_FB6_Pos CAN_F4R2_FB7 RCC_BDCR_RTCSEL_1 IS_CRC_ALL_INSTANCE CAN_F4R2_FB5 CAN_F2R2_FB16 USB_COUNT0_RX_COUNT0_RX_Pos CAN_F6R2_FB25 I2C_SR1_TIMEOUT_Msk DMA_IFCR_CHTIF1_Pos DMA_IFCR_CHTIF4 EXTI_RTSR_TR12 CAN_F4R2_FB13_Msk CAN_F7R2_FB29 PIN_OPT_AF8 RTC_CRL_ALRF_Msk GPIO_LCKR_LCK6_Pos TIM_CR2_MMS_Msk USB_COUNT2_RX_1_NUM_BLOCK_1_3 GPIO_LCKR_LCK2 CAN_F4R1_FB23_Msk DBGMCU_CR_TRACE_IOEN_Msk RCC_CIR_PLLRDYF_Pos USB_COUNT6_RX_0_BLSIZE_0 EXTI_EMR_MR13_Msk AFIO_EVCR_PIN_PX13 +syn keyword CTagsDefinedName CAN_F12R2_FB22_Msk USB_COUNT3_RX_1_COUNT3_RX_1 CAN_RDL0R_DATA3_Pos TIM_CCMR2_IC3F_Pos SDIO_MASK_DBCKENDIE USB_COUNT3_TX_1_COUNT3_TX_1 DBGMCU_CR_DBG_STANDBY USB_DADDR_ADD3_Msk AFIO_EXTICR3_EXTI11 ADC_CR1_DISCEN_Msk ADC_CR1_JDISCEN_Msk CAN_F0R2_FB20_Msk EXTI_RTSR_TR14_Pos GPIO_ODR_ODR15 CAN_TDL2R_DATA1_Pos CAN_F11R1_FB15_Pos TIM_CCMR1_IC2F_3 CAN_TDL1R_DATA2 CAN_F7R2_FB18 GPIO_BSRR_BR15_Pos SDIO_MASK_DCRCFAILIE CAN_TSR_ABRQ2_Pos CAN_F3R2_FB31 CAN_F10R1_FB26_Msk CAN_TDL2R_DATA0 +syn keyword CTagsDefinedName CAN_F9R1_FB11 USART_CR1_RE_Pos BKP_CR_TPE_Pos GPIO_LCKR_LCKK_Msk CAN_F1R2_FB12_Msk RCC_APB1RSTR_BKPRST_Msk AFIO_EXTICR1_EXTI1_PF_Msk GPIO_BSRR_BS12_Pos SDIO_STA_TXACT_Pos EXTI_IMR_MR5 USB_EP3R_SETUP_Msk USB_EP6R_EP_TYPE_0 CAN_IER_FFIE0_Msk TIM_DIER_TDE CAN_F10R1_FB10_Msk CAN_F7R1_FB5_Pos EXTI_FTSR_TR7_Pos CAN_TSR_RQCP1_Pos ADC_SQR1_SQ13_Pos __STM32F1_CMSIS_VERSION_RC EXTI_IMR_MR10_Pos EXTI_RTSR_TR13_Pos WWDG_CR_T_5 CAN_F1R1_FB25 GPIO_LCKR_LCK5 EXTI_RTSR_RT3 CAN_F0R2_FB23 +syn keyword CTagsDefinedName CAN_TSR_LOW2_Msk ADC_SMPR2_SMP3_1 CAN_F10R2_FB10 CAN_F3R1_FB10_Pos I2C_OAR1_ADD7_Msk CAN_F6R1_FB16_Msk TIM_SR_CC2IF CAN_F8R1_FB0 RCC_CIR_PLLRDYIE AFIO_EXTICR1_EXTI3 USB_COUNT6_RX_1_BLSIZE_1 RCC_CFGR_PPRE1_1 RCC_AHBENR_DMA1EN CAN_F2R2_FB28_Msk CAN_F10R1_FB24 CAN_F0R2_FB14 RCC_BDCR_LSERDY_Msk CAN_TI0R_EXID_Msk CAN_F4R2_FB17_Msk CAN_F7R1_FB31 EXTI_FTSR_TR15_Msk EXTI_SWIER_SWIER16 ADC_SQR1_L_3 GPIO_CRL_MODE6_Msk CAN_TDL1R_DATA3_Pos CAN_F0R1_FB23_Pos AFIO_EVCR_EVOE CAN_F7R1_FB22_Msk +syn keyword CTagsDefinedName CAN_F3R1_FB16 DMA_IFCR_CHTIF1 EXTI_PR_PR9_Msk CAN_FA1R_FACT4_Pos I2C_SR1_RXNE PIN_MODE_ALTFUNC ADC_SQR1_L_Msk CAN_TDH2R_DATA7_Msk RCC_AHBENR_CRCEN_Pos AFIO_EXTICR1_EXTI2_PC_Pos CAN_F2R1_FB18_Pos SPI_SR_TXE_Msk SPI_DR_DR CAN_F8R2_FB0_Msk AFIO_EXTICR1_EXTI2_PG FLASH_OBR_nRST_STDBY USART_CR2_CLKEN_Pos CAN_F13R2_FB0_Msk CAN_F10R1_FB11_Msk EXTI_SWIER_SWIER4_Msk CAN_F0R1_FB12_Pos NVIC_NUM_VECTORS TIM_CR2_CCDS AFIO_EVCR_PIN_Msk SDIO_DCTRL_RWSTART_Msk AFIO_EVCR_PIN +syn keyword CTagsDefinedName USB_COUNT0_RX_1_NUM_BLOCK_1_2 GPIO_BRR_BR0 RCC_CIR_HSERDYIE ADC_JSQR_JSQ1_0 CAN_F6R1_FB14_Msk CAN_F4R2_FB11 USB_COUNT1_RX_NUM_BLOCK_3 EXTI_PR_PR17_Pos AFIO_MAPR_TIM3_REMAP_Msk CAN_TSR_ABRQ2 CAN_F3R1_FB27_Pos CAN_MSR_SLAK_Pos GPIO_BSRR_BR11 CAN_F1R1_FB12_Msk RCC_CFGR_PPRE_DIV_NONE CAN_F4R1_FB31 CAN_F6R1_FB25_Msk USB_ADDR3_RX_ADDR3_RX_Msk GPIO_CRH_MODE13_0 CAN_TI1R_EXID_Msk PWR_CSR_SBF_Pos CAN_F6R2_FB22_Msk RCC_APB1RSTR_CAN1RST_Msk FLASH_OBR_DATA1_Pos TIM_CCMR2_OC3M_Pos +syn keyword CTagsDefinedName CAN_F13R1_FB18_Msk EXTI_EMR_MR5_Msk CAN_F1R2_FB24_Msk CAN_F2R2_FB29_Pos EXTI_EMR_MR12 TIM_CCMR2_IC4F_2 AFIO_MAPR_I2C1_REMAP_Pos CAN_F5R2_FB29_Msk EXTI_IMR_IM2 ADC_SQR3_SQ2_Pos USB_ADDR0_TX_ADDR0_TX_Msk EXTI_RTSR_TR0_Pos CAN_F5R1_FB29 CAN_F10R1_FB2_Pos USB_EP5R_EP_KIND_Msk DMA_ISR_GIF7_Pos I2C3_IRQERR_PRIORITY I2C_OAR1_ADD8_Pos CAN_F12R1_FB29_Pos CAN_F8R2_FB11_Pos SDIO_STA_RXDAVL_Msk RCC_CIR_HSIRDYF USART_CR1_RWU_Pos RCC_APB2ENR_IOPAEN_Pos CAN_F7R1_FB8 CAN_F7R1_FB15_Pos +syn keyword CTagsDefinedName CAN_F7R1_FB25_Pos CAN_F10R1_FB15_Msk CAN_TI2R_TXRQ CAN_F2R2_FB3_Pos USB_COUNT6_RX_NUM_BLOCK_0 ADC_CR1_AWDCH CAN_FA1R_FACT6_Msk DMA_IFCR_CGIF6 CAN_F2R1_FB14 CAN_FM1R_FBM7 CAN_F13R2_FB3 USB_EP_TYPE_MASK CAN_F6R2_FB30 CAN_F8R1_FB18_Pos CAN_F3R2_FB29_Msk USB_EP1R_STAT_RX_Msk EXTI_IMR_IM8 I2C_CR2_FREQ_2 GPIO_CRL_MODE3 CAN_TSR_LOW_Msk USB_CNTR_ESOFM CAN_F4R2_FB20_Pos ADC_JOFR3_JOFFSET3_Pos CAN_F2R1_FB18_Msk CAN_F0R2_FB21 CAN_F4R2_FB24_Msk USB_COUNT4_RX_1_BLSIZE_1 GPIO_CRL_MODE6_0 +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI13_PG_Pos CAN_F6R1_FB21 CAN_TI1R_IDE_Msk USB_EP4R_DTOG_TX_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_2 TIM_CCMR2_OC3PE_Pos USB_EP1R_CTR_RX_Msk USB_ADDR2_TX_ADDR2_TX CAN_F3R2_FB7_Msk CAN_F7R2_FB9 TIM_CCMR2_CC3S_0 RCC_APB1ENR_TIM4EN_Pos CAN_FA1R_FACT1_Msk GPIO_BSRR_BS8_Msk USB_COUNT2_RX_BLSIZE_Msk CAN_F6R2_FB31_Msk CAN_F12R1_FB19 CAN_F10R1_FB29 AFIO_MAPR_PD01_REMAP_Msk CAN_F10R1_FB30 SDIO_MASK_TXFIFOFIE USART_BRR_DIV_Mantissa_Pos AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos +syn keyword CTagsDefinedName USB_ADDR0_RX_ADDR0_RX CAN_F9R1_FB19_Pos CAN_F11R1_FB21_Pos CAN_F7R1_FB30_Msk CAN_F13R2_FB29_Msk AFIO_EXTICR3_EXTI10_PB CAN_F11R1_FB10_Pos CAN_F11R2_FB7 USB_ADDR0_RX_ADDR0_RX_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_3 SDIO_STA_TXFIFOHE_Msk CAN_F3R2_FB19 EXTI_IMR_MR14 TIM_CCMR2_CC3S_1 CAN_F7R1_FB24 EXTI_FTSR_TR18_Pos AFIO_EXTICR4_EXTI13_PE_Pos CAN_F0R2_FB29_Pos CAN_RDL0R_DATA3_Msk RCC_CFGR_PLLMULL13_Msk CAN_TDH0R_DATA4_Msk CAN_F10R1_FB31_Pos CAN_F10R2_FB25 RCC_BDCR_RTCSEL_HSE USART_CR1_RE +syn keyword CTagsDefinedName CAN_F4R2_FB29_Pos CAN_F1R1_FB23_Pos USB_COUNT5_RX_1_NUM_BLOCK_1 DMA1 SPI_SR_BSY CAN_F5R1_FB9 GPIO_CRH_CNF10_Msk CAN_TDH2R_DATA6_Msk AFIO_EXTICR1_EXTI0_PB CAN_F7R1_FB9 CAN_F5R2_FB23_Pos DMA_CCR_CIRC SDIO_MASK_TXUNDERRIE TIM_SR_COMIF_Pos CAN_F8R2_FB19_Msk CAN_F5R2_FB29 CAN_F12R1_FB29 EXTI_PR_PR0 WRITE_REG CAN_F0R2_FB22_Msk DMA_IFCR_CTCIF6_Msk CAN_F7R1_FB26_Msk CAN_TSR_ABRQ1 CAN_F4R1_FB10 I2C_SR2_BUSY_Pos TIM_CCMR2_OC4M RCC_APB1RSTR_TIM3RST_Msk CAN_F0R2_FB22_Pos +syn keyword CTagsDefinedName EXTI_SWIER_SWIER8_Msk CAN_F6R2_FB31_Pos CAN_F12R1_FB5 SPI_CR1_SSI_Pos USB_EP7R_EP_KIND_Msk CAN_F10R2_FB13 CAN_F0R1_FB3 EXTI_SWIER_SWI5 ADC_SMPR2_SMP6_1 CAN_F0R1_FB12_Msk CAN_F2R2_FB0_Msk TIM_SMCR_ETPS_Pos DMA_ISR_TCIF2_Pos SDIO_CMD_WAITPEND_Pos DMA_IFCR_CTCIF6_Pos CAN_IER_FMPIE0 CAN_F8R2_FB17_Msk DMA_IFCR_CTEIF7_Pos EXTI_IMR_MR15_Pos TIM_CCMR1_OC1CE_Pos CAN_F12R2_FB4_Pos CAN_F6R2_FB24 USB_ADDR6_RX_ADDR6_RX_Msk I2C_CR2_LAST_Msk ADC_SQR1_SQ15_1 IWDG_SR_PVU_Msk AFIO_MAPR_SWJ_CFG +syn keyword CTagsDefinedName RCC_CIR_HSIRDYF_Msk USART_CR2_ADD_Pos AFIO_EXTICR4_EXTI13_PC_Pos AFIO_EXTICR3_EXTI8_PE_Pos AFIO_EXTICR4_EXTI12_PF_Pos USB_EPTX_DTOG2 EXTI_FTSR_TR13 CAN_F7R2_FB8_Pos RCC_AHBENR_CRCEN RTC_CRH_OWIE I2C_CR1_STOP_Pos ADC_CR1_EOCIE DMA_IFCR_CTEIF6_Pos I2C_CR1_START CAN_TDL2R_DATA2_Pos CAN_F6R1_FB21_Pos CAN_F13R2_FB15_Pos CAN_F3R2_FB26_Msk RCC_CIR_LSERDYIE CAN_F1R2_FB21_Pos RCC_CFGR_MCOSEL_SYSCLK DMA_IFCR_CTEIF3_Pos EXTI_RTSR_TR7 GPIO_BSRR_BS15 RCC_CFGR_PLLMULL2 GPIO_BRR_BR10_Msk +syn keyword CTagsDefinedName CAN_TSR_RQCP0 SRAM_BB_BASE USB_ADDR4_TX_ADDR4_TX_Pos ADC_CR2_CAL_Msk CAN_F6R2_FB10 I2C_SR2_TRA USB_COUNT4_RX_NUM_BLOCK_3 USB_EP5R_STAT_RX CAN1_RX0_IRQn CAN_F0R1_FB29_Pos CAN_F8R2_FB14 CAN_F0R1_FB29 EXTI_PR_PR6_Msk SPI_CR2_RXDMAEN_Msk USB_EP4R_STAT_RX_Msk AFIO_EVCR_EVOE_Msk CAN_F2R2_FB19 CAN_F0R1_FB18_Pos USART_CR1_PS AFIO_EXTICR1_EXTI1_PC TIM_CCER_CC2E_Pos ADC_SMPR1_SMP13_0 USB_COUNT0_RX_1_COUNT0_RX_1 RCC_APB1RSTR_I2C1RST_Pos ADC_SMPR2_SMP1_Msk TIM_CCMR1_OC2CE_Pos +syn keyword CTagsDefinedName CAN_F13R1_FB19_Pos CAN_F4R1_FB10_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_3 CAN_F7R1_FB13 EXTI_RTSR_RT13 CAN_F4R1_FB25_Msk USB_EP2R CAN_F2R1_FB22_Pos SPI_SR_CHSIDE PIN_MODE_ANALOG TIM_SR_CC4OF SYSCFG_EXTI_PA_MASK CAN_F1R1_FB3_Msk USB_COUNT1_RX_0_NUM_BLOCK_0 CAN_TDT1R_DLC_Pos CAN_F0R2_FB20_Pos APB2PERIPH_BASE CAN_F10R2_FB7_Msk RCC_CFGR_PPRE1_DIV1 CAN_F10R1_FB1_Pos CAN_F2R1_FB19 USB_COUNT3_RX_NUM_BLOCK_3 TIM_EGR_CC1G_Msk CAN_F2R1_FB4_Pos DBGMCU_CR_DBG_SLEEP_Pos CAN_F11R2_FB28_Msk +syn keyword CTagsDefinedName PIN_MODE_INPUT CAN_RDT0R_FMI_Pos ADC_SMPR2_SMP5 USB_EP4R_DTOG_RX_Msk TIM_SR_CC4IF_Msk USB_EP3R_EP_KIND_Msk RCC_APB1RSTR_TIM2RST_Pos GPIO_CRL_CNF5_Msk USB_COUNT3_RX_BLSIZE CAN_F1R1_FB11_Msk CAN_RF1R_RFOM1_Pos SDIO_MASK_TXFIFOEIE_Msk EXTI_PR_PR8_Msk CAN_F6R2_FB7_Msk AFIO_EXTICR1_EXTI0_PC_Pos CAN_FM1R_FBM7_Msk ADC_CR2_ALIGN DMA_IFCR_CHTIF7_Msk GPIO_BSRR_BS10_Pos I2C_CCR_CCR_Msk CAN_F7R1_FB8_Pos CAN_TDH1R_DATA7 CAN_F6R2_FB6_Msk PWR_CR_PLS_2 CAN_ESR_EPVF USB_COUNT0_RX_BLSIZE_Pos +syn keyword CTagsDefinedName TIM_CCMR2_IC4F_Msk USB_EP4R_SETUP_Msk EXTI_FTSR_TR8 PWR_CR_CWUF ADC_SQR3_SQ3_2 CAN_F0R1_FB18 CAN_F13R1_FB21 BKP_CSR_TPIE_Msk RCC_CFGR_SWS_1 EXTI_RTSR_RT1 DMA1_Channel4_BASE ADC_SMPR1_SMP15_0 CAN_F6R1_FB27 GPIOE RCC_CFGR_ADCPRE_Pos TIM_CR2_OIS4_Pos CAN_F4R1_FB12_Pos CAN_F7R1_FB19 USART_CR1_M_Pos USB_ADDR3_RX_ADDR3_RX ADC_SQR3_SQ1_3 CAN_F4R2_FB6_Msk CAN_F9R1_FB3_Pos EXTI_PR_PR15_Msk USB_EP0R_DTOG_RX_Pos CAN_F13R1_FB18_Pos EXTI_IMR_MR9 TIM_SMCR_SMS_Msk EXTI_SWIER_SWIER12 +syn keyword CTagsDefinedName USB_EP4R_EA USB_EP3R_CTR_RX USB_COUNT6_RX_NUM_BLOCK_Msk CAN_RDH1R_DATA5_Pos TIM_SR_CC4OF_Msk CAN_F12R2_FB20_Pos CAN_FM1R_FBM SPI_CR1_BIDIMODE_Pos WWDG_CR_WDGA DBGMCU_CR_DBG_IWDG_STOP_Pos USB_COUNT1_RX_1_COUNT1_RX_1 CAN_F12R1_FB1_Pos ADC_SQR3_SQ1 CAN_F6R2_FB29_Msk EXTI_FTSR_TR4 PIN_11 CAN_F2R2_FB30_Pos CAN_F1R2_FB4_Pos CAN_F12R1_FB22 CAN_F2R1_FB27_Pos CAN_F1R2_FB22_Pos CAN_RI1R_IDE_Msk RCC_APB2RSTR_IOPBRST DMA_IFCR_CTCIF2 FLASH_WRP2_WRP2_Msk CAN_FA1R_FACT10 GPIO_ODR_ODR2_Msk +syn keyword CTagsDefinedName TIM_CCMR1_IC1PSC_Msk USART_CR1_TCIE RCC_APB2RSTR_ADC2RST CAN_F10R2_FB17 CAN_F6R2_FB1 EXTI_EMR_MR16_Pos ADC_CR1_JAWDEN ADC_JDR1_JDATA_Pos USB_DADDR_ADD1 CAN_F5R2_FB5 FLASH_DATA0_DATA0_Msk SDIO_DTIMER_DATATIME_Pos CAN_IER_FOVIE0 RTC_DIVH_RTC_DIV_Pos CAN_F10R2_FB15 SDIO_CMD_WAITRESP_0 RCC_CFGR_PLLSRC WWDG_CFR_EWI CAN_F13R2_FB18_Msk USB_EP4R_STAT_TX_1 CAN_F5R1_FB28_Msk TIM_CCMR2_IC3PSC_1 CAN_F6R1_FB21_Msk ADC_CR1_DUALMOD_0 USB_CNTR_RESUME_Msk CAN_F13R1_FB10 CAN_TDH1R_DATA7_Pos +syn keyword CTagsDefinedName TIM_SR_BIF_Msk CAN_F1R1_FB31_Msk AFIO_EXTICR3_EXTI10_PC RCC_CFGR_PPRE1_Msk CAN_RI0R_STID_Pos CAN_F11R2_FB29 USB_COUNT1_RX_0_NUM_BLOCK_0_3 CAN_F5R2_FB14 AFIO_EXTICR4_EXTI13_PG_Msk CAN_F6R2_FB30_Pos EXTI_EMR_MR13 USB_ADDR3_TX_ADDR3_TX_Pos CAN_F2R2_FB26 AFIO_EXTICR3_EXTI11_PC_Msk USB_COUNT7_RX_0_NUM_BLOCK_0_0 CAN_F4R1_FB21_Pos ADC_SQR1_SQ16_4 CAN_RI1R_IDE_Pos _RCC_H_ CAN_RDL1R_DATA3 CAN_F9R1_FB2_Msk SDIO_MASK_RXFIFOHFIE_Pos USB_COUNT3_RX_NUM_BLOCK_1 USB_COUNT0_TX_COUNT0_TX_Msk +syn keyword CTagsDefinedName EXTI_RTSR_TR8_Msk CAN_F7R2_FB19 AFIO_EXTICR3_EXTI10_PF CAN_F9R2_FB26_Msk CAN_F7R2_FB25_Pos ADC_SMPR2_SMP7_Msk CAN_F13R1_FB26_Pos CAN_F6R2_FB8_Msk AFIO_EXTICR3_EXTI10_PB_Msk CAN_F9R1_FB11_Msk USB_CNTR_LP_MODE_Pos PWR_CR_DBP_Msk CAN_F0R2_FB8_Msk AFIO_MAPR_SWJ_CFG_DISABLE DBGMCU_IDCODE_REV_ID_Msk SPI_CR2_RXNEIE_Msk USART_CR1_PCE CAN_F3R1_FB3_Msk AFIO_EXTICR4_EXTI15_PG_Pos ADC_JSQR_JSQ1_4 CAN_F7R2_FB17_Msk CAN_F9R2_FB23_Msk FLASH_OBR_USER_Msk CAN_F13R2_FB26_Pos ADC_CR1_DUALMOD_3 +syn keyword CTagsDefinedName SDIO_RESP1_CARDSTATUS1 FLASH_USER_nUSER_Pos USART_CR1_WAKE_Pos CAN_TDL2R_DATA0_Pos CAN_F3R2_FB23_Msk FLASH_CR_PER_Pos GPIO_CRL_MODE4_Msk CAN_F0R1_FB19 ADC_JOFR3_JOFFSET3 ADC_SQR2_SQ7_Pos USB_COUNT5_TX_1_COUNT5_TX_1 I2C_CR2_DMAEN_Pos RTC_CRH_OWIE_Pos USB_EP4R_STAT_TX AFIO_EXTICR4_EXTI14_PG __SYSTEM_STM32F10X_H I2C_SR1_RXNE_Pos DMA_ISR_TEIF1 SDIO_STA_DTIMEOUT RCC_CR_HSICAL CAN_F13R1_FB26_Msk DBGMCU_IDCODE_REV_ID_7 CAN_F11R2_FB8_Msk FLASH_WRP0_nWRP0_Msk FLASH_CR_MER_Pos +syn keyword CTagsDefinedName USART_CR2_STOP_0 ADC_JSQR_JSQ4_0 CAN_F2R1_FB30_Pos CAN_F10R1_FB26 CAN_F3R2_FB28_Pos GPIO_BRR_BR15 CAN_F2R1_FB23 RCC_CSR_RMVF CAN_TDH2R_DATA6_Pos TIM_EGR_UG_Pos TIM_CCER_CC1NE_Msk USART_CR1_TE DBGMCU_IDCODE_REV_ID_2 ADC_JSQR_JL_Msk CAN_TSR_TXOK1_Pos USB_CNTR_ESOFM_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos CAN_F12R2_FB8_Pos RCC_CIR_LSIRDYIE_Pos CAN_F12R1_FB21_Msk CAN_F7R2_FB11_Pos CAN_F3R1_FB24 CAN_F8R2_FB24 SDIO_CLKCR_CLKDIV USB_COUNT0_RX_NUM_BLOCK_1 CAN_TDT0R_TIME_Pos +syn keyword CTagsDefinedName CAN_TSR_LOW2_Pos AFIO_EXTICR3_EXTI11_PB ADC_SQR2_SQ11_Pos CAN_F5R2_FB2_Msk CAN_F1R2_FB3_Msk CAN_F8R1_FB14_Msk RCC_CR_HSICAL_Pos CAN_F5R2_FB7_Pos CAN_F4R1_FB8 AFIO_MAPR_TIM3_REMAP NVIC_RAM_VECTOR_ADDRESS USART_CR1_UE_Msk DMA1_Channel6_BASE CAN_RF1R_FULL1 USB_EP1R_DTOG_TX_Pos CAN_F0R1_FB8_Msk CAN_F6R1_FB4_Pos ADC_SQR2_SQ10 GPIO_CRH_CNF12 __CM3_REV CAN_FA1R_FACT7 SDIO_MASK_RXFIFOFIE_Msk USB_COUNT3_RX_NUM_BLOCK_2 CAN_F2R1_FB26_Msk FLASH_DATA1_nDATA1_Msk CAN_TSR_ABRQ1_Pos +syn keyword CTagsDefinedName TIM_DCR_DBL_Msk USB_EP_T_FIELD WWDG_CFR_W_6 CAN_F4R2_FB13_Pos I2C_SR1_AF CAN_F0R2_FB22 EXTI_PR_PR3_Msk CAN_F7R1_FB13_Pos EXTI_FTSR_TR13_Msk SDIO_STA_RXDAVL_Pos RCC_APB2RSTR_IOPCRST CAN_F10R2_FB11_Pos USB_COUNT2_RX_NUM_BLOCK_Pos CAN_TI1R_STID_Pos AFIO_MAPR_USART3_REMAP_NOREMAP EXTI_RTSR_TR15_Pos GPIO_CRH_MODE9_Msk ADC_SMPR2_SMP5_1 RCC_APB1RSTR_BKPRST_Pos SPI_I2SCFGR_I2SMOD_Msk TIM_EGR_COMG_Msk __STM32F103xB_H GPIO_BSRR_BS6_Pos EXTI_SWIER_SWIER1 CAN_F1R2_FB13 +syn keyword CTagsDefinedName SDIO_RESP4_CARDSTATUS4 USB_EP2R_STAT_TX_Pos PIN_9 RCC_APB1ENR_TIM3EN_Pos CAN_F5R2_FB12 TIM_CCER_CC3E CAN_RI0R_STID_Msk CAN_F10R1_FB15 CAN_F4R2_FB9 CAN_F10R2_FB27_Msk SDIO_STA_TXDAVL CAN_F3R2_FB26 TIM_SR_TIF CAN_F12R2_FB28_Pos CAN_F3R1_FB16_Msk EXTI_PR_PIF0 CAN_F11R1_FB14_Msk CAN_RDL0R_DATA1 I2C_OAR1_ADD6_Pos CAN_F4R2_FB9_Msk AFIO_EVCR_PORT_PE_Msk RCC_CFGR_HPRE_DIV4 RCC_CFGR_PLLMULL15_Pos GPIO_IDR_IDR8 CAN_F12R1_FB0_Pos USB_EP5R_CTR_TX ADC_SQR2_SQ9_3 SDIO_ICR_CMDSENTC_Msk +syn keyword CTagsDefinedName I2C_OAR1_ADD4_Msk USB_COUNT7_RX_BLSIZE USB_EP4R_DTOG_RX_Pos CAN_F1R2_FB15_Msk EXTI_RTSR_TR8 AFIO_EXTICR2_EXTI4_PB_Msk AFIO_EVCR_PIN_PX11_Msk TIM_DIER_COMIE CAN_RDT0R_FMI RCC_CFGR_SW_PLL EXTI_FTSR_FT8 CAN_IER_TMEIE_Msk CAN_F10R2_FB12 CAN_F12R2_FB22_Pos CAN_F9R2_FB0_Msk SDIO_MASK_STBITERRIE_Msk I2C_OAR1_ADD5_Msk GPIO_CRH_MODE14_0 ADC_SR_JSTRT_Msk CAN_TSR_ABRQ1_Msk CAN_F8R1_FB5_Pos CAN_F10R1_FB14 RCC_CSR_WWDGRSTF_Pos DMA_IFCR_CGIF3 RCC_CIR_LSIRDYC GPIO_IDR_IDR10 CAN_F13R2_FB14_Pos +syn keyword CTagsDefinedName GPIO_CRL_CNF6_0 RCC_APB1RSTR_I2C1RST_Msk EXTI_RTSR_RT16 USB_COUNT5_RX_1_NUM_BLOCK_1_0 CAN_F0R2_FB14_Pos SPI_CR1_DFF_Pos SDIO_MASK_TXFIFOFIE_Msk TIM_SMCR_MSM_Msk CAN_F8R1_FB4_Pos CAN_TSR_LOW CAN_F6R1_FB26 RCC_CFGR_PLLMULL14_Msk RCC_CR_CSSON_Pos CAN_F1R1_FB12 AFIO_EXTICR1_EXTI3_PB_Pos CAN_RI1R_RTR_Pos I2C2_IRQ_PRIORITY CAN_F1R1_FB19_Pos CAN_TSR_TME2_Msk USB_COUNT3_RX_1_BLSIZE_1 CAN_F4R2_FB18_Msk SPI_RXCRCR_RXCRC_Msk AFIO_EXTICR1_EXTI1_PG GPIO_LCKR_LCK3_Msk USB_FNR_RXDM_Pos +syn keyword CTagsDefinedName RCC_CSR_LSION_Msk DBGMCU_CR_TRACE_IOEN CRC_IDR_IDR DBGMCU_CR_TRACE_MODE_0 USB_EP2R_DTOG_TX CAN_F10R1_FB13_Msk SDIO_STA_RXFIFOF_Msk TIM_DIER_UDE_Msk USB_COUNT2_RX_1_NUM_BLOCK_1 CAN_F6R2_FB20_Pos CAN_F13R2_FB23_Msk DBGMCU_CR_DBG_SLEEP PIN_OPT_AF0 ADC_JSQR_JSQ3_Pos USB_COUNT3_RX_0_NUM_BLOCK_0 EXTI_EMR_MR11_Pos CAN_F8R1_FB8_Pos CAN_F3R1_FB6_Msk CAN_F7R2_FB23_Pos I2C_OAR1_ADDMODE SPI_CR1_CRCEN_Pos CAN_F13R2_FB0 USART1_IRQ_PRIORITY ADC_CR1_SCAN CAN_FA1R_FACT6 CAN_F12R1_FB24_Msk +syn keyword CTagsDefinedName CAN_TDL0R_DATA2_Msk ADC_SQR3_SQ5_0 EXTI_RTSR_TR17 CAN_F2R2_FB6 CAN_F6R1_FB10_Pos CAN_F6R1_FB20_Pos DBGMCU_CR_DBG_CAN1_STOP_Pos RTC_CRH_ALRIE_Pos EXTI_FTSR_TR12_Msk EXTI_FTSR_TR2_Msk FLASH_KEY1_Msk TIM_CCER_CC3NE_Pos EXTI_PR_PR4_Pos USB_COUNT7_RX_NUM_BLOCK_Msk AFIO_EXTICR2_EXTI5_PA CAN_F6R1_FB29_Msk CAN_F5R2_FB27_Pos CAN_F8R2_FB17 FLASH_ACR_LATENCY_Pos CAN_F2R1_FB11_Msk CAN_F9R2_FB5_Pos CAN_F7R1_FB17_Msk BKP_CSR_CTE_Pos ADC_CR1_AWDIE_Msk USB_BTABLE_BTABLE_Msk +syn keyword CTagsDefinedName USB_EP4R_STAT_TX_Pos SPI_CR1_DFF_Msk CAN_F11R2_FB12_Pos CAN_F5R1_FB15_Pos I2C_CR1_ENGC EXTI_SWIER_SWIER11_Msk ADC_SMPR1_SMP17_2 CAN_F12R2_FB10 CAN_RDH0R_DATA4 TIM_SR_UIF_Msk FLASH_OBR_USER RCC_CR_CSSON CAN_F9R2_FB10_Pos CAN_F6R2_FB3_Pos CAN_F2R2_FB22_Msk SPI5_IRQ_PRIORITY AFIO_EXTICR3_EXTI8_PC_Msk CAN_F12R2_FB30_Msk CAN_F6R1_FB17_Msk CAN_MSR_TXM_Pos GPIO_CRL_CNF1 TIM_CR2_OIS3N_Pos GPIO_CRL_CNF4_1 SDIO_ICR_CEATAENDC_Pos TIM_SR_CC3OF_Msk ADC_SMPR2_SMP4_2 RCC_CR_HSEBYP_Msk +syn keyword CTagsDefinedName CAN_F10R2_FB27 CAN_F4R2_FB14_Msk AFIO_EXTICR4_EXTI14_PE CAN_F0R2_FB4_Msk CAN_IER_SLKIE CAN_BTR_SJW GPIO_CRL_CNF1_Pos I2C_SR1_SB CAN_F13R2_FB6_Msk DMA_CMAR_MA_Pos CAN_MCR_ABOM_Pos GPIO_BRR_BR11_Pos PWR_CSR_PVDO_Msk USART_SR_FE_Msk ADC_CR1_JAUTO_Msk BKP_DR4_D CAN_RDT0R_TIME_Msk CAN_TSR_TERR0_Pos SDIO_MASK_RXFIFOHFIE ADC_CR1_AWDCH_Msk CAN_FS1R_FSC7_Msk SPI_CRCPR_CRCPOLY CAN_F3R1_FB0_Msk CAN_F10R1_FB14_Msk RCC_CFGR_PLLMULL9_Pos GPIO_CRH_MODE12 SDIO_DCTRL_RWSTOP I2C_SR1_BERR +syn keyword CTagsDefinedName SDIO_MASK_CMDRENDIE_Pos SDIO_RESP4_CARDSTATUS4_Msk CAN_F5R1_FB18_Pos RCC_CFGR_MCOSEL_1 CAN_F13R2_FB25_Msk RCC_APB2ENR_USART1EN_Pos USB_CNTR_SUSPM_Msk CAN_F6R2_FB1_Pos CAN_F5R1_FB30 GPIO_BSRR_BS4_Msk DMA_CCR_PL_0 TIM_EGR_TG_Pos CAN_F11R2_FB28_Pos USB_ADDR3_TX_ADDR3_TX_Msk CAN_F0R1_FB26_Msk AFIO_EXTICR4_EXTI15_PB_Pos CAN_F0R1_FB16_Msk ADC_SQR2_SQ11_4 CAN_F5R1_FB0 CAN_IER_FFIE0_Pos USB_DADDR_ADD_Msk CAN_F0R2_FB31 ADC_SMPR2_SMP9_Msk EXTI_EMR_MR16_Msk CAN_F1R2_FB7_Pos +syn keyword CTagsDefinedName ADC_SMPR2_SMP6_Pos I2C_CCR_CCR_Pos CAN_BTR_TS2_Pos AFIO_MAPR_I2C1_REMAP EXTI_EMR_MR15_Pos TIM_SR_CC4IF AFIO_EXTICR2_EXTI7_PE CAN_F1R2_FB21 CAN_F4R1_FB14_Pos CAN_F11R2_FB22_Msk CAN_F3R2_FB21_Pos USB_COUNT6_RX_0_NUM_BLOCK_0_3 CAN_TI1R_RTR RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_TIM1RST_Msk PWM_CHANNEL_1 CAN_F11R1_FB24_Pos RTC_PRLL_PRL_Pos CAN_F4R1_FB6 CAN_F5R2_FB27_Msk IS_TIM_CC2_INSTANCE CAN_F11R1_FB27_Msk GPIO_IDR_IDR7_Msk CAN_F5R1_FB31 CAN_F0R2_FB27_Msk USB_EP7R_STAT_TX_Pos +syn keyword CTagsDefinedName CAN_F0R1_FB20_Pos SDIO_STA_DCRCFAIL_Pos RTC_PRLL_PRL AFIO_EVCR_PORT_PA RCC_HSE_MIN DBGMCU_IDCODE_REV_ID_1 GPIO_CRL_MODE4 TIM_DIER_CC2IE_Pos EXTI_FTSR_TR8_Msk CAN_FM1R_FBM8_Pos RCC_CIR_PLLRDYC_Msk AFIO_EVCR_PIN_PX10_Msk I2C_OAR1_ADD0_Msk I2C_OAR1_ADD3 CAN_F7R1_FB7_Pos CAN_F8R1_FB16_Msk FLASH_USER_USER USB_COUNT0_TX_COUNT0_TX CAN_TDT1R_TIME_Pos EXTI_SWIER_SWIER2 USART_CR2_LINEN_Pos CAN_F2R1_FB10_Msk CAN_F1R1_FB9_Msk CAN_F10R2_FB13_Pos ADC_SQR1_SQ16_3 CAN_F13R1_FB23_Msk +syn keyword CTagsDefinedName CAN_F7R2_FB31_Pos USB_EP_ISOCHRONOUS DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT CAN_F10R1_FB11 USB_EP5R_EP_KIND CAN_F3R2_FB12_Pos CAN_BTR_TS2_0 CAN_F0R1_FB29_Msk CAN_FFA1R_FFA11_Msk EXTI_IMR_IM USB_EP_CTR_RX CAN_F12R1_FB31_Msk SDIO_STA_SDIOIT_Msk SPI_SR_CHSIDE_Msk ADC_SMPR2_SMP8_0 USB_EP2R_EP_TYPE_Msk IWDG_SR_RVU CAN_F8R1_FB29_Msk AFIO_MAPR_I2C1_REMAP_Msk DMA_IFCR_CHTIF6_Msk CAN_F9R2_FB22_Pos USB_COUNT5_RX_COUNT5_RX_Msk CAN_RF1R_FULL1_Pos DMA_ISR_TCIF4 CAN_F0R2_FB27_Pos +syn keyword CTagsDefinedName AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos CAN_F10R1_FB23_Pos I2C_SR1_TXE_Pos USB_ISTR_EP_ID_Msk CAN_F9R2_FB11_Msk TIM_SR_CC4IF_Pos IS_TIM_DMA_INSTANCE CAN_F9R2_FB13_Pos RCC_BDCR_LSEON_Pos WWDG_CFR_WDGTB_0 CAN_F13R2_FB30 CAN_F9R2_FB27 ADC_SMPR2_SMP9_1 AFIO_MAPR_USART3_REMAP_0 GPIO_CRH_CNF15_1 CAN_F13R1_FB11 EXTI1_IRQ_PRIORITY GPIO_BSRR_BR9 DBGMCU_CR_DBG_STOP CAN_F7R2_FB20_Msk SDIO_RESP0_CARDSTATUS0 USART_DR_DR EXTI_PR_PIF15 FLASH_USER_nUSER_Msk EXTI_IMR_IM13 PWR_CR_PVDE_Pos +syn keyword CTagsDefinedName EXTI_FTSR_TR5 CAN_F3R2_FB8 TIM_DIER_TDE_Pos CAN_F11R1_FB1_Msk ADC_SQR3_SQ6_0 CAN_F2R1_FB10 SDIO_STA_CMDREND CAN_TDT1R_TGT_Msk TIM_CCMR1_IC1PSC_0 USB_EP1R_STAT_TX_Pos USB CAN_F2R1_FB2 USART1_BASE SDIO_DCTRL_DMAEN_Pos DMA_ISR_GIF3 CAN_F9R2_FB8_Pos CAN_MSR_RX_Pos EXTI_FTSR_TR11_Msk WWDG_CR_T_2 SDIO_ICR_CMDSENTC_Pos CAN_F6R1_FB25_Pos USART_CR1_PEIE_Msk CAN_F5R1_FB15 EXTI_SWIER_SWIER14 USB_EP1R_STAT_RX_0 CAN_F11R2_FB26_Msk ADC_SMPR2_SMP9_2 USB_EP1R_CTR_TX CAN_F11R2_FB5_Msk +syn keyword CTagsDefinedName GPIO_BSRR_BR13_Msk CAN_F5R2_FB19_Pos CAN_F0R2_FB30_Msk CAN_F5R1_FB0_Msk CAN_F8R1_FB13 ADC_CR2_DMA TIM_CCMR2_IC4PSC_1 TIM_CR2_CCPC CAN_F3R1_FB24_Pos CAN_F11R1_FB6_Pos CRC_DR_DR_Msk __MPU_PRESENT GPIO_BRR_BR10 CAN_F4R1_FB20_Msk CAN_F12R2_FB21 CAN_F7R1_FB6 TIM1_UP_TIM10_IRQHandler CAN_F2R2_FB12_Pos EXTI_EMR_MR3_Msk USB_EP2R_STAT_RX_0 CAN_F2R2_FB13_Pos CAN_F9R1_FB12_Pos ADC1 RCC_CR_PLLRDY_Pos TIM_DCR_DBL_2 EXTI_EMR_MR7_Pos SDIO_ICR_CTIMEOUTC_Pos USB_ADDR0_TX_ADDR0_TX RCC_CFGR_MCO_0 +syn keyword CTagsDefinedName DMA_ISR_HTIF3_Msk USB_EP5R_STAT_TX CAN_F10R1_FB2 AFIO_EXTICR2_EXTI6_PF_Msk AFIO_EXTICR3_EXTI10_PC_Msk CAN_F7R2_FB4_Pos CAN_F12R1_FB28 CAN_F13R1_FB15_Pos CAN_F8R2_FB9_Msk CAN_F2R2_FB20_Pos CAN_F7R1_FB28_Pos CAN_TSR_ABRQ0 USB_EP_TX_DIS CAN_F13R1_FB8_Msk PIN_ALL SDIO_POWER_PWRCTRL TIM_CR2_OIS1N AFIO_EVCR_PIN_PX10 PWR_CSR_WUF_Msk CAN_F10R2_FB21_Msk CAN_F6R2_FB4 CAN_F12R2_FB6_Pos USB_DADDR_ADD3_Pos AFIO_EXTICR4_EXTI13_PD_Msk CAN_F7R2_FB7_Msk CAN_F9R1_FB13_Pos CAN_F6R1_FB7_Msk +syn keyword CTagsDefinedName AFIO_EVCR_PIN_PX13_Pos CAN_F12R2_FB20 CAN_F12R1_FB4_Msk ADC_SR_JEOS SPI_SR_CHSIDE_Pos DBGMCU_CR_DBG_TIM2_STOP_Pos ADC_CR1_JAUTO_Pos TIM_CR2_MMS_1 USB_EP7R_EA_Msk ADC_SQR3_SQ5 ADC_JSQR_JSQ1_Pos USB_EP1R_CTR_TX_Msk CAN_FM1R_FBM2 CAN_F1R2_FB30_Msk EXTI_SWIER_SWIER17_Pos CAN_F8R2_FB4_Msk CAN_F11R1_FB28_Msk CAN_RF1R_FULL1_Msk SDIO_STA_RXACT_Pos ADC_SQR2_SQ10_2 AFIO_EXTICR1_EXTI0_PD_Pos CAN_F13R2_FB6_Pos SDIO_MASK_TXDAVLIE_Msk DMA_IFCR_CTEIF3 GPIO_BSRR_BR2_Msk CAN_F6R2_FB26_Msk +syn keyword CTagsDefinedName CAN1_BASE SDIO_STA_CMDSENT_Msk ADC_SQR3_SQ2_4 CAN_F4R2_FB6_Pos EXTI_RTSR_RT2 TIM_CCMR2_OC4CE_Msk CAN_F11R2_FB24_Msk CAN_F9R2_FB26_Pos CAN_F11R1_FB12_Msk EXTI_EMR_MR0_Pos FLASH_OBR_IWDG_SW_Pos IS_TIM_COUNTER_MODE_SELECT_INSTANCE USB_EP6R_CTR_TX_Msk CAN_F1R2_FB26_Msk RCC_CFGR_PLLMULL10 WWDG_CR_T_1 EXTI_EMR_EM3 CAN_F8R2_FB12_Pos EXTI_RTSR_RT11 AFIO_EVCR_PIN_PX6_Msk SPI_CR1_SSM_Msk CAN_F1R2_FB15_Pos USB_COUNT0_RX_1_NUM_BLOCK_1 CAN_F12R2_FB28_Msk CAN_F7R1_FB29 +syn keyword CTagsDefinedName USB_COUNT7_RX_BLSIZE_Pos CAN_F10R1_FB7 CAN_F2R2_FB7_Pos CAN_F13R1_FB24_Msk EXTI_IMR_MR11_Pos CAN_RDT0R_TIME CAN_F5R2_FB14_Msk IS_TIM_REPETITION_COUNTER_INSTANCE EXTI_FTSR_TR18_Msk CAN_F2R1_FB24 ADC_HTR_HT_Pos USB_EP4R_STAT_TX_0 CAN_F3R2_FB17_Pos CAN_F6R2_FB16_Msk USB_COUNT4_TX_COUNT4_TX_Pos CAN_F8R2_FB9_Pos TIM_SR_COMIF_Msk RCC_CFGR_ADCPRE_DIV8 USB_COUNT7_RX_NUM_BLOCK_0 USB_DADDR_ADD4_Msk GPIO_CRL_MODE7_1 I2C_SR2_MSL_Msk CAN_F0R1_FB11_Pos EXTI_SWIER_SWIER8 CAN_F0R2_FB11 +syn keyword CTagsDefinedName CAN_F10R1_FB29_Msk CAN_F10R1_FB4_Msk TIM_CR2_OIS3_Msk IS_SMBUS_ALL_INSTANCE GPIO_BSRR_BR0_Msk CAN_IER_FMPIE1_Msk CAN_F11R1_FB16_Pos CAN_F3R1_FB22_Pos CAN_RI0R_EXID FLASH_CR_EOPIE SPI_CR1_SPE_Msk EXTI_EMR_EM1 DMA_IFCR_CTCIF6 AFIO_EXTICR3_EXTI10_PD_Msk ADC_SMPR1_SMP13 CAN_TDH0R_DATA6_Msk AFIO_EXTICR1_EXTI3_Msk RCC_CFGR_PLLMULL15_Msk CAN_F13R1_FB18 EXTI_PR_PIF18 FLASH_DATA1_DATA1_Pos CAN_F3R2_FB12_Msk GPIO_CRH_MODE15_Msk CAN_F13R2_FB29 CAN_F7R1_FB10_Pos CAN_F11R1_FB1 CAN_F8R1_FB4 +syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP_Pos CAN_FM1R_FBM4_Msk CAN_F4R1_FB13_Msk GPIO_CRL_CNF7 GPIO_ODR_ODR12 TIM_CR1_CKD_0 CAN_MCR_INRQ_Msk SDIO_STA_TXFIFOE_Msk TIM_CCER_CC2NE_Pos GPIO_ODR_ODR0_Msk EXTI_FTSR_TR6_Msk RCC_APB2ENR_ADC1EN GPIO_BRR_BR4 CAN_F5R2_FB12_Pos RCC_BDCR_LSEBYP ADC_CR2_CONT_Pos SDIO CAN_F2R2_FB21_Msk CAN_F8R1_FB28_Pos CAN_F5R2_FB10_Msk CAN_F7R2_FB25_Msk AFIO_MAPR_CAN_REMAP_REMAP2_Pos EXTI_RTSR_TR9_Msk CAN_F5R2_FB1 USB_COUNT4_RX_NUM_BLOCK_4 CAN_F11R1_FB12 CAN_F13R1_FB27_Pos +syn keyword CTagsDefinedName CAN_F6R1_FB1 CAN_MSR_TXM_Msk FLASH_CR_OPTPG_Pos EXTI_EMR_EM2 CAN_F1R1_FB7_Pos GPIO_CRL_CNF_Pos EXTI_FTSR_TR15_Pos ADC_CR1_AWDCH_4 GPIO_CRL_MODE0_Pos CAN_IER_FFIE1 PWR_CR_PLS_LEV2 RCC_CFGR_PPRE1_DIV4 CAN_F7R1_FB25_Msk USB_FNR_FN_Pos CAN_F12R1_FB23 USART_CR1_M_Msk AFIO_EVCR_PIN_PX12 CAN_F12R1_FB9_Pos USB_COUNT0_TX_COUNT0_TX_Pos CAN_FS1R_FSC3_Msk CAN_F3R1_FB7_Msk CAN_F0R2_FB17_Msk RCC_CIR_LSIRDYF_Msk CAN_F1R2_FB23_Msk GPIO_IDR_IDR6_Pos EXTI_FTSR_FT15 CAN_F3R1_FB24_Msk +syn keyword CTagsDefinedName ADC_SQR1_SQ15_3 CAN_F13R1_FB5 RCC_CFGR_PLLMULL5_Pos RCC_CR_HSITRIM DMA_CCR_PL_Msk CAN_F11R1_FB2_Pos ADC_SMPR1_SMP16_1 PIN_OPT_AF9 I2C_OAR1_ADDMODE_Msk CAN_ESR_LEC_0 TIM_CR1_OPM RCC_CFGR_PPRE1_DIV16 RCC_CFGR_HPRE_DIV_16 USART_GTPR_PSC_1 USB_EP2R_SETUP_Msk AFIO_EXTICR3_EXTI8_PF_Pos ADC1_IRQHandler CAN_F2R2_FB17_Pos FLASH_WRP1_nWRP1_Pos CAN_RDH0R_DATA6_Pos AFIO_EXTICR3_EXTI11_PB_Msk CAN_FS1R_FSC11 CAN_F11R2_FB7_Pos SPI_CR2_SSOE_Pos GPIO_CRL_CNF7_1 USB_EP0R_EA +syn keyword CTagsDefinedName DBGMCU_CR_DBG_TIM3_STOP_Msk CAN_F6R1_FB1_Msk RTC_DIVL_RTC_DIV ADC_JSQR_JSQ2_1 CAN_F13R1_FB3 CAN_F13R2_FB4 CAN_F10R2_FB18_Msk CAN_F5R2_FB4 DBGMCU_CR_DBG_TIM3_STOP CAN_F9R2_FB16_Msk CAN_F4R2_FB1 CAN_F4R2_FB23_Msk USB_COUNT4_RX_COUNT4_RX TIM_RCR_REP GPIO_BSRR_BR7_Pos GPIO_CRH_CNF15 EXTI_SWIER_SWIER8_Pos CAN_F10R2_FB28 CAN_F3R2_FB6_Pos CAN_F1R2_FB21_Msk DMA_IFCR_CTCIF7_Msk CAN_F7R1_FB28 ADC_SQR2_SQ7_0 CAN_RF0R_RFOM0 GPIO_CRH_CNF10_1 CAN_F5R2_FB7 EXTI_SWIER_SWI4 +syn keyword CTagsDefinedName SDIO_CLKCR_HWFC_EN_Pos CAN_F0R1_FB10_Msk CAN_F1R2_FB2_Pos CAN_F1R1_FB0_Pos USB_DADDR_EF_Msk ADC_JSQR_JSQ2_2 CAN_F10R2_FB25_Msk USB_EP1R_STAT_TX_Msk CAN_TDT0R_DLC GPIO_BRR_BR5_Pos CAN_F0R2_FB12 EXTI_RTSR_TR16_Msk FLASH_WRP3_nWRP3 IS_UART_DMA_INSTANCE USB_COUNT1_RX_1_NUM_BLOCK_1 USB_COUNT6_RX_0_COUNT6_RX_0 USB_COUNT5_RX_BLSIZE USART_CR3_CTSE_Msk USB_EP2R_EP_KIND_Pos EXTI_EMR_MR12_Pos CAN_F8R1_FB3_Pos ADC_JSQR_JSQ1_2 CAN_F10R2_FB27_Pos EXTI_EMR_EM10 EXTI_SWIER_SWIER7 +syn keyword CTagsDefinedName SDIO_ICR_CMDRENDC_Msk I2C_SR2_GENCALL_Pos CAN_F6R1_FB7 CAN_IER_EWGIE AFIO_MAPR_TIM1_REMAP_Pos DMA_IFCR_CTCIF1_Pos ADC_JSQR_JSQ1_Msk CAN_F0R2_FB2 I2C_CR1_ENARP_Msk TIM_CR1_OPM_Msk USB_ADDR6_RX_ADDR6_RX_Pos CAN_F2R1_FB29_Msk EXTI_EMR_MR3_Pos EXTI_PR_PIF3 FLASH_CR_ERRIE_Pos CAN_F10R1_FB17_Msk CAN_F7R1_FB0 CAN_MCR_TXFP USB_EP3R_STAT_RX_Msk CAN_F2R2_FB4_Pos CAN_F4R2_FB16_Pos CAN_TDH2R_DATA5 EXTI3_IRQ_PRIORITY USB_EP0R_CTR_TX_Msk USB_EP7R_STAT_TX_0 AFIO_EXTICR1_EXTI1_PB_Msk +syn keyword CTagsDefinedName CAN_F5R1_FB17_Pos DMA_ISR_GIF6 TIM_CCR1_CCR1 ADC_CR2_RSTCAL_Msk CAN_FA1R_FACT11_Msk RCC_CFGR_HPRE_DIV_512 EXTI_IMR_MR8 ADC_CR1_EOSIE_Pos CAN_F8R2_FB5_Pos CAN_FA1R_FACT2 GPIO_BRR_BR1 CAN_F5R1_FB10_Pos RCC_APB1ENR_I2C1EN_Pos CAN_F8R2_FB24_Msk ADC_JSQR_JSQ1 FLASH_OBR_RDPRT_Pos CAN_F7R1_FB3 GPIO_CRL_CNF AFIO_EXTICR4_EXTI14_PB CAN_F10R1_FB30_Pos USB_COUNT7_RX_COUNT7_RX USB_CNTR_FSUSP_Msk CAN_F12R2_FB19_Pos RCC_CSR_SFTRSTF FLASH_OBR_RDPRT_Msk AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk +syn keyword CTagsDefinedName USB_COUNT6_RX_1_NUM_BLOCK_1 AFIO_EVCR_PORT_PC_Pos USB_COUNT4_RX_BLSIZE_Pos USB_EP6R_CTR_RX_Pos USB_EP6R_STAT_TX AFIO_MAPR_TIM1_REMAP_NOREMAP CAN_F4R1_FB29_Pos FLASH_OBR_RDPRT GPIO_LCKR_LCK12 CAN_F1R1_FB23_Msk USART_CR2_LBDIE CAN_F10R1_FB14_Pos WWDG_CFR_WDGTB CAN_F13R2_FB23 TIM_CR2_MMS_0 __Vendor_SysTickConfig EXTI_EMR_MR15 DMA_CCR_PSIZE_0 GPIO_CRH_MODE14 CAN_F12R1_FB11 CAN_RI1R_EXID_Msk GPIO_LCKR_LCK5_Pos CAN_FS1R_FSC_Pos WWDG_CR_WDGA_Pos CAN_F9R2_FB7_Pos CAN_F6R2_FB5 +syn keyword CTagsDefinedName DBGMCU_BASE GPIO_IDR_IDR0_Msk CAN_F5R2_FB17 CAN_F6R2_FB30_Msk EXTI_SWIER_SWIER1_Msk ADC_SR_JEOC DMA_ISR_GIF3_Msk RCC_CSR_PORRSTF_Pos AFIO_EXTICR3_EXTI10_Pos CAN_F11R1_FB16_Msk ADC_JSQR_JSQ4_4 CAN_F7R2_FB15 CAN_F13R1_FB13 CAN_F11R1_FB3_Pos CAN_F5R2_FB31_Msk RCC_APB1ENR_USART2EN_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_1 CAN_FMR_CAN2SB_Pos CAN_F1R2_FB11_Msk CAN_F13R1_FB16 CAN_F1R2_FB29 USART_CR2_STOP_1 CAN_F0R1_FB0_Pos I2C2 I2C_SR2_SMBDEFAULT_Pos AFIO_EXTICR1_EXTI0_Msk CAN_F4R1_FB17_Pos +syn keyword CTagsDefinedName DMA_ISR_GIF4 DMA1_BASE CAN_F7R2_FB28_Pos TIM_CCMR1_OC1M_Msk CAN_F2R2_FB27_Pos USB_EP5R_CTR_RX_Msk USB_EP4R_CTR_RX_Msk I2C_OAR1_ADD9_Pos CAN_F2R2_FB20 GPIO_IDR_IDR3_Pos SDIO_CLKCR_CLKEN CAN_F0R1_FB27_Msk USART_CR1_RXNEIE CAN_F6R2_FB27 CAN_F11R2_FB29_Pos RCC_APB1ENR_I2C2EN_Pos SDIO_CLKCR_CLKDIV_Pos AFIO_EXTICR1_EXTI3_PD CAN_F2R1_FB5_Pos CAN_F1R2_FB17_Pos CAN_F13R2_FB11_Msk EXTI_IMR_MR0_Msk ADC_JOFR4_JOFFSET4 CAN_BTR_TS2_1 ADC_JOFR3_JOFFSET3_Msk USB_ISTR_EP_ID USB_CNTR_RESETM_Pos +syn keyword CTagsDefinedName USB_EP4R_CTR_TX_Msk CAN_F9R2_FB27_Pos CAN_F5R2_FB18 CAN_F11R1_FB5 CAN_F1R2_FB12 CAN_F5R1_FB1 CAN_F5R1_FB5_Msk CAN_F10R2_FB15_Pos CAN_F11R1_FB11 CAN_F7R2_FB1 AFIO_EXTICR4_EXTI14_PB_Pos CAN_MSR_WKUI SDIO_STA_CTIMEOUT RCC_CFGR_PLLMULL_3 USB_COUNT3_RX_1_NUM_BLOCK_1_0 AFIO_EVCR_PORT_PE_Pos CAN_F6R2_FB15_Msk USB_COUNT2_RX_0_NUM_BLOCK_0_2 USB_EP3R_DTOG_RX AFIO_MAPR_TIM2_REMAP_Pos AFIO_EVCR_PIN_PX14_Pos SDIO_STA_RXDAVL CAN_F1R1_FB12_Pos GPIO_BRR_BR14_Msk CAN_F8R2_FB27_Msk +syn keyword CTagsDefinedName CAN_F4R2_FB1_Msk CAN_FA1R_FACT2_Pos GPIO_CRH_MODE10_Msk EXTI_IMR_MR7_Pos AFIO_EXTICR3_EXTI10_PE FLASH_CR_MER_Msk AFIO_EXTICR3_EXTI8_PD CAN_FA1R_FACT3 CAN_F0R2_FB13 CAN_F8R2_FB13_Msk FLASH_AR_FAR_Pos RCC_CIR_HSERDYF_Msk RTC_CRL_RTOFF I2C_SR2_GENCALL TIM_CCER_CC3E_Msk AFIO_EVCR_PIN_PX5 GPIO_LCKR_LCK8_Pos CAN_F2R2_FB29 WWDG_CR_WDGA_Msk CAN_F1R1_FB4_Pos CAN_IER_BOFIE_Pos GPIOC_BASE CAN_F2R2_FB9_Msk ADC_SQR2_SQ9_Pos USB_EP2R_SETUP CAN_F0R2_FB0_Pos AFIO_EVCR_PIN_PX10_Pos +syn keyword CTagsDefinedName CAN_F13R1_FB17 USB_EP1R_EA_Msk USB_COUNT2_RX_1_COUNT2_RX_1 SDIO_CMD_WAITINT_Pos CAN_F13R2_FB22_Pos ADC2_BASE AFIO_EXTICR2_EXTI6_PD_Pos TIM_CCMR2_OC4M_Pos WWDG_CR_T6 BKP_CR_TPAL_Msk FLASH_KEY2 ADC_SQR1_SQ13_1 CAN_F12R2_FB13_Msk TIM_CCMR1_IC2F RCC_APB1RSTR_CAN1RST FLASH_SR_BSY_Pos CAN_F4R2_FB8_Pos CAN_F10R2_FB18 I2C_CR2_DMAEN_Msk SPI_CR1_BIDIOE CAN_F5R2_FB24_Msk USB_COUNT2_TX_0_COUNT2_TX_0 SDIO_ICR_CCRCFAILC_Pos ADC_JSQR_JSQ2_Msk AFIO_MAPR_TIM1_REMAP_Msk CAN_F0R1_FB31_Pos +syn keyword CTagsDefinedName DMA_IFCR_CHTIF4_Msk FLASH_WRPR_WRP_Msk SDIO_STA_RXFIFOE ADC_SQR2_SQ11_3 CAN_F0R1_FB3_Msk ADC_SMPR1_SMP14_Pos USB_DADDR_ADD4_Pos RCC_CIR_HSERDYF CAN_TSR_LOW1_Pos GPIO_CRL_MODE3_0 USB_EP7R_STAT_RX_Pos CAN_F4R2_FB15_Msk CAN_F13R2_FB2 CAN_F5R2_FB9_Pos USB_EP2R_STAT_TX_1 PIN_12 USART_CR2_CPHA_Pos CAN_F10R1_FB7_Pos CAN_F5R1_FB26_Msk TIM_CCMR2_IC4F CAN_F10R2_FB19_Pos CAN_F10R2_FB7 CAN_F7R2_FB13_Msk USB_ISTR_WKUP CAN_F9R2_FB29 EXTI_EMR_MR8 GPIO_CRL_CNF1_Msk ADC_SQR1_L_Pos +syn keyword CTagsDefinedName FLASH_WRP2_nWRP2_Msk SDIO_CLKCR_BYPASS FLASH_USER_USER_Pos CAN_F2R2_FB19_Pos CAN_F13R1_FB27_Msk CAN_F4R2_FB14_Pos GPIO_BSRR_BS13_Pos GPIO_ODR_ODR7_Pos DBGMCU_IDCODE_REV_ID TIM1_BRK_TIM9_IRQn CAN_F5R2_FB26 I2C_SR2_SMBDEFAULT USB_ADDR5_RX_ADDR5_RX_Pos CAN_FM1R_FBM13_Pos CAN_F9R2_FB18_Pos CAN_F0R2_FB30_Pos SDIO_MASK_TXACTIE_Msk TIM_BDTR_MOE_Pos CAN_F11R2_FB29_Msk BKP_DR8_D CAN_IER_WKUIE_Msk ADC_CR1_AWDEN PIN_OPT_AF11 SDIO_MASK_RXFIFOFIE_Pos CAN_F1R2_FB5_Msk CAN_F6R1_FB19_Msk +syn keyword CTagsDefinedName ADC_SQR1_SQ14_4 DMA_CCR_MEM2MEM I2C_CR2_ITEVTEN_Pos ADC_SQR1_SQ16_Msk RCC_CIR_PLLRDYIE_Pos CAN_F11R2_FB14 AFIO_MAPR_USART3_REMAP_FULLREMAP CAN_F11R2_FB30_Pos FLASH_USER_nUSER USB_COUNT6_RX_0_NUM_BLOCK_0_4 EXTI_SWIER_SWIER13 CAN_F3R1_FB28_Msk GPIO_LCKR_LCK11 ADC_JSQR_JSQ4_3 CAN_F5R1_FB14_Pos CAN_F3R2_FB17_Msk USB_EP4R_EP_KIND_Pos CAN_F12R2_FB14_Pos CAN_F2R1_FB9 USB_EP7R_STAT_TX USB_BASE RCC_CIR_HSERDYF_Pos CAN_F13R2_FB20_Pos CAN_RDT0R_DLC_Pos SDIO_STA_TXFIFOE CAN_F10R2_FB14_Pos +syn keyword CTagsDefinedName CAN_F1R2_FB4 TIM_SMCR_TS_Pos TIM_CCMR2_CC3S_Pos CAN_F0R2_FB10_Msk CAN_F12R1_FB15_Msk SDIO_MASK_TXFIFOEIE_Pos CAN_FM1R_FBM3_Pos TIM_CR1_URS CAN_F12R1_FB21 TIM_CR2_MMS_Pos CAN_FM1R_FBM6_Pos DMA_IFCR_CGIF7_Pos RTC_DIVH_RTC_DIV_Msk CAN_FM1R_FBM_Msk TIM_SR_CC1OF_Pos CAN_FS1R_FSC_Msk CAN_F11R1_FB28_Pos GPIO_ODR_ODR14 SDIO_DCTRL_DBLOCKSIZE_3 AFIO_EXTICR2_EXTI4 CAN_F4R1_FB25_Pos SDIO_STA_TXFIFOHE_Pos GPIO_CRL_CNF3_1 TIM_SR_CC3OF TIM_CCMR2_CC3S CAN_F13R1_FB9_Pos I2C_CR1_PE_Msk +syn keyword CTagsDefinedName RCC_APB1RSTR_BKPRST TIM_DCR_DBL_Pos CAN_F8R1_FB11_Pos CAN_F6R1_FB9_Msk CAN_F3R2_FB24_Msk I2C_SR1_SMBALERT_Pos CAN_F13R2_FB3_Pos CAN_F9R1_FB7_Pos USB_CNTR_FSUSP CAN_TDH1R_DATA5_Pos CAN_F8R1_FB7 TIM_RCR_REP_Msk CAN_TI1R_EXID USB_COUNT3_RX_0_NUM_BLOCK_0_1 CAN_F12R1_FB18_Msk CAN_F5R2_FB20_Msk SDIO_MASK_RXFIFOEIE_Pos CAN_F3R1_FB15_Pos TIM_SMCR_ETPS_1 RCC_APB2ENR_TIM1EN_Pos CAN_F13R1_FB12_Msk CAN_F13R2_FB16_Pos CAN_F11R2_FB30_Msk CAN_F2R2_FB8_Pos AFIO_EXTICR3_EXTI9_PB_Pos +syn keyword CTagsDefinedName CAN_F0R2_FB11_Msk CAN_F5R2_FB1_Msk CAN_F7R2_FB28 I2C_OAR1_ADD4_Pos I2C_SR2_BUSY USB_COUNT1_TX_COUNT1_TX ADC_JDR2_JDATA CAN_F13R1_FB12_Pos RCC_CSR_LSIRDY_Pos CAN_F1R1_FB7_Msk TIM_CCMR1_OC1CE USB_COUNT1_RX_NUM_BLOCK_1 CAN_F1R1_FB0_Msk USB_EP6R_EP_TYPE_Msk RCC_CSR_IWDGRSTF_Msk SDIO_MASK_RXOVERRIE_Pos CAN_F7R1_FB9_Pos CAN_F7R2_FB6_Pos CAN_F1R2_FB3 SDIO_ICR_RXOVERRC USB_COUNT5_RX_0_BLSIZE_0 RCC_CFGR_PLLXTPRE_HSE_DIV2 SDIO_CMD_CMDINDEX WWDG_CFR_WDGTB1 ADC_CR1_JEOSIE_Msk CAN_F6R1_FB23 +syn keyword CTagsDefinedName CAN_MCR_RFLM_Pos AFIO_EXTICR3_EXTI11_Msk AFIO_EXTICR3_EXTI11_PA GPIO_CRH_CNF12_1 CAN_F8R1_FB24 CAN_F9R1_FB2 CAN_F7R1_FB0_Pos CAN_F1R1_FB18_Pos RCC_APB2RSTR_IOPCRST_Msk USB_EP4R_EP_TYPE CAN_F1R2_FB8_Pos CAN_F11R2_FB23 CAN_F6R1_FB18 WWDG_CR_T4 CAN_F9R2_FB5 ADC_SMPR1_SMP10_1 EXTI_PR_PIF9 IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE USART_SR_CTS CAN_FA1R_FACT12_Msk CAN_F12R1_FB18_Pos CAN_RDH0R_DATA7_Msk RCC_CFGR_PLLMULL7_Pos CAN_F4R1_FB2_Pos CAN_RDH0R_DATA6_Msk CAN_F13R1_FB28_Pos +syn keyword CTagsDefinedName CAN_F3R1_FB22_Msk TIM_DIER_COMDE_Msk AFIO_EVCR_PORT_2 SDIO_STA_TXFIFOHE GPIO_IDR_IDR13_Msk SDIO_MASK_DCRCFAILIE_Pos CAN_F11R1_FB9 CAN_F12R1_FB7_Pos GPIO_CRH_MODE12_Pos USB_EP2R_DTOG_TX_Pos GPIO_ODR_ODR5 USB_EP3R_STAT_RX CAN_F2R1_FB1_Pos TIM_SMCR_ETF_Msk USB_COUNT1_RX_NUM_BLOCK_2 GPIO_CRL_MODE_Pos SDIO_ICR_DTIMEOUTC CAN_F3R2_FB5_Pos EXTI_IMR_MR18 CAN_F6R2_FB1_Msk DMA_ISR_GIF2 RCC_CFGR_SWS_0 AFIO_MAPR_TIM3_REMAP_0 CAN_MCR_AWUM_Msk CAN_F1R2_FB6_Msk CAN_F11R2_FB14_Msk CAN_F4R2_FB28 +syn keyword CTagsDefinedName USB_EP5R_EA_Msk CAN_TI0R_TXRQ AFIO_EXTICR4_EXTI15 CAN_F13R2_FB17_Msk ADC_SMPR2_SMP5_0 CAN_F4R2_FB25 GPIO_CRL_CNF6 ADC_SQR3_SQ5_4 EXTI_IMR_IM10 USART_CR2_LBDL_Msk CAN_F8R1_FB19_Msk USB_EP_DTOG_TX_Msk CAN_F5R2_FB25_Msk CAN_F8R2_FB18 SPI_CR2_RXDMAEN_Pos EXTI_EMR_MR7_Msk USB_COUNT2_RX_NUM_BLOCK_Msk AFIO_EXTICR3_EXTI10_PE_Msk DMA_ISR_TEIF2_Pos WWDG_CFR_W_2 CAN_F6R1_FB2_Pos CAN_F1R2_FB28_Pos CAN_F10R2_FB19 CAN_BTR_SJW_1 CAN_F13R1_FB26 CAN_F4R2_FB9_Pos AFIO_EXTICR3_EXTI9_PG_Msk +syn keyword CTagsDefinedName SPI_SR_MODF DBGMCU_IDCODE_REV_ID_4 RCC_CFGR_PLLMULL12_Msk CAN_F3R1_FB12_Pos EXTI_IMR_MR2 GPIO_BSRR_BR1 CAN_BTR_SILM_Pos USB_EP_CTR_TX_Pos USB_EP4R_CTR_RX CAN_F4R1_FB5_Msk AFIO_EVCR_PIN_PX15 CAN_F0R1_FB1_Pos GPIO_CRL_MODE7_0 CAN_IER_SLKIE_Pos CAN_ESR_LEC I2C_SR1_TIMEOUT_Pos I2C_CR2_DMAEN CAN_F2R1_FB27 EXTI_RTSR_TR9 CAN_F4R1_FB6_Pos TIM_DIER_CC1DE_Msk USB_EP2R_EP_TYPE_Pos USB_EP3R_EA USB_EP4R_STAT_RX_0 CAN_F4R1_FB3 TIM_CCMR2_CC4S_1 EXTI_EMR_MR14_Pos TIM_SMCR_TS_Msk CAN_ESR_TEC +syn keyword CTagsDefinedName CAN_F7R1_FB14_Pos USB_COUNT2_RX_0_NUM_BLOCK_0 CAN_F2R1_FB21 EXTI_EMR_MR4_Msk CAN_F1R1_FB28_Msk AFIO_EXTICR4_EXTI13_PC RCC_CFGR_PLLMULL_1 CAN_F2R2_FB13_Msk FLASH_WRP0_nWRP0 CAN_F2R1_FB0 CAN_MCR_ABOM_Msk CAN_F5R1_FB16_Pos TIM_CCER_CC1NE CAN_TDH1R_DATA5_Msk GPIO_BSRR_BR4 CAN_F0R1_FB6 CAN_FM1R_FBM9_Msk SDIO_STA_TXFIFOF ADC_SR_JSTRT_Pos CAN_F7R2_FB17 USB_EP2R_DTOG_TX_Msk CAN_F9R2_FB29_Msk AFIO_EXTICR2_EXTI4_PF CAN_F7R1_FB4_Pos CAN_F8R1_FB15_Msk USB_EP_TX_VALID CAN_F0R2_FB3_Pos +syn keyword CTagsDefinedName CAN_F9R1_FB26 DMA_CPAR_PA_Pos CAN_F5R2_FB16_Pos TIM_CCER_CC4E_Msk RTC_CRL_RSF_Pos RCC_CFGR_PLLXTPRE_Msk PIN_OPT_OUTPUT_OPENDRAIN CAN_F8R2_FB10_Pos GPIO_CRH_MODE11_0 USB_COUNT0_RX_BLSIZE CAN_F0R1_FB10 USART_CR3_RTSE_Pos USB_EP0R_STAT_TX_1 RCC_CFGR_SW_0 CAN_F0R1_FB9_Msk USB_COUNT3_RX_BLSIZE_Msk USB_COUNT2_RX_1_BLSIZE_1 CAN_TSR_LOW_Pos CAN_F2R2_FB22_Pos CAN_F4R1_FB24_Pos CAN_F7R2_FB0_Pos ADC_SMPR2_SMP0_0 CAN_F8R1_FB26_Msk CAN_BTR_TS1 CAN_FS1R_FSC6_Pos CAN_F6R2_FB20_Msk +syn keyword CTagsDefinedName CAN_F3R2_FB2_Msk CAN_F4R1_FB16_Msk CAN_F12R2_FB11_Msk CAN_F11R2_FB17_Pos CAN_F8R2_FB22 CAN_F9R1_FB25_Msk USB_EP5R_DTOG_TX_Pos GPIO_BSRR_BS8 USB_CNTR_SUSPM_Pos DMA_ISR_GIF1_Pos ADC_SQR2_SQ11_2 CAN_RI1R_IDE CAN_F11R1_FB26 USB_ISTR_SOF_Pos USB_ADDR4_RX_ADDR4_RX_Msk CAN_F11R2_FB6 CAN_F8R2_FB12 SPI_CR1_SPE GPIO_LCKR_LCK13 CAN_F13R2_FB7_Pos RCC_CFGR_PLLMULL7 ADC_SQR3_SQ3 USB_EP_TYPE_MASK_Msk AFIO_EXTICR4_EXTI15_PG_Msk CAN_F6R1_FB3_Msk CAN_TDL1R_DATA0_Pos ADC_SQR3_SQ3_4 +syn keyword CTagsDefinedName CAN_F0R2_FB1_Pos USB_BTABLE_BTABLE CAN_F7R2_FB4_Msk __STM32F1XX_H TIM_SMCR_SMS_Pos CAN_F0R1_FB20_Msk AFIO_EXTICR2_EXTI6_PD CAN_TSR_ALST1 AFIO_MAPR_TIM1_REMAP CAN_F7R2_FB31 CAN_IER_WKUIE CAN_F9R2_FB23_Pos IS_UART_LIN_INSTANCE ADC_JSQR_JSQ2_0 CAN_F10R1_FB29_Pos CAN_F13R2_FB12_Pos I2C_SR1_ADDR_Pos RCC_CFGR_ADCPRE_DIV6 USB_COUNT4_RX_0_NUM_BLOCK_0 CAN_F0R2_FB14_Msk CAN_F7R2_FB11_Msk CAN_TDH0R_DATA7 RCC_CFGR_PLLMULL12_Pos CAN_F13R1_FB16_Pos CAN_F5R1_FB27_Msk I2C_CCR_FS +syn keyword CTagsDefinedName DMA_IFCR_CTEIF4_Pos ADC_SMPR1_SMP11_Msk RCC_CFGR_PPRE2_1 RCC_APB1RSTR_USART3RST_Msk AFIO_EXTICR1_EXTI2_PB EXTI4_IRQ_PRIORITY DMA_IFCR_CTCIF7_Pos CAN_F4R2_FB0_Msk CAN_F7R2_FB14_Pos RTC_CRH_SECIE_Msk USART_CR1_UE CAN_F5R1_FB8 WWDG_CR_T_0 SDIO_CMD_WAITPEND_Msk AFIO_EXTICR3_EXTI8_PC_Pos EXTI_RTSR_RT18 EXTI_SWIER_SWIER17 CAN_F6R2_FB3_Msk GPIO_CRL_CNF5_0 EXTI_EMR_EM12 CAN_F0R2_FB29_Msk RCC_CFGR_HPRE_DIV_4 USB_LP_IRQHandler I2C_CR2_ITERREN_Pos CAN_FFA1R_FFA10_Pos CAN_F0R2_FB9_Msk +syn keyword CTagsDefinedName ADC_SQR2_SQ9_4 USB_COUNT6_RX_0_NUM_BLOCK_0_2 USB_EP0R_CTR_TX GPIO_CRH_MODE14_Msk CAN_F13R1_FB0_Pos CAN_F11R2_FB11 CAN_F9R2_FB23 USART_SR_NE_Pos CAN_F10R1_FB28_Msk CAN_F10R1_FB16_Msk GPIO_BRR_BR2 CAN_F3R1_FB2_Msk RCC_APB2ENR_TIM1EN SDIO_DCTRL_DTEN_Msk USB_EP5R_SETUP_Msk TIM_BDTR_BKP_Pos EXTI_RTSR_TR8_Pos TIM_SMCR_ETF_Pos USART_GTPR_PSC_Pos CAN_F13R1_FB17_Msk BKP_DR10_D CAN_RI1R_STID_Msk CAN_F10R2_FB1_Msk AFIO_EVCR_PIN_PX15_Msk TIM_DCR_DBA CRC_IDR_IDR_Msk CAN_FS1R_FSC6 +syn keyword CTagsDefinedName USART_SR_RXNE_Pos CAN_F8R2_FB26_Pos SDIO_MASK_SDIOITIE USB_EP4R_EP_TYPE_0 GPIO_CRL_MODE1_Pos CAN_F10R2_FB12_Pos BKP_DR4_D_Msk CAN_F0R2_FB0 EXTI_FTSR_TR3 CAN_F13R2_FB5_Msk CAN_FFA1R_FFA3_Msk USB_EP6R_EP_KIND_Pos CAN_F10R1_FB25 SPI_CR2_ERRIE_Pos CAN_F0R1_FB25 CAN_F7R2_FB5_Msk CAN_TSR_TERR2 EXTI_RTSR_TR3 CAN_F7R2_FB23 ADC_SR_STRT DMA_CCR_PSIZE_Msk DMA_IFCR_CHTIF2_Msk SPI_CR2_TXDMAEN SDIO_DCTRL_DMAEN RCC_APB2ENR_ADC2EN_Msk CAN_F2R2_FB11 AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos +syn keyword CTagsDefinedName CAN_F8R1_FB13_Pos RCC_APB1ENR_USART2EN_Pos RCC_CSR_IWDGRSTF AFIO_EXTICR1_EXTI1_Msk CAN_F3R1_FB14_Msk FLASH_WRP2_WRP2 USB_EP2R_EP_TYPE_1 CAN_F12R1_FB30 FLASH_CR_OPTWRE_Pos CAN_F12R1_FB22_Msk USB_EP6R_STAT_RX_Pos USB_COUNT6_RX_1_NUM_BLOCK_1_2 SDIO_ICR_CEATAENDC PIN_OPT_AF12 CAN_F1R1_FB24 CAN_F1R1_FB23 EXTI_PR_PR1_Msk DMA_CPAR_PA TIM_SR_CC2OF CAN_F7R2_FB7_Pos CAN_F7R2_FB15_Msk CAN_IER_ERRIE_Pos GPIO_IDR_IDR14_Msk SDIO_CLKCR_CLKEN_Msk SDIO_ICR_DCRCFAILC_Pos CAN_F1R1_FB2_Pos +syn keyword CTagsDefinedName CAN_F1R1_FB5_Pos DMA_ISR_TCIF6_Msk TIM_BDTR_LOCK_0 USB_EP1R_EP_KIND USB_COUNT5_TX_COUNT5_TX_Msk CAN_F6R1_FB30 CRC_DR_DR CAN_F7R2_FB18_Msk AFIO_EXTICR4_EXTI15_PD_Msk CAN_F4R1_FB13 ADC_JDR3_JDATA_Pos CAN_F12R2_FB27_Msk USB_COUNT1_RX_1_NUM_BLOCK_1_3 CAN_F10R1_FB5_Pos AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos IS_TIM_BREAK_INSTANCE FLASH_CR_OPTER_Pos CAN_F6R2_FB10_Pos CAN_FM1R_FBM5_Msk RCC_APB1ENR_USBEN_Msk USB_EP_DTOG_TX_Pos TIM_CR2_MMS_2 DMA_ISR_TCIF1 CAN_F3R1_FB3 AFIO_EVCR_PIN_2 +syn keyword CTagsDefinedName CAN_F2R2_FB5 CAN_F6R2_FB26_Pos CAN_F13R2_FB28_Pos I2C_OAR1_ADD5 DBGMCU_CR_DBG_CAN1_STOP GPIO_ODR_ODR6_Pos CAN_F9R1_FB1 DMA1_Channel3_BASE AFIO_EXTICR2_EXTI7 CAN_F13R2_FB10 CAN_FFA1R_FFA2_Pos FLASH_CR_EOPIE_Msk CAN_RDL1R_DATA1_Pos CAN_F5R2_FB27 ADC_JOFR4_JOFFSET4_Msk CAN_F3R2_FB9_Msk CAN_F0R2_FB31_Msk TIM3_BASE TIM_CCMR1_CC1S_0 CAN_F4R2_FB22 ADC_DR_ADC2DATA_Msk CAN_FFA1R_FFA12_Msk CAN_F3R2_FB9_Pos I2C_SR1_OVR_Msk RCC_BDCR_LSERDY_Pos FLASH_ACR_LATENCY_2 OTG_FS_WKUP_IRQHandler +syn keyword CTagsDefinedName CAN_F5R1_FB4_Msk EXTI_PR_PR1_Pos GPIO_IDR_IDR12_Msk CAN_F4R1_FB26_Msk CAN_F2R1_FB8_Msk AFIO_EXTICR3_EXTI9_PD VECT_TAB_OFFSET FLASH_DATA0_nDATA0 EXTI_SWIER_SWIER6 CAN_F10R2_FB21 CAN_ESR_EPVF_Msk CAN_F4R1_FB28 RCC_CFGR_MCO CAN_F9R2_FB3_Pos CAN_F6R2_FB16 AFIO_EXTICR4_EXTI15_PF_Pos CAN_F9R2_FB3 RCC_CR_HSEON TIM_SMCR_ECE TIM_CCMR1_IC1F_3 TIM_BDTR_DTG_5 CAN_F3R1_FB21 DBGMCU_CR_DBG_TIM4_STOP_Pos ADC_CR1_DISCNUM_Msk TIM_BDTR_DTG_6 CAN_BTR_SJW_0 CAN_RDT0R_DLC ADC_CR1_JEOSIE_Pos +syn keyword CTagsDefinedName CAN_FA1R_FACT12 CAN_IER_BOFIE_Msk CAN_F8R2_FB1_Pos TIM_EGR_COMG USB_EP3R_DTOG_RX_Pos USB_EP1R_EA EXTI_RTSR_RT14 I2C_CR1_PEC_Msk GPIO_BSRR_BS4 USB_COUNT3_RX_0_COUNT3_RX_0 USB_COUNT5_RX_1_NUM_BLOCK_1_1 USB_EP3R_EP_TYPE_Pos EXTI_RTSR_RT6 GPIO_CRH_CNF14 SDIO_MASK_SDIOITIE_Msk CAN_F4R1_FB30_Pos AFIO_EXTICR1_EXTI2_PD_Pos ADC_SQR1_SQ16_Pos TIM_BDTR_DTG_1 RCC_APB2ENR_USART1EN CAN_F0R1_FB8 DMA_IFCR_CHTIF5 SDIO_MASK_RXDAVLIE_Msk SDIO_MASK_STBITERRIE USART_CR3_IREN CAN_F12R2_FB31 +syn keyword CTagsDefinedName CAN_TDL2R_DATA3_Msk TIM_CCMR1_OC2M USB_ISTR_ESOF_Msk ADC_SMPR2_SMP0 SPI_CR1_RXONLY_Pos CAN_F10R1_FB3_Pos AFIO_EXTICR2_EXTI5_PC CAN_F7R1_FB26_Pos DMA_IFCR_CGIF7_Msk CAN_F12R1_FB9 AFIO_EXTICR3_EXTI8_PD_Msk CAN_F3R2_FB22_Pos CAN_F0R2_FB13_Msk EXTI_PR_PR7_Msk TIM_BDTR_OSSR USB_COUNT4_RX_1_NUM_BLOCK_1_4 CAN_F3R1_FB31 USB_EP_TX_NAK CAN_F7R2_FB13 CAN_TSR_LOW0_Pos RTC_CRH_ALRIE_Msk CAN_F5R2_FB6_Msk AFIO_EXTICR2_EXTI5_Pos AFIO_EXTICR3_EXTI8_Pos GPIO_ODR_ODR8_Msk CAN_F10R2_FB28_Msk +syn keyword CTagsDefinedName CAN_TDL1R_DATA2_Pos CAN_TSR_TXOK2_Msk GPIO_LCKR_LCK13_Msk DMA_IFCR_CGIF4_Pos PWR_CR_PDDS_Msk SPI_CR1_BR_Pos SDIO_DCTRL_DMAEN_Msk TIM_CCR3_CCR3_Msk USB_COUNT6_TX_1_COUNT6_TX_1 CAN_F2R1_FB24_Msk ADC_SR_EOS_Pos USB_EPADDR_FIELD_Pos CAN_F0R1_FB17 CAN_FM1R_FBM11 CAN_TI1R_RTR_Pos AFIO_EXTICR4_EXTI15_PC CAN_FA1R_FACT4 GPIO_CRL_MODE5_Pos CAN_F5R1_FB22 USB_COUNT2_RX_1_NUM_BLOCK_1_0 CAN_MCR_RFLM USB_EP6R_STAT_TX_Msk FLASH TIM_SMCR_ETPS_Msk AFIO_EXTICR4_EXTI13_PA FLASH_ACR_PRFTBE_Msk +syn keyword CTagsDefinedName CAN_F6R2_FB8_Pos CAN_F8R1_FB6_Pos IWDG_KR_KEY CAN_BTR_TS1_Msk CAN_F0R2_FB7_Msk CAN_RDL1R_DATA2 IS_I2C_ALL_INSTANCE RCC_BDCR_RTCEN AFIO_MAPR_CAN_REMAP CAN_F5R1_FB30_Msk CAN_F2R1_FB17_Pos CAN_F9R2_FB13 EXTI_SWIER_SWI6 CAN_F0R1_FB17_Pos CAN_F10R1_FB2_Msk CAN_F13R2_FB31_Pos AFIO_MAPR_SWJ_CFG_JTAGDISABLE USB_COUNT4_RX_0_NUM_BLOCK_0_2 CAN_F13R2_FB27_Msk CAN_BTR_LBKM_Msk CAN_F6R2_FB8 GPIO_IDR_IDR1_Pos CAN_F10R1_FB17_Pos RCC_APB1ENR_PWREN_Pos ADC_SMPR1_SMP12_2 USB_EP_BULK +syn keyword CTagsDefinedName EXTI_IMR_MR17_Msk RCC_APB2RSTR_IOPDRST_Pos ADC_JOFR2_JOFFSET2_Msk AFIO_MAPR_TIM1_REMAP_PARTIALREMAP CAN_FFA1R_FFA11 FLASH_OPTKEY1 USB_COUNT7_RX_0_NUM_BLOCK_0_2 CAN_F0R1_FB31 DMA_ISR_TCIF2_Msk CAN_MSR_RXM_Msk ADC_SQR3_SQ4 ADC_SQR3_SQ1_Msk TIM_CR2_MMS CAN_F13R2_FB21_Pos GPIO_ODR_ODR0 CAN_RDL1R_DATA3_Msk DMA_CCR_PSIZE_1 GPIO_BRR_BR7 EXTI_FTSR_FT7 CAN_F6R2_FB13_Pos CAN_RF1R_RFOM1 EXTI_EMR_MR1_Msk TIM_SR_CC4OF_Pos GPIO_CRH_MODE12_Msk USB_COUNT6_TX_COUNT6_TX AFIO_EXTICR1_EXTI0_PG_Msk +syn keyword CTagsDefinedName CAN_F3R2_FB17 CAN_FS1R_FSC8 GPIO_ODR_ODR15_Pos I2C_DR_DR_Pos SDIO_STA_TXFIFOE_Pos RTC_BKP_NUMBER SDIO_CMD_WAITRESP_Pos CAN_F5R2_FB19_Msk CAN_TI1R_RTR_Msk SPI_CR1_RXONLY SDIO_DCTRL_RWSTOP_Msk GPIO_BSRR_BR0_Pos CAN_F10R1_FB9_Msk TIM_CCMR2_IC4PSC_Msk AFIO_EXTICR3_EXTI9_PB_Msk POSITION_VAL CAN_F9R2_FB5_Msk ADC_SMPR2_SMP0_2 CAN_FS1R_FSC1_Pos ADC_SMPR1_SMP10_2 CAN_F6R2_FB21 CAN_F7R2_FB22_Pos I2C_TRISE_TRISE ADC_SMPR2_SMP6 CAN_F0R1_FB5 CAN_F5R2_FB28_Pos CAN_F13R1_FB29_Msk +syn keyword CTagsDefinedName CAN_F10R2_FB30 CAN_F8R2_FB19 CAN_F9R2_FB4_Msk CAN_F6R1_FB31_Pos AFIO_MAPR_SWJ_CFG_Msk USB_COUNT4_RX_NUM_BLOCK_2 USB_EP3R_CTR_TX_Pos CAN_F0R2_FB25 CAN_F4R1_FB31_Pos USB_DADDR_ADD5_Msk CAN_F12R2_FB8_Msk CAN_F12R1_FB16_Msk GPIO_CRH_MODE10_1 CAN_F8R1_FB29_Pos EXTI_RTSR_TR17_Msk AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk CAN_F2R2_FB12_Msk CAN_F9R2_FB12_Pos CAN_F6R2_FB12_Pos EXTI_PR_PR13_Msk CAN_F9R1_FB8_Msk GPIO_CRH_CNF8_Pos CAN_F13R2_FB29_Pos CAN_F1R1_FB5 CAN_F12R2_FB11_Pos CAN_F5R2_FB15 +syn keyword CTagsDefinedName AHBPERIPH_BASE GPIO_CRH_MODE8_0 BKP_DR3_D_Msk CAN_F13R1_FB6_Msk TIM_BDTR_AOE_Pos CAN_F11R2_FB9_Msk EXTI_PR_PIF14 GPIO_CRL_CNF5 TIM_DMAR_DMAB ADC_DR_DATA_Pos ADC_SQR3_SQ3_0 USART_CR2_LBCL_Pos DMA_ISR_GIF7 ADC_MULTIMODE_SUPPORT CAN_F10R2_FB22 CAN_F13R2_FB26_Msk ADC_SQR3_SQ1_4 CAN_F11R1_FB7_Pos GPIO_BSRR_BS8_Pos TIM_CR1_OPM_Pos AFIO_EVCR_PIN_PX9_Pos CAN_F13R1_FB17_Pos USB_CNTR_RESETM_Msk CAN_F7R1_FB24_Msk EXTI_EMR_MR2 CAN_F4R2_FB6 CAN_F0R2_FB16 CAN_F8R1_FB12_Msk EXTI_PR_PR2_Pos +syn keyword CTagsDefinedName CAN_F13R2_FB9_Pos CAN_F6R2_FB3 I2C_CR2_ITERREN_Msk ADC_SQR2_SQ9_2 CAN_BTR_BRP_Pos RCC_APB2ENR_ADC2EN I2C_OAR1_ADD7_Pos AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ADC_CR2_JEXTSEL_2 EXTI_EMR_EM18 BKP_CSR_TIF_Pos GPIO_BSRR_BS9_Pos IWDG_SR_PVU USB_EP1R_EP_TYPE_1 CAN_IER_FOVIE1_Pos AFIO_EXTICR1_EXTI2_PE_Pos ADC_CR2_JEXTSEL_1 CAN_F12R2_FB27 GPIO_CRH_CNF11 ADC_SQR3_SQ4_1 RCC_CIR_LSIRDYF_Pos AFIO_EXTICR1_EXTI0_PG_Pos CAN_F6R1_FB13_Pos AFIO_EXTICR4_EXTI14_PB_Msk USB_EP7R_SETUP_Msk PWR_CR_PLS_2V2 +syn keyword CTagsDefinedName IWDG_PR_PR_0 TIM_CCR1_CCR1_Msk CAN_F12R1_FB18 CAN_F9R1_FB20_Msk CAN_F11R2_FB31 EXTI_PR_PR18_Pos CAN_F12R2_FB3_Pos RCC_CFGR_PLLMULL USB_EP1R_DTOG_TX SPI_CR1_BR AFIO_EXTICR3_EXTI8_PF_Msk CAN_F2R1_FB26 DMA_ISR_TCIF5_Msk STM32F1 EXTI_FTSR_FT1 USB_ISTR_CTR CAN_F4R1_FB16 USB_COUNT6_RX_0_NUM_BLOCK_0 CAN_F12R2_FB31_Msk USART_CR2_CPHA_Msk ADC_SMPR2_SMP4_Msk AFIO_EXTICR2_EXTI7_PD ADC_SQR1_L_2 DBGMCU_CR_TRACE_MODE_Pos GPIO_LCKR_LCK13_Pos WWDG_CR_T2 USART_CR3_NACK_Pos +syn keyword CTagsDefinedName USB_COUNT7_TX_0_COUNT7_TX_0 DBGMCU_IDCODE_REV_ID_5 CAN_F1R2_FB31_Pos CAN_F13R1_FB19 CAN_F4R1_FB8_Pos GPIO_CRL_MODE7_Pos CAN_F4R2_FB22_Pos CAN_F5R2_FB31 RCC_BDCR_RTCSEL SDIO_CMD_ENCMDCOMPL TIM_DIER_CC4DE ADC_SQR2_SQ12_0 CAN_F4R2_FB3_Pos DMA_ISR_HTIF7_Msk CRC CAN_F2R1_FB29_Pos CAN_TSR_LOW2 PIN_OPT_AF3 EXTI_EMR_EM4 CAN_F7R2_FB3 CAN_TI0R_STID_Pos USART_CR3_EIE_Msk CAN_F9R1_FB21 CAN_FM1R_FBM11_Msk RCC_AHBENR_FLITFEN_Pos CAN_F0R2_FB24_Pos SDIO_MASK_TXUNDERRIE_Msk CAN_F7R2_FB26 +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PF_Msk RCC_CFGR_HPRE_DIV128 CAN_F3R2_FB25_Msk CAN_F9R2_FB11 EXTI_PR_PR5_Pos CAN_F0R1_FB14_Msk ADC_SQR2_SQ10_4 SDIO_STA_DATAEND CAN_IER_TMEIE_Pos EXTI_IMR_IM7 ADC_SMPR1_SMP16_0 CAN_F12R2_FB16 AFIO_EXTICR2_EXTI7_PA GPIO_ODR_ODR4_Pos ADC_CR1_DISCNUM CAN_F7R1_FB16 USB_COUNT2_RX_1_NUM_BLOCK_1_4 USART_GTPR_PSC_3 AFIO_EXTICR4_EXTI12_PG_Msk TIM_DIER_CC3IE_Msk USB_COUNT0_RX_NUM_BLOCK_Msk BKP_RTCCR_CAL_Msk CAN_F4R2_FB7_Msk CAN_TDL0R_DATA3_Pos +syn keyword CTagsDefinedName USB_COUNT4_RX_1_NUM_BLOCK_1_0 CAN_F11R2_FB0_Msk TIM_DIER_CC1IE EXTI_EMR_EM6 DMA_CCR_TEIE USB_EP7R_CTR_TX_Pos EXTI_FTSR_FT4 SDIO_CLKCR_CLKEN_Pos CAN_F6R1_FB3 AFIO_EXTICR2_EXTI4_PG_Msk CAN_F5R1_FB24 GPIO_IDR_IDR12 EXTI_SWIER_SWI1 CAN_TSR_TERR0_Msk GPIO_BRR_BR0_Pos CAN_F7R2_FB16 CAN_F2R1_FB20 SPI_CR1_SSM CAN_FA1R_FACT2_Msk CAN_FS1R_FSC13_Msk CAN_F3R1_FB17_Pos CAN_TI2R_IDE_Msk TIM_BDTR_DTG_0 FLASH_CR_STRT_Pos DMA_IFCR_CGIF2_Msk WWDG_CFR_W_5 USART_SR_PE_Msk CAN_MCR_SLEEP_Pos +syn keyword CTagsDefinedName DMA1_Channel2_BASE RTC_ALRH_RTC_ALR_Msk CAN_F1R2_FB23 CAN_F4R2_FB11_Msk GPIO_BRR_BR8_Pos USB_EP3R_CTR_RX_Pos EXTI_RTSR_TR0_Msk ADC_JSQR_JL_Pos CAN_F9R2_FB4 CAN_F10R2_FB5 CAN_F12R2_FB7_Pos CAN_F4R1_FB26 CAN_TDL1R_DATA1 AFIO_EXTICR2_EXTI7_PG_Msk DMA_CCR_MSIZE_1 AFIO_MAPR_USART2_REMAP_Pos ADC_SQR3_SQ3_Pos DMA_ISR_TCIF7 RCC_APB2RSTR_IOPARST_Pos USB_EP2R_STAT_TX CAN_F5R1_FB3_Msk CAN_F11R2_FB2_Msk I2C_OAR1_ADD3_Msk EXTI_PR_PR12_Msk CAN_F0R1_FB16_Pos USB_COUNT1_RX_COUNT1_RX_Pos +syn keyword CTagsDefinedName USB_COUNT1_RX_1_NUM_BLOCK_1_1 CAN_F3R2_FB16_Msk ADC_SQR1_SQ16_2 CAN_RF1R_FMP1 RCC_APB1RSTR_SPI2RST_Msk ADC_SMPR1_SMP13_Pos RCC_APB2RSTR_IOPARST I2C_OAR1_ADD9 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_EXTICR4_EXTI15_PE_Pos CAN_F12R2_FB20_Msk DMA_ISR_TCIF5 EXTI_FTSR_FT9 CAN_F7R1_FB24_Pos CAN_F3R2_FB31_Msk SDIO_ICR_SDIOITC_Pos EXTI_RTSR_TR5_Msk AFIO_EVCR_PIN_PX7_Msk AFIO_EXTICR4_EXTI14_PF_Msk DMA_IFCR_CHTIF2 TIM_CCMR2_OC4M_Msk CAN_FS1R_FSC8_Pos RCC_CSR_PORRSTF I2C_SR1_RXNE_Msk +syn keyword CTagsDefinedName RDP_KEY CAN_F2R1_FB25_Pos USB_COUNT0_RX_0_NUM_BLOCK_0 EXTI_SWIER_SWIER7_Pos CAN_FFA1R_FFA2 CAN_F4R2_FB8_Msk CAN_F7R2_FB9_Msk USB_EP2R_CTR_TX GPIO_ODR_ODR2 AFIO_MAPR_TIM1_REMAP_FULLREMAP GPIO_BSRR_BR1_Msk GPIO_CRH_CNF12_Msk DMA_CCR_PL SPI_CR2_ERRIE USB_EP0R_EP_TYPE_0 IS_TIM_INSTANCE CAN_F3R1_FB9 CAN_F9R2_FB21_Msk CAN_F8R1_FB8 FLASH_WRP2_nWRP2_Pos CAN_F3R1_FB13_Msk USB_COUNT6_TX_COUNT6_TX_Msk ADC_CR1_AWDCH_0 USB_EP0R_CTR_RX_Msk CAN_F9R2_FB28_Msk CAN_F11R2_FB1_Msk CAN_F11R1_FB22 +syn keyword CTagsDefinedName FLASH_OPTKEYR_OPTKEYR_Msk GPIO_CRL_CNF_Msk CAN_F0R1_FB14_Pos GPIO_BSRR_BR15_Msk CAN_F8R2_FB7_Pos RCC_CR_HSION_Msk USB_COUNT5_TX_COUNT5_TX_Pos CAN_F0R1_FB15_Pos TIM_CCMR2_IC3PSC CAN_F12R1_FB31 CAN_F13R2_FB31 USB_ISTR_DIR CAN_F10R2_FB14_Msk CAN_F13R1_FB31 CAN_ESR_EWGF AFIO_EXTICR3_EXTI10_PF_Msk CAN_F12R1_FB3_Msk USB_EP4R_SETUP TIM_CCMR1_OC2M_Pos PWR_CSR_PVDO_Pos EXTI_IMR_MR2_Msk ADC_SMPR1_SMP14_1 CAN_F6R1_FB30_Msk CAN_F10R1_FB4 CAN_F11R1_FB29 CAN_TDH1R_DATA4_Pos FLASH_KEYR_FKEYR +syn keyword CTagsDefinedName I2C_CR1_POS TIM_CCMR1_IC2PSC_0 TIM_CCMR1_IC2PSC_Msk USB_EP7R_SETUP_Pos ADC_SMPR1_SMP16_Msk CAN_F10R1_FB19_Msk DMA_IFCR_CGIF5 CAN_F9R1_FB2_Pos TIM_CCMR1_OC2PE_Pos CAN_F4R2_FB30_Pos EXTI_RTSR_TR3_Pos USB_EP1R_SETUP CAN_F8R2_FB29 GPIO_ODR_ODR5_Msk EXTI_FTSR_TR17_Msk AFIO_EXTICR3_EXTI10 USART_GTPR_PSC_4 BKP_CR_TPAL CAN_RDT1R_FMI_Pos RCC_CFGR_PLLMULL13_Pos DMA_ISR_GIF2_Pos CAN_F4R1_FB26_Pos USB_EP7R_STAT_TX_Msk CAN_F13R2_FB7 AFIO_EXTICR2_EXTI6_PB GPIO_CRH_MODE15_0 CAN_F4R1_FB15_Pos +syn keyword CTagsDefinedName SDIO_STA_TXDAVL_Pos USB_CNTR_PDWN_Msk CAN_F10R1_FB28 USB_ADDR6_RX_ADDR6_RX FLASH_CR_ERRIE_Msk GPIO_IDR_IDR3 TIM_CCMR2_OC3M_1 GPIO_CRL_MODE3_1 I2C_SR1_ADD10 CAN_F4R2_FB0 CAN_RF0R_FULL0 RCC_CFGR_PLLMULL3_Pos CAN_F4R2_FB24 CAN_F4R1_FB29_Msk CAN_F7R2_FB18_Pos FLASH_WRP0_nWRP0_Pos EXTI_PR_PR11_Msk TIM_CCMR1_OC2FE_Msk USART_CR2_LINEN_Msk CAN_F0R1_FB26 ADC_SQR3_SQ4_3 CAN_F10R1_FB1_Msk GPIO_CRL_CNF1_1 USB_COUNT6_RX_BLSIZE USB_COUNT0_TX_1_COUNT0_TX_1 DMA_ISR_TEIF5 DMA_ISR_HTIF3 +syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI3_Pos ADC_CR1_DISCNUM_2 CAN_F8R2_FB21_Pos GPIO_ODR_ODR13_Msk CAN_F12R1_FB1 CAN_F6R2_FB18 USB_EP4R_DTOG_TX USB_COUNT2_RX_NUM_BLOCK_1 CAN_TI1R_TXRQ_Pos CAN_FS1R_FSC5_Msk EXTI_IMR_MR6 EXTI_FTSR_TR10_Msk GPIO_CRL_MODE3_Pos FLASH_SR_EOP_Msk CAN_F11R2_FB1_Pos TIM_CR2_OIS4_Msk USB_COUNT1_RX_0_COUNT1_RX_0 SDIO_STA_CCRCFAIL_Pos CAN_F5R1_FB25_Pos USART_CR2_CPOL CAN_BTR_TS1_Pos CAN_F0R2_FB19_Pos CAN_F10R1_FB3_Msk GPIO_CRH_CNF9_0 USB_COUNT4_TX_COUNT4_TX_Msk +syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI15_PF CAN_F7R1_FB17 GPIO_BRR_BR12 RCC_CSR_LSION_Pos ADC_DR_DATA_Msk CAN_F11R2_FB18_Msk CAN_F1R2_FB1_Pos SDIO_RESP3_CARDSTATUS3 PIN_OPT_NONE USB_EP7R_EA_Pos EXTI_PR_PIF1 EXTI_RTSR_TR6_Msk FLASH_WRP1_WRP1 CAN_F5R2_FB8 DMA_ISR_TEIF3_Msk USB_EP2R_EA_Pos CAN_F10R1_FB6 CAN_F5R2_FB20 CAN_F5R2_FB15_Pos GPIO_BSRR_BR6_Pos SDIO_MASK_DATAENDIE_Msk CAN_F5R1_FB7 I2C_CR1_SMBUS_Pos ADC_SMPR2_SMP2_0 CAN_F4R2_FB11_Pos GPIO_BSRR_BR13_Pos CAN_F10R2_FB30_Msk GPIO_BRR_BR11 +syn keyword CTagsDefinedName PWR_CR_LPDS_Msk AFIO_EVCR_EVOE_Pos TIM_EGR_BG_Msk CAN_F11R1_FB27_Pos CAN_F3R1_FB6_Pos USART2 CAN_F1R1_FB14 GPIO_BSRR_BS2_Pos ADC_SMPR1_SMP15_Pos ADC_CR2_SWSTART_Msk CAN_F10R1_FB18 USART_SR_TC CAN_F6R1_FB5 CAN_F7R1_FB20 IWDG_SR_PVU_Pos CAN_F7R2_FB10_Pos CAN_FFA1R_FFA6_Pos AFIO_EVCR_PIN_PX2 SDIO_DCTRL_DTDIR_Pos TIM_DIER_UIE_Msk AFIO_EXTICR3_EXTI10_PD CAN_F5R1_FB18 ADC_SMPR1_SMP12_1 FLASH_AR_FAR_Msk SPI_CR1_BR_0 AFIO_EVCR_PORT_Pos USB_EP1R_STAT_TX_1 AFIO_EXTICR2_EXTI7_PG +syn keyword CTagsDefinedName USB_EP_DTOG_RX_Msk CAN_F6R1_FB24 GPIO_BRR_BR4_Msk EXTI_SWIER_SWIER15 ADC_SQR3_SQ5_3 AFIO_EXTICR3_EXTI9_PE CAN_F2R2_FB9 USART_CR2_CPOL_Msk GPIO_BSRR_BR10_Pos CAN_TSR_TME1_Msk I2C_SR1_ADDR ADC_SQR2_SQ9_0 CAN_F6R2_FB26 CAN_F2R2_FB23 TIM_CCMR1_OC2FE_Pos TIM1_UP_TIM16_IRQn AFIO_MAPR_SWJ_CFG_Pos CAN_F3R1_FB30 CAN_F7R1_FB29_Msk DMA_IFCR_CTCIF5 USB_EP_DTOG_RX_Pos EXTI_SWIER_SWIER15_Msk ADC_SMPR1_SMP14_0 GPIO_LCKR_LCK11_Pos USB_COUNT0_RX_1_NUM_BLOCK_1_1 TIM_CCMR2_OC4PE_Msk +syn keyword CTagsDefinedName CAN_F6R1_FB3_Pos SDIO_MASK_TXFIFOHEIE_Pos TIM_CCMR2_OC4M_1 USB_FNR_RXDM_Msk CAN_F4R2_FB16_Msk CAN_F9R2_FB24_Pos USB_COUNT3_RX_COUNT3_RX ADC_SQR1_SQ13 CAN_F4R1_FB9_Pos RCC_CFGR_PPRE2_DIV1 BKP_DR2_D_Pos CAN_F7R1_FB28_Msk SDIO_STA_CEATAEND_Pos RCC_CSR_RMVF_Msk GPIO_LCKR_LCK6_Msk CAN_F2R2_FB27 CAN_F5R2_FB18_Msk AFIO_EXTICR3_EXTI9_PF_Pos CAN_ESR_LEC_Msk USB_EP3R_DTOG_TX_Pos RCC_CFGR_PLLMULL16_Pos CAN_F11R2_FB1 TIM_EGR_CC3G GPIO_BSRR_BR5_Pos TIM_CCER_CC3NE DBGMCU_IDCODE_DEV_ID +syn keyword CTagsDefinedName USB_COUNT3_RX_1_NUM_BLOCK_1_3 SDIO_MASK_CCRCFAILIE_Msk GPIO_BSRR_BR6 IS_TIM_32B_COUNTER_INSTANCE pwm_start RCC_CFGR_PLLMULL11 USB_COUNT3_RX_0_NUM_BLOCK_0_2 GPIO_CRL_CNF5_Pos PWR_CR_PLS_Msk CAN_F9R1_FB14_Msk CAN_F8R2_FB0 CAN_F9R2_FB0 EXTI_IMR_MR13_Pos AFIO_EXTICR2_EXTI4_PF_Pos CAN_F4R2_FB4 USB_EP3R_STAT_TX_Msk CAN_F2R1_FB29 EXTI_PR_PR16_Pos CAN_TSR_TXOK1_Msk CAN_F6R2_FB19 CAN_TSR_TERR2_Pos PIN_OPT_IRQ_EDGE_FALL I2C_CR2_LAST CAN_F13R2_FB13_Pos EXTI_IMR_MR5_Msk CAN_F4R2_FB19 +syn keyword CTagsDefinedName CAN_F10R1_FB20_Pos TIM4_IRQ_PRIORITY CAN_F2R2_FB31 DMA_ISR_TEIF6_Pos RCC_APB2RSTR_SPI1RST_Pos EXTI_PR_PR17_Msk TIM_CCMR1_IC1PSC RCC_CFGR_SW_HSI CAN_F10R1_FB30_Msk CAN_F11R2_FB23_Msk CAN_F4R2_FB10_Msk EXTI_RTSR_TR7_Msk DMA_ISR_HTIF1_Msk TIM_DIER_UDE DMA_IFCR_CTEIF1 CAN_F13R1_FB22 DBGMCU_CR_TRACE_MODE_Msk RCC_BDCR_BDRST_Pos GPIO_IDR_IDR9 CAN_F3R2_FB1_Pos GPIO_LCKR_LCK8 ADC_SQR3_SQ1_Pos EXTI_PR_PIF13 USART_CR3_IREN_Pos CAN_F2R1_FB11_Pos USB_EPRX_DTOG2 EXTI_SWIER_SWIER16_Pos +syn keyword CTagsDefinedName CAN_F8R1_FB30_Pos TIM_CR1_CMS_1 AFIO_EXTICR4_EXTI12_PE CAN_F6R1_FB15 RCC_CFGR_PLLMULL4_Pos CAN_F8R2_FB14_Pos CAN_F12R2_FB9 CAN_F1R2_FB12_Pos FLASH_CR_PER_Msk I2C_CR1_STOP_Msk GPIO_BSRR_BS9_Msk GPIO_CRH_CNF9_Pos SDIO_RESP3_CARDSTATUS3_Msk CAN_F8R1_FB14_Pos ADC_SQR1_SQ15_4 ADC_SMPR2_SMP9_Pos CAN_F8R1_FB31 FLASH_CR_OPTWRE_Msk USB_EP5R_CTR_TX_Msk RCC_CFGR_PLLMULL9 CAN_F4R2_FB5_Pos CAN_F11R1_FB13 CAN_F11R2_FB19_Pos CAN_FM1R_FBM4_Pos SPI_CR2_RXDMAEN SDIO_DTIMER_DATATIME +syn keyword CTagsDefinedName RCC_CFGR_PPRE1_2 CAN_TSR_TME1 ADC_CR2_EXTTRIG_Msk AFIO_EXTICR3_EXTI11_PD RCC_CFGR_ADCPRE CAN_F13R2_FB30_Msk USB_ISTR_SUSP EXTI_EMR_MR13_Pos USB_COUNT0_RX_NUM_BLOCK_0 CAN_F1R1_FB31 CAN_F7R1_FB18 CAN_F1R1_FB16_Pos USB_EP4R_EP_TYPE_Msk WWDG_CR_T_Msk CAN_F8R2_FB4 CAN_F9R2_FB30 PWR_CR_DBP CAN_F6R2_FB9_Msk CAN_RDL0R_DATA2_Pos RCC_CFGR_MCOSEL USB_COUNT2_RX_1_NUM_BLOCK_1_1 CAN_F1R1_FB31_Pos TIM_CCER_CC3NE_Msk BKP_DR10_D_Msk AFIO_EXTICR2_EXTI4_PA CAN_F3R1_FB10_Msk CAN_F10R2_FB15_Msk +syn keyword CTagsDefinedName GPIO_ODR_ODR3_Pos GPIO_BSRR_BS1_Pos CAN_F2R2_FB1 TIM_CCMR1_OC2PE EXTI_RTSR_RT9 CAN_F10R2_FB31 CAN_F0R2_FB1 CAN_F6R2_FB13_Msk CAN_F0R2_FB29 TIM_CCER_CC4E CAN_F11R2_FB31_Pos EXTI_FTSR_TR16_Pos EXTI_IMR_MR3_Msk CAN_F5R1_FB24_Pos CAN_F8R2_FB25_Pos I2C_CR2_FREQ_5 GPIO_ODR_ODR8_Pos AFIO_EXTICR1_EXTI2_Msk USB_ADDR4_RX_ADDR4_RX_Pos RCC_HSE_MAX CAN_F3R2_FB22 RTC_ALRH_RTC_ALR_Pos IS_TIM_CC4_INSTANCE DBGMCU_IDCODE_REV_ID_11 CAN_F8R2_FB23_Pos EXTI_PR_PR10 +syn keyword CTagsDefinedName DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos GPIO_CRL_MODE1_0 EXTI_RTSR_RT17 GPIO_BSRR_BS3_Msk USB_COUNT4_RX_1_NUM_BLOCK_1_2 CAN_F6R2_FB17_Pos ADC_CR2_TSVREFE CAN_F5R2_FB22 CAN_FA1R_FACT11_Pos BKP TIM_DIER_CC4IE_Msk ADC_CR2_JEXTTRIG DMA_ISR_GIF3_Pos RCC_CIR_HSERDYIE_Pos FLASH_SR_PGERR_Pos CAN_F6R1_FB20 RCC_CFGR_ADCPRE_DIV4 RCC_APB2RSTR_USART1RST AFIO_MAPR_USART2_REMAP_Msk SDIO_CMD_CPSMEN EXTI_PR_PIF7 USB_ADDR7_TX_ADDR7_TX_Msk EXTI_EMR_MR9_Msk CAN_F10R1_FB5 RTC_CRH_SECIE_Pos +syn keyword CTagsDefinedName CAN_F11R1_FB21_Msk CAN_FA1R_FACT3_Msk CAN_FFA1R_FFA7_Pos CAN_F11R2_FB26 GPIO_CRH_CNF15_Pos CAN_F5R1_FB29_Msk SDIO_DCTRL_RWMOD_Msk IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE USB_EP6R_CTR_RX CAN_F9R1_FB16_Pos GPIO_BSRR_BS14_Msk CAN_F6R2_FB28_Msk AFIO_EXTICR2_EXTI7_PC MBED_CMSIS_NVIC_H SDIO_RESP0_CARDSTATUS0_Pos RCC_AHBENR_SRAMEN RCC_CFGR_SWS_HSI CAN_F4R1_FB22_Msk I2C_OAR1_ADD2 GPIO_BSRR_BS0_Pos USB_LP_IRQn CAN_F1R2_FB11 SDIO_ICR_DBCKENDC_Msk ADC_SQR2_SQ7 DMA_CCR_HTIE CAN_F0R1_FB7_Msk +syn keyword CTagsDefinedName GPIOD_BASE CAN_F12R1_FB16_Pos USB_EP0R_DTOG_TX_Pos CAN_IER_FOVIE1_Msk EXTI_PR_PIF12 CRC_BASE CAN_TDT2R_TGT RCC_CIR_HSIRDYC AFIO_EXTICR1_EXTI2_PE CAN_IER_FOVIE1 TIM_DCR_DBL_3 CAN_BTR_TS2_Msk GPIO_BSRR_BR8 GPIO_ODR_ODR15_Msk RTC_CRH_OWIE_Msk CAN_F1R1_FB30_Msk CAN_RI1R_EXID_Pos TIM_CR2_CCDS_Msk CAN_F5R2_FB21 AFIO_EXTICR1_EXTI2_PA TIM_SMCR_ETPS CAN_F10R2_FB9_Msk TIM_CCMR2_IC4F_0 PWR_CR_LPDS DBGMCU_CR_TRACE_MODE USART3 TIM_CCMR2_IC4F_Pos AFIO_EXTICR4_EXTI12_PB CAN_F3R2_FB2_Pos +syn keyword CTagsDefinedName EXTI_IMR_IM14 BKP_RTCCR_CCO_Msk FLASH_WRPR_WRP CAN_F4R2_FB2_Pos CAN_TSR_TERR0 AFIO_MAPR_TIM2_REMAP_0 CAN_F13R1_FB20_Msk ADC_SMPR2_SMP7_2 CAN_TI0R_STID CAN_F8R1_FB1_Pos USB_DADDR_ADD2 I2C_CR2_FREQ RTC CAN_TDT0R_TGT_Msk CAN_F7R2_FB30 FLASH_OBR_OPTERR_Msk GPIO_CRH_CNF8 ADC_SMPR2_SMP1 CAN_F13R1_FB30_Msk FLASH_AR_FAR CAN_RDL1R_DATA0 AFIO_EXTICR2_EXTI7_PF_Pos USART_BRR_DIV_Fraction DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk USB_ISTR_ERR_Msk USB_COUNT7_RX_0_NUM_BLOCK_0_3 I2C_SR2_PEC_Msk +syn keyword CTagsDefinedName SDIO_CLKCR_WIDBUS_Pos EXTI_IMR_MR4_Pos CAN_F9R1_FB31_Msk RCC_APB1ENR_SPI2EN_Pos CAN_F0R1_FB30 CAN_F8R2_FB30_Msk ADC_SMPR2_SMP0_1 RCC_APB2ENR_TIM1EN_Msk USB_COUNT6_RX_0_NUM_BLOCK_0_1 USART_CR2_CLKEN_Msk GPIOA USB_COUNT1_RX_1_NUM_BLOCK_1_4 CAN_F0R1_FB16 CAN_F1R2_FB31_Msk I2C_SR2_TRA_Msk CAN_F4R1_FB24 ADC_SMPR2_SMP4_1 CAN_TDT0R_DLC_Msk CAN_F5R1_FB20_Msk I2C_OAR1_ADD1 USB_COUNT3_RX_NUM_BLOCK EXTI_IMR_MR18_Msk USB_COUNT4_TX_1_COUNT4_TX_1 CAN_F0R2_FB6 CAN_F6R2_FB11_Pos +syn keyword CTagsDefinedName USB_EP7R_CTR_TX_Msk CAN_RI1R_STID_Pos RCC_CSR_LSIRDY DBGMCU_IDCODE_REV_ID_6 FLASH_SR_EOP AFIO_MAPR_SWJ_CFG_RESET GPIO_CRH_CNF14_Msk CAN_F1R2_FB11_Pos USB_COUNT2_RX_0_NUM_BLOCK_0_3 DBGMCU_IDCODE_DEV_ID_Pos USB_PMAADDR CAN_F4R2_FB27_Pos CAN_F7R2_FB1_Msk EXTI_FTSR_TR4_Msk EXTI_FTSR_TR16_Msk AFIO_EVCR_PORT_Msk AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk CAN_F2R1_FB7_Msk RDP_KEY_Pos CAN_F1R2_FB14 SDIO_DCTRL_DBLOCKSIZE_2 TIM_SMCR_MSM RCC_APB1RSTR_SPI2RST_Pos CAN_F0R2_FB3_Msk I2C_OAR1_ADD5_Pos +syn keyword CTagsDefinedName CAN_F4R2_FB21 TIM_DIER_COMIE_Pos CAN_F4R2_FB26_Msk SYSCFG_EXTI_PD_MASK CAN_F1R1_FB14_Msk AFIO_EXTICR4_EXTI15_PG EXTI_PR_PR10_Msk WWDG_CFR_W_Msk TIM_CCMR2_OC4PE_Pos USB_EP_RX_NAK CAN_BTR_TS1_1 GPIO_IDR_IDR14 CAN_F3R2_FB11_Msk USB_FNR_RXDP_Msk USART_SR_CTS_Msk EXTI_FTSR_TR14_Pos TIM_CCMR2_CC3S_Msk TIM_DIER_TDE_Msk BKP_DR1_D RCC_AHBENR_SRAMEN_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 EXTI_PR_PR18_Msk ADC_SQR2_SQ7_4 SDIO_MASK_CMDSENTIE_Msk AFIO_EXTICR3_EXTI8_PB_Pos GPIO_BRR_BR9_Pos +syn keyword CTagsDefinedName USB_COUNT1_TX_COUNT1_TX_Msk RCC_CIR_PLLRDYIE_Msk GPIO_ODR_ODR11 CAN_F3R1_FB2_Pos CAN_RDH1R_DATA6_Msk CAN_F10R2_FB5_Msk SPI_CR1_CRCEN TIM_CR2_CCPC_Msk CAN_F3R2_FB20_Pos CAN_F7R2_FB27 CAN_TDT0R_TIME CAN_F8R2_FB7_Msk CAN_F6R2_FB4_Pos SDIO_FIFOCNT_FIFOCOUNT_Msk RCC_BDCR_RTCSEL_0 CAN_F5R2_FB31_Pos CAN_F4R1_FB31_Msk CAN_F11R1_FB24 CAN_F4R2_FB10_Pos IS_USB_ALL_INSTANCE CAN_F12R1_FB13_Pos CAN_F13R1_FB0_Msk AFIO_EXTICR2_EXTI4_PC CAN_F8R2_FB19_Pos AFIO_EXTICR1_EXTI0_PE_Msk +syn keyword CTagsDefinedName TIM_BDTR_BKE_Pos USB_EP1R_DTOG_RX_Msk CAN_F12R2_FB19 CAN_F6R2_FB11 CAN_F12R2_FB16_Pos CAN_TDH1R_DATA6_Pos TIM_ARR_ARR_Msk RCC_CFGR_PPRE2 TIM_DIER_CC3DE_Msk CAN_F10R1_FB25_Msk PWR_CR_PLS_2V9 TIM_CCER_CC3E_Pos ADC_CR1_DUALMOD_Msk AFIO_EXTICR1_EXTI0_PA CAN_F13R1_FB6 DMA_ISR_TEIF2 CAN_RF0R_FOVR0_Msk CAN_F3R1_FB8_Pos AFIO_EXTICR2_EXTI5_PG_Msk CAN_F8R1_FB28_Msk FLASH_OBR_nRST_STOP CAN_F6R1_FB9_Pos CAN_F9R2_FB0_Pos TIM_CCMR1_OC2M_Msk CAN_F7R1_FB11_Pos FLASH_OBR_nRST_STDBY_Msk +syn keyword CTagsDefinedName GPIO_CRL_MODE5_1 I2C_OAR1_ADD8_9 CAN_F3R1_FB18_Pos AFIO_EXTICR1_EXTI3_PA FLASH_CR_PG CAN_F9R1_FB5_Pos WWDG_CFR_W2 CAN_F8R1_FB23_Msk DMA_ISR_TCIF7_Msk CAN_IER_LECIE_Pos CAN_F12R2_FB0_Pos IWDG_BASE RCC_BDCR_LSEBYP_Pos DMA_IFCR_CTEIF6 CAN_F10R2_FB20_Pos IS_TIM_ENCODER_INTERFACE_INSTANCE RCC_CFGR_PLLMUL USB_COUNT2_TX_1_COUNT2_TX_1 TIM_CCER_CC2NE_Msk CAN_F10R2_FB5_Pos CAN_F10R2_FB6_Msk CAN_F1R1_FB19 CAN_TSR_TME_Msk USB_COUNT4_RX_0_BLSIZE_0 TIM_CR1_CKD_1 CAN_F12R2_FB27_Pos +syn keyword CTagsDefinedName TIM_CR2_OIS2_Pos CAN_F2R1_FB23_Pos USART2_BASE RCC_CFGR_SW_Msk CAN_F11R1_FB31 GPIO_LCKR_LCK3 USB_EP2R_EP_TYPE RCC_APB2ENR_SPI1EN CAN_F3R2_FB10_Pos ADC_SMPR1_SMP10_0 CAN_F10R2_FB26_Msk AFIO_EVCR_PIN_PX11_Pos AFIO_EXTICR4_EXTI14_PG_Msk EXTI_PR_PR4_Msk SDIO_CMD_NIEN USB_COUNT3_RX_0_BLSIZE_0 ADC_CR2_TSVREFE_Msk CAN_TI2R_TXRQ_Msk DMA_ISR_GIF7_Msk PIN_15 GPIO_LCKR_LCK0_Pos SDIO_DCTRL_DTMODE_Pos CAN_F0R2_FB21_Msk I2C_OAR1_ADD6_Msk SDIO_ICR_STBITERRC_Pos CAN_MCR_DBF_Msk USART_CR3_CTSE +syn keyword CTagsDefinedName ADC_CR1_JEOCIE CAN_TSR_TME2_Pos DMA_ISR_TEIF4 CAN_F11R1_FB30_Msk USB_EP4R_EP_TYPE_1 CAN_F2R1_FB16 DBGMCU_CR_DBG_CAN1_STOP_Msk CAN_F1R2_FB16_Msk GPIO_CRL_CNF5_1 PWM_CHANNEL_3 USART_SR_LBD_Msk CAN_F9R2_FB19_Pos TIM_BDTR_DTG_Pos AFIO_EXTICR2_EXTI4_PD TIM_CCER_CC1NE_Pos ADC_SQR2_SQ11_1 CAN_F12R1_FB12_Pos AFIO_EVCR_PORT_PC_Msk CAN_FM1R_FBM6 CAN_F1R1_FB16_Msk CAN_TDT1R_DLC_Msk ADC_SQR2_SQ10_Msk I2C_CR1_ENPEC ADC_CR1_DUALMOD_2 EXTI_PR_PR13 PIN_OPT_AF15 TIM_CCER_CC3P_Pos +syn keyword CTagsDefinedName ADC_CR2_DMA_Pos AFIO_EXTICR4_EXTI15_PA CAN_F4R2_FB19_Pos CAN_F8R2_FB13_Pos AFIO_EXTICR1_EXTI0 CAN_F3R1_FB5 GPIO_IDR_IDR4_Msk USB_EP3R_SETUP FLASH_OBR_nRST_STOP_Msk CAN_F6R1_FB10 EXTI_SWIER_SWI9 AFIO_EXTICR1_EXTI0_PF FLASH_WRP3_WRP3 CAN_FM1R_FBM2_Msk ADC_SMPR2_SMP9 CAN_F4R2_FB26_Pos TIM_CR1_CEN CAN_F5R2_FB28_Msk RCC_CFGR_PLLXTPRE CAN_F8R1_FB30_Msk CAN_FS1R_FSC AFIO_EXTICR1_EXTI2_PB_Msk USB_COUNT6_TX_COUNT6_TX_Pos AFIO_EVCR_PORT_PB_Msk CAN_F6R1_FB15_Pos EXTI_RTSR_TR13 I2C_CCR_CCR +syn keyword CTagsDefinedName DMA_IFCR_CTEIF7_Msk USART_CR3_CTSIE EXTI_RTSR_TR13_Msk RCC_CFGR_PLLMULL16 ADC_JSQR_JSQ3_0 CAN_F9R2_FB2_Pos ADC_SMPR1_SMP11_2 CAN_F10R1_FB6_Pos GPIO_LCKR_LCK1 ADC_SQR1_SQ15_Msk USB_EP5R EXTI_IMR_MR18_Pos SDIO_MASK_CEATAENDIE_Pos ADC_SQR1_SQ16 AFIO_EXTICR4_EXTI12_Pos CAN_FFA1R_FFA12_Pos RCC_CR_HSIRDY_Msk DMA_ISR_GIF4_Msk FLASH_CR_STRT CAN_F5R1_FB11_Msk SDIO_STA_STBITERR_Pos CAN_F8R1_FB30 CAN_F7R1_FB1_Msk RTC_DIVL_RTC_DIV_Msk CAN_F0R1_FB22_Pos CAN_TDL0R_DATA3 ADC_SQR1_SQ15_2 TIM3 +syn keyword CTagsDefinedName CAN_F8R2_FB22_Pos CAN_F13R1_FB20 CAN_F4R1_FB24_Msk EXTI_IMR_IM5 CAN_F6R2_FB23_Msk TIM_SMCR_ETF_0 DMA_ISR_HTIF4_Msk GPIO_BSRR_BR14_Msk GPIO_BSRR_BR12_Msk CAN_F0R2_FB5 SDIO_STA_RXOVERR_Pos RCC_CFGR_HPRE USB_ISTR_DIR_Msk CAN_F1R1_FB22_Pos GPIO_BRR_BR5 GPIO_BSRR_BS11_Pos GPIO_CRH_CNF11_0 CAN_F4R1_FB5_Pos CAN_F9R1_FB23 CAN_F0R1_FB17_Msk CAN_FS1R_FSC7_Pos RCC_CFGR_HPRE_DIV256 EXTI_IMR_MR12_Msk GPIO_BRR_BR15_Msk SPI_CR1_CPHA_Pos CAN_F8R1_FB17_Pos CAN_TDH1R_DATA5 +syn keyword CTagsDefinedName DBGMCU_IDCODE_REV_ID_12 CAN_F12R1_FB8 CAN_TDL2R_DATA1 CAN_F11R2_FB30 TIM_CCER_CC2NP_Msk CAN_F10R1_FB0_Msk CAN_F6R2_FB5_Pos CAN_IER_BOFIE CAN_F10R1_FB21_Pos CAN_F2R1_FB16_Msk ADC_SMPR2_SMP7_1 CAN_ESR_EWGF_Msk SDIO_CMD_ENCMDCOMPL_Pos EXTI_SWIER_SWI13 DMA_IFCR_CTCIF4 GPIO_CRH_MODE9_0 CAN_F11R2_FB2 PIN_OPT_IRQ_EDGE_BOTH USART_CR1_RWU_Msk SPI1 ADC_SQR1_L CAN_F9R1_FB6_Pos ADC_SQR1_SQ15_0 USB_COUNT7_RX_NUM_BLOCK_Pos CAN_F11R1_FB27 ADC_SMPR1_SMP11_Pos USB_EP_SETUP GPIO_LCKR_LCK0_Msk +syn keyword CTagsDefinedName TIM_CCER_CC1P_Msk TIM_EGR_CC4G_Msk ADC_CR1_JDISCEN_Pos CAN_F5R1_FB5 SPI_SR_TXE_Pos EXTI_PR_PR15 ADC12_COMMON AFIO_EXTICR4_EXTI12_PF SDIO_STA_CTIMEOUT_Msk EXTI_EMR_MR9 CAN_F12R2_FB17_Msk ADC_JDR1_JDATA_Msk USB_FNR_FN_Msk CAN_F1R2_FB19_Pos I2C_OAR1_ADD2_Pos ADC_SR_JEOS_Pos I2C_SR2_SMBHOST_Pos IWDG_PR_PR_Msk PWR_CR_PLS_2V3 AFIO_EXTICR2_EXTI4_PE_Msk RTC_CNTL_RTC_CNT_Pos DMA_IFCR_CTEIF2_Pos ADC_SMPR1_SMP11_0 WWDG_CFR_W_0 AFIO_EXTICR3_EXTI8_PG_Pos BKP_RTCCR_ASOE_Msk CAN_F4R1_FB27_Msk +syn keyword CTagsDefinedName CAN_F5R1_FB27 CAN_F12R1_FB8_Msk TIM_EGR_UG SDIO_STA_TXACT CAN_F9R2_FB6_Msk CAN_F9R2_FB2 EXTI_EMR_MR18_Msk CAN_F3R1_FB30_Msk CAN_MSR_SAMP I2C_CR2_ITBUFEN_Pos EXTI_SWIER_SWIER15_Pos EXTI_FTSR_TR6 PWR_CR_PLS_Pos WWDG_CFR_WDGTB_Pos CAN_F10R1_FB9 PIN_OPT_RESISTOR_PULLUP CAN_F1R2_FB8 CAN_F11R2_FB24_Pos DMA_IFCR_CHTIF5_Pos RCC_CFGR_ADCPRE_DIV2 USART_CR3_HDSEL_Pos DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos CAN_F9R2_FB10_Msk DMA_IFCR_CTCIF1 IWDG_KR_KEY_Pos ADC_JSQR_JSQ2 CAN_F9R2_FB24_Msk +syn keyword CTagsDefinedName GPIO_BSRR_BR2 USB_COUNT4_RX_0_NUM_BLOCK_0_3 CAN_F13R1_FB21_Msk SDIO_MASK_TXACTIE PWR DBGMCU_CR_DBG_STOP_Msk USB_EP7R_DTOG_RX CAN_RDL1R_DATA3_Pos CAN_F3R2_FB0 CAN_F1R2_FB30 TIM_CCMR2_IC3F_3 RCC_CFGR_HPRE_2 ADC_JDR4_JDATA_Pos TIM_CCMR1_OC1PE_Pos USB_COUNT0_RX_1_NUM_BLOCK_1_3 CAN_F11R2_FB12 ADC_SMPR2_SMP3_2 USB_COUNT4_RX_BLSIZE_Msk TIM1_TRG_COM_TIM17_IRQn RCC_CFGR_HPRE_DIV_256 CAN_F3R2_FB3_Msk CAN_F5R1_FB20 USART_GTPR_GT_Msk USB_EP5R_STAT_TX_1 CAN_F13R2_FB19_Msk CAN_F10R2_FB17_Pos +syn keyword CTagsDefinedName DMA_IFCR_CHTIF3_Pos EXTI_EMR_EM11 CAN_TI0R_EXID CAN_F11R2_FB3_Msk DMA_CCR_TEIE_Msk SPI_CR1_BR_2 ADC_SMPR2_SMP0_Pos CAN_F7R2_FB5_Pos CAN_F1R2_FB6 GPIO_LCKR_LCK10_Pos AFIO_EXTICR3_EXTI9_Pos GPIO_CRL_MODE5 TIM_CCER_CC1P_Pos CAN_F2R2_FB12 CAN_F12R2_FB2 AFIO_EXTICR2_EXTI6_PC_Msk CAN_F12R2_FB1_Msk CAN_F9R2_FB16 AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk CAN_FM1R_FBM1 RCC_CFGR_MCOSEL_HSE TIM1_TRG_COM_TIM11_IRQn ADC_SQR3_SQ5_2 GPIO_BRR_BR6 CAN_F8R1_FB17_Msk USB_EP6R_EP_TYPE_1 +syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PG USB_CNTR_PDWN_Pos AFIO_EXTICR3_EXTI11_PG_Msk FLASH_CR_OPTWRE RCC_CR_PLLON I2C_CR2_FREQ_0 AFIO_MAPR_TIM2_REMAP_1 USB_EP5R_CTR_RX CAN_F13R2_FB24_Pos CAN_F1R1_FB27_Msk RTC_ALRL_RTC_ALR_Pos CAN_F13R1_FB2 CAN_F10R1_FB31_Msk CAN_ESR_REC FLASH_OBR_IWDG_SW_Msk AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk CAN_MCR_NART_Pos USB_EP3R_STAT_TX_1 CAN_F5R2_FB24_Pos TIM_DIER_BIE_Msk USART_CR1_TCIE_Msk _TIMER_H_ AFIO_EVCR_PORT_PB PIN_6 CAN_F2R1_FB21_Pos AFIO_EXTICR4_EXTI14_PD_Msk +syn keyword CTagsDefinedName AFIO_MAPR_USART3_REMAP_PARTIALREMAP CAN_F8R1_FB11 CAN_F8R2_FB18_Pos EXTI_RTSR_TR18 ADC_SMPR2_SMP4 GPIO_BSRR_BS15_Pos EXTI_SWIER_SWI8 EXTI_PR_PR7_Pos EXTI_SWIER_SWIER3 CAN_F1R1_FB4 CAN_F6R1_FB27_Msk RTC_CRL_OWF_Msk CAN_RDH0R_DATA4_Pos FLASH_WRP1_nWRP1 USART_CR1_IDLEIE_Msk CAN_F13R2_FB23_Pos CAN_F5R1_FB28 USB_EP_KIND_Msk RCC_APB1RSTR_WWDGRST_Msk CAN_F13R1_FB2_Pos DMA_ISR_TCIF4_Pos RCC_CR_HSIRDY CAN_IER_WKUIE_Pos CAN_RF0R_FMP0_Pos ADC_CR1_DISCNUM_1 RCC_CR_HSEON_Msk +syn keyword CTagsDefinedName CAN_RI0R_EXID_Msk EXTI_FTSR_TR15 SDIO_MASK_RXOVERRIE_Msk AFIO_EXTICR2_EXTI7_PF USB_EP7R_STAT_RX_Msk GPIO_CRH_MODE11_Pos USB_EP7R_EP_TYPE_Msk USART_CR2_LBCL CAN_F0R2_FB28 DMA_CCR_EN_Pos CAN_F3R2_FB0_Msk CAN_TDT0R_TIME_Msk CAN_F11R1_FB3_Msk EXTI_EMR_MR2_Pos ADC_JDR2_JDATA_Pos CAN_F6R2_FB9_Pos SDIO_ICR_DCRCFAILC_Msk EXTI_SWIER_SWIER11_Pos EXTI_EMR_MR14_Msk AFIO_EXTICR4_EXTI15_PE_Msk USB_COUNT5_RX_NUM_BLOCK_Pos CAN_F10R1_FB26_Pos DBGMCU_CR_DBG_TIM2_STOP CAN_F1R2_FB29_Msk +syn keyword CTagsDefinedName CAN_F9R1_FB13_Msk RCC_CR_HSIRDY_Pos USB_EP_RX_VALID CAN_F6R2_FB7_Pos GPIO_BSRR_BS7 TIM_CNT_CNT USB_EP5R_STAT_RX_0 FLASH_ACR_LATENCY_1 EXTI_IMR_MR0 CAN_F5R1_FB1_Pos CAN_F4R2_FB26 CAN_F5R1_FB15_Msk CAN_F1R1_FB22 CAN_F5R1_FB10_Msk CAN_F7R2_FB13_Pos DBGMCU_CR_DBG_TIM2_STOP_Msk EXTI_IMR_MR16_Msk RTC_DIVL_RTC_DIV_Pos RCC_CFGR_MCO_SYSCLK CAN_F9R1_FB15_Msk RCC_CFGR_MCOSEL_2 CAN_F7R2_FB14_Msk CAN_F6R1_FB1_Pos SDIO_STA_DCRCFAIL CAN_F0R1_FB5_Msk ADC_SQR2_SQ9_1 CAN_TSR_TERR1 +syn keyword CTagsDefinedName SPI_CR1_LSBFIRST CAN_TDH1R_DATA4 CAN_F5R2_FB3_Pos CAN_F7R1_FB29_Pos CAN_FM1R_FBM1_Msk GPIO_IDR_IDR15_Pos CAN_F7R2_FB14 USB_COUNT2_RX_NUM_BLOCK CAN_F8R2_FB23 TIM_CR1_DIR_Msk GPIO_CRH_MODE14_1 CAN_F7R1_FB6_Msk CAN_F11R1_FB23_Pos CAN_F13R2_FB12_Msk SPI_SR_MODF_Pos EXTI_EMR_MR6 CAN_F13R2_FB16 RCC_CIR_HSERDYC_Msk CAN_F9R2_FB29_Pos ADC_SR_JSTRT CAN_F1R2_FB23_Pos SPI_CR1_BR_1 CAN_F7R2_FB6_Msk CAN_F6R2_FB17 CAN_F10R1_FB8_Pos CAN_F6R1_FB2 RCC_AHBENR_FLITFEN_Msk CAN_FA1R_FACT13_Msk +syn keyword CTagsDefinedName USB_EP5R_STAT_RX_Msk RCC_APB2RSTR_TIM1RST_Pos CAN_F5R1_FB28_Pos I2C_CR1_ENARP_Pos USB_EP_SETUP_Msk CAN_F0R1_FB7_Pos CAN_F1R2_FB20 GPIO_IDR_IDR13 DMA_ISR_TEIF1_Msk I2C_SR1_ARLO AFIO_EXTICR4_EXTI12_PB_Msk PIN_OPT_AF5 TIM_CR1_ARPE_Msk PWM_CHANNEL_2 CAN_F5R1_FB23_Msk SPI_SR_CRCERR_Pos CAN_F10R1_FB16_Pos USB_COUNT1_RX_1_NUM_BLOCK_1_0 RCC_CFGR_PLLMULL6 CAN_TI2R_IDE CAN_F11R2_FB3 CAN_F9R2_FB28_Pos CAN_FM1R_FBM0_Msk GPIO_CRL_CNF4_Pos CAN_ESR_BOFF_Msk RCC_APB2RSTR_USART1RST_Pos +syn keyword CTagsDefinedName ADC_JDR2_JDATA_Msk SDIO_MASK_CCRCFAILIE_Pos BKP_DR8_D_Msk TIM_CR2_OIS2N_Msk CAN_F9R1_FB18 SDIO_STA_CMDACT_Pos USART_GTPR_GT_Pos CAN_F8R2_FB16 PWR_CR_PVDE_Msk USART_CR3_IRLP_Pos SDIO_POWER_PWRCTRL_Pos GPIOD GPIO_ODR_ODR7 RCC_CIR_LSERDYF USB_DADDR_ADD_Pos RCC_CFGR_PLLMULL10_Pos CAN_RDH1R_DATA4_Pos GPIO_BRR_BR0_Msk ADC_SR_STRT_Pos AFIO_EXTICR2_EXTI6_PE_Pos CAN_F2R1_FB3 CAN_F6R1_FB22_Pos CAN_F10R2_FB4_Pos CAN_F12R1_FB31_Pos CAN_F8R2_FB26_Msk CAN_F12R2_FB2_Msk CAN_F10R2_FB11 +syn keyword CTagsDefinedName USB_COUNT1_RX_NUM_BLOCK ADC_CR2_EXTTRIG CAN_F6R2_FB22_Pos AFIO_MAPR_CAN_REMAP_0 +