Changed Memory to Peripheral

The "Memory" name  is too restrictive given that the bus itself
implement that trait.

src/bus.rs

@@ -1,6 +1,6 @@
 use std::fmt;
 
-use crate::memory::{Memory, Ram};
+use crate::peripherals::{Peripheral, Ram};
 
 pub struct Bus {
     ram: Ram<0x800>,
@@ -18,7 +18,7 @@ impl fmt::Debug for Bus {
     }
 }
 
-impl Memory for Bus {
+impl Peripheral for Bus {
 
     fn read_addr(&self, addr: u16) -> u8 {
         
@@ -127,7 +127,7 @@ impl fmt::Debug for FileBus {
     }
 }
 
-impl Memory for FileBus {
+impl Peripheral for FileBus {
 
     fn read_addr(&self, addr: u16) -> u8 {
         self.mem.read_addr(addr)    //RAM is mirrored 3 times

src/cpu.rs

@@ -5,7 +5,7 @@ use bitflags::bitflags;
 
 use crate::{
     bus::FileBus,
-    memory::Memory,
+    peripherals::Peripheral,
 };
 
 use std::fmt;
@@ -17,11 +17,11 @@ trait Input {
 }
 
 trait RInput: Input {
-    fn read<M: Memory>(&self, acc: &u8, bus: &M) -> u8;
+    fn read<M: Peripheral>(&self, acc: &u8, bus: &M) -> u8;
 }
 
 trait WInput: Input {
-    fn write<M: Memory>(&mut self, acc: &mut u8, bus: &mut M, data: u8);
+    fn write<M: Peripheral>(&mut self, acc: &mut u8, bus: &mut M, data: u8);
 }
 
 trait RWInput: RInput + WInput {}
@@ -33,11 +33,11 @@ impl Input for Accumulator {
 }
 
 impl RInput for Accumulator {
-    fn read<M: Memory>(&self, acc: &u8, _bus: &M) -> u8 { *acc }
+    fn read<M: Peripheral>(&self, acc: &u8, _bus: &M) -> u8 { *acc }
 }
 
 impl WInput for Accumulator {
-    fn write<M: Memory>(&mut self, acc: &mut u8, _bus: &mut M, data: u8) { *acc = data }
+    fn write<M: Peripheral>(&mut self, acc: &mut u8, _bus: &mut M, data: u8) { *acc = data }
 }
 
 impl RWInput for Accumulator {}
@@ -51,7 +51,7 @@ impl Input for Data {
 }
 
 impl RInput for Data {
-    fn read<M: Memory>(&self, _acc: &u8, _bus: &M) -> u8 { self.data }
+    fn read<M: Peripheral>(&self, _acc: &u8, _bus: &M) -> u8 { self.data }
 }
 
 struct MemoryVal {
@@ -64,13 +64,13 @@ impl Input for MemoryVal {
 }
 
 impl RInput for MemoryVal {
-    fn read<M: Memory>(&self, _acc: &u8, bus: &M) -> u8 {
+    fn read<M: Peripheral>(&self, _acc: &u8, bus: &M) -> u8 {
         bus.read_addr(self.addr)
     }
 }
 
 impl WInput for MemoryVal {
-    fn write<M: Memory>(&mut self, _acc: &mut u8, bus: &mut M, data: u8) {
+    fn write<M: Peripheral>(&mut self, _acc: &mut u8, bus: &mut M, data: u8) {
         bus.write_addr(self.addr, data);
     }
 }
@@ -93,13 +93,13 @@ impl Input for MemoryValExtra {
 }
 
 impl RInput for MemoryValExtra {
-    fn read<M: Memory>(&self, _acc: &u8, bus: &M) -> u8 {
+    fn read<M: Peripheral>(&self, _acc: &u8, bus: &M) -> u8 {
         bus.read_addr(self.addr)
     }
 }
 
 impl WInput for MemoryValExtra {
-    fn write<M: Memory>(&mut self, _acc: &mut u8, bus: &mut M, data: u8) {
+    fn write<M: Peripheral>(&mut self, _acc: &mut u8, bus: &mut M, data: u8) {
         bus.write_addr(self.addr, data);
 
         self.extra_cycle = true;

src/main.rs

@@ -5,7 +5,7 @@ mod cpu;
 use cpu::Cpu;
 
 mod bus;
-mod memory;
+mod peripherals;
 mod utils;
 
 fn main() -> Result<(), &'static str> {

src/peripherals.rs

@@ -1,7 +1,7 @@
 use std::fmt;
 
 //--------------------------------------------------------------------------------------------------
-pub trait Memory {
+pub trait Peripheral {
 
     fn read_addr(&self, addr: u16) -> u8;
 
@@ -27,7 +27,7 @@ impl<const SIZE: usize> fmt::Debug for Ram<SIZE> {
     }
 }
 
-impl<const SIZE: usize> Memory for Ram<SIZE> {
+impl<const SIZE: usize> Peripheral for Ram<SIZE> {
 
     fn read_addr(&self, addr: u16) -> u8 {
         self.buffer[addr as usize]