From 0628c4c07ce89ee8130b05b608d0c2a4b6be3a2f Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 18:35:36 +0200 Subject: [PATCH] Use TC instead of TXE Transfer Complete is preferable to TX Empty when using a DMA since we could be polling the bit between transfers. TXE would be 1 but the DMA would be transfering another at the same time. TC takes the DMA into account --- drv/usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drv/usart.c b/drv/usart.c index 800235b..4901ed2 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -107,7 +107,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) if (buffer->buffers) { //if the tx register is empty, there is no need to go through the dma - if (regs->SR.TXE) { + if (regs->SR.TC) { reg_write(regs->DR, USART_DR_DR, byte); //enable IRQ, disable DMA reg_reset(regs->CR3, USART_CR3_DMAT);