From 2f40111dbb2f9d06ec86cf30b951ba5e00ed28e0 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 20:53:30 +0200 Subject: [PATCH] Create gpio's register map --- drivers/gpio_regs.h | 215 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 drivers/gpio_regs.h diff --git a/drivers/gpio_regs.h b/drivers/gpio_regs.h new file mode 100644 index 0000000..5ab539b --- /dev/null +++ b/drivers/gpio_regs.h @@ -0,0 +1,215 @@ +/** @file gpio_regs.h + * Module defining the GPIO registers. + * + * Mainly made to be used by the gpio module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define GPIO_BASE_ADDRESS 0x40010800 + +union GPIO_CRL { + struct __attribute__((packed)) { + uint32_t MODE0:2; + uint32_t CNF0:2; + uint32_t MODE1:2; + uint32_t CNF1:2; + uint32_t MODE2:2; + uint32_t CNF2:2; + uint32_t MODE3:2; + uint32_t CNF3:2; + uint32_t MODE4:2; + uint32_t CNF4:2; + uint32_t MODE5:2; + uint32_t CNF5:2; + uint32_t MODE6:2; + uint32_t CNF6:2; + uint32_t MODE7:2; + uint32_t CNF7:2; + }; + uint32_t word; +}; + +union GPIO_CRH { + struct __attribute__((packed)) { + uint32_t MODE8:2; + uint32_t CNF8:2; + uint32_t MODE9:2; + uint32_t CNF9:2; + uint32_t MODE10:2; + uint32_t CNF10:2; + uint32_t MODE11:2; + uint32_t CNF11:2; + uint32_t MODE12:2; + uint32_t CNF12:2; + uint32_t MODE13:2; + uint32_t CNF13:2; + uint32_t MODE14:2; + uint32_t CNF14:2; + uint32_t MODE15:2; + uint32_t CNF15:2; + }; + uint32_t word; +}; + +union GPIO_IDR { + struct __attribute__((packed)) { + uint32_t IDR0:1; + uint32_t IDR1:1; + uint32_t IDR2:1; + uint32_t IDR3:1; + uint32_t IDR4:1; + uint32_t IDR5:1; + uint32_t IDR6:1; + uint32_t IDR7:1; + uint32_t IDR8:1; + uint32_t IDR9:1; + uint32_t IDR10:1; + uint32_t IDR11:1; + uint32_t IDR12:1; + uint32_t IDR13:1; + uint32_t IDR14:1; + uint32_t IDR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_ODR { + struct __attribute__((packed)) { + uint32_t ODR0:1; + uint32_t ODR1:1; + uint32_t ODR2:1; + uint32_t ODR3:1; + uint32_t ODR4:1; + uint32_t ODR5:1; + uint32_t ODR6:1; + uint32_t ODR7:1; + uint32_t ODR8:1; + uint32_t ODR9:1; + uint32_t ODR10:1; + uint32_t ODR11:1; + uint32_t ODR12:1; + uint32_t ODR13:1; + uint32_t ODR14:1; + uint32_t ODR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_BSRR { + struct __attribute__((packed)) { + uint32_t BS0:1; + uint32_t BS1:1; + uint32_t BS2:1; + uint32_t BS3:1; + uint32_t BS4:1; + uint32_t BS5:1; + uint32_t BS6:1; + uint32_t BS7:1; + uint32_t BS8:1; + uint32_t BS9:1; + uint32_t BS10:1; + uint32_t BS11:1; + uint32_t BS12:1; + uint32_t BS13:1; + uint32_t BS14:1; + uint32_t BS15:1; + uint32_t BR0:1; + uint32_t BR1:1; + uint32_t BR2:1; + uint32_t BR3:1; + uint32_t BR4:1; + uint32_t BR5:1; + uint32_t BR6:1; + uint32_t BR7:1; + uint32_t BR8:1; + uint32_t BR9:1; + uint32_t BR10:1; + uint32_t BR11:1; + uint32_t BR12:1; + uint32_t BR13:1; + uint32_t BR14:1; + uint32_t BR15:1; + }; + uint32_t word; +}; + +union GPIO_BRR { + struct __attribute__((packed)) { + uint32_t BR0:1; + uint32_t BR1:1; + uint32_t BR2:1; + uint32_t BR3:1; + uint32_t BR4:1; + uint32_t BR5:1; + uint32_t BR6:1; + uint32_t BR7:1; + uint32_t BR8:1; + uint32_t BR9:1; + uint32_t BR10:1; + uint32_t BR11:1; + uint32_t BR12:1; + uint32_t BR13:1; + uint32_t BR14:1; + uint32_t BR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_LCKK { + struct __attribute__((packed)) { + uint32_t LCK0:1; + uint32_t LCK1:1; + uint32_t LCK2:1; + uint32_t LCK3:1; + uint32_t LCK4:1; + uint32_t LCK5:1; + uint32_t LCK6:1; + uint32_t LCK7:1; + uint32_t LCK8:1; + uint32_t LCK9:1; + uint32_t LCK10:1; + uint32_t LCK11:1; + uint32_t LCK12:1; + uint32_t LCK13:1; + uint32_t LCK14:1; + uint32_t LCK15:1; + uint32_t LCKK:1; + uint32_t reserved1:15; + }; + uint32_t word; +}; + +struct __attribute__((packed)) GPIO_PORT { + union GPIO_CRL CRL; + union GPIO_CRH CRH; + union GPIO_IDR IDR; + union GPIO_ODR ODR; + union GPIO_BSRR BSRR; + union GPIO_BRR BRR; + union GPIO_LCKK LCKK; + uint32_t reserved1[249]; +}; + +struct __attribute__((packed)) GPIO { + struct GPIO_PORT PORTS[7]; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_GPIO_REGS_H_ +