Cleanup dma's configuration code
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parent
12c0b16b39
commit
43cdb55c48
@ -13,21 +13,22 @@
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#include "nvic.h"
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#include "rcc.h"
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#include "stddef.h"
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//--local definitions-----------------------------------------------------------
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static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel,
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enum DmaConfig config_mask, void* periph, void* mem,
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uint16_t size);
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static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs);
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//--local variables-------------------------------------------------------------
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static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS;
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static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS;
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static DmaCallback dm1_callbacks[7];
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static DmaCallback dm2_callbacks[5];
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static DmaCallback dma1_callbacks[7];
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static DmaCallback dma2_callbacks[5];
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//--public functions------------------------------------------------------------
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@ -44,7 +45,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
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rcc_enable(RCC_AHB_DMA1, RCC_APB1_NONE, RCC_APB2_NONE);
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configure_dma(dma1, channel, config_mask, periph, mem, size);
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if (callback) {
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dm1_callbacks[channel] = callback;
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dma1_callbacks[channel] = callback;
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nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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}
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break;
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@ -52,7 +53,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
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rcc_enable(RCC_AHB_DMA2, RCC_APB1_NONE, RCC_APB2_NONE);
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configure_dma(dma2, channel, config_mask, periph, mem, size);
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if (callback) {
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dm2_callbacks[channel] = callback;
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dma2_callbacks[channel] = callback;
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nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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}
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break;
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@ -69,10 +70,12 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel)
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switch (dma) {
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case DMA_PERIPH_1:
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periph = dma1;
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dma1_callbacks[channel] = NULL;
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nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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break;
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case DMA_PERIPH_2:
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periph = dma2;
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dma2_callbacks[channel] = NULL;
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nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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break;
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default:
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@ -88,6 +91,48 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel)
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regs->CPAR = 0;
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}
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void dma_enable(enum DmaPeriph dma, enum DmaChannel channel)
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{
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switch (dma) {
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case DMA_PERIPH_1:
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reg_set(dma1->CHANNELS[channel].CCR, DMA_CCR_EN);
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if (dma1_callbacks[channel]) {
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nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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}
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break;
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case DMA_PERIPH_2:
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reg_set(dma2->CHANNELS[channel].CCR, DMA_CCR_EN);
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if (dma2_callbacks[channel]) {
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nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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}
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break;
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default:
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return;
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break;
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}
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}
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void dma_disable(enum DmaPeriph dma, enum DmaChannel channel)
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{
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switch (dma) {
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case DMA_PERIPH_1:
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reg_reset(dma1->CHANNELS[channel].CCR, DMA_CCR_EN);
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if (dma1_callbacks[channel]) {
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nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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}
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break;
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case DMA_PERIPH_2:
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reg_reset(dma2->CHANNELS[channel].CCR, DMA_CCR_EN);
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if (dma2_callbacks[channel]) {
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nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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}
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break;
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default:
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return;
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break;
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}
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}
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//--local functions-------------------------------------------------------------
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@ -107,23 +152,6 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel,
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reg_set(regs->CCR, DMA_CCR_EN);
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}
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static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs)
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{
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switch (periph) {
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case DMA_PERIPH_1:
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*regs = dma1;
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break;
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case DMA_PERIPH_2:
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*regs = dma2;
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break;
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default:
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return 1;
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break;
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}
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return 0;
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}
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//--ISRs------------------------------------------------------------------------
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@ -134,7 +162,7 @@ void hdr_dma1_channel1(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF1);
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dm1_callbacks[0](src);
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dma1_callbacks[0](src);
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}
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void hdr_dma1_channel2(void)
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@ -144,7 +172,7 @@ void hdr_dma1_channel2(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF2);
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dm1_callbacks[1](src);
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dma1_callbacks[1](src);
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}
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void hdr_dma1_channel3(void)
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@ -154,7 +182,7 @@ void hdr_dma1_channel3(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF3);
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dm1_callbacks[2](src);
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dma1_callbacks[2](src);
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}
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void hdr_dma1_channel4(void)
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@ -164,7 +192,7 @@ void hdr_dma1_channel4(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF4);
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dm1_callbacks[3](src);
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dma1_callbacks[3](src);
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}
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void hdr_dma1_channel5(void)
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@ -174,7 +202,7 @@ void hdr_dma1_channel5(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF5);
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dm1_callbacks[4](src);
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dma1_callbacks[4](src);
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}
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void hdr_dma1_channel6(void)
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@ -184,7 +212,7 @@ void hdr_dma1_channel6(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF6);
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dm1_callbacks[5](src);
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dma1_callbacks[5](src);
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}
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void hdr_dma1_channel7(void)
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@ -194,7 +222,7 @@ void hdr_dma1_channel7(void)
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enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF7);
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dm1_callbacks[6](src);
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dma1_callbacks[6](src);
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}
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void hdr_dma2_channel1(void)
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@ -204,7 +232,7 @@ void hdr_dma2_channel1(void)
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enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF1);
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dm1_callbacks[0](src);
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dma1_callbacks[0](src);
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}
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void hdr_dma2_channel2(void)
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@ -214,7 +242,7 @@ void hdr_dma2_channel2(void)
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enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF2);
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dm2_callbacks[1](src);
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dma2_callbacks[1](src);
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}
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void hdr_dma2_channel3(void)
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@ -224,7 +252,7 @@ void hdr_dma2_channel3(void)
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enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF3);
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dm2_callbacks[2](src);
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dma2_callbacks[2](src);
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}
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void hdr_dma2_channel4_5(void)
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@ -234,13 +262,13 @@ void hdr_dma2_channel4_5(void)
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enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7;
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if (src != 0) {
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reg_set(dma2->IFCR, DMA_IFCR_CGIF4);
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dm1_callbacks[3](src);
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dma1_callbacks[3](src);
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}
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src = (dma2->IFCR.word >> 17) & 0x7;
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if (src != 0) {
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reg_set(dma2->IFCR, DMA_IFCR_CGIF5);
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dm1_callbacks[4](src);
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dma1_callbacks[4](src);
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}
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}
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