Implement dma's basic functions
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6ddc2266e1
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45452ce49e
246
drivers/dma.c
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246
drivers/dma.c
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/** @file dma.h
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* Module handling Direct Memory Access controller
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*
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* The module provides functions to configure the dma channels and controller
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* transfers
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*/
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//--includes--------------------------------------------------------------------
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#include "dma.h"
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#include "dma_regs.h"
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#include "nvic.h"
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#include "rcc.h"
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//--local definitions-----------------------------------------------------------
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static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel,
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enum DmaConfig config_mask, void* periph, void* mem,
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uint16_t size);
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static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs);
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//--local variables-------------------------------------------------------------
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static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS;
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static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS;
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static DmaCallback dm1_callbacks[7];
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static DmaCallback dm2_callbacks[5];
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//--public functions------------------------------------------------------------
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void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
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enum DmaConfig config_mask, void* periph, void* mem,
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uint16_t size, DmaCallback callback)
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{
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//reset peripheral first, to ensure proper configuration
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dma_reset(dma, channel);
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switch (dma) {
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case DMA_PERIPH_1:
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rcc_enable(RCC_AHB_DMA1, RCC_APB1_NONE, RCC_APB2_NONE);
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configure_dma(dma1, channel, config_mask, periph, mem, size);
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if (callback) {
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dm1_callbacks[channel] = callback;
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nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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}
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break;
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case DMA_PERIPH_2:
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rcc_enable(RCC_AHB_DMA2, RCC_APB1_NONE, RCC_APB2_NONE);
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configure_dma(dma2, channel, config_mask, periph, mem, size);
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if (callback) {
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dm2_callbacks[channel] = callback;
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nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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}
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break;
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default:
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break;
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}
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}
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void dma_reset(enum DmaPeriph dma, enum DmaChannel channel)
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{
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volatile struct DMA* periph;
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//first, disable IRQs
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switch (dma) {
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case DMA_PERIPH_1:
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periph = dma1;
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nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
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break;
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case DMA_PERIPH_2:
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periph = dma2;
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nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
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break;
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default:
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return;
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break;
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}
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//then, set all registers to reset value
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volatile struct DMA_CHANNEL* regs = &periph->CHANNELS[channel];
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regs->CCR.word = 0;
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regs->CNDTR.word = 0;
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regs->CMAR = 0;
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regs->CPAR = 0;
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}
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//--local functions-------------------------------------------------------------
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static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel,
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enum DmaConfig config_mask, void* periph, void* mem,
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uint16_t size)
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{
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volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel];
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//registers should already be at reset value, apply new config
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regs->CCR.word = config_mask;
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reg_write(regs->CNDTR, DMA_CNDTR_NDT, size);
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regs->CPAR = (uint32_t)periph;
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regs->CMAR = (uint32_t)mem;
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//only enable channel when everything is configured
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reg_set(regs->CCR, DMA_CCR_EN);
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}
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static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs)
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{
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switch (periph) {
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case DMA_PERIPH_1:
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*regs = dma1;
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break;
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case DMA_PERIPH_2:
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*regs = dma2;
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break;
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default:
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return 1;
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break;
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}
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return 0;
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}
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//--ISRs------------------------------------------------------------------------
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void hdr_dma1_channel1(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL1);
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enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF1);
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dm1_callbacks[0](src);
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}
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void hdr_dma1_channel2(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL2);
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enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF2);
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dm1_callbacks[1](src);
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}
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void hdr_dma1_channel3(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL3);
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enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF3);
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dm1_callbacks[2](src);
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}
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void hdr_dma1_channel4(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL4);
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enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF4);
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dm1_callbacks[3](src);
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}
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void hdr_dma1_channel5(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL5);
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enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF5);
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dm1_callbacks[4](src);
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}
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void hdr_dma1_channel6(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL6);
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enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF6);
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dm1_callbacks[5](src);
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}
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void hdr_dma1_channel7(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL7);
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enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7;
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reg_set(dma1->IFCR, DMA_IFCR_CGIF7);
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dm1_callbacks[6](src);
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}
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void hdr_dma2_channel1(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL1);
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enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF1);
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dm1_callbacks[0](src);
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}
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void hdr_dma2_channel2(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL2);
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enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF2);
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dm2_callbacks[1](src);
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}
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void hdr_dma2_channel3(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL3);
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enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7;
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reg_set(dma2->IFCR, DMA_IFCR_CGIF3);
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dm2_callbacks[2](src);
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}
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void hdr_dma2_channel4_5(void)
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{
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nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL4_5);
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enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7;
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if (src != 0) {
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reg_set(dma2->IFCR, DMA_IFCR_CGIF4);
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dm1_callbacks[3](src);
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}
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src = (dma2->IFCR.word >> 17) & 0x7;
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if (src != 0) {
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reg_set(dma2->IFCR, DMA_IFCR_CGIF5);
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dm1_callbacks[4](src);
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}
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}
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99
drivers/dma.h
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99
drivers/dma.h
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@ -0,0 +1,99 @@
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/** @file dma.h
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* Module handling Direct Memory Access controller
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*
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* The module provides functions to configure the dma channels and controller
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* transfers
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*/
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#ifndef _DMA_H_
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#define _DMA_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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//--type definitions------------------------------------------------------------
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enum DmaPeriph {
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DMA_PERIPH_1,
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DMA_PERIPH_2,
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};
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enum DmaChannel {
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DMA_CHANNEL_1 = 0,
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DMA_CHANNEL_2,
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DMA_CHANNEL_3,
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DMA_CHANNEL_4,
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DMA_CHANNEL_5,
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DMA_CHANNEL_6, //not available for DMA 2
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DMA_CHANNEL_7, //not available for DMA 2
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};
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enum DmaConfig {
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DMA_CONFIG_IRQ_COMPLETE = (0x1 << 1),
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DMA_CONFIG_IRQ_HALF = (0x1 << 2),
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DMA_CONFIG_IRQ_ERROR = (0x1 << 3),
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DMA_CONFIG_FROM_MEM = (0x1 << 4),
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DMA_CONFIG_FROM_PERIPH = (0x0 << 4),
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DMA_CONFIG_CIRCULAR = (0x1 << 5),
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DMA_CONFIG_INC_PERIPH = (0x1 << 6),
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DMA_CONFIG_INC_MEM = (0x1 << 7),
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DMA_CONFIG_PSIZE_8BITS = (0x0 << 8),
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DMA_CONFIG_PSIZE_16BITS = (0x1 << 8),
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DMA_CONFIG_PSIZE_32BITS = (0x2 << 8),
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DMA_CONFIG_MSIZE_8BITS = (0x0 << 10),
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DMA_CONFIG_MSIZE_16BITS = (0x1 << 10),
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DMA_CONFIG_MSIZE_32BITS = (0x2 << 10),
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DMA_CONFIG_PRIO_LOW = (0x0 << 12),
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DMA_CONFIG_PRIO_MEDIUM = (0x1 << 12),
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DMA_CONFIG_PRIO_HIGH = (0x2 << 12),
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DMA_CONFIG_PRIO_VHIGH = (0x3 << 12),
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};
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enum DmaConfigM2M {
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DMA_CONFIG_M2M_IRQ_COMPLETE = (0x1 << 1),
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DMA_CONFIG_M2M_IRQ_HALF = (0x1 << 2),
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DMA_CONFIG_M2M_IRQ_ERROR = (0x1 << 3),
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DMA_CONFIG_M2M_INC_SRC = (0x1 << 6),
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DMA_CONFIG_M2M_INC_DEST = (0x1 << 7),
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DMA_CONFIG_M2M_SSIZE_8BITS = (0x0 << 8),
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DMA_CONFIG_M2M_SSIZE_16BITS = (0x1 << 8),
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DMA_CONFIG_M2M_SSIZE_32BITS = (0x2 << 8),
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DMA_CONFIG_M2M_DSIZE_8BITS = (0x0 << 10),
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DMA_CONFIG_M2M_DSIZE_16BITS = (0x1 << 10),
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DMA_CONFIG_M2M_DSIZE_32BITS = (0x2 << 10),
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DMA_CONFIG_M2M_PRIO_LOW = (0x0 << 12),
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DMA_CONFIG_M2M_PRIO_MEDIUM = (0x1 << 12),
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DMA_CONFIG_M2M_PRIO_HIGH = (0x2 << 12),
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DMA_CONFIG_M2M_PRIO_VHIGH = (0x3 << 12),
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};
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enum DmaIRQSource {
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DMA_IRQ_SOURCE_COMPLETE = (0x1 << 1),
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DMA_IRQ_SOURCE_HALF = (0x1 << 2),
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DMA_IQR_SOURCE_ERROR = (0x2 << 3),
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};
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typedef void (*DmaCallback)(enum DmaIRQSource);
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//--functions-------------------------------------------------------------------
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void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
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enum DmaConfig config_mask, void* periph, void* mem,
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uint16_t size, DmaCallback callback);
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void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel,
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enum DmaConfigM2M config_mask, const void* src, void* dest,
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uint16_t size, DmaCallback callback);
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void dma_reset(enum DmaPeriph dma, enum DmaChannel channel);
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void dma_enable(enum DmaPeriph dma, enum DmaChannel channel);
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void dma_disable(enum DmaPeriph dma, enum DmaChannel channel);
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#endif //_DMA_H_
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