From 50dc10b76e0de904727eaae263bcbe614615d184 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 19 Mar 2023 21:57:37 +0100 Subject: [PATCH] Create RCC register map --- drivers/rcc_regs.h | 269 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 269 insertions(+) create mode 100644 drivers/rcc_regs.h diff --git a/drivers/rcc_regs.h b/drivers/rcc_regs.h new file mode 100644 index 0000000..8177b3e --- /dev/null +++ b/drivers/rcc_regs.h @@ -0,0 +1,269 @@ + +#ifndef _RCC_REGS_H_ +#define _RCC_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define RCC_BASE_ADDRESS 0x40021000 + +union RCC_CR { + struct __attribute__((packed)) { + uint32_t HSION:1; + uint32_t HSIRDY:1; + uint32_t reserved1:1; + uint32_t HSITRIM:5; + uint32_t HSICAL:8; + uint32_t HSEON:1; + uint32_t HSERDY:1; + uint32_t HSEBYP:1; + uint32_t CCSON:1; + uint32_t reserved2:4; + uint32_t PLLON:1; + uint32_t PLLRDY:1; + uint32_t reserved3:6; + }; + uint32_t word; +}; + +union RCC_CFGR { + struct __attribute__((packed)) { + uint32_t SW:2; + uint32_t SWS:2; + uint32_t HPRE:4; + uint32_t PPRE1:3; + uint32_t PPRE2:3; + uint32_t ADCPRE:2; + uint32_t PLLSCR:1; + uint32_t PLLXTPRE:1; + uint32_t PLLMUL:4; + uint32_t USBPRE:1; + uint32_t reserved1:1; + uint32_t MCO:3; + uint32_t reserved2:5; + }; + uint32_t word; +}; + +union RCC_CIR { + struct __attribute__((packed)) { + uint32_t LSIRDYF:1; + uint32_t LSERDYF:1; + uint32_t HSIRDYF:1; + uint32_t HSERDYF:1; + uint32_t PLLRDYF:1; + uint32_t reserved1:2; + uint32_t CSSF:1; + uint32_t LSIRDYIE:1; + uint32_t LSERDYIE:1; + uint32_t HSIRDYIE:1; + uint32_t HSERDYIE:1; + uint32_t PLLRDYIE:1; + uint32_t RSE2:3; + uint32_t LSIRDYC:1; + uint32_t LSERDYC:1; + uint32_t HSIRDYC:1; + uint32_t HSERDYC:1; + uint32_t PLLRDYC:1; + uint32_t reserved3:2; + uint32_t CSSC:1; + uint32_t reserved4:8; + }; + uint32_t word; +}; + +union RCC_APB2RSTR { + struct __attribute__((packed)) { + uint32_t AFIORST:1; + uint32_t reserved1:1; + uint32_t IOPARST:1; + uint32_t IOPBRST:1; + uint32_t IOPCRST:1; + uint32_t IOPDRST:1; + uint32_t IOPERST:1; + uint32_t IOPFRST:1; + uint32_t IOPGRST:1; + uint32_t ADC1RST:1; + uint32_t ACD2RST:1; + uint32_t TIM1RST:1; + uint32_t SPI1RST:1; + uint32_t TIM8RST:1; + uint32_t USART1RST:1; + uint32_t ADC3RST:1; + uint32_t reserved2:3; + uint32_t TIM9RST:1; + uint32_t TIM10RST:1; + uint32_t TIM11RST:1; + uint32_t reserved3:10; + }; + uint32_t word; +}; + +union RCC_APB1RSTR { + struct __attribute__((packed)) { + uint32_t TIM2RST:1; + uint32_t TIM3RST:1; + uint32_t TIM4RST:1; + uint32_t TIM5RST:1; + uint32_t TIM6RST:1; + uint32_t TIM7RST:1; + uint32_t TIM12RST:1; + uint32_t TIM13RST:1; + uint32_t TIM14RST:1; + uint32_t reserved1:2; + uint32_t WWDGRST:1; + uint32_t reserved2:2; + uint32_t SPI2RST:1; + uint32_t SPI3RST:1; + uint32_t reserved3:1; + uint32_t USART2RST:1; + uint32_t USART3RST:1; + uint32_t UART4RST:1; + uint32_t UART5RST:1; + uint32_t I2C12RST:1; + uint32_t I2C2RST:1; + uint32_t USB2RST:1; + uint32_t reserved4:1; + uint32_t CANRST:1; + uint32_t reserved5:1; + uint32_t BKPRST:1; + uint32_t PWRRST:1; + uint32_t DACRST:1; + uint32_t reserved6:2; + }; + uint32_t word; +}; + +union RCC_AHBENR { + struct __attribute__((packed)) { + uint32_t DMA1EN:1; + uint32_t DMA2EN:1; + uint32_t SRAMEN:1; + uint32_t reserved1:1; + uint32_t FLITFEN:1; + uint32_t reserved2:1; + uint32_t CRCEN:1; + uint32_t reserved3:1; + uint32_t FSMCEN:1; + uint32_t reserved4:1; + uint32_t SDIOEN:1; + uint32_t reserved5:21; + }; + uint32_t word; +}; + +union RCC_APB2ENR { + struct __attribute__((packed)) { + uint32_t AFIOEN:1; + uint32_t reserved1:1; + uint32_t IOPAEN:1; + uint32_t IOPBEN:1; + uint32_t IOPCEN:1; + uint32_t IOPDEN:1; + uint32_t IOPEEN:1; + uint32_t IOPFEN:1; + uint32_t IOPGEN:1; + uint32_t ADC1EN:1; + uint32_t ACD2EN:1; + uint32_t TIM1EN:1; + uint32_t SPI1EN:1; + uint32_t TIM8EN:1; + uint32_t USART1EN:1; + uint32_t ADC3EN:1; + uint32_t reserved2:3; + uint32_t TIM9EN:1; + uint32_t TIM10EN:1; + uint32_t TIM11EN:1; + uint32_t reserved3:10; + }; + uint32_t word; +}; + +union RCC_APB1ENR { + struct __attribute__((packed)) { + uint32_t TIM2EN:1; + uint32_t TIM3EN:1; + uint32_t TIM4EN:1; + uint32_t TIM5EN:1; + uint32_t TIM6EN:1; + uint32_t TIM7EN:1; + uint32_t TIM12EN:1; + uint32_t TIM13EN:1; + uint32_t TIM14EN:1; + uint32_t reserved1:2; + uint32_t WWDGEN:1; + uint32_t reserved2:2; + uint32_t SPI2EN:1; + uint32_t SPI3EN:1; + uint32_t reserved3:1; + uint32_t USART2EN:1; + uint32_t USART3EN:1; + uint32_t UART4EN:1; + uint32_t UART5EN:1; + uint32_t I2C12EN:1; + uint32_t I2C2EN:1; + uint32_t USB2EN:1; + uint32_t reserved4:1; + uint32_t CANEN:1; + uint32_t reserved5:1; + uint32_t BKPEN:1; + uint32_t PWREN:1; + uint32_t DACEN:1; + uint32_t reserved6:2; + }; + uint32_t word; +}; + +union RCC_BDCR { + struct __attribute__((packed)) { + uint32_t LSEON:1; + uint32_t LSERDY:1; + uint32_t LSEBYP:1; + uint32_t reserved1:5; + uint32_t RTCSEL:2; + uint32_t reserved2:5; + uint32_t RTCEN:1; + uint32_t BDRST:1; + uint32_t reserved3:15; + }; + uint32_t word; +}; + +union RCC_CSR { + struct __attribute__((packed)) { + uint32_t LSION:1; + uint32_t LSIRDY:1; + uint32_t reserved1:22; + uint32_t RMVF:1; + uint32_t reserved2:1; + uint32_t PINRSTF:1; + uint32_t PORRSTF:1; + uint32_t SFTRSTF:1; + uint32_t IWDGRSTF:1; + uint32_t WWDGRSTF:1; + uint32_t LPWRSTF:1; + }; + uint32_t word; +}; + +struct __attribute__((packed)) RCC { + union RCC_CR CR; + union RCC_CFGR CFGR; + union RCC_CIR CIR; + union RCC_APB2RSTR APB2RSTR; + union RCC_APB1RSTR APB1RSTR; + union RCC_AHBENR AHBENR; + union RCC_APB2ENR APB2ENR; + union RCC_APB1ENR APB1ENR; + union RCC_BDCR BDCR; + union RCC_CSR CSR; +}; + +//--functions------------------------------------------------------------------- + +#endif //_RCC_REGS_H_ +