Implement nvic's control functions
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691b360eb1
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87
drivers/nvic.c
Normal file
87
drivers/nvic.c
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@ -0,0 +1,87 @@
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/** @file nvic.c
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* Module handling the Nested Vector Interrupt Controller (NVIC)
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*
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* The module provides functions to configure the different interrupts and
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* their priority suiing the NVIC's interface
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*/
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//--includes--------------------------------------------------------------------
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#include "nvic.h"
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#include "nvic_regs.h"
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//--local definitions-----------------------------------------------------------
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/**
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* NVIC's register are only accessible by 32 bits words, and data is stored
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* accors 3 consecutive registers. This macro sets the right bit from the
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* right register based on the IRQ number
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*/
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#define set_bit(reg, irq) \
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do { \
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uint8_t n = irq / 32; \
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uint8_t r = irq - n * 32; \
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regs->reg[n] |= (0x1 << r); \
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} while (0)
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/**
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* NVIC's register are only accessible by 32 bits words, and data is stored
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* accors 3 consecutive registers. This macro fetches the right bit from the
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* right register based on the IRQ number
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*/
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#define get_bit(reg, irq, res) \
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do { \
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uint8_t n = irq / 32; \
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uint8_t r = irq - n * 32; \
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res = 0 != (regs->reg[n] | (0x1 << r)); \
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} while (0)
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//--local variables-------------------------------------------------------------
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static volatile struct NVIC1* regs = (struct NVIC1*)NVIC1_BASE_ADDRESS;
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//--public functions------------------------------------------------------------
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void nvic_enable(enum NvicIrq irq)
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{
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set_bit(ISERX, irq);
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}
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void nvic_disable(enum NvicIrq irq)
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{
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set_bit(ICERX, irq);
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}
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void nvic_clear_pending(enum NvicIrq irq)
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{
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set_bit(ICPRX, irq);
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}
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void nvic_set_priority(enum NvicIrq irq, uint8_t priority)
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{
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uint8_t n = irq / 4;
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uint8_t r = (irq - n * 4); //get the division's reminder
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r *= 8; //mul by 8 since each 'slot' is 8 bits
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r += 4; //add 4 since we only write to the upper 4 bits
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regs->IPRX[n] &= ~(0x0F << r);
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regs->IPRX[n] |= (priority & 0x0F) << r;
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}
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void nvic_set_pending(enum NvicIrq irq)
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{
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set_bit(ISPRX, irq);
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}
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bool nvic_is_pending(enum NvicIrq irq)
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{
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bool res = false;
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get_bit(ISPRX, irq, res);
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return res;
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}
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//--local functions-------------------------------------------------------------
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125
drivers/nvic.h
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125
drivers/nvic.h
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@ -0,0 +1,125 @@
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/** @file nvic.h
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* Module handling the Nested Vector Interrupt Controller (NVIC)
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*
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* The module provides functions to configure the different interrupts and
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* their priority suiing the NVIC's interface
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*/
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#ifndef _NVIC_H_
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#define _NVIC_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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#include "stdbool.h"
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//--type definitions------------------------------------------------------------
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/**
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* Available System IRQs. This does not include CPU's IRQs
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*/
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enum NvicIrq {
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NVIC_IRQ_WWDG = 0,
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NVIC_IRQ_PVD,
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NVIC_IRQ_TAMPER,
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NVIC_IRQ_RTC,
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NVIC_IRQ_FLASH,
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NVIC_IRQ_RCC,
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NVIC_IRQ_EXTI0,
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NVIC_IRQ_EXTI1,
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NVIC_IRQ_EXTI2,
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NVIC_IRQ_EXTI3,
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NVIC_IRQ_EXTI4,
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NVIC_IRQ_DMA1_CHANNEL1,
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NVIC_IRQ_DMA1_CHANNEL2,
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NVIC_IRQ_DMA1_CHANNEL3,
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NVIC_IRQ_DMA1_CHANNEL4,
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NVIC_IRQ_DMA1_CHANNEL5,
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NVIC_IRQ_DMA1_CHANNEL6,
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NVIC_IRQ_DMA1_CHANNEL7,
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NVIC_IRQ_ADC1_2,
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NVIC_IRQ_HP_CAN_TX,
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NVIC_IRQ_LP_CAN_RX0,
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NVIC_IRQ_CAN_RX1,
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NVIC_IRQ_CAN_SCE,
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NVIC_IRQ_EXTI9_5,
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NVIC_IRQ_TIM1_BRK,
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NVIC_IRQ_TIM1_UP,
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NVIC_IRQ_TIM1_TRG_COM,
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NVIC_IRQ_TIM1_CC,
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NVIC_IRQ_TIM2,
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NVIC_IRQ_TIM3,
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NVIC_IRQ_TIM4,
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NVIC_IRQ_I2C1_EVENT,
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NVIC_IRQ_I2C1_ERROR,
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NVIC_IRQ_I2C2_EVENT,
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NVIC_IRQ_I2C2_ERROR,
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NVIC_IRQ_SPI1,
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NVIC_IRQ_SPI2,
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NVIC_IRQ_USART1,
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NVIC_IRQ_USART2,
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NVIC_IRQ_USART3,
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NVIC_IRQ_EXTI15_10,
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NVIC_IRQ_RTC_ALARM,
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NVIC_IRQ_USB_WAKEUP,
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NVIC_IRQ_TIM8_BRK,
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NVIC_IRQ_TIM8_UP,
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NVIC_IRQ_TIM8_TRG_COM,
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NVIC_IRQ_TIM8_CC,
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NVIC_IRQ_ADC3,
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NVIC_IRQ_FSMC,
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NVIC_IRQ_SDIO,
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NVIC_IRQ_TIM5,
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NVIC_IRQ_SPI3,
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NVIC_IRQ_UART4,
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NVIC_IRQ_UART5,
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NVIC_IRQ_TIM6,
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NVIC_IRQ_TIM7,
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NVIC_IRQ_DMA2_CHANNEL1,
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NVIC_IRQ_DMA2_CHANNEL2,
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NVIC_IRQ_DMA2_CHANNEL3,
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NVIC_IRQ_DMA2_CHANNEL4_5,
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};
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//--functions-------------------------------------------------------------------
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/**
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* Enables the selected IRQ
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*/
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void nvic_enable(enum NvicIrq irq);
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/**
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* Disables the selected IRQ
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*/
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void nvic_disable(enum NvicIrq irq);
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/**
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* Clears the pending state of an IRQ. Should be called when reaching an IRQ
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* handler so that the IRQ isn't triggered again when exiting the handler
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*/
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void nvic_clear_pending(enum NvicIrq irq);
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/**
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* Sets the priority for the selected IRQ. The lower the priority value, the
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* higher the effective priority. Valid priority values range from 0 to 15. Any
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* higher value will be ignored. When multiple IRQs with the same priority are
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* triggered, they will be serviced from the lowest ID to the highest
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*/
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void nvic_set_priority(enum NvicIrq irq, uint8_t priority);
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/**
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* Sets the selected IRQ's pending state. If the IRQ is active, it will be
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* triggered
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*/
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void nvic_set_pending(enum NvicIrq irq);
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/**
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* Returns wether the selected IRQ is currently pending or not
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*/
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bool nvic_is_pending(enum NvicIrq irq);
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#endif //_RCC_H_
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113
startup.s
113
startup.s
@ -99,13 +99,13 @@ vector_table:
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.word hdr_exti2
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.word hdr_exti3
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.word hdr_exti4
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.word hdr_dma_channel1
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.word hdr_dma_channel2
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.word hdr_dma_channel3
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.word hdr_dma_channel4
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.word hdr_dma_channel5
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.word hdr_dma_channel6
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.word hdr_dma_channel7
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.word hdr_dma1_channel1
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.word hdr_dma1_channel2
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.word hdr_dma1_channel3
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.word hdr_dma1_channel4
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.word hdr_dma1_channel5
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.word hdr_dma1_channel6
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.word hdr_dma1_channel7
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.word hdr_adc1_2
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.word hdr_hp_can_tx
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.word hdr_lp_can_rx0
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@ -131,23 +131,23 @@ vector_table:
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.word hdr_exti15_10
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.word hdr_rtc_alarm
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.word hdr_usb_wakeup
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word hdr_tim8_brk
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.word hdr_tim8_up
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.word hdr_tim8_trg_com
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.word hdr_tim8_cc
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.word hdr_adc3
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.word hdr_fsmc
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.word hdr_sdio
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.word hdr_tim5
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.word hdr_spi3
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.word hdr_uart4
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.word hdr_uart5
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.word hdr_tim6
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.word hdr_tim7
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.word hdr_dma2_channel1
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.word hdr_dma2_channel2
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.word hdr_dma2_channel3
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.word hdr_dma2_channel4_5
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//--Weak definitions------------------------------------------------------------
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@ -211,25 +211,25 @@ vector_table:
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.weak hdr_exti4
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.thumb_set hdr_exti4, hdr_default
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.weak hdr_dma_channel1
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.weak hdr_dma1_channel1
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.thumb_set hdr_dma_channel1, hdr_default
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.weak hdr_dma_channel2
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.weak hdr_dma1_channel2
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.thumb_set hdr_dma_channel2, hdr_default
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.weak hdr_dma_channel3
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.weak hdr_dma1_channel3
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.thumb_set hdr_dma_channel3, hdr_default
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.weak hdr_dma_channel4
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.weak hdr_dma1_channel4
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.thumb_set hdr_dma_channel4, hdr_default
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.weak hdr_dma_channel5
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.weak hdr_dma1_channel5
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.thumb_set hdr_dma_channel5, hdr_default
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.weak hdr_dma_channel6
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.weak hdr_dma1_channel6
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.thumb_set hdr_dma_channel6, hdr_default
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.weak hdr_dma_channel7
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.weak hdr_dma1_channel7
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.thumb_set hdr_dma_channel7, hdr_default
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.weak hdr_adc1_2
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@ -307,3 +307,54 @@ vector_table:
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.weak hdr_usb_wakeup
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.thumb_set hdr_usb_wakeup, hdr_default
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.weak hdr_tim8_brk
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.thumb_set hdr_tim8_brk, hdr_default
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.weak hdr_tim8_up
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.thumb_set hdr_tim8_up, hdr_default
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.weak hdr_tim8_trg_com
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.thumb_set hdr_tim8_trg_com, hdr_default
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.weak hdr_tim8_cc
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.thumb_set hdr_tim8_cc, hdr_default
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.weak hdr_adc3
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.thumb_set hdr_adc3, hdr_default
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.weak hdr_fsmc
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.thumb_set hdr_fsmc, hdr_default
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.weak hdr_sdio
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.thumb_set hdr_sdio, hdr_default
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.weak hdr_tim5
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.thumb_set hdr_tim5, hdr_default
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.weak hdr_spi3
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.thumb_set hdr_spi3, hdr_default
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.weak hdr_uart4
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.thumb_set hdr_uart4, hdr_default
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.weak hdr_uart5
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.thumb_set hdr_uart5, hdr_default
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.weak hdr_tim6
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.thumb_set hdr_tim6, hdr_default
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.weak hdr_tim7
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.thumb_set hdr_tim7, hdr_default
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.weak hdr_dma2_channel1
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.thumb_set hdr_dma_channel1, hdr_default
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.weak hdr_dma2_channel2
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.thumb_set hdr_dma_channel2, hdr_default
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.weak hdr_dma2_channel3
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.thumb_set hdr_dma_channel3, hdr_default
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.weak hdr_dma2_channel4_5
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.thumb_set hdr_dma_channel4_5, hdr_default
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