From 6ddc2266e157ac36101e9e46b0407ded5d6344d4 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:13:05 +0200 Subject: [PATCH] Create dma's register map --- drivers/dma_regs.h | 216 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 drivers/dma_regs.h diff --git a/drivers/dma_regs.h b/drivers/dma_regs.h new file mode 100644 index 0000000..bfbb8f9 --- /dev/null +++ b/drivers/dma_regs.h @@ -0,0 +1,216 @@ +/** @file dma_regs.h + * Module defining the DMA registers. + * + * Mainly made to be used by the dma module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _DMA_REGS_H_ +#define _DMA_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "reg.h" + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define DMA1_BASE_ADDRESS 0x40020000 +#define DMA2_BASE_ADDRESS 0x40020400 + +union DMA_ISR { + struct __attribute__((packed)) { + uint32_t GIF1:1; + uint32_t TCIF1:1; + uint32_t HTIF1:1; + uint32_t TEIF1:1; + uint32_t GIF2:1; + uint32_t TCIF2:1; + uint32_t HTIF2:1; + uint32_t TEIF2:1; + uint32_t GIF3:1; + uint32_t TCIF3:1; + uint32_t HTIF3:1; + uint32_t TEIF3:1; + uint32_t GIF4:1; + uint32_t TCIF4:1; + uint32_t HTIF4:1; + uint32_t TEIF4:1; + uint32_t GIF5:1; + uint32_t TCIF5:1; + uint32_t HTIF5:1; + uint32_t TEIF5:1; + uint32_t GIF6:1; + uint32_t TCIF6:1; + uint32_t HTIF6:1; + uint32_t TEIF6:1; + uint32_t GIF7:1; + uint32_t TCIF7:1; + uint32_t HTIF7:1; + uint32_t TEIF7:1; + uint32_t reserved1:4; + }; + uint32_t word; +}; + +#define DMA_ISR_GIF1 reg_def( 0, 1) +#define DMA_ISR_TCIF1 reg_def( 1, 1) +#define DMA_ISR_HTIF1 reg_def( 2, 1) +#define DMA_ISR_TEIF1 reg_def( 3, 1) +#define DMA_ISR_GIF2 reg_def( 4, 1) +#define DMA_ISR_TCIF2 reg_def( 5, 1) +#define DMA_ISR_HTIF2 reg_def( 6, 1) +#define DMA_ISR_TEIF2 reg_def( 7, 1) +#define DMA_ISR_GIF3 reg_def( 8, 1) +#define DMA_ISR_TCIF3 reg_def( 9, 1) +#define DMA_ISR_HTIF3 reg_def(10, 1) +#define DMA_ISR_TEIF3 reg_def(11, 1) +#define DMA_ISR_GIF4 reg_def(12, 1) +#define DMA_ISR_TCIF4 reg_def(13, 1) +#define DMA_ISR_HTIF4 reg_def(14, 1) +#define DMA_ISR_TEIF4 reg_def(15, 1) +#define DMA_ISR_GIF5 reg_def(16, 1) +#define DMA_ISR_TCIF5 reg_def(17, 1) +#define DMA_ISR_HTIF5 reg_def(18, 1) +#define DMA_ISR_TEIF5 reg_def(19, 1) +#define DMA_ISR_GIF6 reg_def(20, 1) +#define DMA_ISR_TCIF6 reg_def(21, 1) +#define DMA_ISR_HTIF6 reg_def(22, 1) +#define DMA_ISR_TEIF6 reg_def(23, 1) +#define DMA_ISR_GIF7 reg_def(24, 1) +#define DMA_ISR_TCIF7 reg_def(25, 1) +#define DMA_ISR_HTIF7 reg_def(26, 1) +#define DMA_ISR_TEIF7 reg_def(27, 1) +#define DMA_ISR_reserved1 reg_def(28, 4) + +union DMA_IFCR { + struct __attribute__((packed)) { + uint32_t CGIF1:1; + uint32_t CTCIF1:1; + uint32_t CHTIF1:1; + uint32_t CTEIF1:1; + uint32_t CGIF2:1; + uint32_t CTCIF2:1; + uint32_t CHTIF2:1; + uint32_t CTEIF2:1; + uint32_t CGIF3:1; + uint32_t CTCIF3:1; + uint32_t CHTIF3:1; + uint32_t CTEIF3:1; + uint32_t CGIF4:1; + uint32_t CTCIF4:1; + uint32_t CHTIF4:1; + uint32_t CTEIF4:1; + uint32_t CGIF5:1; + uint32_t CTCIF5:1; + uint32_t CHTIF5:1; + uint32_t CTEIF5:1; + uint32_t CGIF6:1; + uint32_t CTCIF6:1; + uint32_t CHTIF6:1; + uint32_t CTEIF6:1; + uint32_t CGIF7:1; + uint32_t CTCIF7:1; + uint32_t CHTIF7:1; + uint32_t CTEIF7:1; + uint32_t reserved1:4; + }; + uint32_t word; +}; + +#define DMA_IFCR_CGIF1 reg_def( 0, 1) +#define DMA_IFCR_CTCIF1 reg_def( 1, 1) +#define DMA_IFCR_CHTIF1 reg_def( 2, 1) +#define DMA_IFCR_CTEIF1 reg_def( 3, 1) +#define DMA_IFCR_CGIF2 reg_def( 4, 1) +#define DMA_IFCR_CTCIF2 reg_def( 5, 1) +#define DMA_IFCR_CHTIF2 reg_def( 6, 1) +#define DMA_IFCR_CTEIF2 reg_def( 7, 1) +#define DMA_IFCR_CGIF3 reg_def( 8, 1) +#define DMA_IFCR_CTCIF3 reg_def( 9, 1) +#define DMA_IFCR_CHTIF3 reg_def(10, 1) +#define DMA_IFCR_CTEIF3 reg_def(11, 1) +#define DMA_IFCR_CGIF4 reg_def(12, 1) +#define DMA_IFCR_CTCIF4 reg_def(13, 1) +#define DMA_IFCR_CHTIF4 reg_def(14, 1) +#define DMA_IFCR_CTEIF4 reg_def(15, 1) +#define DMA_IFCR_CGIF5 reg_def(16, 1) +#define DMA_IFCR_CTCIF5 reg_def(17, 1) +#define DMA_IFCR_CHTIF5 reg_def(18, 1) +#define DMA_IFCR_CTEIF5 reg_def(19, 1) +#define DMA_IFCR_CGIF6 reg_def(20, 1) +#define DMA_IFCR_CTCIF6 reg_def(21, 1) +#define DMA_IFCR_CHTIF6 reg_def(22, 1) +#define DMA_IFCR_CTEIF6 reg_def(23, 1) +#define DMA_IFCR_CGIF7 reg_def(24, 1) +#define DMA_IFCR_CTCIF7 reg_def(25, 1) +#define DMA_IFCR_CHTIF7 reg_def(26, 1) +#define DMA_IFCR_CTEIF7 reg_def(27, 1) +#define DMA_IFCR_reserved1 reg_def(28, 4) + +union DMA_CCR { + struct __attribute__((packed)) { + uint32_t EN:1; + uint32_t TCIE:1; + uint32_t HTIE:1; + uint32_t TEIE:1; + uint32_t DIR:1; + uint32_t CIRC:1; + uint32_t PINC:1; + uint32_t MINC:1; + uint32_t PSIZE:2; + uint32_t MSIZE:2; + uint32_t PL:2; + uint32_t MEM2MEM:1; + uint32_t reserved1:17; + }; + uint32_t word; +}; + +#define DMA_CCR_EN reg_def( 0, 1) +#define DMA_CCR_TCIE reg_def( 1, 1) +#define DMA_CCR_HTIE reg_def( 2, 1) +#define DMA_CCR_TEIE reg_def( 3, 1) +#define DMA_CCR_DIR reg_def( 4, 1) +#define DMA_CCR_CIRC reg_def( 5, 1) +#define DMA_CCR_PINC reg_def( 6, 1) +#define DMA_CCR_MINC reg_def( 7, 1) +#define DMA_CCR_PSIZE reg_def( 8, 2) +#define DMA_CCR_MSIZE reg_def(10, 2) +#define DMA_CCR_PL reg_def(12, 2) +#define DMA_CCR_MEM2MEM reg_def(14, 1) +#define DMA_CCR_reserved1 reg_def(15, 17) + +union DMA_CNDTR { + struct __attribute__((packed)) { + uint32_t NDT:16; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +#define DMA_CNDTR_NDT reg_def( 0, 16) +#define DMA_CNDTR_reserved1 reg_def(16, 16) + +struct __attribute__((packed)) DMA_CHANNEL { + union DMA_CCR CCR; + union DMA_CNDTR CNDTR; + uint32_t CPAR; + uint32_t CMAR; + uint32_t reserved1; +}; + +struct __attribute__((packed)) DMA { + union DMA_ISR ISR; + union DMA_IFCR IFCR; + struct DMA_CHANNEL CHANNELS[7]; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_DMA_REGS_H_ +