From 7a660c29d21052acd90f4cf9287319986c4085eb Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 23:40:36 +0200 Subject: [PATCH] Implement and validate all USARTs --- drivers/dma_mbuf.c | 2 +- drivers/usart.c | 135 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 113 insertions(+), 24 deletions(-) diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c index 66c3520..68462a7 100644 --- a/drivers/dma_mbuf.c +++ b/drivers/dma_mbuf.c @@ -70,7 +70,7 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, buffers[buffer->buffer_index][buffer->byte_index] = byte; ++buffer->byte_index; - dma_exit_critical(DMA_PERIPH_1, buffer->channel); + dma_exit_critical(buffer->dma, buffer->channel); return 0; } diff --git a/drivers/usart.c b/drivers/usart.c index 2224845..e5b8491 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -37,12 +37,12 @@ static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -static uint32_t write_to_buffer(volatile struct USART* regs, - volatile struct DmaMultiBuffer *buffer, uint8_t byte); static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte); static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param); +static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param); +static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param); //--local variables------------------------------------------------------------- @@ -53,6 +53,10 @@ static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; static volatile struct CircularBuffer usart1_rx_buffer; static volatile struct DmaMultiBuffer usart1_tx_buffer; +static volatile struct CircularBuffer usart2_rx_buffer; +static volatile struct DmaMultiBuffer usart2_tx_buffer; +static volatile struct CircularBuffer usart3_rx_buffer; +static volatile struct DmaMultiBuffer usart3_tx_buffer; //--public functions------------------------------------------------------------ @@ -69,16 +73,21 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); usart1_tx_buffer.buffers = NULL; + usart1_rx_buffer.buffer = NULL; break; case USART_PERIPH_2: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); configure_baudrate(usart2, clocks.apb1_freq, baudrate); configure_usart(usart2, config); + usart2_tx_buffer.buffers = NULL; + usart2_rx_buffer.buffer = NULL; break; case USART_PERIPH_3: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE); configure_baudrate(usart3, clocks.apb1_freq, baudrate); configure_usart(usart3, config); + usart3_tx_buffer.buffers = NULL; + usart3_rx_buffer.buffer = NULL; break; default: break; @@ -89,21 +98,41 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; volatile struct DmaMultiBuffer* buffer; + enum NvicIrq irq; switch (periph) { case USART_PERIPH_1: regs = usart1; buffer = &usart1_tx_buffer; + irq = NVIC_IRQ_USART1; break; case USART_PERIPH_2: + regs = usart2; + buffer = &usart2_tx_buffer; + irq = NVIC_IRQ_USART2; + break; case USART_PERIPH_3: + regs = usart3; + buffer = &usart3_tx_buffer; + irq = NVIC_IRQ_USART3; + break; default: return 1; break; } if (buffer->buffers) { - return write_to_buffer(regs, buffer, byte); + //if the tx register is empty, there is no need to go through the dma + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + //enable IRQ, disable DMA + reg_reset(regs->CR3, USART_CR3_DMAT); + reg_set(regs->CR1, USART_CR1_TXEIE); + nvic_enable(irq); + return 0; + } else { + return dma_mbuf_write_byte(buffer, byte); + } } else { while (regs->SR.TXE == 0) {} reg_write(regs->DR, USART_DR_DR, byte); @@ -124,7 +153,15 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) dma_channel = DMA_CHANNEL_5; break; case USART_PERIPH_2: + regs = usart2; + buffer = &usart2_rx_buffer; + dma_channel = DMA_CHANNEL_6; + break; case USART_PERIPH_3: + regs = usart3; + buffer = &usart3_rx_buffer; + dma_channel = DMA_CHANNEL_3; + break; default: return 1; break; @@ -152,8 +189,14 @@ void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, DMA_CONFIG); break; case USART_PERIPH_2: + dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR, + buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7, + DMA_CONFIG); break; case USART_PERIPH_3: + dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR, + buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2, + DMA_CONFIG); break; } } @@ -176,8 +219,32 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_6, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS + | DMA_CONFIG_PRIO_LOW, (void*)&usart2->DR, buffer, + size, usart2_rx_callback, NULL); + usart2_rx_buffer.buffer = buffer; + usart2_rx_buffer.size = size; + usart2_rx_buffer.begin = 0; + usart2_rx_buffer.dmaLooped = false; + reg_set(usart2->CR3, USART_CR3_DMAR); break; + case USART_PERIPH_3: + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_3, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS + | DMA_CONFIG_PRIO_LOW, (void*)&usart3->DR, buffer, + size, usart3_rx_callback, NULL); + usart3_rx_buffer.buffer = buffer; + usart3_rx_buffer.size = size; + usart3_rx_buffer.begin = 0; + usart3_rx_buffer.dmaLooped = false; + reg_set(usart3->CR3, USART_CR3_DMAR); + break; } } @@ -283,26 +350,6 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } -/** - * Writes the given byte to the given UART, using a FragmentedBuffer and a DMA - * to bufferize the write if the peripheral is already busy. - */ -static uint32_t write_to_buffer(volatile struct USART* regs, - volatile struct DmaMultiBuffer* buffer, uint8_t byte) -{ - //if the tx register is empty, there is no need to go through the dma - if (regs->SR.TXE) { - reg_write(regs->DR, USART_DR_DR, byte); - //enable IRQ, disable DMA - reg_reset(regs->CR3, USART_CR3_DMAT); - reg_set(regs->CR1, USART_CR1_TXEIE); - nvic_enable(NVIC_IRQ_USART1); - return 0; - } - - return dma_mbuf_write_byte(buffer, byte); -} - /** * Reads the oldest byte from the given CircularBuffer if any. Returns 0 if the * read was successfull, 1 otherwise @@ -345,6 +392,26 @@ static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param) usart1_rx_buffer.dmaLooped = true; } +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ +static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + usart2_rx_buffer.dmaLooped = true; +} + +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ +static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + usart3_rx_buffer.dmaLooped = true; +} + //--ISRs------------------------------------------------------------------------ @@ -359,3 +426,25 @@ void hdr_usart1(void) dma_mbuf_refresh(&usart1_tx_buffer); } +void hdr_usart2(void) +{ + //disable the interrupt. It will be reenabled on a write if needed + nvic_clear_pending(NVIC_IRQ_USART2); + nvic_disable(NVIC_IRQ_USART2); + reg_reset(usart2->CR1, USART_CR1_TXEIE); + reg_set(usart2->CR3, USART_CR3_DMAT); + + dma_mbuf_refresh(&usart2_tx_buffer); +} + +void hdr_usart3(void) +{ + //disable the interrupt. It will be reenabled on a write if needed + nvic_clear_pending(NVIC_IRQ_USART3); + nvic_disable(NVIC_IRQ_USART3); + reg_reset(usart3->CR1, USART_CR1_TXEIE); + reg_set(usart3->CR3, USART_CR3_DMAT); + + dma_mbuf_refresh(&usart3_tx_buffer); +} +