diff --git a/drv/tim_regs.h b/drv/tim_regs.h
new file mode 100644
index 0000000..a97f204
--- /dev/null
+++ b/drv/tim_regs.h
@@ -0,0 +1,455 @@
+/** @file tim_regs.h
+ * Module defining the TIMers registers.
+ *
+ * Mainly made to be used by the tim module. It is recommanded to go through
+ * the functions provided by that module instead of directly using the registers
+ * defined here.
+ */
+
+#ifndef _TIM_REGS_H_
+#define _TIM_REGS_H_
+
+//--includes--------------------------------------------------------------------
+
+#include "stdint.h"
+
+
+//--type definitions------------------------------------------------------------
+
+#define TIM1_BASE_ADDRESS 0x40012C00
+#define TIM2_BASE_ADDRESS 0x40000000
+#define TIM3_BASE_ADDRESS 0x40000400
+#define TIM4_BASE_ADDRESS 0x40000800
+
+union TIM_CR1 {
+	struct {
+		uint32_t CEN:1;
+		uint32_t UDIS:1;
+		uint32_t URS:1;
+		uint32_t OPM:1;
+		uint32_t DIR:1;
+		uint32_t CMS:2;
+		uint32_t ARPE:1;
+		uint32_t CKD:2;
+		uint32_t reserved1:22;
+	};
+	uint32_t word;
+};
+
+union TIM_CR2 {
+	struct {
+		uint32_t reserved1:3;
+		uint32_t CCDS:1;
+		uint32_t MMS:3;
+		uint32_t TI1S:1;
+		uint32_t reserved2:24;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_CR2 {
+	struct {
+		uint32_t CCPC:1;
+		uint32_t reserved1:1;
+		uint32_t CCUS:1;
+		uint32_t CCDS:1;
+		uint32_t MMS:3;
+		uint32_t TI1S:1;
+		uint32_t OI1S:1;
+		uint32_t OIS1N:1;
+		uint32_t OIS2:1;
+		uint32_t OIS2N:1;
+		uint32_t OIS3:1;
+		uint32_t OIS3N:1;
+		uint32_t OIS4:1;
+		uint32_t reserved2:17;
+	};
+	uint32_t word;
+};
+
+union TIM_SMCR {
+	struct {
+		uint32_t SMS:3;
+		uint32_t reserved1:1;
+		uint32_t TS:3;
+		uint32_t MSM:1;
+		uint32_t ETF:4;
+		uint32_t ETPS:2;
+		uint32_t ECE:1;
+		uint32_t ETP:1;
+		uint32_t reserved2:16;
+	};
+	uint32_t word;
+};
+
+union TIM_DIER {
+	struct {
+		uint32_t UIE:1;
+		uint32_t CC1IE:1;
+		uint32_t CC2IE:1;
+		uint32_t CC3IE:1;
+		uint32_t CC4IE:1;
+		uint32_t reserved1:1;
+		uint32_t TIE:1;
+		uint32_t reserved2:1;
+		uint32_t UDE:1;
+		uint32_t CC1DE:1;
+		uint32_t CC2DE:1;
+		uint32_t CC3DE:1;
+		uint32_t CC4DE:1;
+		uint32_t COMDE:1;
+		uint32_t TDE:1;
+		uint32_t reserved3:17;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_DIER {
+	struct {
+		uint32_t UIE:1;
+		uint32_t CC1IE:1;
+		uint32_t CC2IE:1;
+		uint32_t CC3IE:1;
+		uint32_t CC4IE:1;
+		uint32_t COMIE:1;
+		uint32_t TIE:1;
+		uint32_t BIE:1;
+		uint32_t UDE:1;
+		uint32_t CC1DE:1;
+		uint32_t CC2DE:1;
+		uint32_t CC3DE:1;
+		uint32_t CC4DE:1;
+		uint32_t COMDE:1;
+		uint32_t TDE:1;
+		uint32_t reserved1:17;
+	};
+	uint32_t word;
+};
+
+
+union TIM_SR {
+	struct {
+		uint32_t UIF:1;
+		uint32_t CC1IF:1;
+		uint32_t CC2IF:1;
+		uint32_t CC3IF:1;
+		uint32_t CC4IF:1;
+		uint32_t reserved1:1;
+		uint32_t TIF:1;
+		uint32_t reserved2:2;
+		uint32_t CC1OF:1;
+		uint32_t CC2OF:1;
+		uint32_t CC3OF:1;
+		uint32_t CC4OF:1;
+		uint32_t reserved3:19;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_SR {
+	struct {
+		uint32_t UIF:1;
+		uint32_t CC1IF:1;
+		uint32_t CC2IF:1;
+		uint32_t CC3IF:1;
+		uint32_t CC4IF:1;
+		uint32_t COMIF:1;
+		uint32_t TIF:1;
+		uint32_t BIF:1;
+		uint32_t reserved1:1;
+		uint32_t CC1OF:1;
+		uint32_t CC2OF:1;
+		uint32_t CC3OF:1;
+		uint32_t CC4OF:1;
+		uint32_t reserved2:19;
+	};
+	uint32_t word;
+};
+
+union TIM_EGR {
+	struct {
+		uint32_t UG:1;
+		uint32_t CC1G:1;
+		uint32_t CC2G:1;
+		uint32_t CC3G:1;
+		uint32_t CC4G:1;
+		uint32_t reserved1:1;
+		uint32_t TG:1;
+		uint32_t reserved2:25;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_EGR {
+	struct {
+		uint32_t UG:1;
+		uint32_t CC1G:1;
+		uint32_t CC2G:1;
+		uint32_t CC3G:1;
+		uint32_t CC4G:1;
+		uint32_t COMG:1;
+		uint32_t TG:1;
+		uint32_t BG:1;
+		uint32_t reserved1:24;
+	};
+	uint32_t word;
+};
+
+union TIM_CCMR1_INPUT {
+	struct {
+		uint32_t CC1S:2;
+		uint32_t OC1FE:1;
+		uint32_t OC1PE:1;
+		uint32_t OC1M:3;
+		uint32_t OC1CE:1;
+		uint32_t CC2S:2;
+		uint32_t OC2FE:1;
+		uint32_t OC2PE:1;
+		uint32_t OC2M:3;
+		uint32_t OC2CE:1;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCMR1_OUTPUT {
+	struct {
+		uint32_t CC1S:2;
+		uint32_t IC1PSC:2;
+		uint32_t IC1F:4;
+		uint32_t CC2S:2;
+		uint32_t IC2PSC:2;
+		uint32_t IC2F:4;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCMR1 {
+	union TIM_CCMR1_INPUT input;
+	union TIM_CCMR1_OUTPUT output;
+};
+
+union TIM_CCMR2_INPUT {
+	struct {
+		uint32_t CC3S:2;
+		uint32_t OC3FE:1;
+		uint32_t OC3PE:1;
+		uint32_t OC3M:3;
+		uint32_t OC3CE:1;
+		uint32_t CC4S:2;
+		uint32_t OC4FE:1;
+		uint32_t OC4PE:1;
+		uint32_t OC4M:3;
+		uint32_t OC4CE:1;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCMR2_OUTPUT {
+	struct {
+		uint32_t CC3S:2;
+		uint32_t IC3PSC:2;
+		uint32_t IC3F:4;
+		uint32_t CC4S:2;
+		uint32_t IC4PSC:2;
+		uint32_t IC4F:4;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCMR2 {
+	union TIM_CCMR2_INPUT input;
+	union TIM_CCMR2_OUTPUT output;
+};
+
+union TIM_CCER {
+	struct {
+		uint32_t CC1E:1;
+		uint32_t CC1P:1;
+		uint32_t reserved1:2;
+		uint32_t CC2E:1;
+		uint32_t CC2P:1;
+		uint32_t reserved2:2;
+		uint32_t CC3E:1;
+		uint32_t CC3P:1;
+		uint32_t reserved3:2;
+		uint32_t CC4E:1;
+		uint32_t CC4P:1;
+		uint32_t reserved4:18;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_CCER {
+	struct {
+		uint32_t CC1E:1;
+		uint32_t CC1P:1;
+		uint32_t CC1NE:1;
+		uint32_t CC1NP:1;
+		uint32_t CC2E:1;
+		uint32_t CC2P:1;
+		uint32_t CC2NE:1;
+		uint32_t CC2NP:1;
+		uint32_t CC3E:1;
+		uint32_t CC3P:1;
+		uint32_t CC3NE:1;
+		uint32_t CC3NP:1;
+		uint32_t CC4E:1;
+		uint32_t CC4P:1;
+		uint32_t CC4NE:1;
+		uint32_t CC4NP:1;
+		uint32_t reserved1:18;
+	};
+	uint32_t word;
+};
+
+union TIM_CNT {
+	struct {
+		uint32_t CNT:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_PSC {
+	struct {
+		uint32_t PSC:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_ARR {
+	struct {
+		uint32_t ARR:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_RCR {
+	struct {
+		uint32_t REP:8;
+		uint32_t reserved1:24;
+	};
+	uint32_t word;
+};
+
+union TIM_CCR1 {
+	struct {
+		uint32_t CCR1:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCR2 {
+	struct {
+		uint32_t CCR2:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCR3 {
+	struct {
+		uint32_t CCR3:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_CCR4 {
+	struct {
+		uint32_t CCR4:16;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_ADV_BDTR {
+	struct {
+		uint32_t DT:8;
+		uint32_t LOCK:2;
+		uint32_t OSSI:1;
+		uint32_t OSSR:1;
+		uint32_t BKE:1;
+		uint32_t BKP:1;
+		uint32_t AOE:1;
+		uint32_t MOE:1;
+		uint32_t reserved1:16;
+	};
+	uint32_t word;
+};
+
+union TIM_DCR {
+	struct {
+		uint32_t DBA:5;
+		uint32_t reserved1:3;
+		uint32_t MBL:5;
+		uint32_t reserved2:19;
+	};
+	uint32_t word;
+};
+
+union TIM_DMAR {
+	struct {
+		uint32_t DMAB;
+	};
+	uint32_t word;
+};
+
+struct TIM {
+	union TIM_CR1 cr1;
+	union TIM_CR2 cr2;
+	union TIM_SMCR smcr;
+	union TIM_DIER dier;
+	union TIM_SR sr;
+	union TIM_EGR egr;
+	union TIM_CCMR1 ccmr1;
+	union TIM_CCMR2 ccmr2;
+	union TIM_CCER ccer;
+	union TIM_CNT cnt;
+	union TIM_PSC psc;
+	union TIM_ARR arr;
+	uint32_t reserved1;
+	union TIM_CCR1 ccr1;
+	union TIM_CCR2 ccr2;
+	union TIM_CCR3 ccr3;
+	union TIM_CCR4 ccr4;
+	uint32_t reserved2;
+	union TIM_DCR dcr;
+	union TIM_DMAR dmar;
+};
+
+struct TIM_ADV {
+	union TIM_CR1 cr1;
+	union TIM_ADV_CR2 cr2;
+	union TIM_SMCR smcr;
+	union TIM_ADV_DIER dier;
+	union TIM_ADV_SR sr;
+	union TIM_ADV_EGR egr;
+	union TIM_CCMR1 ccmr1;
+	union TIM_CCMR2 ccmr2;
+	union TIM_ADV_CCER ccer;
+	union TIM_CNT cnt;
+	union TIM_PSC psc;
+	union TIM_ARR arr;
+	union TIM_ADV_RCR rcr;
+	union TIM_CCR1 ccr1;
+	union TIM_CCR2 ccr2;
+	union TIM_CCR3 ccr3;
+	union TIM_CCR4 ccr4;
+	union TIM_ADV_BDTR bdtr;
+	union TIM_DCR dcr;
+	union TIM_DMAR dmar;
+};
+
+
+//--functions-------------------------------------------------------------------
+
+#endif //_TIM_REGS_H_
+