diff --git a/drv/scb_regs.h b/drv/scb_regs.h
new file mode 100644
index 0000000..90622e4
--- /dev/null
+++ b/drv/scb_regs.h
@@ -0,0 +1,192 @@
+/** @file scb_regs.h
+ * Module defining System Control Block (SCB) registers.
+ *
+ * Mainly made to be used by the scb module. It is recommanded to go through
+ * the functions provided by that module instead of directly using the registers
+ * defined here.
+ */
+
+#ifndef _SCB_REGS_H_
+#define _SCB_REGS_H_
+
+//--includes--------------------------------------------------------------------
+
+#include "stdint.h"
+
+
+//--type definitions------------------------------------------------------------
+
+#define SCB_BASE_ADDRESS 0xE000ED00
+
+union SCB_CPUID {
+	struct {
+		uint32_t revision:4;
+		uint32_t part_no:12;
+		uint32_t constant:4;
+		uint32_t variant:4;
+		uint32_t implementer:8;
+	};
+	uint32_t word;
+};
+
+union SCB_ICSR {
+	struct {
+		uint32_t VECTACTIVE:9;
+		uint32_t reserved1:2;
+		uint32_t RETOBASE:1;
+		uint32_t VECTPENDING:10;
+		uint32_t ISRPENDING:1;
+		uint32_t reserved2:2;
+		uint32_t PENDSTCLR:1;
+		uint32_t PENDSTSET:1;
+		uint32_t PENDSVCRL:1;
+		uint32_t PENDSVSET:1;
+		uint32_t reserved3:2;
+		uint32_t NMIPENDSET:1;
+	};
+	uint32_t word;
+};
+
+union SCB_VTOR {
+	struct {
+		uint32_t reserved1:9;
+		uint32_t TABLEOFF:21;
+		uint32_t reserved2:2;
+	};
+	uint32_t word;
+};
+
+union SCB_AIRCR {
+	struct {
+		uint32_t VECTRESET:1;
+		uint32_t VECTCRLACTIVE:1;
+		uint32_t SYSRESETREQ:1;
+		uint32_t reserved1:5;
+		uint32_t PRIGROUP:3;
+		uint32_t reserved2:4;
+		uint32_t ENDIANESS:1;
+		uint32_t VECTKEY:16;
+	};
+	uint32_t word;
+};
+
+union SCB_SCR {
+	struct {
+		uint32_t reserved1:1;
+		uint32_t SLEEPONEXIT:1;
+		uint32_t SLEEPDEEP:1;
+		uint32_t reserved2:1;
+		uint32_t SEVONPEND:1;
+		uint32_t reserved3:27;
+	};
+	uint32_t word;
+};
+
+union SCB_CCR {
+	struct {
+		uint32_t NONBASETHRDEN:1;
+		uint32_t USERSETMPEND:1;
+		uint32_t reserved1:1;
+		uint32_t UNALIGN_TRP:1;
+		uint32_t DIV_0_TRP:1;
+		uint32_t reserved2:3;
+		uint32_t BFHFNIGN:1;
+		uint32_t STKALIGN:1;
+		uint32_t reserved3:22;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR1 {
+	struct {
+		uint32_t PRI4:8;
+		uint32_t PRI5:8;
+		uint32_t PRI6:8;
+		uint32_t reserved1:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR2 {
+	struct {
+		uint32_t reserved1:24;
+		uint32_t PRI11:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR3 {
+	struct {
+		uint32_t reserved1:16;
+		uint32_t PRI14:8;
+		uint32_t PRI15:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHCRS {
+	struct {
+		uint32_t MEMFAULTACT:1;
+		uint32_t BUSFAULTACT:1;
+		uint32_t reserved1:1;
+		uint32_t USGFAULTACT:1;
+		uint32_t reserved2:3;
+		uint32_t SVCALLACT:1;
+		uint32_t MONITORACT:1;
+		uint32_t reserved3:1;
+		uint32_t PENDSVACT:1;
+		uint32_t SYSTICKACT:1;
+		uint32_t USGFAULTPENDED:1;
+		uint32_t MEMFAULTPENDED:1;
+		uint32_t BUSFAULTPENDED:1;
+		uint32_t SVCALLPENDED:1;
+		uint32_t MEMFAULTENA:1;
+		uint32_t BUSFAULTENA:1;
+		uint32_t USGFAULTENA:1;
+		uint32_t reserved4:13;
+	};
+	uint32_t word;
+};
+
+union SCB_CFSR {
+	struct {
+		uint32_t MMFSR:8;
+		uint32_t BFSR:8;
+		uint32_t UFSR:16;
+	};
+	uint32_t word;
+};
+
+union SCB_HFSR {
+	struct {
+		uint32_t reserved1:1;
+		uint32_t VECTTBL:1;
+		uint32_t reserved2:28;
+		uint32_t FORCED:1;
+		uint32_t DEBUG_VT:1;
+	};
+	uint32_t word;
+};
+
+struct SCB {
+	union SCB_CPUID CPUID;
+	union SCB_ICSR ICSR;
+	union SCB_VTOR VTOR;
+	union SCB_AIRCR AIRCR;
+	union SCB_SCR SCR;
+	union SCB_CCR CCR;
+	union SCB_SHPR1 SHPR1;
+	union SCB_SHPR2 SHPR2;
+	union SCB_SHPR3 SHPR3;
+	union SCB_SHCRS SHCRS;
+	union SCB_CFSR CFSR;
+	union SCB_HFSR HFSR;
+	uint32_t MMAR;
+	uint32_t BFAR;
+};
+
+
+//--functions-------------------------------------------------------------------
+
+#endif //_PWR_REGS_H_
+