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Fix majors bugs in tim module

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This commit is contained in:
Steins7 2024-10-21 17:04:45 +02:00
parent a0dadf166d
commit ae9cdc3582
1 changed files with 9 additions and 40 deletions
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47
drv/tim.c
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@ -47,13 +47,12 @@ void tim_configure_master(enum TimPeriph periph, enum TimConfig config_mask,
callbacks[periph] = callback;
regs[periph]->dier.TIE = 1;
regs[periph]->dier.UIE = 1;
regs[periph]->dier.UIE = 0;
enum NvicIrq irq = 0;
switch (periph) {
case TIM_PERIPH_1:
irq = NVIC_IRQ_TIM1_BRK | NVIC_IRQ_TIM1_UP
| NVIC_IRQ_TIM1_TRG_COM | NVIC_IRQ_TIM1_CC;
irq = NVIC_IRQ_TIM1_UP;
break;
case TIM_PERIPH_2:
irq = NVIC_IRQ_TIM2;
@ -71,6 +70,12 @@ void tim_configure_master(enum TimPeriph periph, enum TimConfig config_mask,
//trigger update to force application of the config
regs[periph]->egr.UG = 1;
while (regs[periph]->sr.UIF == 0) {}
regs[periph]->sr.UIF = 0;
if (callback != nullptr) {
regs[periph]->dier.UIE = 1;
}
}
@ -144,48 +149,12 @@ static enum TimIRQSource computeIRQSource(enum TimPeriph periph)
//--ISRs------------------------------------------------------------------------
void hdr_tim1_brk(void)
{
nvic_clear_pending(NVIC_IRQ_TIM1_BRK);
enum TimIRQSource src = computeIRQSource(TIM_PERIPH_1);
if (callbacks[TIM_PERIPH_1] != nullptr) {
callbacks[TIM_PERIPH_1](src);
}
}
void hdr_tim1_up(void)
{
nvic_clear_pending(NVIC_IRQ_TIM1_UP);
enum TimIRQSource src = computeIRQSource(TIM_PERIPH_1);
if (callbacks[TIM_PERIPH_1] != nullptr) {
callbacks[TIM_PERIPH_1](src);
}
}
void hdr_tim1_trg_com(void)
{
nvic_clear_pending(NVIC_IRQ_TIM1_TRG_COM);
enum TimIRQSource src = computeIRQSource(TIM_PERIPH_1);
if (callbacks[TIM_PERIPH_1] != nullptr) {
callbacks[TIM_PERIPH_1](src);
}
}
void hdr_tim1_cc(void)
{
nvic_clear_pending(NVIC_IRQ_TIM1_CC);
enum TimIRQSource src = computeIRQSource(TIM_PERIPH_1);
if (callbacks[TIM_PERIPH_1] != nullptr) {
callbacks[TIM_PERIPH_1](src);
}
}
void hdr_tim2(void)