Replace rcc's bitfields with macros
Bitfields can use byte acces, which the bus doesn't permit. When that happens, the bus adds extra bytes to form a word, modifying fields that shouldn't be. Bitfields can be kept for debug and read, but writes must be done though masks
This commit is contained in:
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aeba78cfcc
commit
c1b3f0d073
@ -25,6 +25,7 @@ static void apply_speed_preset(void);
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//--local variables-------------------------------------------------------------
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static volatile struct RCC* regs = (struct RCC*)RCC_BASE_ADDRESS;
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static enum RccPreset current_preset = RCC_PRESET_DEFAULT;
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//--public functions------------------------------------------------------------
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@ -44,9 +45,11 @@ void rcc_configure(enum RccPreset preset)
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switch (preset) {
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case RCC_PRESET_DEFAULT:
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apply_default_preset();
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current_preset = RCC_PRESET_DEFAULT;
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break;
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case RCC_PRESET_SPEED:
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apply_speed_preset();
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current_preset = RCC_PRESET_SPEED;
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break;
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default:
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break;
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@ -79,6 +82,26 @@ void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask)
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regs->APB2RSTR.word &= !(apb2_mask & APB2_MASK);
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}
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void rcc_get_clocks(struct RccClocks* clocks)
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{
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switch (current_preset)
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{
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case RCC_PRESET_DEFAULT:
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clocks->ahb_freq = 8000000;
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clocks->apb1_freq = 8000000;
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clocks->apb2_freq = 8000000;
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break;
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case RCC_PRESET_SPEED:
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clocks->ahb_freq = 72000000;
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clocks->apb1_freq = 36000000;
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clocks->apb2_freq = 72000000;
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break;
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default:
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//TODO hardfault
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break;
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}
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}
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//--local functions-------------------------------------------------------------
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@ -90,25 +113,26 @@ void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask)
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static void apply_default_preset(void)
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{
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//ensures HSI is enabled
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regs->CR.HSION = 0x1;
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reg_set(regs->CR, RCC_CR_HSION);
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while (regs->CR.HSIRDY != 0x1);
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//set HSI as main clock source and disable prescalers
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regs->CFGR.word &= ~0x077fff3;
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//disable all options
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regs->CR.HSITRIM = 0x10;
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regs->CR.HSEON = 0x0;
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regs->CR.HSEBYP = 0x0;
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regs->CR.CCSON = 0x0;
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regs->CR.PLLON = 0x0;
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reg_reset(regs->CR, RCC_CR_HSITRIM);
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reg_write(regs->CR, RCC_CR_HSITRIM, 0x10);
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reg_reset(regs->CR, RCC_CR_HSEON);
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reg_reset(regs->CR, RCC_CR_HSEBYP);
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reg_reset(regs->CR, RCC_CR_CCSON);
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reg_reset(regs->CR, RCC_CR_PLLON);
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//disable all interrupts
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regs->CIR.LSIRDYIE = 0x0;
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regs->CIR.LSERDYIE = 0x0;
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regs->CIR.HSIRDYIE = 0x0;
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regs->CIR.HSERDYIE = 0x0;
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regs->CIR.PLLRDYIE = 0x0;
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reg_reset(regs->CIR, RCC_CIR_LSIRDYIE);
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reg_reset(regs->CIR, RCC_CIR_LSERDYIE);
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reg_reset(regs->CIR, RCC_CIR_HSIRDYIE);
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reg_reset(regs->CIR, RCC_CIR_HSERDYIE);
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reg_reset(regs->CIR, RCC_CIR_PLLRDYIE);
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//reconfigure flash
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flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED);
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@ -125,35 +149,35 @@ static void apply_speed_preset(void)
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apply_default_preset();
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//try enabling HSE, fallback to HSI if HSE fails
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regs->CR.HSEON = 0x1;
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reg_set(regs->CR, RCC_CR_HSEON);
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for (uint32_t i=0; i<1000; ++i) {
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__asm__("nop");
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}
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if (regs->CR.HSERDY == 0x1) {
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regs->CFGR.PLLSCR = 0x1;
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reg_set(regs->CFGR, RCC_CFGR_PLLSCR);
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} else {
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regs->CR.HSEON = 0;
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reg_reset(regs->CR, RCC_CR_HSEON);
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}
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//configure PLL, fallback to HSI if PLL fails
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regs->CFGR.PLLMUL = 0x7; //PLL x9
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regs->CR.PLLON = 0x1;
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reg_write(regs->CFGR, RCC_CFGR_PLLMUL, 0x7); //PLL x9
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reg_set(regs->CR, RCC_CR_PLLON);
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for (uint32_t i=0; i<1000; ++i) {
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__asm__("nop");
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}
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if (regs->CR.PLLRDY != 0x1) {
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regs->CR.PLLON = 0x0;
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reg_reset(regs->CR, RCC_CR_PLLON);
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return; //clock low enough, no need for prescalers
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}
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//configure prescalers
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regs->CFGR.PPRE1 = 0x4; // /2
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regs->CFGR.ADCPRE = 0x2; // /6
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reg_write(regs->CFGR, RCC_CFGR_PPRE1, 0x4); // /2
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reg_write(regs->CFGR, RCC_CFGR_ADCPRE, 0x2); // /6
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//reconfigure flash
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flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED);
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//switch to PLL output
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regs->CFGR.SW = 0x2;
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reg_write(regs->CFGR, RCC_CFGR_SW, 0x2);
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}
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@ -95,6 +95,12 @@ enum RccApb2 {
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RCC_APB2_TIM11 = (0x1 << 21),
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};
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struct RccClocks {
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uint32_t ahb_freq;
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uint32_t apb1_freq;
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uint32_t apb2_freq;
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};
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//--functions-------------------------------------------------------------------
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@ -129,6 +135,8 @@ void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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*/
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void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask);
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void rcc_get_clocks(struct RccClocks* clocks);
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#endif //_RCC_H_
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@ -11,6 +11,8 @@
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//--includes--------------------------------------------------------------------
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#include "reg.h"
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#include "stdint.h"
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@ -37,6 +39,20 @@ union RCC_CR {
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uint32_t word;
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};
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#define RCC_CR_HSION reg_def( 0, 1)
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#define RCC_CR_HSIRDY reg_def( 1, 1)
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#define RCC_CR_reserved1 reg_def( 2, 1)
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#define RCC_CR_HSITRIM reg_def( 3, 5)
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#define RCC_CR_HSICAL reg_def( 8, 8)
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#define RCC_CR_HSEON reg_def(16, 1)
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#define RCC_CR_HSERDY reg_def(17, 1)
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#define RCC_CR_HSEBYP reg_def(18, 1)
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#define RCC_CR_CCSON reg_def(19, 1)
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#define RCC_CR_reserved2 reg_def(20, 4)
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#define RCC_CR_PLLON reg_def(24, 1)
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#define RCC_CR_PLLRDY reg_def(25, 1)
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#define RCC_CR_reserved3 reg_def(26, 6)
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union RCC_CFGR {
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struct __attribute__((packed)) {
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uint32_t SW:2;
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@ -56,6 +72,20 @@ union RCC_CFGR {
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uint32_t word;
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};
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#define RCC_CFGR_SW reg_def( 0, 2)
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#define RCC_CFGR_SWS reg_def( 2, 2)
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#define RCC_CFGR_HPRE reg_def( 4, 4)
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#define RCC_CFGR_PPRE1 reg_def( 8, 3)
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#define RCC_CFGR_PPRE2 reg_def(11, 3)
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#define RCC_CFGR_ADCPRE reg_def(14, 2)
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#define RCC_CFGR_PLLSCR reg_def(16, 1)
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#define RCC_CFGR_PLLXTPRE reg_def(17, 1)
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#define RCC_CFGR_PLLMUL reg_def(18, 4)
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#define RCC_CFGR_USBPRE reg_def(22, 1)
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#define RCC_CFGR_reserved1 reg_def(23, 1)
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#define RCC_CFGR_MCO reg_def(24, 3)
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#define RCC_CFGR_reserved2 reg_def(27, 5)
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union RCC_CIR {
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struct __attribute__((packed)) {
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uint32_t LSIRDYF:1;
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@ -83,6 +113,28 @@ union RCC_CIR {
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uint32_t word;
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};
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#define RCC_CIR_LSIRDYF reg_def( 0, 1)
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#define RCC_CIR_LSERDYF reg_def( 1, 1)
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#define RCC_CIR_HSIRDYF reg_def( 2, 1)
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#define RCC_CIR_HSERDYF reg_def( 3, 1)
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#define RCC_CIR_PLLRDYF reg_def( 4, 1)
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#define RCC_CIR_reserved1 reg_def( 5, 2)
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#define RCC_CIR_CSSF reg_def( 7, 1)
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#define RCC_CIR_LSIRDYIE reg_def( 8, 1)
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#define RCC_CIR_LSERDYIE reg_def( 9, 1)
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#define RCC_CIR_HSIRDYIE reg_def(10, 1)
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#define RCC_CIR_HSERDYIE reg_def(11, 1)
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#define RCC_CIR_PLLRDYIE reg_def(12, 1)
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#define RCC_CIR_RSE2 reg_def(13, 3)
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#define RCC_CIR_LSIRDYC reg_def(16, 1)
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#define RCC_CIR_LSERDYC reg_def(17, 1)
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#define RCC_CIR_HSIRDYC reg_def(18, 1)
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#define RCC_CIR_HSERDYC reg_def(19, 1)
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#define RCC_CIR_PLLRDYC reg_def(20, 1)
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#define RCC_CIR_reserved3 reg_def(21, 2)
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#define RCC_CIR_CSSC reg_def(23, 1)
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#define RCC_CIR_reserved4 reg_def(24, 8)
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union RCC_APB2RSTR {
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struct __attribute__((packed)) {
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uint32_t AFIORST:1;
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@ -110,6 +162,28 @@ union RCC_APB2RSTR {
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uint32_t word;
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};
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#define RCC_APB2RSTR_AFIORST reg_def( 0, 1)
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#define RCC_APB2RSTR_reserved1 reg_def( 1, 1)
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#define RCC_APB2RSTR_IOPARST reg_def( 2, 1)
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#define RCC_APB2RSTR_IOPBRST reg_def( 3, 1)
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#define RCC_APB2RSTR_IOPCRST reg_def( 4, 1)
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#define RCC_APB2RSTR_IOPDRST reg_def( 5, 1)
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#define RCC_APB2RSTR_IOPERST reg_def( 6, 1)
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#define RCC_APB2RSTR_IOPFRST reg_def( 7, 1)
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#define RCC_APB2RSTR_IOPGRST reg_def( 8, 1)
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#define RCC_APB2RSTR_ADC1RST reg_def( 9, 1)
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#define RCC_APB2RSTR_ACD2RST reg_def(10, 1)
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#define RCC_APB2RSTR_TIM1RST reg_def(11, 1)
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#define RCC_APB2RSTR_SPI1RST reg_def(12, 1)
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#define RCC_APB2RSTR_TIM8RST reg_def(13, 1)
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#define RCC_APB2RSTR_USART1RST reg_def(14, 1)
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#define RCC_APB2RSTR_ADC3RST reg_def(15, 1)
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#define RCC_APB2RSTR_reserved2 reg_def(16, 3)
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#define RCC_APB2RSTR_TIM9RST reg_def(19, 1)
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#define RCC_APB2RSTR_TIM10RST reg_def(20, 1)
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#define RCC_APB2RSTR_TIM11RST reg_def(21, 1)
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#define RCC_APB2RSTR_reserved3 reg_def(22, 10)
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union RCC_APB1RSTR {
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struct __attribute__((packed)) {
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uint32_t TIM2RST:1;
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@ -145,6 +219,36 @@ union RCC_APB1RSTR {
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uint32_t word;
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};
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#define RCC_APB1RSTR_TIM2RST reg_def( 0, 1)
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#define RCC_APB1RSTR_TIM3RST reg_def( 1, 1)
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#define RCC_APB1RSTR_TIM4RST reg_def( 2, 1)
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#define RCC_APB1RSTR_TIM5RST reg_def( 3, 1)
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#define RCC_APB1RSTR_TIM6RST reg_def( 4, 1)
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#define RCC_APB1RSTR_TIM7RST reg_def( 5, 1)
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#define RCC_APB1RSTR_TIM12RST reg_def( 6, 1)
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#define RCC_APB1RSTR_TIM13RST reg_def( 7, 1)
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#define RCC_APB1RSTR_TIM14RST reg_def( 8, 1)
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#define RCC_APB1RSTR_reserved1 reg_def( 9, 2)
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#define RCC_APB1RSTR_WWDGRST reg_def(11, 1)
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#define RCC_APB1RSTR_reserved2 reg_def(12, 2)
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#define RCC_APB1RSTR_SPI2RST reg_def(14, 1)
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#define RCC_APB1RSTR_SPI3RST reg_def(15, 1)
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#define RCC_APB1RSTR_reserved3 reg_def(16, 1)
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#define RCC_APB1RSTR_USART2RST reg_def(17, 1)
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#define RCC_APB1RSTR_USART3RST reg_def(18, 1)
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#define RCC_APB1RSTR_UART4RST reg_def(19, 1)
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#define RCC_APB1RSTR_UART5RST reg_def(20, 1)
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#define RCC_APB1RSTR_I2C12RST reg_def(21, 1)
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#define RCC_APB1RSTR_I2C2RST reg_def(22, 1)
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#define RCC_APB1RSTR_USB2RST reg_def(23, 1)
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#define RCC_APB1RSTR_reserved4 reg_def(24, 1)
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#define RCC_APB1RSTR_CANRST reg_def(25, 1)
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#define RCC_APB1RSTR_reserved5 reg_def(26, 1)
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#define RCC_APB1RSTR_BKPRST reg_def(27, 1)
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#define RCC_APB1RSTR_PWRRST reg_def(28, 1)
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#define RCC_APB1RSTR_DACRST reg_def(29, 1)
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#define RCC_APB1RSTR_reserved6 reg_def(30, 2)
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union RCC_AHBENR {
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struct __attribute__((packed)) {
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uint32_t DMA1EN:1;
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@ -163,6 +267,19 @@ union RCC_AHBENR {
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uint32_t word;
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};
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#define RCC_AHBENR_DMA1EN reg_def( 0, 1)
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#define RCC_AHBENR_DMA2EN reg_def( 1, 1)
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#define RCC_AHBENR_SRAMEN reg_def( 2, 1)
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#define RCC_AHBENR_reserved1 reg_def( 3, 1)
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#define RCC_AHBENR_FLITFEN reg_def( 4, 1)
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#define RCC_AHBENR_reserved2 reg_def( 5, 1)
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#define RCC_AHBENR_CRCEN reg_def( 6, 1)
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#define RCC_AHBENR_reserved3 reg_def( 7, 1)
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#define RCC_AHBENR_FSMCEN reg_def( 8, 1)
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#define RCC_AHBENR_reserved4 reg_def( 9, 1)
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#define RCC_AHBENR_SDIOEN reg_def(10, 1)
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#define RCC_AHBENR_reserved5 reg_def(11, 21)
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union RCC_APB2ENR {
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struct __attribute__((packed)) {
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uint32_t AFIOEN:1;
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@ -190,6 +307,28 @@ union RCC_APB2ENR {
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uint32_t word;
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};
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#define RCC_APB2ENR_AFIOEN reg_def( 0, 1)
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#define RCC_APB2ENR_reserved1 reg_def( 1, 1)
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#define RCC_APB2ENR_IOPAEN reg_def( 2, 1)
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#define RCC_APB2ENR_IOPBEN reg_def( 3, 1)
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#define RCC_APB2ENR_IOPCEN reg_def( 4, 1)
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#define RCC_APB2ENR_IOPDEN reg_def( 5, 1)
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#define RCC_APB2ENR_IOPEEN reg_def( 6, 1)
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#define RCC_APB2ENR_IOPFEN reg_def( 7, 1)
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#define RCC_APB2ENR_IOPGEN reg_def( 8, 1)
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#define RCC_APB2ENR_ADC1EN reg_def( 9, 1)
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#define RCC_APB2ENR_ACD2EN reg_def(10, 1)
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#define RCC_APB2ENR_TIM1EN reg_def(11, 1)
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#define RCC_APB2ENR_SPI1EN reg_def(12, 1)
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#define RCC_APB2ENR_TIM8EN reg_def(13, 1)
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#define RCC_APB2ENR_USART1EN reg_def(14, 1)
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#define RCC_APB2ENR_ADC3EN reg_def(15, 1)
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#define RCC_APB2ENR_reserved2 reg_def(16, 3)
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#define RCC_APB2ENR_TIM9EN reg_def(19, 1)
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#define RCC_APB2ENR_TIM10EN reg_def(20, 1)
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#define RCC_APB2ENR_TIM11EN reg_def(21, 1)
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#define RCC_APB2ENR_reserved3 reg_def(22, 10)
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union RCC_APB1ENR {
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struct __attribute__((packed)) {
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uint32_t TIM2EN:1;
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@ -225,6 +364,36 @@ union RCC_APB1ENR {
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uint32_t word;
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};
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#define RCC_APB1ENR_TIM2EN reg_def( 0, 1)
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#define RCC_APB1ENR_TIM3EN reg_def( 1, 1)
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#define RCC_APB1ENR_TIM4EN reg_def( 2, 1)
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#define RCC_APB1ENR_TIM5EN reg_def( 3, 1)
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#define RCC_APB1ENR_TIM6EN reg_def( 4, 1)
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#define RCC_APB1ENR_TIM7EN reg_def( 5, 1)
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#define RCC_APB1ENR_TIM12EN reg_def( 6, 1)
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#define RCC_APB1ENR_TIM13EN reg_def( 7, 1)
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#define RCC_APB1ENR_TIM14EN reg_def( 8, 1)
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#define RCC_APB1ENR_reserved1 reg_def( 9, 2)
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#define RCC_APB1ENR_WWDGEN reg_def(11, 1)
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#define RCC_APB1ENR_reserved reg_def(12, 2)
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#define RCC_APB1ENR_SPI2EN reg_def(14, 1)
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#define RCC_APB1ENR_SPI3EN reg_def(15, 1)
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#define RCC_APB1ENR_reserved2 reg_def(16, 1)
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#define RCC_APB1ENR_USART2EN reg_def(17, 1)
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#define RCC_APB1ENR_USART3EN reg_def(18, 1)
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#define RCC_APB1ENR_UART4EN reg_def(19, 1)
|
||||
#define RCC_APB1ENR_UART5EN reg_def(20, 1)
|
||||
#define RCC_APB1ENR_I2C12EN reg_def(21, 1)
|
||||
#define RCC_APB1ENR_I2C2EN reg_def(22, 1)
|
||||
#define RCC_APB1ENR_USB2EN reg_def(23, 1)
|
||||
#define RCC_APB1ENR_reserved3 reg_def(24, 1)
|
||||
#define RCC_APB1ENR_CANEN reg_def(25, 1)
|
||||
#define RCC_APB1ENR_reserved4 reg_def(26, 1)
|
||||
#define RCC_APB1ENR_BKPEN reg_def(27, 1)
|
||||
#define RCC_APB1ENR_PWREN reg_def(28, 1)
|
||||
#define RCC_APB1ENR_DACEN reg_def(29, 1)
|
||||
#define RCC_APB1ENR_reserved5 reg_def(30, 2)
|
||||
|
||||
union RCC_BDCR {
|
||||
struct __attribute__((packed)) {
|
||||
uint32_t LSEON:1;
|
||||
@ -240,6 +409,16 @@ union RCC_BDCR {
|
||||
uint32_t word;
|
||||
};
|
||||
|
||||
#define RCC_BDCR_LSEON reg_def( 0, 1)
|
||||
#define RCC_BDCR_LSERDY reg_def( 1, 1)
|
||||
#define RCC_BDCR_LSEBYP reg_def( 2, 1)
|
||||
#define RCC_BDCR_reserved1 reg_def( 3, 5)
|
||||
#define RCC_BDCR_RTCSEL reg_def( 8, 2)
|
||||
#define RCC_BDCR_reserved2 reg_def(10, 5)
|
||||
#define RCC_BDCR_RTCEN reg_def(15, 1)
|
||||
#define RCC_BDCR_BDRST reg_def(16, 1)
|
||||
#define RCC_BDCR_reserved3 reg_def(17, 15)
|
||||
|
||||
union RCC_CSR {
|
||||
struct __attribute__((packed)) {
|
||||
uint32_t LSION:1;
|
||||
@ -257,6 +436,18 @@ union RCC_CSR {
|
||||
uint32_t word;
|
||||
};
|
||||
|
||||
#define RCC_CSR_LSION reg_def( 0, 1)
|
||||
#define RCC_CSR_LSIRDY reg_def( 1, 1)
|
||||
#define RCC_CSR_reserved1 reg_def( 2, 22)
|
||||
#define RCC_CSR_RMVF reg_def(24, 1)
|
||||
#define RCC_CSR_reserved2 reg_def(25, 1)
|
||||
#define RCC_CSR_PINRSTF reg_def(26, 1)
|
||||
#define RCC_CSR_PORRSTF reg_def(27, 1)
|
||||
#define RCC_CSR_SFTRSTF reg_def(28, 1)
|
||||
#define RCC_CSR_IWDGRSTF reg_def(29, 1)
|
||||
#define RCC_CSR_WWDGRSTF reg_def(30, 1)
|
||||
#define RCC_CSR_LPWRSTF reg_def(31, 1)
|
||||
|
||||
struct __attribute__((packed)) RCC {
|
||||
union RCC_CR CR;
|
||||
union RCC_CFGR CFGR;
|
||||
|
||||
15
drivers/reg.h
Normal file
15
drivers/reg.h
Normal file
@ -0,0 +1,15 @@
|
||||
|
||||
#define reg_def(pos, size) pos, (((0x1 << size) - 1) << pos)
|
||||
|
||||
#define reg_set(reg, field) _reg_set(reg, field)
|
||||
#define _reg_set(reg, pos, mask) do { reg.word |= mask; } while (false)
|
||||
|
||||
#define reg_reset(reg, field) _reg_reset(reg, field)
|
||||
#define _reg_reset(reg, pos, mask) do { reg.word &= ~mask; } while (false)
|
||||
|
||||
#define reg_write(reg, field, value) _reg_write(reg, field, value)
|
||||
#define _reg_write(reg, pos, mask, value) \
|
||||
do { \
|
||||
reg.word |= value << pos; \
|
||||
} while (false) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user