Add LSI configuration function to RCC

drv/pwr.c

@@ -0,0 +1,51 @@
+/** @file pwr.c
+ * Module handling the power management's control
+ *
+ * The module provides functions to enter the different sleep states, control
+ * and filter wakeup events (WKUP and RTC) and configure power voltage
+ * detection
+ */
+
+//--includes--------------------------------------------------------------------
+
+#include "pwr.h"
+#include "pwr_regs.h"
+#include "scb.h"
+
+
+//--local definitions-----------------------------------------------------------
+
+//--local variables-------------------------------------------------------------
+
+static volatile struct PWR* regs = (struct PWR*)PWR_BASE_ADDRESS;
+
+
+//--public functions------------------------------------------------------------
+
+void pwr_sleep(void)
+{
+	scb_configure_deepsleep(false);
+	__asm("wfi");
+}
+
+void pwr_stop(enum PwrWakeupSpeed speed)
+{
+	scb_configure_deepsleep(true);
+	regs->CR.PDDS = 0;
+	regs->CR.LPDS = speed;
+	__asm("wfi");
+}
+
+void pwr_standby(void)
+{
+	scb_configure_deepsleep(true);
+	regs->CR.PDDS = 1;
+	__asm("wfi");
+}
+
+
+//--local functions-------------------------------------------------------------
+
+//--ISRs------------------------------------------------------------------------
+
+

drv/pwr.h

@@ -0,0 +1,51 @@
+/** @file pwr.h
+ * Module handling the power management's control
+ *
+ * The module provides functions to enter the different sleep states, control
+ * and filter wakeup events (WKUP and RTC) and configure power voltage
+ * detection
+ */
+
+#ifndef _PWR_H_
+#define _PWR_H_
+
+//--includes--------------------------------------------------------------------
+
+//--type definitions------------------------------------------------------------
+
+enum PwrWakeupSpeed {
+	PWR_WAKEUP_SPEED_FAST, //faster wakeup, higher consumption in stop mode
+	PWR_WAKEUP_SPEED_SLOW, //slower wakeup, lower consumption in stop mode
+};
+
+enum PwrPvdThreshold {
+	PWR_PVD_THRESHOLD_2_2V,
+	PWR_PVD_THRESHOLD_2_3V,
+	PWR_PVD_THRESHOLD_2_4V,
+	PWR_PVD_THRESHOLD_2_5V,
+	PWR_PVD_THRESHOLD_2_6V,
+	PWR_PVD_THRESHOLD_2_7V,
+	PWR_PVD_THRESHOLD_2_8V,
+	PWR_PVD_THRESHOLD_2_9V,
+
+};
+
+typedef void (*PwrPvdCallback)(void);
+
+
+//--functions-------------------------------------------------------------------
+
+void pwr_sleep(void);
+void pwr_stop(enum PwrWakeupSpeed speed);
+void pwr_standby(void);
+
+bool pwr_wakeup_event(void);
+bool pwr_standby_exit(void);
+
+void pwr_configure_bkp_write(bool enable);
+void pwr_configure_wakeup_pin(bool enable);
+void pwr_configure_pvd(enum PwrPvdThreshold treshold);
+
+
+#endif //_PWR_H_
+

drv/pwr_regs.h

@@ -0,0 +1,56 @@
+/** @file pwr_regs.h
+ * Module defining Power control (PWR) registers.
+ *
+ * Mainly made to be used by the pwr module. It is recommanded to go through
+ * the functions provided by that module instead of directly using the registers
+ * defined here.
+ */
+
+#ifndef _PWR_REGS_H_
+#define _PWR_REGS_H_
+
+//--includes--------------------------------------------------------------------
+
+#include "stdint.h"
+
+
+//--type definitions------------------------------------------------------------
+
+#define PWR_BASE_ADDRESS 0x40007000
+
+union PWR_CR {
+	struct {
+		uint32_t LPDS:1;
+		uint32_t PDDS:1;
+		uint32_t CWUF:1;
+		uint32_t CSBF:1;
+		uint32_t PVDE:1;
+		uint32_t PLS:3;
+		uint32_t DBP:1;
+		uint32_t reserved1:23;
+	};
+	uint32_t word;
+};
+
+union PWR_CSR  {
+	struct {
+		uint32_t WUF:1;
+		uint32_t SBF:1;
+		uint32_t PVDO:1;
+		uint32_t reserved1:5;
+		uint32_t EWUP:1;
+		uint32_t reserved2:23;
+	};
+	uint32_t word;
+};
+
+struct PWR {
+	union PWR_CR CR;
+	union PWR_CSR CSR;
+};
+
+
+//--functions-------------------------------------------------------------------
+
+#endif //_PWR_REGS_H_
+

drv/rcc.c

@@ -60,6 +60,16 @@ void rcc_configure(enum RccPreset preset)
 	regs->APB2ENR = apb2_enr;
 }
 
+void rcc_configure_lsi(bool enable)
+{
+	regs->CSR.LSION = enable;
+
+	//ensure LSI is enabled
+	if (enable) {
+		while (regs->CSR.LSIRDY != 0x1);
+	}
+}
+
 void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
 		enum RccApb2 apb2_mask)
 {

drv/rcc.h

@@ -112,6 +112,12 @@ struct RccClocks {
  */
 void rcc_configure(enum RccPreset preset);
 
+/**
+ * Configures the Low Speed Internal (LSI) oscillator for low power
+ * applications.
+ */
+void rcc_configure_lsi(bool enable);
+
 /**
  * Enables peripherals on the different buses. The enums values can used as
  * masks to enable multiple peripherals at the same time. Invalid values will be

drv/scb.c

@@ -0,0 +1,64 @@
+/** @file scb.c
+ * Module handling the System Control Block
+ *
+ * The module provides functions to configure miscelaneous options of the cortex
+ * m3, including sleep behavior, event handler priorities, resets and fault
+ * handlers
+ */
+
+//--includes--------------------------------------------------------------------
+
+#include "scb.h"
+#include "scb_regs.h"
+
+
+//--local definitions-----------------------------------------------------------
+
+//--local variables-------------------------------------------------------------
+
+static volatile struct SCB* regs = (struct SCB*)SCB_BASE_ADDRESS;
+
+
+//--public functions------------------------------------------------------------
+
+uint16_t scb_pending_exception(void)
+{
+	return regs->ICSR.VECTPENDING;
+}
+
+uint16_t scb_active_exception(void)
+{
+	return regs->ICSR.VECTACTIVE;
+}
+
+void scb_configure_vector_table(uint32_t offset)
+{
+	//TODO check that last LSB is 0 (alignement restrictions)
+	regs->VTOR.TABLEOFF = offset & 0x1FFFFF;
+}
+
+void scb_reset_system(void)
+{
+	regs->AIRCR.SYSRESETREQ = 1;
+}
+
+void scb_configure_deepsleep(bool enable)
+{
+	regs->SCR.SLEEPDEEP = enable;
+}
+
+void scb_configure_div0_fault(bool enable)
+{
+	regs->CCR.DIV_0_TRP = enable;
+}
+
+void scb_configure_unalign_fault(bool enable)
+{
+	regs->CCR.UNALIGN_TRP = enable;
+}
+
+
+//--local functions-------------------------------------------------------------
+
+//--ISRs------------------------------------------------------------------------
+

drv/scb.h

@@ -0,0 +1,32 @@
+/** @file scb.h
+ * Module handling the System Control Block
+ *
+ * The module provides functions to configure miscelaneous options of the cortex
+ * m3, including sleep behavior, event handler priorities, resets and fault
+ * handlers
+ */
+
+#ifndef _SCB_H_
+#define _SCB_H_
+
+//--includes--------------------------------------------------------------------
+
+#include "stdint.h"
+
+
+//--type definitions------------------------------------------------------------
+
+//--functions-------------------------------------------------------------------
+
+uint16_t scb_pending_exception(void);
+uint16_t scb_active_exception(void);
+
+void scb_configure_vector_table(uint32_t offset);
+void scb_reset_system(void);
+void scb_configure_deepsleep(bool enable);
+void scb_configure_div0_fault(bool enable);
+void scb_configure_unalign_fault(bool enable);
+
+
+#endif //_SCB_H_
+

drv/scb_regs.h

@@ -0,0 +1,192 @@
+/** @file scb_regs.h
+ * Module defining System Control Block (SCB) registers.
+ *
+ * Mainly made to be used by the scb module. It is recommanded to go through
+ * the functions provided by that module instead of directly using the registers
+ * defined here.
+ */
+
+#ifndef _SCB_REGS_H_
+#define _SCB_REGS_H_
+
+//--includes--------------------------------------------------------------------
+
+#include "stdint.h"
+
+
+//--type definitions------------------------------------------------------------
+
+#define SCB_BASE_ADDRESS 0xE000ED00
+
+union SCB_CPUID {
+	struct {
+		uint32_t revision:4;
+		uint32_t part_no:12;
+		uint32_t constant:4;
+		uint32_t variant:4;
+		uint32_t implementer:8;
+	};
+	uint32_t word;
+};
+
+union SCB_ICSR {
+	struct {
+		uint32_t VECTACTIVE:9;
+		uint32_t reserved1:2;
+		uint32_t RETOBASE:1;
+		uint32_t VECTPENDING:10;
+		uint32_t ISRPENDING:1;
+		uint32_t reserved2:2;
+		uint32_t PENDSTCLR:1;
+		uint32_t PENDSTSET:1;
+		uint32_t PENDSVCRL:1;
+		uint32_t PENDSVSET:1;
+		uint32_t reserved3:2;
+		uint32_t NMIPENDSET:1;
+	};
+	uint32_t word;
+};
+
+union SCB_VTOR {
+	struct {
+		uint32_t reserved1:9;
+		uint32_t TABLEOFF:21;
+		uint32_t reserved2:2;
+	};
+	uint32_t word;
+};
+
+union SCB_AIRCR {
+	struct {
+		uint32_t VECTRESET:1;
+		uint32_t VECTCRLACTIVE:1;
+		uint32_t SYSRESETREQ:1;
+		uint32_t reserved1:5;
+		uint32_t PRIGROUP:3;
+		uint32_t reserved2:4;
+		uint32_t ENDIANESS:1;
+		uint32_t VECTKEY:16;
+	};
+	uint32_t word;
+};
+
+union SCB_SCR {
+	struct {
+		uint32_t reserved1:1;
+		uint32_t SLEEPONEXIT:1;
+		uint32_t SLEEPDEEP:1;
+		uint32_t reserved2:1;
+		uint32_t SEVONPEND:1;
+		uint32_t reserved3:27;
+	};
+	uint32_t word;
+};
+
+union SCB_CCR {
+	struct {
+		uint32_t NONBASETHRDEN:1;
+		uint32_t USERSETMPEND:1;
+		uint32_t reserved1:1;
+		uint32_t UNALIGN_TRP:1;
+		uint32_t DIV_0_TRP:1;
+		uint32_t reserved2:3;
+		uint32_t BFHFNIGN:1;
+		uint32_t STKALIGN:1;
+		uint32_t reserved3:22;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR1 {
+	struct {
+		uint32_t PRI4:8;
+		uint32_t PRI5:8;
+		uint32_t PRI6:8;
+		uint32_t reserved1:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR2 {
+	struct {
+		uint32_t reserved1:24;
+		uint32_t PRI11:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHPR3 {
+	struct {
+		uint32_t reserved1:16;
+		uint32_t PRI14:8;
+		uint32_t PRI15:8;
+	};
+	uint32_t word;
+};
+
+union SCB_SHCRS {
+	struct {
+		uint32_t MEMFAULTACT:1;
+		uint32_t BUSFAULTACT:1;
+		uint32_t reserved1:1;
+		uint32_t USGFAULTACT:1;
+		uint32_t reserved2:3;
+		uint32_t SVCALLACT:1;
+		uint32_t MONITORACT:1;
+		uint32_t reserved3:1;
+		uint32_t PENDSVACT:1;
+		uint32_t SYSTICKACT:1;
+		uint32_t USGFAULTPENDED:1;
+		uint32_t MEMFAULTPENDED:1;
+		uint32_t BUSFAULTPENDED:1;
+		uint32_t SVCALLPENDED:1;
+		uint32_t MEMFAULTENA:1;
+		uint32_t BUSFAULTENA:1;
+		uint32_t USGFAULTENA:1;
+		uint32_t reserved4:13;
+	};
+	uint32_t word;
+};
+
+union SCB_CFSR {
+	struct {
+		uint32_t MMFSR:8;
+		uint32_t BFSR:8;
+		uint32_t UFSR:16;
+	};
+	uint32_t word;
+};
+
+union SCB_HFSR {
+	struct {
+		uint32_t reserved1:1;
+		uint32_t VECTTBL:1;
+		uint32_t reserved2:28;
+		uint32_t FORCED:1;
+		uint32_t DEBUG_VT:1;
+	};
+	uint32_t word;
+};
+
+struct SCB {
+	union SCB_CPUID CPUID;
+	union SCB_ICSR ICSR;
+	union SCB_VTOR VTOR;
+	union SCB_AIRCR AIRCR;
+	union SCB_SCR SCR;
+	union SCB_CCR CCR;
+	union SCB_SHPR1 SHPR1;
+	union SCB_SHPR2 SHPR2;
+	union SCB_SHPR3 SHPR3;
+	union SCB_SHCRS SHCRS;
+	union SCB_CFSR CFSR;
+	union SCB_HFSR HFSR;
+	uint32_t MMAR;
+	uint32_t BFAR;
+};
+
+
+//--functions-------------------------------------------------------------------
+
+#endif //_PWR_REGS_H_
+