From 4a12fa7a3d00a589141b5f9e281611c62cd210e6 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 11 Feb 2023 21:55:32 +0100 Subject: [PATCH 01/85] Reorganize repository to be used as a library Project was organized as an application, wich makes it less practical to include in other projects. A template project may be added back to make up for the missing files --- LICENSE | 21 - Makefile | 189 - README.md | 2 - {include/cmsis => cmsis}/arm_math.h | 0 {include/cmsis => cmsis}/cmsis_armcc.h | 0 {include/cmsis => cmsis}/cmsis_armclang.h | 0 {include/cmsis => cmsis}/cmsis_armclang_ltm.h | 0 {include/cmsis => cmsis}/cmsis_compiler.h | 0 {include/cmsis => cmsis}/cmsis_gcc.h | 0 {include/cmsis => cmsis}/cmsis_iccarm.h | 0 {include/cmsis => cmsis}/cmsis_version.h | 0 {include/cmsis => cmsis}/core_armv81mml.h | 0 {include/cmsis => cmsis}/core_armv8mbl.h | 0 {include/cmsis => cmsis}/core_armv8mml.h | 0 {include/cmsis => cmsis}/core_cm0.h | 0 {include/cmsis => cmsis}/core_cm0plus.h | 0 {include/cmsis => cmsis}/core_cm1.h | 0 {include/cmsis => cmsis}/core_cm23.h | 0 {include/cmsis => cmsis}/core_cm3.h | 0 {include/cmsis => cmsis}/core_cm33.h | 0 {include/cmsis => cmsis}/core_cm35p.h | 0 {include/cmsis => cmsis}/core_cm4.h | 0 {include/cmsis => cmsis}/core_cm7.h | 0 {include/cmsis => cmsis}/core_sc000.h | 0 {include/cmsis => cmsis}/core_sc300.h | 0 {include/cmsis => cmsis}/mpu_armv7.h | 0 {include/cmsis => cmsis}/mpu_armv8.h | 0 {include/cmsis => cmsis}/tz_context.h | 0 {docs => doc}/devices/HD44780.pdf | Bin {docs => doc}/en.CD00171190.pdf | Bin {docs => doc}/stm32f103c8.pdf | Bin src/target/STM32F103XB.ld => linker.ld | 0 openocd | 3 - src/drivers/io.c | 14 +- src/drivers/rnd.c | 20 + src/drivers/rnd.h | 11 + src/drivers/timer.c | 195 +- src/drivers/timer.h | 177 +- src/main.c | 52 - .../{stm32f1xx.h => stm32f1xx.h.unused} | 0 .../{system_clock.c => system_clock.c.unused} | 0 ..._stm32f1xx.h => system_stm32f1xx.h.unused} | 0 src/target/startup_stm32f103xb.s => startup.s | 0 src/target/stm32f103xb.h => target.h | 5120 ++++++++--------- 44 files changed, 2798 insertions(+), 3006 deletions(-) delete mode 100644 LICENSE delete mode 100644 Makefile delete mode 100644 README.md rename {include/cmsis => cmsis}/arm_math.h (100%) rename {include/cmsis => cmsis}/cmsis_armcc.h (100%) rename {include/cmsis => cmsis}/cmsis_armclang.h (100%) rename {include/cmsis => cmsis}/cmsis_armclang_ltm.h (100%) rename {include/cmsis => cmsis}/cmsis_compiler.h (100%) rename {include/cmsis => cmsis}/cmsis_gcc.h (100%) rename {include/cmsis => cmsis}/cmsis_iccarm.h (100%) rename {include/cmsis => cmsis}/cmsis_version.h (100%) rename {include/cmsis => cmsis}/core_armv81mml.h (100%) rename {include/cmsis => cmsis}/core_armv8mbl.h (100%) rename {include/cmsis => cmsis}/core_armv8mml.h (100%) rename {include/cmsis => cmsis}/core_cm0.h (100%) rename {include/cmsis => cmsis}/core_cm0plus.h (100%) rename {include/cmsis => cmsis}/core_cm1.h (100%) rename {include/cmsis => cmsis}/core_cm23.h (100%) rename {include/cmsis => cmsis}/core_cm3.h (100%) rename {include/cmsis => cmsis}/core_cm33.h (100%) rename {include/cmsis => cmsis}/core_cm35p.h (100%) rename {include/cmsis => cmsis}/core_cm4.h (100%) rename {include/cmsis => cmsis}/core_cm7.h (100%) rename {include/cmsis => cmsis}/core_sc000.h (100%) rename {include/cmsis => cmsis}/core_sc300.h (100%) rename {include/cmsis => cmsis}/mpu_armv7.h (100%) rename {include/cmsis => cmsis}/mpu_armv8.h (100%) rename {include/cmsis => cmsis}/tz_context.h (100%) rename {docs => doc}/devices/HD44780.pdf (100%) rename {docs => doc}/en.CD00171190.pdf (100%) rename {docs => doc}/stm32f103c8.pdf (100%) rename src/target/STM32F103XB.ld => linker.ld (100%) delete mode 100755 openocd create mode 100644 src/drivers/rnd.c create mode 100644 src/drivers/rnd.h delete mode 100644 src/main.c rename src/target/{stm32f1xx.h => stm32f1xx.h.unused} (100%) rename src/target/{system_clock.c => system_clock.c.unused} (100%) rename src/target/{system_stm32f1xx.h => system_stm32f1xx.h.unused} (100%) rename src/target/startup_stm32f103xb.s => startup.s (100%) rename src/target/stm32f103xb.h => target.h (77%) diff --git a/LICENSE b/LICENSE deleted file mode 100644 index c663abe..0000000 --- a/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2020 Steins7 - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/Makefile b/Makefile deleted file mode 100644 index 8858482..0000000 --- a/Makefile +++ /dev/null @@ -1,189 +0,0 @@ -#------------------------------------------------------------------------------- -# this GNU-makefile relies on the GCC toolchain - -# --- control global project settings -# RELEASE=1 -> enable optimisation, then disable debug -# RELEASE=0 -> disable optimisation, then enable debug -RELEASE=0 - -# --- project architecture -# program name -EXE_PREFIX=main -# project folders, This Makefile should be in the same folder as the SRC folder -SRC=src -BIN=bin -INC=include -LIB=lib -OBJ=${BIN}/obj -DEP=${BIN}/dep -# code folders, in the SRC folder -SUBFOLDERS=drivers target -# Define linker script file here -LDSCRIPT=${SRC}/target/STM32F103XB.ld - -# --- advanced config -# List all user C define here -UDEFS= -# Define ASM defines here -UADEFS= - -# --- toolchain configuration -TARGET=arm-none-eabi- -CC=${TARGET}gcc -CPP=${TARGET}g++ -OBJCOPY=${TARGET}objcopy -AS=${TARGET}gcc -x assembler-with-cpp -c -SIZE=${TARGET}size -OBJDUMP=${TARGET}objdump - -# --- hardware settings -ARCH=armv7-m -FLOAT-ABI=soft #no FPU on stm32f103 -CPU=cortex-m3 -CPUFLAGS=-mthumb -FPU=fpv4-sp-d16 #"FLOAT-ABI=soft" disable that - -#------------------------------------------------------------------------------- -# --- makefile pre-incantation - -# List all de:fault C defines here, like -D_DEBUG=1 -DDEFS=-march=${ARCH} -mfloat-abi=${FLOAT-ABI} -mcpu=${CPU} -mfpu=${FPU} $\ - ${CPUFLAGS} -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS=-D__ASSEMBLY__ - -# --- deduce file names -MAIN_C_FILES=${wildcard ${SRC}/${strip ${EXE_PREFIX}}*.c} -MAIN_CPP_FILES=${wildcard ${SRC}/${strip ${EXE_PREFIX}}*.cpp} - -COMMON_C_FILES=${filter-out ${MAIN_C_FILES},${wildcard ${SRC}/*.c}} -COMMON_C_FILES+=${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.c}} - -COMMON_CPP_FILES=${filter-out ${MAIN_CPP_FILES},${wildcard ${SRC}/*.cpp}} -COMMON_CPP_FILES+=${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.cpp}} - -COMMON_ASM_FILES=${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.s}} - -MAIN_OBJECT_FILES=${sort ${patsubst ${src}/%.c,${obj}/%.o,${MAIN_C_FILES}} \ - ${patsubst ${src}/%.cpp,${obj}/%.o,${MAIN_CPP_FILES}}} -COMMON_OBJECT_FILES=${sort \ - ${patsubst ${SRC}/%.c,${OBJ}/%.o,${COMMON_C_FILES}} \ - ${patsubst ${SRC}/%.cpp,${OBJ}/%.o,${COMMON_CPP_FILES}} \ - ${patsubst ${SRC}/%s,${OBJ}/%o,${COMMON_ASM_FILES}}} - -LIBRARIES=${foreach dir,${wildcard ${LIB}/*},${wildcard ${LIB}/${dir}/*.a}} - -OBJECT_FILES=${MAIN_OBJECT_FILES} ${COMMON_OBJECT_FILES} -DEPEND_FILES=${OBJECT_FILES:%.o,%.d} - -#------------------------------------------------------------------------------- -# --- makefile incantation -# down here is black magic, you probably don't want to modify anything - -DEFS=${DDEFS} ${UDEFS} -ADEFS=${DADEFS} ${UADEFS} - -# --- otpimisation -ifeq (${strip ${RELEASE}},0) - CFLAGS=-g3 -O0 -else - CFLAGS=-O3 -endif - -# --- c/cpp -ifneq (${strip ${MAIN_CPP_FILES} ${COMMON_CPP_FILES}},) - CC:=${CPP} - CFLAGS+=-std=c++17 -else - CFLAGS+=-std=c17 -endif - -ASFLAGS=${LIB} $(DEFS) -Wa,--gdwarf2 $(ADEFS) -CFLAGS+=-Wall ${DEFS} -Wextra -Warray-bounds -Wno-unused-parameter $\ - -fomit-frame-pointer -LDFLAGS=-T ${LDSCRIPT} -lc -lgcc -lgcov -lm -Wl,-Map=$@.map,--gc-sections $\ - --specs=nosys.specs -INCLUDE=-I ${INC} - -# --- Generate dependency information -CFLAGS+=-MD -MP -MF ${patsubst %o,%d,$@} -ASFLAGS+=#-MD -MP -MF ${patsubst %o,%d,$@} - -# --- folder tree -DIR_GUARD=@mkdir -p ${@D} - -#------------------------------------------------------------------------------- -# --- make rules -all: ${BIN}/${EXE_PREFIX}.elf ${BIN}/${EXE_PREFIX}.hex ${BIN}/${EXE_PREFIX}.bin - -rebuild : clean all - -.SUFFIXES: -.SECONDARY: -.PHONY: all clean rebuild - -# --- compiler command for elf file -${BIN}/%.elf : ${MAIN_OBJECT_FILES} ${COMMON_OBJECT_FILES} - @echo -e '\e[32;1m ==== linking $@ ====\e[0m' - @echo ${COMMON_OBJECT_FILES} - @echo - ${DIR_GUARD} - ${CC} ${INCLUDE} ${CFLAGS} -o $@ $^ ${LIBRARIES} ${LDFLAGS} - ${OBJDUMP} -h $@ - ${SIZE} $@ - @echo - -# --- compiler commands for uploadable files -${BIN}/%.hex : ${BIN}/%.elf - @echo -e '\e[33;1m ==== translating $< ====\e[0m' - ${OBJCOPY} -O ihex $< $@ - @echo - -${BIN}/%.bin : ${BIN}/%.elf - @echo -e '\e[33;1m ==== translating $< ====\e[0m' - ${OBJCOPY} -O binary $< $@ - @echo - -# --- compiler commands for every source file -${OBJ}/%.o : ${SRC}/%.cpp - @echo -e '\e[36;1m ==== compiling $< ====\e[0m' - ${DIR_GUARD} - ${CPP} ${INCLUDE} -c ${CFLAGS} $< -o $@ ${LIBRARIES} - @echo - -${BIN}/%.o : ${SRC}/%.cpp - @echo -e '\e[36;1m ==== compiling $< ====\e[0m' - ${DIR_GUARD} - ${CPP} ${INCLUDE} -c ${CFLAGS} $< -o $@ ${LIBRARIES} - @echo - -${OBJ}/%.o : ${SRC}/%.c - @echo -e '\e[34;1m ==== compiling $< ====\e[0m' - ${DIR_GUARD} - ${CC} ${INCLUDE} -c ${CFLAGS} $< -o $@ ${LIBRARIES} - @echo - -${BIN}/%.o : ${SRC}/%.c - @echo -e '\e[34;1m ==== compiling $< ====\e[0m' - ${DIR_GUARD} - ${CC} ${INCLUDE} -c ${CFLAGS} $< -o $@ ${LIBRARIES} - @echo - -${OBJ}/%.o : ${SRC}/%.s - @echo -e '\e[35;1m ==== compiling $^ ====\e[0m' - ${DIR_GUARD} - ${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES} - @echo - -${BIN}/%.o : ${SRC}/%.s - @echo -e '\e[35;1m ==== compiling $^ ====\e[0m' - ${DIR_GUARD} - ${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES} - @echo - -# --- remove generated files -clean: - -rm -rf ${BIN}/* - --include ${DEPEND_FILES} - diff --git a/README.md b/README.md deleted file mode 100644 index 98bd856..0000000 --- a/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# stm32f1xx_HBL -simplified HAL for stm32f1 microcontrollers, designed to be easily customized diff --git a/include/cmsis/arm_math.h b/cmsis/arm_math.h similarity index 100% rename from include/cmsis/arm_math.h rename to cmsis/arm_math.h diff --git a/include/cmsis/cmsis_armcc.h b/cmsis/cmsis_armcc.h similarity index 100% rename from include/cmsis/cmsis_armcc.h rename to cmsis/cmsis_armcc.h diff --git a/include/cmsis/cmsis_armclang.h b/cmsis/cmsis_armclang.h similarity index 100% rename from include/cmsis/cmsis_armclang.h rename to cmsis/cmsis_armclang.h diff --git a/include/cmsis/cmsis_armclang_ltm.h b/cmsis/cmsis_armclang_ltm.h similarity index 100% rename from include/cmsis/cmsis_armclang_ltm.h rename to cmsis/cmsis_armclang_ltm.h diff --git a/include/cmsis/cmsis_compiler.h b/cmsis/cmsis_compiler.h similarity index 100% rename from include/cmsis/cmsis_compiler.h rename to cmsis/cmsis_compiler.h diff --git a/include/cmsis/cmsis_gcc.h b/cmsis/cmsis_gcc.h similarity index 100% rename from include/cmsis/cmsis_gcc.h rename to cmsis/cmsis_gcc.h diff --git a/include/cmsis/cmsis_iccarm.h b/cmsis/cmsis_iccarm.h similarity index 100% rename from include/cmsis/cmsis_iccarm.h rename to cmsis/cmsis_iccarm.h diff --git a/include/cmsis/cmsis_version.h b/cmsis/cmsis_version.h similarity index 100% rename from include/cmsis/cmsis_version.h rename to cmsis/cmsis_version.h diff --git a/include/cmsis/core_armv81mml.h b/cmsis/core_armv81mml.h similarity index 100% rename from include/cmsis/core_armv81mml.h rename to cmsis/core_armv81mml.h diff --git a/include/cmsis/core_armv8mbl.h b/cmsis/core_armv8mbl.h similarity index 100% rename from include/cmsis/core_armv8mbl.h rename to cmsis/core_armv8mbl.h diff --git a/include/cmsis/core_armv8mml.h b/cmsis/core_armv8mml.h similarity index 100% rename from include/cmsis/core_armv8mml.h rename to cmsis/core_armv8mml.h diff --git a/include/cmsis/core_cm0.h b/cmsis/core_cm0.h similarity index 100% rename from include/cmsis/core_cm0.h rename to cmsis/core_cm0.h diff --git a/include/cmsis/core_cm0plus.h b/cmsis/core_cm0plus.h similarity index 100% rename from include/cmsis/core_cm0plus.h rename to cmsis/core_cm0plus.h diff --git a/include/cmsis/core_cm1.h b/cmsis/core_cm1.h similarity index 100% rename from include/cmsis/core_cm1.h rename to cmsis/core_cm1.h diff --git a/include/cmsis/core_cm23.h b/cmsis/core_cm23.h similarity index 100% rename from include/cmsis/core_cm23.h rename to cmsis/core_cm23.h diff --git a/include/cmsis/core_cm3.h b/cmsis/core_cm3.h similarity index 100% rename from include/cmsis/core_cm3.h rename to cmsis/core_cm3.h diff --git a/include/cmsis/core_cm33.h b/cmsis/core_cm33.h similarity index 100% rename from include/cmsis/core_cm33.h rename to cmsis/core_cm33.h diff --git a/include/cmsis/core_cm35p.h b/cmsis/core_cm35p.h similarity index 100% rename from include/cmsis/core_cm35p.h rename to cmsis/core_cm35p.h diff --git a/include/cmsis/core_cm4.h b/cmsis/core_cm4.h similarity index 100% rename from include/cmsis/core_cm4.h rename to cmsis/core_cm4.h diff --git a/include/cmsis/core_cm7.h b/cmsis/core_cm7.h similarity index 100% rename from include/cmsis/core_cm7.h rename to cmsis/core_cm7.h diff --git a/include/cmsis/core_sc000.h b/cmsis/core_sc000.h similarity index 100% rename from include/cmsis/core_sc000.h rename to cmsis/core_sc000.h diff --git a/include/cmsis/core_sc300.h b/cmsis/core_sc300.h similarity index 100% rename from include/cmsis/core_sc300.h rename to cmsis/core_sc300.h diff --git a/include/cmsis/mpu_armv7.h b/cmsis/mpu_armv7.h similarity index 100% rename from include/cmsis/mpu_armv7.h rename to cmsis/mpu_armv7.h diff --git a/include/cmsis/mpu_armv8.h b/cmsis/mpu_armv8.h similarity index 100% rename from include/cmsis/mpu_armv8.h rename to cmsis/mpu_armv8.h diff --git a/include/cmsis/tz_context.h b/cmsis/tz_context.h similarity index 100% rename from include/cmsis/tz_context.h rename to cmsis/tz_context.h diff --git a/docs/devices/HD44780.pdf b/doc/devices/HD44780.pdf similarity index 100% rename from docs/devices/HD44780.pdf rename to doc/devices/HD44780.pdf diff --git a/docs/en.CD00171190.pdf b/doc/en.CD00171190.pdf similarity index 100% rename from docs/en.CD00171190.pdf rename to doc/en.CD00171190.pdf diff --git a/docs/stm32f103c8.pdf b/doc/stm32f103c8.pdf similarity index 100% rename from docs/stm32f103c8.pdf rename to doc/stm32f103c8.pdf diff --git a/src/target/STM32F103XB.ld b/linker.ld similarity index 100% rename from src/target/STM32F103XB.ld rename to linker.ld diff --git a/openocd b/openocd deleted file mode 100755 index 2e3a0d2..0000000 --- a/openocd +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -openocd -f interface/stlink.cfg -f target/cs32f1x.cfg - diff --git a/src/drivers/io.c b/src/drivers/io.c index c3256b7..56e7913 100644 --- a/src/drivers/io.c +++ b/src/drivers/io.c @@ -111,7 +111,7 @@ int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint16_t pin_cfg, OnIO cb) { gpio->BSRR |= odr; //TODO manage alternate functions - + // manage IRQs //TODO allow IRQ reset if (!cb) return 0; //no callback attached @@ -198,26 +198,26 @@ int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint16_t pin_cfg, OnIO cb) { uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask) -{ - return gpio->IDR & mask; +{ + return gpio->IDR & mask; } void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) { - gpio->BSRR = (uint32_t)(mask) << (val ? 0 : 16); + gpio->BSRR = (uint32_t)(mask) << (val ? 0 : 16); } void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) { - gpio->BSRR = (uint32_t)(mask) << (val ? 16 : 0); + gpio->BSRR = (uint32_t)(mask) << (val ? 16 : 0); } void io_set(GPIO_TypeDef *gpio, uint16_t mask) { - gpio->BSRR = mask; + gpio->BSRR = mask; } void io_clear(GPIO_TypeDef *gpio, uint16_t mask) { - gpio->BSRR = (uint32_t)(mask) << 16; + gpio->BSRR = (uint32_t)(mask) << 16; } diff --git a/src/drivers/rnd.c b/src/drivers/rnd.c new file mode 100644 index 0000000..d266b5c --- /dev/null +++ b/src/drivers/rnd.c @@ -0,0 +1,20 @@ +#include "rnd.h" + +uint32_t rnd_seed = 251; + +void set_rnd_seed(uint32_t seed) { + rnd_seed = seed; +} + +uint8_t rnd_byte() { + + static uint32_t r = 251; + static uint32_t Y = 7; + + if (r==0 || r==1 || r==0xFFFFFFFF) r=251; + r = (9973 * ~r) + ((Y) % 701); + Y = (r>>24) % 255; + + return (uint8_t)Y; +} + diff --git a/src/drivers/rnd.h b/src/drivers/rnd.h new file mode 100644 index 0000000..3a572cd --- /dev/null +++ b/src/drivers/rnd.h @@ -0,0 +1,11 @@ +#ifndef RND_H +#define RND_H + +#include "stdint.h" + +void set_rnd_seed(uint32_t seed); + +uint8_t rnd_byte(); + +#endif + diff --git a/src/drivers/timer.c b/src/drivers/timer.c index 58d8900..3f611ca 100644 --- a/src/drivers/timer.c +++ b/src/drivers/timer.c @@ -33,52 +33,62 @@ int timer_config_cb(TIM_TypeDef* tmr, uint32_t* clk, OnTick cb) { IRQn_Type irqn; uint32_t irq_priority; - // get clocks config - if (tmr == TIM1) { - *clk = sysclks.apb2_timer_freq; + switch((uint32_t)tmr) { + case (uint32_t)TIM1: + // get clocks config + *clk = sysclks.apb2_timer_freq; - // register callback function - callback1 = cb; - irqn = TIM1_UP_IRQn; //every update - irq_priority = TIM1_IRQ_PRIORITY; + // register callback function + callback1 = cb; + irqn = TIM1_UP_IRQn; //every update + irq_priority = TIM1_IRQ_PRIORITY; - // enable timer clocking - RCC->APB2ENR |= 1<<11; + // enable timer clocking + RCC->APB2ENR |= 1<<11; + break; - } else if (tmr == TIM2) { - *clk = sysclks.apb1_timer_freq; + case (uint32_t)TIM2: + // get clocks config + *clk = sysclks.apb1_timer_freq; - // register callback function - callback2 = cb; - irqn = TIM2_IRQn; - irq_priority = TIM2_IRQ_PRIORITY; + // register callback function + callback2 = cb; + irqn = TIM2_IRQn; + irq_priority = TIM2_IRQ_PRIORITY; - // enable timer clocking - RCC->APB1ENR |= 1<<0; + // enable timer clocking + RCC->APB1ENR |= 1<<0; + break; - } else if (tmr == TIM3) { - *clk = sysclks.apb1_timer_freq; + case (uint32_t)TIM3: + // get clocks config + *clk = sysclks.apb1_timer_freq; - // register callback function - callback3 = cb; - irqn = TIM3_IRQn; - irq_priority = TIM3_IRQ_PRIORITY; + // register callback function + callback3 = cb; + irqn = TIM3_IRQn; + irq_priority = TIM3_IRQ_PRIORITY; - // enable timer clocking - RCC->APB1ENR |= 1<<1; + // enable timer clocking + RCC->APB1ENR |= 1<<1; + break; - } else if (tmr == TIM4) { - *clk = sysclks.apb1_timer_freq; + case (uint32_t)TIM4: + // get clocks config + *clk = sysclks.apb1_timer_freq; - // register callback function - callback4 = cb; - irqn = TIM4_IRQn; - irq_priority = TIM4_IRQ_PRIORITY; + // register callback function + callback4 = cb; + irqn = TIM4_IRQn; + irq_priority = TIM4_IRQ_PRIORITY; - // enable timer clocking - RCC->APB1ENR |= 1<<2; - - } else return -1; + // enable timer clocking + RCC->APB1ENR |= 1<<2; + break; + + default: + return -1; + } // clear pending interrupts tmr->SR &= !1; @@ -184,52 +194,62 @@ int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb) { IRQn_Type irqn; uint32_t irq_priority, clk; - // get back the clock frequency - if (tmr == TIM1) { - clk = sysclks.apb2_timer_freq; + switch((uint32_t)tmr) { + case (uint32_t)TIM1: + // get back the clock frequency + clk = sysclks.apb2_timer_freq; - // register callback function - callback1 = cb; - irqn = TIM1_UP_IRQn; //every update - irq_priority = TIM1_IRQ_PRIORITY; + // register callback function + callback1 = cb; + irqn = TIM1_UP_IRQn; //every update + irq_priority = TIM1_IRQ_PRIORITY; - // enable timer clocking - RCC->APB2ENR |= 1<<11; + // enable timer clocking + RCC->APB2ENR |= 1<<11; + break; + + case (uint32_t)TIM2: + // get back the clock frequency + clk = sysclks.apb1_timer_freq; - } else if (tmr == TIM2) { - clk = sysclks.apb1_timer_freq; + // register callback function + callback2 = cb; + irqn = TIM2_IRQn; + irq_priority = TIM2_IRQ_PRIORITY; - // register callback function - callback2 = cb; - irqn = TIM2_IRQn; - irq_priority = TIM2_IRQ_PRIORITY; + // enable timer clocking + RCC->APB1ENR |= 1<<0; + break; - // enable timer clocking - RCC->APB1ENR |= 1<<0; + case (uint32_t)TIM3: + // get back the clock frequency + clk = sysclks.apb1_timer_freq; - } else if (tmr == TIM3) { - clk = sysclks.apb1_timer_freq; + // register callback function + callback3 = cb; + irqn = TIM3_IRQn; + irq_priority = TIM3_IRQ_PRIORITY; - // register callback function - callback3 = cb; - irqn = TIM3_IRQn; - irq_priority = TIM3_IRQ_PRIORITY; + // enable timer clocking + RCC->APB1ENR |= 1<<1; + break; - // enable timer clocking - RCC->APB1ENR |= 1<<1; + case (uint32_t)TIM4: + // get back the clock frequency + clk = sysclks.apb1_timer_freq; - } else if (tmr == TIM4) { - clk = sysclks.apb1_timer_freq; + // register callback function + callback4 = cb; + irqn = TIM4_IRQn; + irq_priority = TIM4_IRQ_PRIORITY; - // register callback function - callback4 = cb; - irqn = TIM4_IRQn; - irq_priority = TIM4_IRQ_PRIORITY; + // enable timer clocking + RCC->APB1ENR |= 1<<2; + break; - // enable timer clocking - RCC->APB1ENR |= 1<<2; - - } else return -1; + default: + return -1; + } // clear pending interrupts tmr->SR &= !1; @@ -238,15 +258,15 @@ int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb) { tmr->CR1 = (1<<7) | (1<<2); //buffering and update settings tmr->DIER = (1<<0); //Enable interrupts - // set prescaler 1ms - tmr->PSC = 8*(clk/1000)-1; //PSC = clk/f - 1 | don't know why 8 times... + // set prescaler 0.5ms + tmr->PSC = 8*(clk/2000)-1; //PSC = clk/f - 1 | don't know why 8 times... // set period - if(timer_set_period(tmr,tick_ms)) return -1; + if(timer_set_period(tmr, tick_ms)) return -1; if (cb) { NVIC_SetPriority(irqn,irq_priority); - NVIC_EnableIRQ(irqn); //unmask IRQ + NVIC_EnableIRQ(irqn); //unmask IRQ } return 0; @@ -254,7 +274,7 @@ int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb) { int timer_set_period(TIM_TypeDef *tmr, uint16_t tick) { // set period - tmr->ARR = tick-1; //tickms = (ARR+1)Tpsc + tmr->ARR = tick*2-1; //tickms = (ARR+1)Tpsc // force update to reset counter and apply prescaler tmr->EGR |= 1; @@ -277,19 +297,26 @@ void timer_stop(TIM_TypeDef *tmr) { //------------------------------------------------------------------------------ int timer_enc_init(TIM_TypeDef* tmr) { // enable timer - if (tmr == TIM1) { - RCC->APB2ENR |= 1<<11; + switch((uint32_t)tmr) { + case (uint32_t)TIM1: + RCC->APB2ENR |= 1<<11; + break; - } else if (tmr == TIM2) { - RCC->APB1ENR |= 1<<0; + case (uint32_t)TIM2: + RCC->APB1ENR |= 1<<0; + break; - } else if (tmr == TIM3) { - RCC->APB1ENR |= 1<<1; + case (uint32_t)TIM3: + RCC->APB1ENR |= 1<<1; + break; - } else if (tmr == TIM4) { - RCC->APB1ENR |= 1<<2; + case (uint32_t)TIM4: + RCC->APB1ENR |= 1<<2; + break; - } else return -1; //no such timer + default: + return -1; //no such timer + } //TODO set registers at reset value diff --git a/src/drivers/timer.h b/src/drivers/timer.h index b6cde97..f2efe22 100644 --- a/src/drivers/timer.h +++ b/src/drivers/timer.h @@ -1,88 +1,89 @@ -#ifndef TIMER_H -#define TIMER_H - -#include "../target/stm32f103xb.h" -#include "../config.h" -#include "rcc.h" - -typedef void (*OnTick)(void); - -//------------------------------------------------------------------------------ -/** timer_wait_ms - * wait for ms milliseconds function - */ -int timer_wait_ms(TIM_TypeDef *tmr, uint16_t ms, OnTick cb); - -/** timer_wait_us - * wait for us microseconds function - */ -int timer_wait_us(TIM_TypeDef *tmr, uint16_t us, OnTick cb); - -//------------------------------------------------------------------------------ -/** timer_tick_init - * setup timer to call cb function periodically, each tick_ms - */ -int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb); - -/** timer_set_period - * change the period, in ms when called after tick_init, - * otherwise in whatever unit the timer is configured - * reset count when used - */ -int timer_set_period(TIM_TypeDef *tmr, uint16_t tick); - -/** timer_start - * reset count and start counting - */ -void timer_start(TIM_TypeDef *tmr); - -/** timer_stop - * stop counting - */ -void timer_stop(TIM_TypeDef *tmr); - -//------------------------------------------------------------------------------ -/** timer_enc_init - * setup timer to read encoder output and keep track of it's position in the - * CNT register whithout using CPU time - */ -int timer_enc_init(TIM_TypeDef* tmr); - -//------------------------------------------------------------------------------ -//#define PWM_CHANNEL_1 0 -//#define PWM_CHANNEL_2 1 -//#define PWM_CHANNEL_3 2 -//#define PWM_CHANNEL_4 3 -// -///** pwm_init -// * setup pwm timer period, each tick_ms -// */ -//int pwm_init(TIM_TypeDef *pwm, uint32_t period_ms, OnTick cb); -// -///** pwm_channel_enable -// * set up pwm channel -// */ -//int pwm_channel_enable(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle, uint32_t oe); -// -///** pwm_channel_disable -// * disable pwm channel -// */ -//int pwm_channel_disable(TIM_TypeDef *pwm, uint32_t channel); -// -///** pwm_channel_set -// * set up dutycycle for pwm channel -// */ -//int pwm_channel_set(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle); -// -///** pwm_start -// * start counting -// */ -//#define pwm_start(pwm) timer_start(pwm) -// -///** pwm_stop -// * stop and reset counting -// */ -//#define pwm_stop(pwm) timer_stop(pwm) - -#endif - +#ifndef TIMER_H +#define TIMER_H + +#include "../target/stm32f103xb.h" +#include "../config.h" +#include "rcc.h" + +typedef void (*OnTick)(void); + +//------------------------------------------------------------------------------ +/** timer_wait_ms + * wait for ms milliseconds function + */ +int timer_wait_ms(TIM_TypeDef *tmr, uint16_t ms, OnTick cb); + +/** timer_wait_us + * wait for us microseconds function + */ +int timer_wait_us(TIM_TypeDef *tmr, uint16_t us, OnTick cb); + +//------------------------------------------------------------------------------ + +/** timer_tick_init + * setup timer to call cb function periodically, each tick_ms + */ +int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb); + +/** timer_set_period + * change the period, in ms when called after tick_init, + * otherwise in whatever unit the timer is configured + * reset count when used + */ +int timer_set_period(TIM_TypeDef *tmr, uint16_t tick); + +/** timer_start + * reset count and start counting + */ +void timer_start(TIM_TypeDef *tmr); + +/** timer_stop + * stop counting + */ +void timer_stop(TIM_TypeDef *tmr); + +//------------------------------------------------------------------------------ +/** timer_enc_init + * setup timer to read encoder output and keep track of it's position in the + * CNT register whithout using CPU time + */ +int timer_enc_init(TIM_TypeDef* tmr); + +//------------------------------------------------------------------------------ +//#define PWM_CHANNEL_1 0 +//#define PWM_CHANNEL_2 1 +//#define PWM_CHANNEL_3 2 +//#define PWM_CHANNEL_4 3 +// +///** pwm_init +// * setup pwm timer period, each tick_ms +// */ +//int pwm_init(TIM_TypeDef *pwm, uint32_t period_ms, OnTick cb); +// +///** pwm_channel_enable +// * set up pwm channel +// */ +//int pwm_channel_enable(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle, uint32_t oe); +// +///** pwm_channel_disable +// * disable pwm channel +// */ +//int pwm_channel_disable(TIM_TypeDef *pwm, uint32_t channel); +// +///** pwm_channel_set +// * set up dutycycle for pwm channel +// */ +//int pwm_channel_set(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle); +// +///** pwm_start +// * start counting +// */ +//#define pwm_start(pwm) timer_start(pwm) +// +///** pwm_stop +// * stop and reset counting +// */ +//#define pwm_stop(pwm) timer_stop(pwm) + +#endif + diff --git a/src/main.c b/src/main.c deleted file mode 100644 index fffa31b..0000000 --- a/src/main.c +++ /dev/null @@ -1,52 +0,0 @@ -// standard headers -#include -#include - -// driver includes -#include "drivers/rcc.h" -#include "drivers/io.h" - -Clock_t sysclks; -#include "drivers/timer.h" - -extern uint32_t end; - -//------------------------------------------------------------------------------ -/* static variables */; -int val = 0; //debug led - -//------------------------------------------------------------------------------ -/* Timer IRQ */ -static void timeout_cb(void) { - io_write(GPIOC, val, PIN_13); - val = !val; -} - -//------------------------------------------------------------------------------ -/* main function */ -int main(void) { - - // configure clocks (necessary before using timers) - rcc_config_clock(CLOCK_CONFIG_PERFORMANCE, &sysclks); - - // configure GPIO for LED - if(io_configure(GPIOC, PIN_13, IO_MODE_OUTPUT | IO_OUT_PUSH_PULL, 0)) - return -1; - io_write(GPIOC, 1, PIN_13); - - // start timed interruption - timer_tick_init(TIM2, 1000, timeout_cb); - timer_start(TIM2); - - uint32_t test = (uint32_t)(&end); - test++; - int* tab = (int*)malloc(10*sizeof(int)); - for(int i=0; i<10; ++i) { - tab[i] = i; - } - - // main loop - for(;;); - - return 0; -} diff --git a/src/target/stm32f1xx.h b/src/target/stm32f1xx.h.unused similarity index 100% rename from src/target/stm32f1xx.h rename to src/target/stm32f1xx.h.unused diff --git a/src/target/system_clock.c b/src/target/system_clock.c.unused similarity index 100% rename from src/target/system_clock.c rename to src/target/system_clock.c.unused diff --git a/src/target/system_stm32f1xx.h b/src/target/system_stm32f1xx.h.unused similarity index 100% rename from src/target/system_stm32f1xx.h rename to src/target/system_stm32f1xx.h.unused diff --git a/src/target/startup_stm32f103xb.s b/startup.s similarity index 100% rename from src/target/startup_stm32f103xb.s rename to startup.s diff --git a/src/target/stm32f103xb.h b/target.h similarity index 77% rename from src/target/stm32f103xb.h rename to target.h index 5d98ae4..fe33bd0 100644 --- a/src/target/stm32f103xb.h +++ b/target.h @@ -4,15 +4,15 @@ * @author MCD Application Team * @version V4.2.0 * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware - * + * ****************************************************************************** * @attention * @@ -51,19 +51,19 @@ /** @addtogroup stm32f103xb * @{ */ - + #ifndef __STM32F103xB_H #define __STM32F103xB_H #ifdef __cplusplus extern "C" { -#endif +#endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ @@ -79,8 +79,8 @@ */ /** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ @@ -153,10 +153,10 @@ typedef enum /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct @@ -192,8 +192,8 @@ typedef struct __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ } ADC_Common_TypeDef; -/** - * @brief Backup Registers +/** + * @brief Backup Registers */ typedef struct @@ -213,9 +213,9 @@ typedef struct __IO uint32_t CR; __IO uint32_t CSR; } BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox + +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -226,10 +226,10 @@ typedef struct __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; @@ -238,20 +238,20 @@ typedef struct __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; @@ -278,8 +278,8 @@ typedef struct CAN_FilterRegister_TypeDef sFilterRegister[14]; } CAN_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -287,12 +287,12 @@ typedef struct __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; -/** +/** * @brief Debug MCU */ @@ -302,7 +302,7 @@ typedef struct __IO uint32_t CR; }DBGMCU_TypeDef; -/** +/** * @brief DMA Controller */ @@ -322,7 +322,7 @@ typedef struct -/** +/** * @brief External Interrupt/Event Controller */ @@ -336,7 +336,7 @@ typedef struct __IO uint32_t PR; } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -353,10 +353,10 @@ typedef struct __IO uint32_t WRPR; } FLASH_TypeDef; -/** +/** * @brief Option Bytes Registers */ - + typedef struct { __IO uint16_t RDP; @@ -369,7 +369,7 @@ typedef struct __IO uint16_t WRP3; } OB_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -384,7 +384,7 @@ typedef struct __IO uint32_t LCKR; } GPIO_TypeDef; -/** +/** * @brief Alternate Function I/O */ @@ -394,9 +394,9 @@ typedef struct __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; - __IO uint32_t MAPR2; + __IO uint32_t MAPR2; } AFIO_TypeDef; -/** +/** * @brief Inter Integrated Circuit Interface */ @@ -413,7 +413,7 @@ typedef struct __IO uint32_t TRISE; } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -425,7 +425,7 @@ typedef struct __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ } IWDG_TypeDef; -/** +/** * @brief Power Control */ @@ -435,7 +435,7 @@ typedef struct __IO uint32_t CSR; } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -455,7 +455,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -473,7 +473,7 @@ typedef struct __IO uint32_t ALRL; } RTC_TypeDef; -/** +/** * @brief SD host Interface */ @@ -501,7 +501,7 @@ typedef struct __IO uint32_t FIFO; } SDIO_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -546,10 +546,10 @@ typedef struct } TIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ @@ -561,42 +561,42 @@ typedef struct __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; -/** +/** * @brief Universal Serial Bus Full Speed Device */ - + typedef struct { - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -610,7 +610,7 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_memory_map * @{ */ @@ -687,10 +687,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *)TIM2_BASE) #define TIM3 ((TIM_TypeDef *)TIM3_BASE) @@ -743,11 +743,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -759,17 +759,17 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ @@ -780,23 +780,23 @@ typedef struct /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Pos (0U) #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Pos (1U) #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Pos (2U) #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Pos (3U) #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ -#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Pos (4U) #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ -#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Pos (5U) #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ @@ -823,22 +823,22 @@ typedef struct #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 -#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ -#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Pos (1U) #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ -#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Pos (2U) #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ -#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Pos (8U) #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ @@ -849,93 +849,93 @@ typedef struct /******************************************************************************/ /******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Pos (0U) #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Pos (0U) #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Pos (0U) #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Pos (0U) #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Pos (0U) #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Pos (0U) #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Pos (0U) #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Pos (0U) #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Pos (0U) #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Pos (0U) #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ #define RTC_BKP_NUMBER 10 /****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Pos (0U) #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ -#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Pos (7U) #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Pos (8U) #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Pos (9U) #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ /******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Pos (0U) #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ -#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Pos (1U) #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ /******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Pos (0U) #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ -#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Pos (1U) #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Pos (2U) #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Pos (8U) #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ -#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Pos (9U) #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ @@ -946,41 +946,41 @@ typedef struct /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Pos (0U) #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Pos (1U) #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Pos (3U) #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Pos (8U) #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Pos (18U) #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ -#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ -#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ @@ -991,7 +991,7 @@ typedef struct #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ @@ -1002,7 +1002,7 @@ typedef struct #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ @@ -1021,7 +1021,7 @@ typedef struct #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Pos (8U) #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ @@ -1035,7 +1035,7 @@ typedef struct #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Pos (11U) #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ @@ -1049,7 +1049,7 @@ typedef struct #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Pos (14U) #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ @@ -1060,16 +1060,16 @@ typedef struct #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ -#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Pos (17U) #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Pos (18U) #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ @@ -1081,54 +1081,54 @@ typedef struct #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Pos (19U) #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Pos (18U) #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Pos (20U) #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Pos (18U) #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Pos (19U) #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Pos (18U) #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Pos (21U) #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ -#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Pos (18U) #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Pos (19U) #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Pos (18U) #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Pos (20U) #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Pos (18U) #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Pos (19U) #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ -#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Pos (22U) #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ /*!< MCO configuration */ -#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Pos (24U) #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ @@ -1153,95 +1153,95 @@ typedef struct #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Pos (1U) #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Pos (2U) #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Pos (3U) #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Pos (4U) #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Pos (7U) #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Pos (8U) #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Pos (9U) #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Pos (10U) #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Pos (11U) #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Pos (12U) #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Pos (16U) #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Pos (17U) #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Pos (18U) #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Pos (19U) #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Pos (20U) #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Pos (23U) #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Pos (2U) #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Pos (3U) #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Pos (4U) #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Pos (5U) #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Pos (9U) #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ -#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Pos (10U) #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ -#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ -#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ @@ -1249,47 +1249,47 @@ typedef struct /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ -#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ -#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Pos (27U) #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ -#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Pos (2U) #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ -#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ -#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ -#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ -#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ @@ -1299,16 +1299,16 @@ typedef struct /****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Pos (2U) #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Pos (4U) #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Pos (6U) #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ @@ -1316,41 +1316,41 @@ typedef struct /****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Pos (2U) #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Pos (3U) #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Pos (4U) #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Pos (5U) #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Pos (9U) #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ -#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Pos (10U) #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ -#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Pos (11U) #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ -#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ @@ -1358,47 +1358,47 @@ typedef struct /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Pos (1U) #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ -#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ -#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Pos (27U) #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ -#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Pos (2U) #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ -#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Pos (14U) #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ -#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Pos (18U) #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ -#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Pos (22U) #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ -#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Pos (23U) #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ @@ -1408,17 +1408,17 @@ typedef struct /******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ @@ -1430,44 +1430,44 @@ typedef struct #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ -#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ -#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION_Pos (0U) +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Pos (24U) #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Pos (27U) #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ - + /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ @@ -1475,521 +1475,521 @@ typedef struct /******************************************************************************/ /******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Pos (0U) #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ -#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Pos (0U) #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ -#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Pos (4U) #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ -#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Pos (8U) #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ -#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Pos (12U) #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ -#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Pos (16U) #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ -#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Pos (20U) #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ -#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Pos (24U) #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ -#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Pos (28U) #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ -#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Pos (2U) #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ -#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Pos (2U) #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ -#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Pos (6U) #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ -#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Pos (10U) #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ -#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Pos (14U) #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ -#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Pos (18U) #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ -#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Pos (22U) #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ -#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Pos (26U) #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ -#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Pos (30U) #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Pos (0U) #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ -#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Pos (0U) #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ -#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Pos (4U) #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ -#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Pos (8U) #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ -#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Pos (12U) #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ -#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Pos (16U) #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ -#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Pos (20U) #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ -#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Pos (24U) #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ -#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Pos (28U) #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ -#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Pos (2U) #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ -#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Pos (2U) #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ -#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Pos (6U) #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ -#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Pos (10U) #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ -#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Pos (14U) #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ -#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Pos (18U) #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ -#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Pos (22U) #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ -#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Pos (26U) #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ -#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Pos (30U) #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ /*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Pos (0U) #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Pos (1U) #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Pos (2U) #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Pos (3U) #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Pos (4U) #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Pos (5U) #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Pos (6U) #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Pos (7U) #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Pos (8U) #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Pos (9U) #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Pos (10U) #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Pos (11U) #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Pos (12U) #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Pos (13U) #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Pos (14U) #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Pos (15U) #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Pos (0U) #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Pos (1U) #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Pos (2U) #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Pos (3U) #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Pos (4U) #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Pos (5U) #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Pos (6U) #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Pos (7U) #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Pos (8U) #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Pos (9U) #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Pos (10U) #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Pos (11U) #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Pos (12U) #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Pos (13U) #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Pos (14U) #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Pos (15U) #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ -#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Pos (0U) #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ @@ -1999,53 +1999,53 @@ typedef struct /*!< PIN configuration */ #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Pos (1U) #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Pos (0U) #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Pos (2U) #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Pos (0U) #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Pos (1U) #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Pos (0U) #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Pos (3U) #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Pos (0U) #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Pos (1U) #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Pos (0U) #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Pos (2U) #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Pos (0U) #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Pos (1U) #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Pos (0U) #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ -#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Pos (4U) #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ @@ -2054,38 +2054,38 @@ typedef struct /*!< PORT configuration */ #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Pos (5U) #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Pos (4U) #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Pos (6U) #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ -#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Pos (7U) #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ /****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Pos (2U) #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Pos (3U) #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ -#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ @@ -2093,14 +2093,14 @@ typedef struct /* USART3_REMAP configuration */ #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ -#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ @@ -2108,14 +2108,14 @@ typedef struct /*!< TIM1_REMAP configuration */ #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ -#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ @@ -2123,17 +2123,17 @@ typedef struct /*!< TIM2_REMAP configuration */ #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ @@ -2141,18 +2141,18 @@ typedef struct /*!< TIM3_REMAP configuration */ #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ -#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ -#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Pos (13U) #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ @@ -2160,19 +2160,19 @@ typedef struct /*!< CAN_REMAP configuration */ #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ -#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Pos (15U) #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ /*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Pos (24U) #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ @@ -2180,406 +2180,406 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Pos (4U) #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Pos (8U) #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Pos (12U) #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ -/*!< EXTI2 configuration */ +/*!< EXTI2 configuration */ #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Pos (0U) #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Pos (4U) #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Pos (8U) #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Pos (12U) #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ -/*!< EXTI6 configuration */ +/*!< EXTI6 configuration */ #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Pos (0U) #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Pos (4U) #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Pos (8U) #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Pos (12U) #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ -/*!< EXTI10 configuration */ +/*!< EXTI10 configuration */ #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Pos (0U) #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Pos (4U) #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Pos (8U) #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Pos (12U) #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ -/*!< EXTI14 configuration */ +/*!< EXTI14 configuration */ #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ @@ -2594,61 +2594,61 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Pos (0U) #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Pos (1U) #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Pos (2U) #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Pos (3U) #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Pos (4U) #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Pos (5U) #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Pos (6U) #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Pos (7U) #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Pos (8U) #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Pos (9U) #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Pos (10U) #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Pos (11U) #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Pos (12U) #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Pos (13U) #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Pos (14U) #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Pos (15U) #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Pos (16U) #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ @@ -2673,63 +2673,63 @@ typedef struct #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ - + /******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Pos (1U) #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Pos (2U) #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Pos (3U) #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Pos (4U) #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Pos (5U) #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Pos (6U) #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Pos (7U) #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Pos (8U) #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Pos (9U) #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Pos (10U) #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Pos (11U) #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Pos (12U) #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Pos (13U) #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Pos (14U) #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Pos (15U) #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Pos (16U) #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ @@ -2755,61 +2755,61 @@ typedef struct #define EXTI_EMR_EM18 EXTI_EMR_MR18 /****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Pos (0U) #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Pos (1U) #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Pos (2U) #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Pos (3U) #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Pos (4U) #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Pos (5U) #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Pos (6U) #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Pos (7U) #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Pos (8U) #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Pos (9U) #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Pos (10U) #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Pos (11U) #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Pos (12U) #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Pos (13U) #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Pos (14U) #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Pos (15U) #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Pos (16U) #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ @@ -2835,61 +2835,61 @@ typedef struct #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 /****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Pos (0U) #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Pos (1U) #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Pos (2U) #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Pos (3U) #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Pos (4U) #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Pos (5U) #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Pos (6U) #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Pos (7U) #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Pos (8U) #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Pos (9U) #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Pos (10U) #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Pos (11U) #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Pos (12U) #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Pos (13U) #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Pos (14U) #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Pos (15U) #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Pos (16U) #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ @@ -2915,61 +2915,61 @@ typedef struct #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 /****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Pos (0U) #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Pos (1U) #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Pos (2U) #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Pos (3U) #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Pos (4U) #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Pos (5U) #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Pos (6U) #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Pos (7U) #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Pos (8U) #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Pos (9U) #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Pos (10U) #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Pos (11U) #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Pos (12U) #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Pos (13U) #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Pos (14U) #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Pos (15U) #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Pos (16U) #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ @@ -2995,61 +2995,61 @@ typedef struct #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 /******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Pos (4U) #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Pos (5U) #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Pos (6U) #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Pos (7U) #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Pos (8U) #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Pos (9U) #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Pos (10U) #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Pos (11U) #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Pos (12U) #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Pos (13U) #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Pos (14U) #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Pos (15U) #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Pos (16U) #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ @@ -3081,237 +3081,237 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Pos (0U) #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Pos (1U) #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Pos (2U) #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Pos (3U) #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Pos (4U) #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Pos (5U) #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Pos (6U) #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Pos (7U) #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Pos (8U) #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Pos (9U) #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Pos (10U) #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Pos (11U) #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Pos (12U) #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Pos (13U) #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Pos (14U) #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Pos (15U) #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Pos (16U) #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Pos (17U) #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Pos (18U) #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Pos (19U) #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Pos (20U) #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Pos (21U) #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Pos (22U) #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Pos (23U) #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Pos (24U) #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Pos (25U) #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Pos (26U) #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Pos (27U) #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Pos (0U) #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Pos (1U) #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Pos (2U) #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Pos (3U) #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Pos (4U) #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Pos (5U) #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Pos (6U) #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Pos (7U) #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Pos (8U) #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Pos (9U) #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Pos (10U) #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Pos (12U) #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Pos (13U) #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Pos (14U) #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Pos (15U) #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Pos (16U) #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Pos (17U) #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Pos (18U) #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Pos (19U) #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Pos (20U) #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Pos (21U) #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Pos (22U) #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Pos (23U) #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Pos (24U) #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Pos (25U) #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Pos (26U) #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Pos (27U) #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register *******************/ -#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Pos (2U) #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Pos (3U) #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Pos (4U) #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ -#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Pos (5U) #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ -#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Pos (6U) #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ -#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Pos (10U) #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Pos (14U) #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register ******************/ -#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Pos (0U) #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register *******************/ -#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Pos (0U) #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register *******************/ -#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Pos (0U) #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ @@ -3327,19 +3327,19 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Pos (1U) #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Pos (2U) #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ @@ -3348,7 +3348,7 @@ typedef struct #define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ @@ -3357,39 +3357,39 @@ typedef struct #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ -#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Pos (5U) #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Pos (7U) #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ -#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Pos (16U) #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ @@ -3397,10 +3397,10 @@ typedef struct #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ -#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ @@ -3409,107 +3409,107 @@ typedef struct #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Pos (2U) #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Pos (3U) #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Pos (12U) #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ -#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Pos (15U) #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ -#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Pos (17U) #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ -#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Pos (20U) #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Pos (21U) #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Pos (22U) #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Pos (23U) #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Pos (0U) #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Pos (3U) #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Pos (6U) #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Pos (9U) #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Pos (12U) #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Pos (15U) #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Pos (18U) #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Pos (21U) #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ @@ -3517,70 +3517,70 @@ typedef struct #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Pos (0U) #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Pos (3U) #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Pos (6U) #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Pos (9U) #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Pos (12U) #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Pos (15U) #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Pos (18U) #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Pos (21U) #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Pos (24U) #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Pos (27U) #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ @@ -3588,37 +3588,37 @@ typedef struct #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Pos (0U) #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ @@ -3627,7 +3627,7 @@ typedef struct #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ -#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Pos (5U) #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ @@ -3636,7 +3636,7 @@ typedef struct #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Pos (10U) #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ @@ -3645,7 +3645,7 @@ typedef struct #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Pos (15U) #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ @@ -3654,7 +3654,7 @@ typedef struct #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ @@ -3663,7 +3663,7 @@ typedef struct #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Pos (0U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ @@ -3672,7 +3672,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Pos (5U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ @@ -3681,7 +3681,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Pos (10U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ @@ -3690,7 +3690,7 @@ typedef struct #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Pos (15U) #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ @@ -3699,7 +3699,7 @@ typedef struct #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Pos (20U) #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ @@ -3708,7 +3708,7 @@ typedef struct #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Pos (25U) #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ @@ -3718,7 +3718,7 @@ typedef struct #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Pos (0U) #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ @@ -3727,7 +3727,7 @@ typedef struct #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Pos (5U) #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ @@ -3736,7 +3736,7 @@ typedef struct #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Pos (10U) #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ @@ -3745,7 +3745,7 @@ typedef struct #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Pos (15U) #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ @@ -3754,7 +3754,7 @@ typedef struct #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Pos (20U) #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ @@ -3763,7 +3763,7 @@ typedef struct #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Pos (25U) #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ @@ -3773,7 +3773,7 @@ typedef struct #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ @@ -3782,7 +3782,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ @@ -3791,7 +3791,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ @@ -3800,7 +3800,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ @@ -3809,37 +3809,37 @@ typedef struct #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Pos (16U) #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ @@ -3850,101 +3850,101 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! Date: Sat, 11 Feb 2023 21:57:21 +0100 Subject: [PATCH 02/85] Update .gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 1042eb2..31f9fa1 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,4 @@ bin .gdb_history *tags *.taghl +.cache -- 2.45.2 From c2aec8e9edd321a3b197c9ff22dab8dca11ca7a3 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 13 Mar 2023 11:37:07 +0100 Subject: [PATCH 03/85] Rewrite linker and startup files The files previously used were from StmCubeMx and Mbed but they contain a lots off things that we don't need, like a heap and a space for special debug symbols --- linker.ld | 220 +++-------- src/config.h | 29 -- src/drivers/adc.c | 41 -- src/drivers/adc.h | 15 - src/drivers/io.c | 223 ----------- src/drivers/io.h | 132 ------- src/drivers/lcd.c | 186 --------- src/drivers/lcd.h | 93 ----- src/drivers/rcc.c | 258 ------------- src/drivers/rcc.h | 33 -- src/drivers/rnd.c | 20 - src/drivers/rnd.h | 11 - src/drivers/timer.c | 338 ----------------- src/drivers/timer.h | 89 ----- src/target/stm32f1xx.h.unused | 238 ------------ src/target/system_clock.c.unused | 109 ------ src/target/system_stm32f1xx.h.unused | 118 ------ startup.s | 548 ++++++++++++--------------- 18 files changed, 304 insertions(+), 2397 deletions(-) delete mode 100644 src/config.h delete mode 100644 src/drivers/adc.c delete mode 100644 src/drivers/adc.h delete mode 100644 src/drivers/io.c delete mode 100644 src/drivers/io.h delete mode 100644 src/drivers/lcd.c delete mode 100644 src/drivers/lcd.h delete mode 100644 src/drivers/rcc.c delete mode 100644 src/drivers/rcc.h delete mode 100644 src/drivers/rnd.c delete mode 100644 src/drivers/rnd.h delete mode 100644 src/drivers/timer.c delete mode 100644 src/drivers/timer.h delete mode 100644 src/target/stm32f1xx.h.unused delete mode 100644 src/target/system_clock.c.unused delete mode 100644 src/target/system_stm32f1xx.h.unused diff --git a/linker.ld b/linker.ld index e6d79bf..4f30b65 100644 --- a/linker.ld +++ b/linker.ld @@ -1,177 +1,79 @@ -/** - ****************************************************************************** - * @file LinkerScript.ld - * @author Auto-generated by STM32CubeIDE - * @brief Linker script for STM32F103C8Tx Device from STM32F1 series - * 64Kbytes FLASH - * 20Kbytes RAM +/** @file + * Linker to be used with the HBL. * - * Set heap size, stack size and stack location according - * to application requirements. - * - * Set memory bank area and size if external memory is used - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + * This linker file provides the basic architecture for a projet. Stack size and + * memory layout can be configured at will. Note that this file doesn't provide + * a heap space since the HBL doesn't provide or use any form of dynamic + * allocation. */ -/* Entry Point */ -ENTRY(Reset_Handler) +/*--Configuration-------------------------------------------------------------*/ -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +/* minimal stack size */ +_min_stack_size = 0x400; -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ +/* memory layout of the chip */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (!rx) : ORIGIN = 0x20000000, LENGTH = 20K } -/* Sections */ +/*--Description---------------------------------------------------------------*/ + +ENTRY(hdr_reset) + +/* end of "RAM" Ram type memory */ +_estack = ORIGIN(RAM) + LENGTH(RAM); +/* ROM adress to load data from */ +_sromdata = LOADADDR(.data); + SECTIONS { - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH + /* vector table, cpu will look for it at adress 0 on reset */ + .vector_table : + { + KEEP(*(.vector_table)) + } > ROM - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) + /* program code */ + .text : + { + . = ALIGN(4); + *(.text) + } > ROM - KEEP (*(.init)) - KEEP (*(.fini)) + /* const data */ + .rodata : + { + . = ALIGN(4); + *(.rodata) + } > ROM - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH + /* initialized data from ROM */ + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data) + . = ALIGN(4); + _edata = .; + } > RAM AT > ROM - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH + /* uninitialized data, zeroed */ + .bss : + { + . = ALIGN(4); + *(.bss) + } > RAM - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type - * memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } + /* memory space allocated to stack. The stack is situated at the very end of + * the RAM while this section may not, thus it is only used to enforce a + * minimal stack size */ + .stack : + { + . = ALIGN(8); + . = . + _min_stack_size; + } > RAM } diff --git a/src/config.h b/src/config.h deleted file mode 100644 index 5bd4f41..0000000 --- a/src/config.h +++ /dev/null @@ -1,29 +0,0 @@ -//------------------------------------------------------------------------------ -/* priorities */ -#define EXTI0_IRQ_PRIORITY 8 -#define EXTI1_IRQ_PRIORITY 8 -#define EXTI2_IRQ_PRIORITY 8 -#define EXTI3_IRQ_PRIORITY 8 -#define EXTI4_IRQ_PRIORITY 8 -#define EXTI9_5_IRQ_PRIORITY 8 -#define EXTI15_10_IRQ_PRIORITY 8 - -#define TIM1_IRQ_PRIORITY 4 -#define TIM2_IRQ_PRIORITY 4 -#define TIM3_IRQ_PRIORITY 4 -#define TIM4_IRQ_PRIORITY 4 - -#define USART1_IRQ_PRIORITY 3 -#define USART2_IRQ_PRIORITY 3 -#define USART3_IRQ_PRIORITY 3 - -#define I2C1_IRQ_PRIORITY 2 -#define I2C1_IRQERR_PRIORITY 1 -#define I2C2_IRQ_PRIORITY 2 -#define I2C2_IRQERR_PRIORITY 1 - -#define SPI1_IRQ_PRIORITY 4 -#define SPI2_IRQ_PRIORITY 4 - -#define ADC1_2_IRQ_PRIORITY 5 - diff --git a/src/drivers/adc.c b/src/drivers/adc.c deleted file mode 100644 index 6fb4c8d..0000000 --- a/src/drivers/adc.c +++ /dev/null @@ -1,41 +0,0 @@ -#include "adc.h" - -extern Clock_t sysclks; - -int adc_init(ADC_TypeDef* adc) { - // enable adc clock - if(adc == ADC1) RCC->APB2ENR |= 0x1 << 9; - else if(adc == ADC2) RCC->APB2ENR |= 0x1 << 10; - else return -1; //no such adc - - // enable adc - adc->CR2 |= 0x1; - - // configure regular channels - adc->CR1 = 0; //reset value - adc->CR1 |= 0x1 << 23; //enable analog watchdog - adc->CR1 |= 0x1 << 11; //discontinuous mode - - // set trigger to manual - adc->CR1 |= 0x7 << 3; - adc->SMPR2 |= 0x3FFFFFFF; - - // calibrate - adc->CR2 |= 0x1 << 2; - while((adc->CR2 >> 2) & 0x1); - - return 0; -} - -uint16_t adc_read(ADC_TypeDef* adc, uint8_t channel) { - - adc->SQR1 &= ~(0xF << 20); //one conversion only - adc->SQR3 = (adc->SQR3 & ~(0x1F)) | channel; //set channel - - //adc->CR2 |= 0x1 << 22; //start convertion - adc->CR2 |= 0x1; - while(!((adc->SR >> 1) & 0x1)); //waiting for convertion - - return adc->DR & 0xFFF; -} - diff --git a/src/drivers/adc.h b/src/drivers/adc.h deleted file mode 100644 index 64fe6b4..0000000 --- a/src/drivers/adc.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef ADC_H -#define ADC_H - -#include "../target/stm32f103xb.h" -#include "../config.h" -#include "rcc.h" - - -int adc_init(ADC_TypeDef* adc); - -uint16_t adc_read(ADC_TypeDef* adc, uint8_t channel); - - -#endif - diff --git a/src/drivers/io.c b/src/drivers/io.c deleted file mode 100644 index 56e7913..0000000 --- a/src/drivers/io.c +++ /dev/null @@ -1,223 +0,0 @@ -//driver header -#include "io.h" - -static OnIO io_cb[16]={ - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}; - -void EXTI0_IRQHandler() { - if (io_cb[0]) (io_cb[0])(); - EXTI->PR = 1<<0; -} - -void EXTI1_IRQHandler() { - if (io_cb[1]) (io_cb[1])(); - EXTI->PR = 1<<1; -} - -void EXTI2_IRQHandler() { - if (io_cb[2]) (io_cb[2])(); - EXTI->PR = 1<<2; -} - -void EXTI3_IRQHandler() { - if (io_cb[3]) (io_cb[3])(); - EXTI->PR = 1<<3; -} - -void EXTI4_IRQHandler() { - if (io_cb[4]) (io_cb[4])(); - EXTI->PR = 1<<4; -} - -void EXTI9_5_IRQHandler() { - if (EXTI->PR & (1<<5)) { - if (io_cb[5]) (io_cb[5])(); - EXTI->PR = 1<<5; - } else if (EXTI->PR & (1<<6)) { - if (io_cb[6]) (io_cb[6])(); - EXTI->PR = 1<<6; - } else if (EXTI->PR & (1<<7)) { - if (io_cb[7]) (io_cb[7])(); - EXTI->PR = 1<<7; - } else if (EXTI->PR & (1<<8)) { - if (io_cb[8]) (io_cb[8])(); - EXTI->PR = 1<<8; - } else if (EXTI->PR & (1<<9)) { - if (io_cb[9]) (io_cb[9])(); - EXTI->PR = 1<<9; - } -} - -void EXTI15_10_IRQHandler() { - if (EXTI->PR & (1<<10)) { - if (io_cb[10]) (io_cb[10])(); - EXTI->PR = 1<<10; - } else if (EXTI->PR & (1<<11)) { - if (io_cb[11]) (io_cb[11])(); - EXTI->PR = 1<<11; - } else if (EXTI->PR & (1<<12)) { - if (io_cb[12]) (io_cb[12])(); - EXTI->PR = 1<<12; - } else if (EXTI->PR & (1<<13)) { - if (io_cb[13]) (io_cb[13])(); - EXTI->PR = 1<<13; - } else if (EXTI->PR & (1<<14)) { - if (io_cb[14]) (io_cb[14])(); - EXTI->PR = 1<<14; - } else if (EXTI->PR & (1<<15)) { - if (io_cb[15]) (io_cb[15])(); - EXTI->PR = 1<<15; - } -} - -/* Definitions for EXTI configuration */ -enum io_exti_mask { - SYSCFG_EXTI_PA_MASK = 0x0, - SYSCFG_EXTI_PB_MASK = 0x1, - SYSCFG_EXTI_PC_MASK = 0x2, - SYSCFG_EXTI_PD_MASK = 0x3, - SYSCFG_EXTI_PE_MASK = 0x4 -}; - -int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint16_t pin_cfg, OnIO cb) { - - // enable GPIOx subsystem clocking - if (gpio == GPIOA) RCC->APB2ENR |= 1<<2; - else if (gpio == GPIOB) RCC->APB2ENR |= 1<<3; - else if (gpio == GPIOC) RCC->APB2ENR |= 1<<4; - else if (gpio == GPIOD) RCC->APB2ENR |= 1<<5; - else if (gpio == GPIOE) RCC->APB2ENR |= 1<<6; - - // setup pin mask for crx registers - uint64_t pin_mask = 0; - for(int i=0; i<16; ++i) { - if((pin >> i) & 0x1) pin_mask |= 0x1ll << 4*i; - } - - // clear previous data - uint64_t crx = pin_mask * 0x4; //reset value is 0x4 - uint16_t odr = pin; - gpio->CRH &= ~(crx >> 32); - gpio->CRL &= ~(crx & 0xFFFFFFFF); - gpio->BSRR |= odr << 16; - - // set up the new configuration - crx = pin_mask * (pin_cfg & 0xF); - odr = pin * ((pin_cfg & 0x10) >> 4); - gpio->CRH |= crx >> 32; - gpio->CRL |= crx & 0xFFFFFFFF; - gpio->BSRR |= odr; - - //TODO manage alternate functions - - // manage IRQs //TODO allow IRQ reset - if (!cb) return 0; //no callback attached - - if (pin_cfg & 0x7) return -1; //callback set, but not in input mode - - RCC->APB2ENR |= 0x1; //enable AFIO clocking - - // prepare mask - uint8_t port_mask = 0; - // uint32_t pin_mask = 0; - if (gpio == GPIOA) port_mask = SYSCFG_EXTI_PA_MASK; - else if (gpio == GPIOB) port_mask = SYSCFG_EXTI_PB_MASK; - else if (gpio == GPIOC) port_mask = SYSCFG_EXTI_PC_MASK; - else if (gpio == GPIOD) port_mask = SYSCFG_EXTI_PD_MASK; - else if (gpio == GPIOE) port_mask = SYSCFG_EXTI_PE_MASK; - - // setup external IRQ lines - uint64_t afio_mask; - for(int i=0; i<4; ++i) { - afio_mask = ((pin_mask & (0xFFFFll << (i*16))) >> (i*16)) * port_mask; - if(afio_mask) AFIO->EXTICR[i] |= afio_mask; - } - - // clear pending IRQs on concerned lines - EXTI->PR |= pin; - - // configure IRQ options and masks - EXTI->IMR |= pin; - if(pin_cfg & 0x100) EXTI->RTSR |= pin; - if(pin_cfg & 0x200) EXTI->FTSR |= pin; //in case both falling and rising - //are set, both will be a trigger - - // register IRQ callbacks - for(int i=0; i<16; ++i) { - if((pin >> i) & 0x1) { - io_cb[i] = cb; - - // Setup NVIC - switch (i) { - case 0: - NVIC_SetPriority(EXTI0_IRQn, EXTI0_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI0_IRQn); - break; - case 1: - NVIC_SetPriority(EXTI1_IRQn, EXTI1_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI1_IRQn); - break; - case 2: - NVIC_SetPriority(EXTI2_IRQn, EXTI2_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI2_IRQn); - break; - case 3: - NVIC_SetPriority(EXTI3_IRQn, EXTI3_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI3_IRQn); - break; - case 4: - NVIC_SetPriority(EXTI4_IRQn, EXTI4_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI4_IRQn); - break; - case 5: - case 6: - case 7: - case 8: - case 9: - NVIC_SetPriority(EXTI9_5_IRQn, EXTI9_5_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI9_5_IRQn); - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - NVIC_SetPriority(EXTI15_10_IRQn, EXTI15_10_IRQ_PRIORITY); - NVIC_EnableIRQ(EXTI15_10_IRQn); - break; - default: - return -1; //impossible to get there - } - } - } - return 0; -} - - -uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask) -{ - return gpio->IDR & mask; -} - -void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) -{ - gpio->BSRR = (uint32_t)(mask) << (val ? 0 : 16); -} - -void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask) -{ - gpio->BSRR = (uint32_t)(mask) << (val ? 16 : 0); -} - -void io_set(GPIO_TypeDef *gpio, uint16_t mask) -{ - gpio->BSRR = mask; -} - -void io_clear(GPIO_TypeDef *gpio, uint16_t mask) -{ - gpio->BSRR = (uint32_t)(mask) << 16; -} diff --git a/src/drivers/io.h b/src/drivers/io.h deleted file mode 100644 index dc822eb..0000000 --- a/src/drivers/io.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef IO_H -#define IO_H - -//std headers -#include -#include - -//target header -#include "../target/stm32f103xb.h" - -//custom header -#include "../config.h" - -//------------------------------------------------------------------------------ -/* GPIO pin mask definitions */ -enum io_pin { - PIN_0 = (1 << 0), - PIN_1 = (1 << 1), - PIN_2 = (1 << 2), - PIN_3 = (1 << 3), - PIN_4 = (1 << 4), - PIN_5 = (1 << 5), - PIN_6 = (1 << 6), - PIN_7 = (1 << 7), - PIN_8 = (1 << 8), - PIN_9 = (1 << 9), - PIN_10 = (1 << 10), - PIN_11 = (1 << 11), - PIN_12 = (1 << 12), - PIN_13 = (1 << 13), - PIN_14 = (1 << 14), - PIN_15 = (1 << 15), - PIN_ALL = 0xFFFF -}; - -//------------------------------------------------------------------------------ -/* GPIO pin mode definitions */ -enum io_mode { - IO_MODE_INPUT = (0x0), - IO_MODE_OUTPUT = (0x1), // 10Mhz max - IO_MODE_OUTPUT_SLOW = (0x3), // 2MHz max - IO_MODE_OUTPUT_FAST = (0x4) // 50 MHz max -}; - -//------------------------------------------------------------------------------ -/* GPIO pin conf definitions */ -enum io_conf { - IO_IN_ANALOG = (0b0 << 2), - IO_IN_FLOATING = (0b1 << 2), - IO_IN_PULL_UP = (0b110 << 2), - IO_IN_PULL_DOWN = (0b010 << 2), - IO_OUT_ALT_FNCT = (0b10 << 2), - IO_OUT_PUSH_PULL = (0b0 << 2), - IO_OUT_OPEN_DRAIN = (0b1 << 2) -}; - -//------------------------------------------------------------------------------ -/* GPIO pin clear */ -#define IO_CLEAR (0) - -//------------------------------------------------------------------------------ -/* alternate function selection option */ -//TODO not supported for now -//enum io_alt_fnct { -// PIN_OPT_AF0 0x0, -// PIN_OPT_AF1 0x1, -// PIN_OPT_AF2 0x2, -// PIN_OPT_AF3 0x3, -// PIN_OPT_AF4 0x4, -// PIN_OPT_AF5 0x5, -// PIN_OPT_AF6 0x6, -// PIN_OPT_AF7 0x7, -// PIN_OPT_AF8 0x8, -// PIN_OPT_AF9 0x9, -// PIN_OPT_AF10 0xA, -// PIN_OPT_AF11 0xB, -// PIN_OPT_AF12 0xC, -// PIN_OPT_AF13 0xD, -// PIN_OPT_AF14 0xE, -// PIN_OPT_AF15 0xF -//}; - -//------------------------------------------------------------------------------ -/* GPIO IRQ conf definitons */ -enum io_irq_conf { - IO_IRQ_EDGE_RISE = (0x1 << 8), - IO_IRQ_EDGE_FALL = (0x2 << 8), - IO_IRQ_EDGE_BOTH = (0x3 << 8) -}; - -typedef void (*OnIO)(); - -//------------------------------------------------------------------------------ -/* io_configure - * - * configure pins referenced in 'pin_mask' of specified port - * 'gpio' according to 'pin_cfg' and associate a callback - * function 'cb' if not NULL. - * returns 0 if success - */ -int io_configure(GPIO_TypeDef *gpio, uint16_t pin_mask, uint16_t pin_cfg, - OnIO cb); - -/* io_read - * - * read 32 bit data from port 'gpio', filter the result with mask - */ -uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask); - -/* io_write - * - * write 16 bit data filtered by mask to port 'gpio' - * '1' in val are written as HIGH level on port pins - */ -void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask); - -/* io_write_n - * - * write 16 bit data filtered by mask to port 'gpio' - * '1' in val are written as LOW level on port pins - */ -void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask); - -/* io_set/clear - * - * set or clear outputs according to bit mask - */ -void io_set(GPIO_TypeDef *gpio, uint16_t mask); -void io_clear(GPIO_TypeDef *gpio, uint16_t mask); - -#endif - diff --git a/src/drivers/lcd.c b/src/drivers/lcd.c deleted file mode 100644 index 35754fc..0000000 --- a/src/drivers/lcd.c +++ /dev/null @@ -1,186 +0,0 @@ -#include "lcd.h" - -enum mode { - WRITE, - READ, - UNDEFINED -}; - -//TODO make the driver dynamic ? -static TIM_TypeDef* timer = 0; -static uint8_t mode = UNDEFINED; -static uint8_t rows = 0; -static uint8_t columns = 0; -static uint8_t rows_offset[4] = {}; - -//------------------------------------------------------------------------------ -// internal functions -int set_mode_read(void) { - // configure pins - if(io_configure(GPIOA, PIN_8 | PIN_12 | PIN_15, IO_MODE_INPUT | - IO_IN_FLOATING, 0)) return -1; - if(io_configure(GPIOB, PIN_3 | PIN_4 | PIN_13 | PIN_14 | PIN_15, - IO_MODE_INPUT | IO_IN_FLOATING, 0)) return -1; - - // put lcd in read mode - io_set(GPIOA, PIN_9); // after the pins are ready to recieve voltage - mode = READ; - - return 0; -} - -int set_mode_write(void) { - // put lcd in write mode - io_clear(GPIOA, PIN_9); //before the pin can send voltage - - // configure pins - if(io_configure(GPIOA, PIN_8 | PIN_12 | PIN_15, IO_MODE_OUTPUT | - IO_OUT_PUSH_PULL, 0)) return -1; - if(io_configure(GPIOB, PIN_3 | PIN_4 | PIN_13 | PIN_14 | PIN_15, - IO_MODE_OUTPUT | IO_OUT_PUSH_PULL, 0)) return -1; - mode = WRITE; - - return 0; -} - -void wait_for_ready(void) { - //TODO debug that -// // configure the lcd -// if(mode != READ) if(set_mode_read()) return; -// -// // read D7 pin -// for(;;) { -// io_set(GPIOA, PIN_11); -// for(int i=0; i<1000; ++i); //timer_wait is overkill here -// if(!io_read(GPIOB, PIN_4)) break; -// io_clear(GPIOA, PIN_11); -// for(int i=0; i<1000; ++i); //same -// } - timer_wait_ms(timer, 2, 0); //wait max delay -} - -void write_byte(uint8_t byte) { - // put the lcd bus in write mode - if(mode != WRITE) if(set_mode_write()) return; - - // start tranfert - io_set(GPIOA, PIN_11); - timer_wait_us(timer, 1, 0); - - // send the data - io_write(GPIOA, (byte >> 0) & 0x1, PIN_8); - io_write(GPIOA, (byte >> 1) & 0x1, PIN_12); - io_write(GPIOB, (byte >> 2) & 0x1, PIN_15); - io_write(GPIOA, (byte >> 3) & 0x1, PIN_15); - io_write(GPIOB, (byte >> 4) & 0x1, PIN_14); - io_write(GPIOB, (byte >> 5) & 0x1, PIN_3); - io_write(GPIOB, (byte >> 6) & 0x1, PIN_13); - io_write(GPIOB, (byte >> 7) & 0x1, PIN_4); - - // validate data - io_clear(GPIOA, PIN_11); -} - -//------------------------------------------------------------------------------ -int lcd_init(TIM_TypeDef* tim, uint8_t col, uint8_t row) { - - timer = tim; - columns = col; - rows = row; - rows_offset[0] = 0x00; - rows_offset[1] = 0x40; - rows_offset[2] = 0x00 + columns; - rows_offset[3] = 0x40 + columns; - - // disable JTAG, as it utilise needed pins, SWD remains usable in - // synchronous mode - RCC->APB2ENR |= 0x1; //enable AFIO clocking - AFIO->MAPR = (AFIO->MAPR & ~(0x8 << 24)) | 0x2 << 24; - - // configure the lcd control pins - if(io_configure(GPIOA, PIN_9 | PIN_10 | PIN_11, IO_MODE_OUTPUT | - IO_OUT_PUSH_PULL, 0)) return -1; - - // put the lcd bus in write mode - if(set_mode_write()) return -1; //no check in case the pins were used - //somewhere else - - // select instruction register - io_write(GPIOA, LCD_MODE_CMD, PIN_10); - - // begin initialisation sequence - timer_wait_ms(timer, 15, 0); - write_byte(LCD_FUNC_SET | LCD_FUNC_8BIT | LCD_FUNC_2LINE | - LCD_FUNC_5x8DOTS); - timer_wait_ms(timer, 5, 0); - write_byte(LCD_FUNC_SET | LCD_FUNC_8BIT | LCD_FUNC_2LINE | - LCD_FUNC_5x8DOTS); - timer_wait_us(timer, 150, 0); - write_byte(LCD_FUNC_SET | LCD_FUNC_8BIT | LCD_FUNC_2LINE | - LCD_FUNC_5x8DOTS); - wait_for_ready(); - write_byte(LCD_FUNC_SET | LCD_FUNC_8BIT | LCD_FUNC_2LINE | - LCD_FUNC_5x8DOTS); - wait_for_ready(); - write_byte(LCD_DISP_CTRL | LCD_CTRL_DISP_OFF | LCD_CTRL_CUR_OFF | - LCD_CTRL_BLINK_OFF); - wait_for_ready(); - write_byte(LCD_CLEAR); - wait_for_ready(); - write_byte(LCD_ENTRY | LCD_ENTRY_LEFT | LCD_ENTRY_SHIFT_DEC); - wait_for_ready(); - - // post initialisation setup - write_byte(LCD_DISP_CTRL | LCD_CTRL_DISP_ON | LCD_CTRL_CUR_ON | - LCD_CTRL_BLINK_ON); - wait_for_ready(); - write_byte(LCD_CLEAR); - - return 0; -} - -void lcd_send_cmd(uint8_t cmd) { - // wait for the screen - wait_for_ready(); - - // select instruction register - io_write(GPIOA, LCD_MODE_CMD, PIN_10); - - // send the command - write_byte(cmd); -} - -void lcd_print(const char* txt) { - // prepare data - const char* c = txt; - - // wait for the screen - wait_for_ready(); - - // select data register - io_write(GPIOA, LCD_MODE_DATA, PIN_10); - - // send the caracters until end of string - // TODO implement '\n' - while(*c != '\0') { - wait_for_ready(); - write_byte(*c); - c++; - } -} - -void lcd_print_c(char c) { - // wait for the screen - wait_for_ready(); - - // select data register - io_write(GPIOA, LCD_MODE_DATA, PIN_10); - - // send the caracter - write_byte(c); -} - -void lcd_set_cursor(uint8_t col, uint8_t row) { - lcd_send_cmd(LCD_DDRAM_ADDR | (col + rows_offset[row])); -} - diff --git a/src/drivers/lcd.h b/src/drivers/lcd.h deleted file mode 100644 index 00fb737..0000000 --- a/src/drivers/lcd.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef LCD_H -#define LCD_H - -#include "../target/stm32f103xb.h" -#include "../config.h" -#include "timer.h" -#include "io.h" -#include - -//------------------------------------------------------------------------------ -/* LCD mode selection */ -enum lcd_register { - LCD_MODE_CMD = 0, - LCD_MODE_DATA = 1 -}; - -//------------------------------------------------------------------------------ -/* LCD commands */ -enum lcd_command { - LCD_CLEAR = 0x01, - LCD_CUR_HOME = 0x02, - LCD_ENTRY = 0x04, - LCD_DISP_CTRL = 0x08, - LCD_SHIFT = 0x10, - LCD_FUNC_SET = 0x20, - LCD_CGRAM_ADDR = 0x40, - LCD_DDRAM_ADDR = 0x80 -}; - -//------------------------------------------------------------------------------ -/* LCD_ENTRY command options */ -enum lcd_entry_option { - LCD_ENTRY_RIGHT = 0x00, - LCD_ENTRY_LEFT = 0x02, - LCD_ENTRY_SHIFT_INC = 0x01, - LCD_ENTRY_SHIFT_DEC = 0x00 -}; - -//------------------------------------------------------------------------------ -/* LCD_DISP_CTRL command options */ -enum lcd_ctrl_option { - LCD_CTRL_DISP_ON = 0x04, - LCD_CTRL_DISP_OFF = 0x00, - LCD_CTRL_CUR_ON = 0x02, - LCD_CTRL_CUR_OFF = 0x00, - LCD_CTRL_BLINK_ON = 0x01, - LCD_CTRL_BLINK_OFF = 0x00 -}; - -//------------------------------------------------------------------------------ -/* LCD_SHIFT command options */ -enum lcd_shift_option { - LCD_SHIFT_DISP = 0x08, - LCD_SHIFT_CUR = 0x00, - LCD_SHIFT_RIGHT = 0x04, - LCD_SHIFT_LEFT = 0x00 -}; - -//------------------------------------------------------------------------------ -/* LCD_FUNC_SET command options */ -enum lcd_func_option { - LCD_FUNC_8BIT = 0x10, - LCD_FUNC_4BIT = 0x00, - LCD_FUNC_2LINE = 0x08, - LCD_FUNC_1LINE = 0x00, - LCD_FUNC_5x10DOTS = 0x04, - LCD_FUNC_5x8DOTS = 0x00 -}; - -//------------------------------------------------------------------------------ -/** lcd_init - * initialise the lcd, needed before anything else can be done - * the timer is used for delays and can't be in use when lcd functions are - * called - */ -int lcd_init(TIM_TypeDef* tim, uint8_t col, uint8_t row); - -/** lcd_send_cmd - * send the specified command to the lcd - */ -void lcd_send_cmd(uint8_t cmd); - -/** lcd_print - * print a null-terminated string on the lcd - */ -void lcd_print(const char* txt); - -void lcd_print_c(char c); - -void lcd_set_cursor(uint8_t col, uint8_t row); - -#endif - diff --git a/src/drivers/rcc.c b/src/drivers/rcc.c deleted file mode 100644 index 5f4cacb..0000000 --- a/src/drivers/rcc.c +++ /dev/null @@ -1,258 +0,0 @@ -/* -============================================================================== -##### RCC specific features ##### -============================================================================== -[..] -After reset the device is running from Internal High Speed oscillator -(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache -and I-Cache are disabled, and all peripherals are off except internal -SRAM, Flash and JTAG. -(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; -all peripherals mapped on these busses are running at HSI speed. -(+) The clock for all peripherals is switched off, except the SRAM and FLASH. -(+) All GPIOs are in input floating state, except the JTAG pins which -are assigned to be used for debug purpose. - -[..] -Once the device started from reset, the user application has to: -(+) Configure the clock source to be used to drive the System clock -(if the application needs higher frequency/performance) -(+) Configure the System clock frequency and Flash settings -(+) Configure the AHB and APB busses prescalers -(+) Enable the clock for the peripheral(s) to be used -(+) Configure the clock source(s) for peripherals which clocks are not -derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - -##### RCC Limitations ##### -============================================================================== -[..] -A delay between an RCC peripheral clock enable and the effective peripheral -enabling should be taken into account in order to manage the peripheral -read/write from/to registers. -(+) This delay depends on the peripheral mapping. -(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle -after the clock enable bit is set on the hardware register -(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle -after the clock enable bit is set on the hardware register - -[..] -Possible Workarounds: -(#) Enable the peripheral clock sometimes before the peripheral read/write -register is required. -(#) For AHB peripheral, insert two dummy read to the peripheral register. -(#) For APB peripheral, insert a dummy read to the peripheral register. -*/ - -#include "rcc.h" - -/* HPRE: AHB high-speed prescaler */ -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) - -/* PPRE1/2: APB high-speed prescalers */ -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 - -/* PPLMUL: PPL multiplier */ -#define RCC_CFGR_PLLMUL(fac) (fac + 2) - -/* ADC: ADCPRE prescalers */ -#define RCC_CFGR_ADCPRE_DIV_2 0x0 -#define RCC_CFGR_ADCPRE_DIV_4 0x1 -#define RCC_CFGR_ADCPRE_DIV_6 0x2 -#define RCC_CFGR_ADCPRE_DIV_8 0x3 - -enum rcc_osc { - RCC_HSI, - RCC_HSE, - RCC_PLL, - RCC_LSI, - RCC_LSE -}; - -struct ClockConfig_t { - uint8_t type; - uint8_t pll_src; - uint8_t pllmul; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - uint8_t adcpre; - uint32_t flash_cfg; - uint32_t ahb_freq; - uint32_t apb1_freq; - uint32_t apb2_freq; -}; - -static struct ClockConfig_t _clock_config[] = { - {/* Performance Mode */ - .type = RCC_PLL, - .pll_src = RCC_HSE, //8MHz - .pllmul = RCC_CFGR_PLLMUL(9), //freq should noot exceed 72MHz - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, //freq should not exceed 36MHz - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .adcpre = RCC_CFGR_ADCPRE_DIV_6, //freq should not exceed 14MHz - .flash_cfg = FLASH_ACR_LATENCY_2, - .ahb_freq = 72000000, - .apb1_freq = 36000000, - .apb2_freq = 72000000 - }, - - {/* Powersave Mode */ - .type = RCC_HSE, - .hpre = RCC_CFGR_HPRE_DIV_16, - .ppre1 = RCC_CFGR_PPRE_DIV_16, - .ppre2 = RCC_CFGR_PPRE_DIV_16, - .adcpre = RCC_CFGR_ADCPRE_DIV_2, - .flash_cfg = FLASH_ACR_LATENCY_0, - .ahb_freq = 500000, - .apb1_freq = 500000, - .apb2_freq = 500000 - } -}; - -static void rcc_osc_on(enum rcc_osc osc) -{ - switch (osc) { - case RCC_HSI: - if (!(RCC->CR & RCC_CR_HSION)) { - RCC->CR |= RCC_CR_HSION; - while ((RCC->CR & RCC_CR_HSIRDY)==0); - } - break; - case RCC_HSE: - if (!(RCC->CR & RCC_CR_HSEON)) { - RCC->CR |= RCC_CR_HSEON; - while ((RCC->CR & RCC_CR_HSERDY)==0); - } - break; - case RCC_PLL: - if (!(RCC->CR & RCC_CR_PLLON)) { - RCC->CR |= RCC_CR_PLLON; - while ((RCC->CR & RCC_CR_PLLRDY)==0); - } - break; - case RCC_LSI: - if (!(RCC->CSR & RCC_CSR_LSION)) { - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY)==0); - } - break; - case RCC_LSE: - if (!(RCC->BDCR & RCC_BDCR_LSEON)) { - RCC->BDCR |= RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY)==0); - } - break; - } -} - -static void rcc_osc_off(enum rcc_osc osc) -{ - switch (osc) { - case RCC_HSI: - RCC->CR &= ~RCC_CR_HSION; - break; - case RCC_HSE: - RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); - break; - case RCC_PLL: - RCC->CR &= ~RCC_CR_PLLON; - break; - case RCC_LSI: - RCC->CSR &= ~RCC_CSR_LSION; - break; - case RCC_LSE: - RCC->BDCR &= ~RCC_BDCR_LSEON; - break; - } -} - -static void rcc_set_sysclk(enum rcc_osc osc) -{ - RCC->CFGR = (RCC->CFGR & ~0x3) | (osc & 3); - while (((RCC->CFGR & 0xC)>>2) != osc); -} - -void rcc_config_clock(uint32_t config, Clock_t *sysclks) -{ - struct ClockConfig_t *clk; - - if (config < CLOCK_CONFIG_END) { - clk=&(_clock_config[config]); - } else { - clk=&(_clock_config[CLOCK_CONFIG_PERFORMANCE]); - } - - if (clk->type == RCC_HSE) { // HSE Clock - rcc_osc_on(RCC_HSE); - rcc_set_sysclk(RCC_HSE); - rcc_osc_off(RCC_PLL); - rcc_osc_off(RCC_HSI); - - } else if (clk->type == RCC_PLL) { - // enable PWR module clocking - RCC->APB1ENR |= 1<<28; - - if (clk->pll_src == RCC_HSE) { // HSE Clock src - rcc_osc_on(RCC_HSE); - } else { // Default: HSI Clock src - rcc_osc_on(RCC_HSI); - } - - // configure prescalers for - // AHB: AHBCLK > 25MHz - // APB1: APB1CLK <= 36MHz - // APB2: APB2CLK <= 72MHz - RCC->CFGR = ( RCC->CFGR & ~((0x3F<<8) | (0xF<<4) | (0x3<<14)) ) | - ((clk->hpre & 0xF) << 4) | - ((clk->ppre1 & 0x7) << 8) | - ((clk->ppre2 & 0x7) << 11)| - (clk->adcpre << 14); - - // configure PLL - RCC->CFGR &= !(0xF<<18); - RCC->CFGR |= clk->pllmul<<18; - - // enable PLL oscillator - rcc_osc_on(RCC_PLL); - - // set Flash timings - FLASH->ACR &= !0x8; - FLASH->ACR |= clk->flash_cfg; - //TODO set buffer bits - - // connect to PLL - rcc_set_sysclk(RCC_PLL); - - // stop unused clock - if ((clk->pll_src == RCC_HSE) && (RCC->CR & RCC_CR_HSION)) - rcc_osc_off(RCC_HSI); - else - rcc_osc_off(RCC_HSE); - - } else { // Default: HSI Clock - rcc_osc_on(RCC_HSI); - rcc_set_sysclk(RCC_HSI); - rcc_osc_off(RCC_PLL); - rcc_osc_off(RCC_HSE); - } - sysclks->ahb_freq = clk->ahb_freq; - sysclks->apb1_freq = clk->apb1_freq; - sysclks->apb2_freq = clk->apb2_freq; - sysclks->apb1_timer_freq = - clk->ppre1==RCC_CFGR_PPRE_DIV_NONE ? clk->apb1_freq : 2*clk->apb1_freq; - sysclks->apb2_timer_freq = - clk->ppre2==RCC_CFGR_PPRE_DIV_NONE ? clk->apb2_freq : 2*clk->apb2_freq; -} diff --git a/src/drivers/rcc.h b/src/drivers/rcc.h deleted file mode 100644 index 8996c09..0000000 --- a/src/drivers/rcc.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _RCC_H_ -#define _RCC_H_ - -#include "../target/stm32f103xb.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct _Clock_t { - uint32_t ahb_freq; - uint32_t apb1_freq; - uint32_t apb1_timer_freq; - uint32_t apb2_freq; - uint32_t apb2_timer_freq; -} Clock_t; - -enum Clock_config { - CLOCK_CONFIG_PERFORMANCE, - CLOCK_CONFIG_POWERSAVE, - CLOCK_CONFIG_END -}; - -//void SystemInit(void); - -void rcc_config_clock(uint32_t config, Clock_t *sysclks); - -# -#ifdef __cplusplus -} -#endif - -#endif diff --git a/src/drivers/rnd.c b/src/drivers/rnd.c deleted file mode 100644 index d266b5c..0000000 --- a/src/drivers/rnd.c +++ /dev/null @@ -1,20 +0,0 @@ -#include "rnd.h" - -uint32_t rnd_seed = 251; - -void set_rnd_seed(uint32_t seed) { - rnd_seed = seed; -} - -uint8_t rnd_byte() { - - static uint32_t r = 251; - static uint32_t Y = 7; - - if (r==0 || r==1 || r==0xFFFFFFFF) r=251; - r = (9973 * ~r) + ((Y) % 701); - Y = (r>>24) % 255; - - return (uint8_t)Y; -} - diff --git a/src/drivers/rnd.h b/src/drivers/rnd.h deleted file mode 100644 index 3a572cd..0000000 --- a/src/drivers/rnd.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef RND_H -#define RND_H - -#include "stdint.h" - -void set_rnd_seed(uint32_t seed); - -uint8_t rnd_byte(); - -#endif - diff --git a/src/drivers/timer.c b/src/drivers/timer.c deleted file mode 100644 index 3f611ca..0000000 --- a/src/drivers/timer.c +++ /dev/null @@ -1,338 +0,0 @@ -#include "timer.h" - -extern Clock_t sysclks; - -//------------------------------------------------------------------------------ -static OnTick callback1 = 0; -static OnTick callback2 = 0; -static OnTick callback3 = 0; -static OnTick callback4 = 0; - -void TIM1_UP_IRQHandler(void) { - if (callback1) callback1(); - TIM1->SR &= ~0x1F; -} - -void TIM2_IRQHandler(void) { - if (callback2) callback2(); - TIM2->SR &= ~0x1F; -} - -void TIM3_IRQHandler(void) { - if (callback3) callback3(); - TIM3->SR &= ~0x1F; -} - -void TIM4_IRQHandler(void) { - if (callback4) callback4(); - TIM4->SR &= ~0x1F; -} - -//------------------------------------------------------------------------------ -int timer_config_cb(TIM_TypeDef* tmr, uint32_t* clk, OnTick cb) { - IRQn_Type irqn; - uint32_t irq_priority; - - switch((uint32_t)tmr) { - case (uint32_t)TIM1: - // get clocks config - *clk = sysclks.apb2_timer_freq; - - // register callback function - callback1 = cb; - irqn = TIM1_UP_IRQn; //every update - irq_priority = TIM1_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB2ENR |= 1<<11; - break; - - case (uint32_t)TIM2: - // get clocks config - *clk = sysclks.apb1_timer_freq; - - // register callback function - callback2 = cb; - irqn = TIM2_IRQn; - irq_priority = TIM2_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<0; - break; - - case (uint32_t)TIM3: - // get clocks config - *clk = sysclks.apb1_timer_freq; - - // register callback function - callback3 = cb; - irqn = TIM3_IRQn; - irq_priority = TIM3_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<1; - break; - - case (uint32_t)TIM4: - // get clocks config - *clk = sysclks.apb1_timer_freq; - - // register callback function - callback4 = cb; - irqn = TIM4_IRQn; - irq_priority = TIM4_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<2; - break; - - default: - return -1; - } - - // clear pending interrupts - tmr->SR &= !1; - - // Enable interrupts - tmr->DIER = (1<<0); - NVIC_SetPriority(irqn,irq_priority); - NVIC_EnableIRQ(irqn); - - return 0; -} - -//------------------------------------------------------------------------------ -int timer_wait_ms(TIM_TypeDef* tmr, uint16_t ms, OnTick cb) { - uint32_t clk = 0; - - if(!cb) { //blocking - //get clocks config - if (tmr == TIM1) { - clk = sysclks.apb2_timer_freq; - RCC->APB2ENR |= 1<<11; - } - else { - clk = sysclks.apb1_timer_freq; - if (tmr == TIM2) RCC->APB1ENR |= 1<<0; - else if (tmr == TIM3) RCC->APB1ENR |= 1<<1; - else if (tmr == TIM4) RCC->APB1ENR |= 1<<2; - else return -1; // no such timer - } - - // set period - tmr->ARR = 0xFFFFFFFF; - - } else { //non-blocking - if(timer_config_cb(tmr, &clk, cb)) return -1; - - // set period - tmr->ARR = ms-1; - } - - // set mode - tmr->CR1 = (1<<7) | (1<<2); //buffering and update settings - tmr->CR1 |= (1<<3); //one pulse mode - - // set prescaler 1ms - tmr->PSC = 8*(clk/1000)-1; //PSC = clk/f - 1 | don't know why 8 times.. - - timer_start(tmr); - - if(!cb) { - while(tmr->CNT < ms); //waiting for end of delay - } - - return 0; -} - -int timer_wait_us(TIM_TypeDef* tmr, uint16_t us, OnTick cb) { - uint32_t clk = 0; - - if(!cb) { //blocking - //get clocks config - if (tmr == TIM1) { - clk = sysclks.apb2_timer_freq; - RCC->APB2ENR |= 1<<11; - } - else { - clk = sysclks.apb1_timer_freq; - if (tmr == TIM2) RCC->APB1ENR |= 1<<0; - else if (tmr == TIM3) RCC->APB1ENR |= 1<<1; - else if (tmr == TIM4) RCC->APB1ENR |= 1<<2; - else return -1; // no such timer - } - - // set period - tmr->ARR = 0xFFFFFFFF; - - } else { //non-blocking - if(timer_config_cb(tmr, &clk, cb)) return -1; - - // set period - tmr->ARR = us-1; - } - - // set mode - tmr->CR1 = (1<<7) | (1<<2); //buffering and update settings - tmr->CR1 |= (1<<3); //one pulse mode - - // set prescaler 1us - tmr->PSC = 8*(clk/1000000)-1; //PSC = clk/f - 1 | don't know why 8 times.. - - timer_start(tmr); - - if(!cb) { - while(tmr->CNT < us); //waiting for end of delay - } - - return 0; -} - - -//------------------------------------------------------------------------------ -int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb) { - IRQn_Type irqn; - uint32_t irq_priority, clk; - - switch((uint32_t)tmr) { - case (uint32_t)TIM1: - // get back the clock frequency - clk = sysclks.apb2_timer_freq; - - // register callback function - callback1 = cb; - irqn = TIM1_UP_IRQn; //every update - irq_priority = TIM1_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB2ENR |= 1<<11; - break; - - case (uint32_t)TIM2: - // get back the clock frequency - clk = sysclks.apb1_timer_freq; - - // register callback function - callback2 = cb; - irqn = TIM2_IRQn; - irq_priority = TIM2_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<0; - break; - - case (uint32_t)TIM3: - // get back the clock frequency - clk = sysclks.apb1_timer_freq; - - // register callback function - callback3 = cb; - irqn = TIM3_IRQn; - irq_priority = TIM3_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<1; - break; - - case (uint32_t)TIM4: - // get back the clock frequency - clk = sysclks.apb1_timer_freq; - - // register callback function - callback4 = cb; - irqn = TIM4_IRQn; - irq_priority = TIM4_IRQ_PRIORITY; - - // enable timer clocking - RCC->APB1ENR |= 1<<2; - break; - - default: - return -1; - } - - // clear pending interrupts - tmr->SR &= !1; - - // set mode - tmr->CR1 = (1<<7) | (1<<2); //buffering and update settings - tmr->DIER = (1<<0); //Enable interrupts - - // set prescaler 0.5ms - tmr->PSC = 8*(clk/2000)-1; //PSC = clk/f - 1 | don't know why 8 times... - - // set period - if(timer_set_period(tmr, tick_ms)) return -1; - - if (cb) { - NVIC_SetPriority(irqn,irq_priority); - NVIC_EnableIRQ(irqn); //unmask IRQ - } - - return 0; -} - -int timer_set_period(TIM_TypeDef *tmr, uint16_t tick) { - // set period - tmr->ARR = tick*2-1; //tickms = (ARR+1)Tpsc - - // force update to reset counter and apply prescaler - tmr->EGR |= 1; - return 0; -} - -void timer_start(TIM_TypeDef *tmr) { - // force update to reset counter and prescaler - tmr->EGR |= 1; - - // enable counting - tmr->CR1 |= 1; -} - -void timer_stop(TIM_TypeDef *tmr) { - // disable counting - tmr->CR1 &= !1; -} - -//------------------------------------------------------------------------------ -int timer_enc_init(TIM_TypeDef* tmr) { - // enable timer - switch((uint32_t)tmr) { - case (uint32_t)TIM1: - RCC->APB2ENR |= 1<<11; - break; - - case (uint32_t)TIM2: - RCC->APB1ENR |= 1<<0; - break; - - case (uint32_t)TIM3: - RCC->APB1ENR |= 1<<1; - break; - - case (uint32_t)TIM4: - RCC->APB1ENR |= 1<<2; - break; - - default: - return -1; //no such timer - } - - //TODO set registers at reset value - - tmr->SMCR |= 0x1; //count on only one edge - tmr->ARR = (1 << 16)-1; - - // map inputs - tmr->CCMR1 |= 0x9; - tmr->CCMR1 |= 0x9 << 8; - - // enable input channels and invert them //TODO add an otpion for that - tmr->CCER |= 0x3; - tmr->CCER |= 0x3 << 4; - - tmr->CR1 |= 0x1; //enable timer - - return 0; -} - diff --git a/src/drivers/timer.h b/src/drivers/timer.h deleted file mode 100644 index f2efe22..0000000 --- a/src/drivers/timer.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef TIMER_H -#define TIMER_H - -#include "../target/stm32f103xb.h" -#include "../config.h" -#include "rcc.h" - -typedef void (*OnTick)(void); - -//------------------------------------------------------------------------------ -/** timer_wait_ms - * wait for ms milliseconds function - */ -int timer_wait_ms(TIM_TypeDef *tmr, uint16_t ms, OnTick cb); - -/** timer_wait_us - * wait for us microseconds function - */ -int timer_wait_us(TIM_TypeDef *tmr, uint16_t us, OnTick cb); - -//------------------------------------------------------------------------------ - -/** timer_tick_init - * setup timer to call cb function periodically, each tick_ms - */ -int timer_tick_init(TIM_TypeDef *tmr, uint16_t tick_ms, OnTick cb); - -/** timer_set_period - * change the period, in ms when called after tick_init, - * otherwise in whatever unit the timer is configured - * reset count when used - */ -int timer_set_period(TIM_TypeDef *tmr, uint16_t tick); - -/** timer_start - * reset count and start counting - */ -void timer_start(TIM_TypeDef *tmr); - -/** timer_stop - * stop counting - */ -void timer_stop(TIM_TypeDef *tmr); - -//------------------------------------------------------------------------------ -/** timer_enc_init - * setup timer to read encoder output and keep track of it's position in the - * CNT register whithout using CPU time - */ -int timer_enc_init(TIM_TypeDef* tmr); - -//------------------------------------------------------------------------------ -//#define PWM_CHANNEL_1 0 -//#define PWM_CHANNEL_2 1 -//#define PWM_CHANNEL_3 2 -//#define PWM_CHANNEL_4 3 -// -///** pwm_init -// * setup pwm timer period, each tick_ms -// */ -//int pwm_init(TIM_TypeDef *pwm, uint32_t period_ms, OnTick cb); -// -///** pwm_channel_enable -// * set up pwm channel -// */ -//int pwm_channel_enable(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle, uint32_t oe); -// -///** pwm_channel_disable -// * disable pwm channel -// */ -//int pwm_channel_disable(TIM_TypeDef *pwm, uint32_t channel); -// -///** pwm_channel_set -// * set up dutycycle for pwm channel -// */ -//int pwm_channel_set(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle); -// -///** pwm_start -// * start counting -// */ -//#define pwm_start(pwm) timer_start(pwm) -// -///** pwm_stop -// * stop and reset counting -// */ -//#define pwm_stop(pwm) timer_stop(pwm) - -#endif - diff --git a/src/target/stm32f1xx.h.unused b/src/target/stm32f1xx.h.unused deleted file mode 100644 index 4c0fecc..0000000 --- a/src/target/stm32f1xx.h.unused +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f1xx.h - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The STM32F1xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_HAL_DRIVER" - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f1xx - * @{ - */ - -#ifndef __STM32F1XX_H -#define __STM32F1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F1) -#define STM32F1 -#endif /* STM32F1 */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ - !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ - !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) - /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ - /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ - /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ - /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ - /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ - /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ - /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ - /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ - /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ -#define STM32F103xB /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ - /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ - /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ - /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ - /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -//#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V4.2.0 - */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ - |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F1_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F100xB) - #include "stm32f100xb.h" -#elif defined(STM32F100xE) - #include "stm32f100xe.h" -#elif defined(STM32F101x6) - #include "stm32f101x6.h" -#elif defined(STM32F101xB) - #include "stm32f101xb.h" -#elif defined(STM32F101xE) - #include "stm32f101xe.h" -#elif defined(STM32F101xG) - #include "stm32f101xg.h" -#elif defined(STM32F102x6) - #include "stm32f102x6.h" -#elif defined(STM32F102xB) - #include "stm32f102xb.h" -#elif defined(STM32F103x6) - #include "stm32f103x6.h" -#elif defined(STM32F103xB) - #include "stm32f103xb.h" -#elif defined(STM32F103xE) - #include "stm32f103xe.h" -#elif defined(STM32F103xG) - #include "stm32f103xg.h" -#elif defined(STM32F105xC) - #include "stm32f105xc.h" -#elif defined(STM32F107xC) - #include "stm32f107xc.h" -#else - #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/target/system_clock.c.unused b/src/target/system_clock.c.unused deleted file mode 100644 index cb0916b..0000000 --- a/src/target/system_clock.c.unused +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 8 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 36 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | NO | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32f1xx.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= 0xF8FF0000U; -#else - RCC->CFGR &= 0xF0FF0000U; -#endif /* STM32F105xC */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - -#if defined(STM32F105xC) || defined(STM32F107xC) - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEBFFFFFFU; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#elif defined(STM32F100xB) || defined(STM32F100xE) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; -#endif /* STM32F105xC */ - -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - diff --git a/src/target/system_stm32f1xx.h.unused b/src/target/system_stm32f1xx.h.unused deleted file mode 100644 index f2557fa..0000000 --- a/src/target/system_stm32f1xx.h.unused +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.h - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/startup.s b/startup.s index e429ded..3d4080e 100644 --- a/startup.s +++ b/startup.s @@ -1,371 +1,309 @@ -/** - *************** (C) COPYRIGHT 2016 STMicroelectronics ************************ - * @file startup_stm32f103xb.s - * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 - * @brief STM32F103xB Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/** @file + * Startup script to be used with the HBL + * + * This startup file provides a reset handler to setup the basics for c to run + * (stack pointer, static data, ...) as well as the vector table and the + * differents interrupt handlers that go with it. By default, all handlers use + * the default handler wich is simply and infinite loop + */ - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ +.word _sromdata .word _sdata -/* end address for the .data section. defined in linker script */ .word _edata -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ -// bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - bl main - //bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler +//--Handler definitions--------------------------------------------------------- /** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors + * Reset handler, first thing executed at boot + * The handler configures the stack pointer and loads data from ROM to RAM + */ + .section .text.hdr_reset + .weak hdr_reset + .type hdr_reset, %function +hdr_reset: + ldr r0, = _estack + mov sp, r0 + +//load data from ROM to RAM + ldr r1, = _sdata + ldr r2, = _edata + subs r2, r2, r1 + bcc startup_init_end + ldr r3, = _sromdata + + movs r0, #0 + +startup_init_loop: + ldr r4, [r3, r0] + str r4, [r1, r0] + adds r0, r0, #4 + cmp r0, r2 + bcc startup_init_loop + +startup_init_end: + b main + b hdr_reset + + .size hdr_reset, .-hdr_reset + +/** + * Default handler, called on reception of an unexpected interrupt + * This is the handler used by default for all interrupts unless a specific + * handler was defined elsewhere + */ + .section .text.hdr_default, "ax", %progbits + .weak hdr_default +hdr_default: + b hdr_default + + .size hdr_default, .-hdr_default -g_pfnVectors: +//--Vector table---------------------------------------------------------------- - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ + .section .vector_table, "a", %progbits + .type vector_table, %object + .size vector_table, .-vector_table -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ +vector_table: + .word _estack + .word hdr_reset + .word hdr_nmi + .word hdr_hard_fault + .word hdr_mem_manage + .word hdr_bus_fault + .word hdr_usage_fault + .word 0 + .word 0 + .word 0 + .word 0 + .word hdr_svc + .word hdr_debug_monitor + .word 0 + .word hdr_pend_sys_service + .word hdr_sys_tick + .word hdr_wwdg + .word hdr_pvd + .word hdr_tamper + .word hdr_rtc + .word hdr_flash + .word hdr_rcc + .word hdr_exti0 + .word hdr_exti1 + .word hdr_exti2 + .word hdr_exti3 + .word hdr_exti4 + .word hdr_dma_channel1 + .word hdr_dma_channel2 + .word hdr_dma_channel3 + .word hdr_dma_channel4 + .word hdr_dma_channel5 + .word hdr_dma_channel6 + .word hdr_dma_channel7 + .word hdr_adc1_2 + .word hdr_hp_can_tx + .word hdr_lp_can_rx0 + .word hdr_can_rx1 + .word hdr_can_sce + .word hdr_exti9_5 + .word hdr_tim1_brk + .word hdr_tim1_up + .word hdr_tim1_trg_com + .word hdr_tim1_cc + .word hdr_tim2 + .word hdr_tim3 + .word hdr_tim4 + .word hdr_i2c1_event + .word hdr_i2c1_error + .word hdr_i2c2_event + .word hdr_i2c2_error + .word hdr_spi1 + .word hdr_spi2 + .word hdr_usart1 + .word hdr_usart2 + .word hdr_usart3 + .word hdr_exti15_10 + .word hdr_rtc_alarm + .word hdr_usb_wakeup + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler +//--Weak definitions------------------------------------------------------------ - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler + .weak hdr_nmi + .thumb_set hdr_nmi, hdr_default - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler + .weak hdr_hard_fault + .thumb_set hdr_hard_fault, hdr_default - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler + .weak hdr_mem_manage + .thumb_set hdr_mem_manage, hdr_default - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler + .weak hdr_bus_fault + .thumb_set hdr_bus_fault, hdr_default - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler + .weak hdr_usage_fault + .thumb_set hdr_usage_fault, hdr_default - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler + .weak hdr_svc + .thumb_set hdr_svc, hdr_default - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler + .weak hdr_debug_monitor + .thumb_set hdr_debug_monitor, hdr_default - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler + .weak hdr_pend_sys_service + .thumb_set hdr_pend_sys_service, hdr_default - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler + .weak hdr_sys_tick + .thumb_set hdr_sys_tick, hdr_default - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler + .weak hdr_wwdg + .thumb_set hdr_wwdg, hdr_default - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler + .weak hdr_pvd + .thumb_set hdr_pvd, hdr_default - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler + .weak hdr_tamper + .thumb_set hdr_tamper, hdr_default - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler + .weak hdr_rtc + .thumb_set hdr_rtc, hdr_default - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler + .weak hdr_flash + .thumb_set hdr_flash, hdr_default - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler + .weak hdr_rcc + .thumb_set hdr_rcc, hdr_default - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler + .weak hdr_exti0 + .thumb_set hdr_exti0, hdr_default - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler + .weak hdr_exti1 + .thumb_set hdr_exti1, hdr_default - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler + .weak hdr_exti2 + .thumb_set hdr_exti2, hdr_default - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler + .weak hdr_exti3 + .thumb_set hdr_exti3, hdr_default - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + .weak hdr_exti4 + .thumb_set hdr_exti4, hdr_default - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + .weak hdr_dma_channel1 + .thumb_set hdr_dma_channel1, hdr_default - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + .weak hdr_dma_channel2 + .thumb_set hdr_dma_channel2, hdr_default - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + .weak hdr_dma_channel3 + .thumb_set hdr_dma_channel3, hdr_default - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + .weak hdr_dma_channel4 + .thumb_set hdr_dma_channel4, hdr_default - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + .weak hdr_dma_channel5 + .thumb_set hdr_dma_channel5, hdr_default - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + .weak hdr_dma_channel6 + .thumb_set hdr_dma_channel6, hdr_default - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler + .weak hdr_dma_channel7 + .thumb_set hdr_dma_channel7, hdr_default - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + .weak hdr_adc1_2 + .thumb_set hdr_adc1_2, hdr_default - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + .weak hdr_hp_can_tx + .thumb_set hdr_hp_can_tx, hdr_default - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler + .weak hdr_lp_can_rx0 + .thumb_set hdr_lp_can_rx0, hdr_default - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler + .weak hdr_can_rx1 + .thumb_set hdr_can_rx1, hdr_default - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler + .weak hdr_can_sce + .thumb_set hdr_can_sce, hdr_default - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler + .weak hdr_exti9_5 + .thumb_set hdr_exti9_5, hdr_default - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler + .weak hdr_tim1_brk + .thumb_set hdr_tim1_brk, hdr_default - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + .weak hdr_tim1_up + .thumb_set hdr_tim1_up, hdr_default - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler + .weak hdr_tim1_trg_com + .thumb_set hdr_tim1_trg_com, hdr_default - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler + .weak hdr_tim1_cc + .thumb_set hdr_tim1_cc, hdr_default - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler + .weak hdr_tim2 + .thumb_set hdr_tim2, hdr_default - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler + .weak hdr_tim3 + .thumb_set hdr_tim3, hdr_default - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler + .weak hdr_tim4 + .thumb_set hdr_tim4, hdr_default - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler + .weak hdr_i2c1_event + .thumb_set hdr_i2c1_event, hdr_default - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler + .weak hdr_i2c1_error + .thumb_set hdr_i2c1_error, hdr_default - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler + .weak hdr_i2c2_event + .thumb_set hdr_i2c2_event, hdr_default - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler + .weak hdr_i2c2_error + .thumb_set hdr_i2c2_error, hdr_default - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler + .weak hdr_spi1 + .thumb_set hdr_spi1, hdr_default - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler + .weak hdr_spi2 + .thumb_set hdr_spi2, hdr_default - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler + .weak hdr_usart1 + .thumb_set hdr_usart1, hdr_default - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler + .weak hdr_usart2 + .thumb_set hdr_usart2, hdr_default - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler + .weak hdr_usart3 + .thumb_set hdr_usart3, hdr_default - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler + .weak hdr_exti15_10 + .thumb_set hdr_exti15_10, hdr_default - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler + .weak hdr_rtc_alarm + .thumb_set hdr_rtc_alarm, hdr_default -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + .weak hdr_usb_wakeup + .thumb_set hdr_usb_wakeup, hdr_default -- 2.45.2 From 50dc10b76e0de904727eaae263bcbe614615d184 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 19 Mar 2023 21:57:37 +0100 Subject: [PATCH 04/85] Create RCC register map --- drivers/rcc_regs.h | 269 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 269 insertions(+) create mode 100644 drivers/rcc_regs.h diff --git a/drivers/rcc_regs.h b/drivers/rcc_regs.h new file mode 100644 index 0000000..8177b3e --- /dev/null +++ b/drivers/rcc_regs.h @@ -0,0 +1,269 @@ + +#ifndef _RCC_REGS_H_ +#define _RCC_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define RCC_BASE_ADDRESS 0x40021000 + +union RCC_CR { + struct __attribute__((packed)) { + uint32_t HSION:1; + uint32_t HSIRDY:1; + uint32_t reserved1:1; + uint32_t HSITRIM:5; + uint32_t HSICAL:8; + uint32_t HSEON:1; + uint32_t HSERDY:1; + uint32_t HSEBYP:1; + uint32_t CCSON:1; + uint32_t reserved2:4; + uint32_t PLLON:1; + uint32_t PLLRDY:1; + uint32_t reserved3:6; + }; + uint32_t word; +}; + +union RCC_CFGR { + struct __attribute__((packed)) { + uint32_t SW:2; + uint32_t SWS:2; + uint32_t HPRE:4; + uint32_t PPRE1:3; + uint32_t PPRE2:3; + uint32_t ADCPRE:2; + uint32_t PLLSCR:1; + uint32_t PLLXTPRE:1; + uint32_t PLLMUL:4; + uint32_t USBPRE:1; + uint32_t reserved1:1; + uint32_t MCO:3; + uint32_t reserved2:5; + }; + uint32_t word; +}; + +union RCC_CIR { + struct __attribute__((packed)) { + uint32_t LSIRDYF:1; + uint32_t LSERDYF:1; + uint32_t HSIRDYF:1; + uint32_t HSERDYF:1; + uint32_t PLLRDYF:1; + uint32_t reserved1:2; + uint32_t CSSF:1; + uint32_t LSIRDYIE:1; + uint32_t LSERDYIE:1; + uint32_t HSIRDYIE:1; + uint32_t HSERDYIE:1; + uint32_t PLLRDYIE:1; + uint32_t RSE2:3; + uint32_t LSIRDYC:1; + uint32_t LSERDYC:1; + uint32_t HSIRDYC:1; + uint32_t HSERDYC:1; + uint32_t PLLRDYC:1; + uint32_t reserved3:2; + uint32_t CSSC:1; + uint32_t reserved4:8; + }; + uint32_t word; +}; + +union RCC_APB2RSTR { + struct __attribute__((packed)) { + uint32_t AFIORST:1; + uint32_t reserved1:1; + uint32_t IOPARST:1; + uint32_t IOPBRST:1; + uint32_t IOPCRST:1; + uint32_t IOPDRST:1; + uint32_t IOPERST:1; + uint32_t IOPFRST:1; + uint32_t IOPGRST:1; + uint32_t ADC1RST:1; + uint32_t ACD2RST:1; + uint32_t TIM1RST:1; + uint32_t SPI1RST:1; + uint32_t TIM8RST:1; + uint32_t USART1RST:1; + uint32_t ADC3RST:1; + uint32_t reserved2:3; + uint32_t TIM9RST:1; + uint32_t TIM10RST:1; + uint32_t TIM11RST:1; + uint32_t reserved3:10; + }; + uint32_t word; +}; + +union RCC_APB1RSTR { + struct __attribute__((packed)) { + uint32_t TIM2RST:1; + uint32_t TIM3RST:1; + uint32_t TIM4RST:1; + uint32_t TIM5RST:1; + uint32_t TIM6RST:1; + uint32_t TIM7RST:1; + uint32_t TIM12RST:1; + uint32_t TIM13RST:1; + uint32_t TIM14RST:1; + uint32_t reserved1:2; + uint32_t WWDGRST:1; + uint32_t reserved2:2; + uint32_t SPI2RST:1; + uint32_t SPI3RST:1; + uint32_t reserved3:1; + uint32_t USART2RST:1; + uint32_t USART3RST:1; + uint32_t UART4RST:1; + uint32_t UART5RST:1; + uint32_t I2C12RST:1; + uint32_t I2C2RST:1; + uint32_t USB2RST:1; + uint32_t reserved4:1; + uint32_t CANRST:1; + uint32_t reserved5:1; + uint32_t BKPRST:1; + uint32_t PWRRST:1; + uint32_t DACRST:1; + uint32_t reserved6:2; + }; + uint32_t word; +}; + +union RCC_AHBENR { + struct __attribute__((packed)) { + uint32_t DMA1EN:1; + uint32_t DMA2EN:1; + uint32_t SRAMEN:1; + uint32_t reserved1:1; + uint32_t FLITFEN:1; + uint32_t reserved2:1; + uint32_t CRCEN:1; + uint32_t reserved3:1; + uint32_t FSMCEN:1; + uint32_t reserved4:1; + uint32_t SDIOEN:1; + uint32_t reserved5:21; + }; + uint32_t word; +}; + +union RCC_APB2ENR { + struct __attribute__((packed)) { + uint32_t AFIOEN:1; + uint32_t reserved1:1; + uint32_t IOPAEN:1; + uint32_t IOPBEN:1; + uint32_t IOPCEN:1; + uint32_t IOPDEN:1; + uint32_t IOPEEN:1; + uint32_t IOPFEN:1; + uint32_t IOPGEN:1; + uint32_t ADC1EN:1; + uint32_t ACD2EN:1; + uint32_t TIM1EN:1; + uint32_t SPI1EN:1; + uint32_t TIM8EN:1; + uint32_t USART1EN:1; + uint32_t ADC3EN:1; + uint32_t reserved2:3; + uint32_t TIM9EN:1; + uint32_t TIM10EN:1; + uint32_t TIM11EN:1; + uint32_t reserved3:10; + }; + uint32_t word; +}; + +union RCC_APB1ENR { + struct __attribute__((packed)) { + uint32_t TIM2EN:1; + uint32_t TIM3EN:1; + uint32_t TIM4EN:1; + uint32_t TIM5EN:1; + uint32_t TIM6EN:1; + uint32_t TIM7EN:1; + uint32_t TIM12EN:1; + uint32_t TIM13EN:1; + uint32_t TIM14EN:1; + uint32_t reserved1:2; + uint32_t WWDGEN:1; + uint32_t reserved2:2; + uint32_t SPI2EN:1; + uint32_t SPI3EN:1; + uint32_t reserved3:1; + uint32_t USART2EN:1; + uint32_t USART3EN:1; + uint32_t UART4EN:1; + uint32_t UART5EN:1; + uint32_t I2C12EN:1; + uint32_t I2C2EN:1; + uint32_t USB2EN:1; + uint32_t reserved4:1; + uint32_t CANEN:1; + uint32_t reserved5:1; + uint32_t BKPEN:1; + uint32_t PWREN:1; + uint32_t DACEN:1; + uint32_t reserved6:2; + }; + uint32_t word; +}; + +union RCC_BDCR { + struct __attribute__((packed)) { + uint32_t LSEON:1; + uint32_t LSERDY:1; + uint32_t LSEBYP:1; + uint32_t reserved1:5; + uint32_t RTCSEL:2; + uint32_t reserved2:5; + uint32_t RTCEN:1; + uint32_t BDRST:1; + uint32_t reserved3:15; + }; + uint32_t word; +}; + +union RCC_CSR { + struct __attribute__((packed)) { + uint32_t LSION:1; + uint32_t LSIRDY:1; + uint32_t reserved1:22; + uint32_t RMVF:1; + uint32_t reserved2:1; + uint32_t PINRSTF:1; + uint32_t PORRSTF:1; + uint32_t SFTRSTF:1; + uint32_t IWDGRSTF:1; + uint32_t WWDGRSTF:1; + uint32_t LPWRSTF:1; + }; + uint32_t word; +}; + +struct __attribute__((packed)) RCC { + union RCC_CR CR; + union RCC_CFGR CFGR; + union RCC_CIR CIR; + union RCC_APB2RSTR APB2RSTR; + union RCC_APB1RSTR APB1RSTR; + union RCC_AHBENR AHBENR; + union RCC_APB2ENR APB2ENR; + union RCC_APB1ENR APB1ENR; + union RCC_BDCR BDCR; + union RCC_CSR CSR; +}; + +//--functions------------------------------------------------------------------- + +#endif //_RCC_REGS_H_ + -- 2.45.2 From dd6d5fbdd19c62bb25c45d7006d85989fd287cc5 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 22 Mar 2023 23:30:29 +0100 Subject: [PATCH 05/85] Implement RCC's clock configuration For now, flash configuration is hard-coded. This will fixed in future commits --- drivers/rcc.c | 126 +++++++++++++++++++++++++++++++++++++++++++++ drivers/rcc.h | 38 ++++++++++++++ drivers/rcc_regs.h | 7 +++ 3 files changed, 171 insertions(+) create mode 100644 drivers/rcc.c create mode 100644 drivers/rcc.h diff --git a/drivers/rcc.c b/drivers/rcc.c new file mode 100644 index 0000000..c071afa --- /dev/null +++ b/drivers/rcc.c @@ -0,0 +1,126 @@ +/** @file rcc.c + * Module handling Reset and Clocks Control (RCC). + * + * The module provides functions to configure clocks according to presets as + * well as to enable/disable/reset peripherals. + */ + +//--includes-------------------------------------------------------------------- + +#include "rcc.h" +#include "rcc_regs.h" + + +//--local definitions----------------------------------------------------------- + +static void apply_default_preset(void); +static void apply_speed_preset(void); + + +//--local variables------------------------------------------------------------- + +static volatile struct RCC* regs = (struct RCC*)RCC_BASE_ADDRESS; + + +//--public functions------------------------------------------------------------ + +void rcc_configure(enum RccPreset preset) +{ + //disable all peripherals during clock configuration + union RCC_APB1ENR apb1_enr = regs->APB1ENR; + regs->APB1ENR.word = 0x0; + union RCC_APB2ENR apb2_enr = regs->APB2ENR; + regs->APB2ENR.word = 0x0; + + switch (preset) { + case RCC_PRESET_DEFAULT: + apply_default_preset(); + break; + case RCC_PRESET_SPEED: + apply_speed_preset(); + break; + default: + break; + } + + //re-enable peripherals + regs->APB1ENR = apb1_enr; + regs->APB2ENR = apb2_enr; +} + + +//--local functions------------------------------------------------------------- + +/** + * Apply the default clock preset, using HSI whithout PLL or prescalers. This is + * similar to the reset configuration. Most buses run at 8Mhz, except ADCs wich + * run at 4Mhz, and Systick wich only reaches 1Mhz. + */ +static void apply_default_preset(void) +{ + //ensures HSI is enabled + regs->CR.HSION = 0x1; + while (regs->CR.HSIRDY != 0x1); + + //set HSI as main clock source and disable prescalers + regs->CFGR.word &= !0x077fff3; + + //disable all options + regs->CR.HSITRIM = 0x10; + regs->CR.HSEON = 0x0; + regs->CR.HSEBYP = 0x0; + regs->CR.CCSON = 0x0; + regs->CR.PLLON = 0x0; + + //disable all interrupts + regs->CIR.LSIRDYIE = 0x0; + regs->CIR.LSERDYIE = 0x0; + regs->CIR.HSIRDYIE = 0x0; + regs->CIR.HSERDYIE = 0x0; + regs->CIR.PLLRDYIE = 0x0; +} + +/** + * Apply the speed preset, using HSE with PLL to achieve 72MHz on AHB, APB2 and + * timer buses. APB1 is limited to its maximum clock of 36Mhz and the ADCs run + * at 12MHz. Systick runs at 9Mhz. + */ +static void apply_speed_preset(void) +{ + //restore sane values + apply_default_preset(); + + //try enabling HSE, fallback to HSI if HSE fails + regs->CR.HSEON = 0x1; + for (uint32_t i=0; i<1000; ++i) { + __asm__("nop"); + } + if (regs->CR.HSERDY == 0x1) { + regs->CFGR.PLLSCR = 0x1; + } else { + regs->CR.HSEON = 0; + } + + //configure PLL, fallback to HSI if PLL fails + regs->CFGR.PLLMUL = 0x7; //PLL x9 + regs->CR.PLLON = 0x1; + for (uint32_t i=0; i<1000; ++i) { + __asm__("nop"); + } + if (regs->CR.PLLRDY != 0x1) { + regs->CR.PLLON = 0x0; + return; //clock low enough, no need for prescalers + } + + //configure prescalers + regs->CFGR.PPRE1 = 0x4; // /2 + regs->CFGR.ADCPRE = 0x2; // /6 + + //configure flash + volatile uint32_t* ACR = (uint32_t*)0x40022000; + *ACR |= 0x12; + + //switch to PLL output + regs->CFGR.SW = 0x2; +} + diff --git a/drivers/rcc.h b/drivers/rcc.h new file mode 100644 index 0000000..09d71d4 --- /dev/null +++ b/drivers/rcc.h @@ -0,0 +1,38 @@ +/** @file rcc.h + * Module handling Reset and Clocks Control (RCC). + * + * The module provides functions to configure clocks according to presets as + * well as to enable/disable/reset peripherals. + */ + +#ifndef _RCC_H_ +#define _RCC_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +/** + * Available clock configuration presets + */ +enum RccPreset { + RCC_PRESET_DEFAULT, //sane values, identical to reset config + RCC_PRESET_SPEED, //highest clocks, uses 8MHz HSE if available +}; + + +//--functions------------------------------------------------------------------- + +/** + * Configures the clocks and buses according to the given preset. + * + * @param preset the preset to use for configuration + */ +void rcc_configure(enum RccPreset preset); + + +#endif //_RCC_H_ + diff --git a/drivers/rcc_regs.h b/drivers/rcc_regs.h index 8177b3e..3c804fb 100644 --- a/drivers/rcc_regs.h +++ b/drivers/rcc_regs.h @@ -1,3 +1,10 @@ +/** @file rcc_regs.h + * Module defining Reset and Clocks Control (RCC) registers. + * + * Mainly made to be used by the rcc module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ #ifndef _RCC_REGS_H_ #define _RCC_REGS_H_ -- 2.45.2 From 7f7cb077dc5acf6ac892909e90fd62acc3fec96f Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 24 Mar 2023 19:05:43 +0100 Subject: [PATCH 06/85] Create flash register map --- drivers/flash_regs.h | 97 ++++++++++++++++++++++++++++++++++++++++++++ drivers/rcc_regs.h | 1 + 2 files changed, 98 insertions(+) create mode 100644 drivers/flash_regs.h diff --git a/drivers/flash_regs.h b/drivers/flash_regs.h new file mode 100644 index 0000000..26f4593 --- /dev/null +++ b/drivers/flash_regs.h @@ -0,0 +1,97 @@ +/** @file flash_regs.h + * Module defining flash memory interface registers. + * + * Mainly made to be used by the rcc module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _FLASH_REGS_H_ +#define _FLASH_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define FLASH_BASE_ADDRESS 0x40022000 + +union FLASH_ACR { + struct __attribute__((packed)) { + uint32_t LATENCY:3; + uint32_t HLFCYA:1; + uint32_t PRFTBE:1; + uint32_t PRFTBS:1; + uint32_t reserved1:26; + }; + uint32_t word; +}; + +union FLASH_KEYR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_OPTKEYR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_SR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_CR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_AR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_OBR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +union FLASH_WRPR { + struct __attribute__((packed)) { + uint32_t reserved1; //TODO + }; + uint32_t word; +}; + +struct __attribute__((packed)) FLASH { + union FLASH_ACR ACR; + union FLASH_KEYR KEYR; + union FLASH_OPTKEYR OPTKEYR; + union FLASH_SR SR; + union FLASH_CR CR; + union FLASH_AR AR; + uint32_t reserved1; + union FLASH_OBR OBR; + union FLASH_WRPR WRPR; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_FLASH_REGS_H_ + diff --git a/drivers/rcc_regs.h b/drivers/rcc_regs.h index 3c804fb..047f7e9 100644 --- a/drivers/rcc_regs.h +++ b/drivers/rcc_regs.h @@ -270,6 +270,7 @@ struct __attribute__((packed)) RCC { union RCC_CSR CSR; }; + //--functions------------------------------------------------------------------- #endif //_RCC_REGS_H_ -- 2.45.2 From 3a768d9190d5dc3fac206ff0722a4a4c7f99bb2d Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 26 Mar 2023 21:07:37 +0200 Subject: [PATCH 07/85] Implement Flash configuration --- drivers/flash.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/flash.h | 39 +++++++++++++++++++++++++++++++++++++++ drivers/rcc.c | 9 ++++++--- 3 files changed, 92 insertions(+), 3 deletions(-) create mode 100644 drivers/flash.c create mode 100644 drivers/flash.h diff --git a/drivers/flash.c b/drivers/flash.c new file mode 100644 index 0000000..bed13ea --- /dev/null +++ b/drivers/flash.c @@ -0,0 +1,47 @@ +/** @file flash.c + * Module handling flash memory interface registers. + * + * The module provides functions to configure the flash and perform read and + * writes + */ + +//--includes-------------------------------------------------------------------- + +#include "flash.h" +#include "flash_regs.h" + + +//--local definitions----------------------------------------------------------- + +//--local variables------------------------------------------------------------- + +static volatile struct FLASH* regs = (struct FLASH*)FLASH_BASE_ADDRESS; + + +//--public functions------------------------------------------------------------ + +void flash_configure(enum FlashPreset preset) +{ + //restore default configuration + regs->ACR.word &= !0x3f; + regs->ACR.word |= 0x30; + + //apply new configuration + switch (preset) { + case FLASH_PRESET_LOW_CLOCK_SPEED: + regs->ACR.HLFCYA = 0x1; //half cycle for power saving + break; + case FLASH_PRESET_MEDIUM_CLOCK_SPEED: + regs->ACR.LATENCY = 0x1; + break; + case FLASH_PRESET_HIGH_CLOCK_SPEED: + regs->ACR.LATENCY = 0x2; + break; + default: + break; + } +} + + +//--local functions------------------------------------------------------------- + diff --git a/drivers/flash.h b/drivers/flash.h new file mode 100644 index 0000000..4e49659 --- /dev/null +++ b/drivers/flash.h @@ -0,0 +1,39 @@ +/** @file flash.h + * Module handling flash memory interface registers. + * + * The module provides functions to configure the flash and perform read and + * writes + */ + +#ifndef _FLASH_H_ +#define _FLASH_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +/** + * Available flash configuration presets + */ +enum FlashPreset { + FLASH_PRESET_LOW_CLOCK_SPEED, //for 0 < clock <= 24Mz + FLASH_PRESET_MEDIUM_CLOCK_SPEED, //for 24MHz < clock <= 48MHz + FLASH_PRESET_HIGH_CLOCK_SPEED, //for 48MHz < clock <= 72MHz +}; + + +//--functions------------------------------------------------------------------- + +/** + * Configure the flash according to the given preset. Warning: calling this + * function with a sysclk higher than 24Mhz may cause the system to crash, + * please lower the clocks first + */ +void flash_configure(enum FlashPreset preset); + + +#endif //_FLASH_H_ + diff --git a/drivers/rcc.c b/drivers/rcc.c index c071afa..dc488ec 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -9,6 +9,7 @@ #include "rcc.h" #include "rcc_regs.h" +#include "flash.h" //--local definitions----------------------------------------------------------- @@ -78,6 +79,9 @@ static void apply_default_preset(void) regs->CIR.HSIRDYIE = 0x0; regs->CIR.HSERDYIE = 0x0; regs->CIR.PLLRDYIE = 0x0; + + //reconfigure flash + flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED); } /** @@ -116,9 +120,8 @@ static void apply_speed_preset(void) regs->CFGR.PPRE1 = 0x4; // /2 regs->CFGR.ADCPRE = 0x2; // /6 - //configure flash - volatile uint32_t* ACR = (uint32_t*)0x40022000; - *ACR |= 0x12; + //reconfigure flash + flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED); //switch to PLL output regs->CFGR.SW = 0x2; -- 2.45.2 From a101f07009aea384888bdb2902ffb91469dc0281 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 31 Mar 2023 14:04:36 +0200 Subject: [PATCH 08/85] Implement peripheral control functions --- drivers/rcc.c | 33 ++++++++++++++++++ drivers/rcc.h | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/drivers/rcc.c b/drivers/rcc.c index dc488ec..cf99db1 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -14,6 +14,9 @@ //--local definitions----------------------------------------------------------- +#define APB1_MASK 0x3afec9ff +#define APB2_MASK 0x0038fffd + static void apply_default_preset(void); static void apply_speed_preset(void); @@ -49,6 +52,36 @@ void rcc_configure(enum RccPreset preset) regs->APB2ENR = apb2_enr; } +void rcc_enable_apb1(enum RccApb1 mask) +{ + regs->APB1ENR.word |= mask & APB1_MASK; +} + +void rcc_disable_apb1(enum RccApb1 mask) +{ + regs->APB1ENR.word &= !(mask & APB1_MASK); +} + +void rcc_reset_apb1(enum RccApb1 mask) +{ + regs->APB1RSTR.word &= !(mask & APB1_MASK); +} + +void rcc_enable_apb2(enum RccApb2 mask) +{ + regs->APB2ENR.word |= mask & APB2_MASK; +} + +void rcc_disable_apb2(enum RccApb2 mask) +{ + regs->APB2ENR.word &= !(mask & APB2_MASK); +} + +void rcc_reset_apb2(enum RccApb2 mask) +{ + regs->APB2RSTR.word &= !(mask & APB2_MASK); +} + //--local functions------------------------------------------------------------- diff --git a/drivers/rcc.h b/drivers/rcc.h index 09d71d4..30455b6 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -23,6 +23,61 @@ enum RccPreset { RCC_PRESET_SPEED, //highest clocks, uses 8MHz HSE if available }; +/** + * Available peripherals on the APB1 bus. Note that some of these peripherals + * may not be availables on all chips + */ +enum RccApb1 { + RCC_APB1_TIM2 = (0x1 << 0), + RCC_APB1_TIM3 = (0x1 << 1), + RCC_APB1_TIM4 = (0x1 << 2), + RCC_APB1_TIM5 = (0x1 << 3), + RCC_APB1_TIM6 = (0x1 << 4), + RCC_APB1_TIM7 = (0x1 << 5), + RCC_APB1_TIM12 = (0x1 << 6), + RCC_APB1_TIM13 = (0x1 << 7), + RCC_APB1_TIM14 = (0x1 << 8), + RCC_APB1_WWDG = (0x1 << 11), + RCC_APB1_SPI2 = (0x1 << 14), + RCC_APB1_SPI3 = (0x1 << 15), + RCC_APB1_USART2 = (0x1 << 17), + RCC_APB1_USART3 = (0x1 << 18), + RCC_APB1_UART4 = (0x1 << 19), + RCC_APB1_UART5 = (0x1 << 20), + RCC_APB1_I2C1 = (0x1 << 21), + RCC_APB1_I2C2 = (0x1 << 22), + RCC_APB1_USB = (0x1 << 23), + RCC_APB1_CAN = (0x1 << 25), + RCC_APB1_BKP = (0x1 << 27), + RCC_APB1_PWR = (0x1 << 28), + RCC_APB1_DAC = (0x1 << 29), +}; + +/** + * Available peripherals on the APB2 bus. Note that some of these peripherals + * may not be available on all chips + */ +enum RccApb2 { + RCC_APB2_AFOI = (0x1 << 0), + RCC_APB2_IOPA = (0x1 << 2), + RCC_APB2_IOPB = (0x1 << 3), + RCC_APB2_IOPC = (0x1 << 4), + RCC_APB2_IOPD = (0x1 << 5), + RCC_APB2_IOPE = (0x1 << 6), + RCC_APB2_IOPF = (0x1 << 7), + RCC_APB2_IOPG = (0x1 << 8), + RCC_APB2_ADC1 = (0x1 << 9), + RCC_APB2_ADC2 = (0x1 << 10), + RCC_APB2_TIM1 = (0x1 << 11), + RCC_APB2_SPI1 = (0x1 << 12), + RCC_APB2_TIM8 = (0x1 << 13), + RCC_APB2_USART = (0x1 << 14), + RCC_APB2_ADC3 = (0x1 << 15), + RCC_APB2_TIM9 = (0x1 << 19), + RCC_APB2_TIM10 = (0x1 << 20), + RCC_APB2_TIM11 = (0x1 << 21), +}; + //--functions------------------------------------------------------------------- @@ -33,6 +88,48 @@ enum RccPreset { */ void rcc_configure(enum RccPreset preset); +/** + * Enables peripherals on the APB1 bus according to the given mask. + * + * @param mask the mask for the peripherals to enable + */ +void rcc_enable_apb1(enum RccApb1 mask); + +/** + * Disables peripherals on the APB1 bus according to the given mask. + * + * @param mask the mask for the peripherals to disable + */ +void rcc_disable_apb1(enum RccApb1 mask); + +/** + * Resets peripherals on the APB1 bus according to the given mask. + * + * @param mask the mask for the peripherals to reset + */ +void rcc_reset_apb1(enum RccApb1 mask); + +/** + * Enables peripherals on the APB2 bus according to the given mask. + * + * @param mask the mask for the peripherals to enable + */ +void rcc_enable_apb2(enum RccApb2 mask); + +/** + * Disables peripherals on the APB2 bus according to the given mask. + * + * @param mask the mask for the peripherals to disable + */ +void rcc_disable_apb2(enum RccApb2 mask); + +/** + * Resets peripherals on the APB2 bus according to the given mask. + * + * @param mask the mask for the peripherals to reset + */ +void rcc_reset_apb2(enum RccApb2 mask); + #endif //_RCC_H_ -- 2.45.2 From ca935a7650153208f2708078ba7f78bdf15caf5c Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 31 Mar 2023 14:15:42 +0200 Subject: [PATCH 09/85] Rework comments Avoid repitions between comments and code. Additionnal usage information can be added as header comment and additionnal technical information can be added in the source file --- drivers/flash.c | 5 +++++ drivers/rcc.c | 4 ++++ drivers/rcc.h | 31 ++++++++++--------------------- 3 files changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/flash.c b/drivers/flash.c index bed13ea..a49df48 100644 --- a/drivers/flash.c +++ b/drivers/flash.c @@ -20,6 +20,11 @@ static volatile struct FLASH* regs = (struct FLASH*)FLASH_BASE_ADDRESS; //--public functions------------------------------------------------------------ +/** + * Sets the correct latency to compensate the core's clock speed. Latency must + * never be too low or the system will crash due to errors when accessing the + * flash, hence the warning in the header + */ void flash_configure(enum FlashPreset preset) { //restore default configuration diff --git a/drivers/rcc.c b/drivers/rcc.c index cf99db1..4af833b 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -28,6 +28,10 @@ static volatile struct RCC* regs = (struct RCC*)RCC_BASE_ADDRESS; //--public functions------------------------------------------------------------ +/** + * Configures the clock sources, PLL, prescalers, etc. All peripherals are + * disabled prior to any modifications to avoid unwanted side effects. + */ void rcc_configure(enum RccPreset preset) { //disable all peripherals during clock configuration diff --git a/drivers/rcc.h b/drivers/rcc.h index 30455b6..b3ccc6e 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -82,51 +82,40 @@ enum RccApb2 { //--functions------------------------------------------------------------------- /** - * Configures the clocks and buses according to the given preset. - * - * @param preset the preset to use for configuration + * Configures the clocks and buses according to the given preset. Peripheral + * states are kept during the change and additional reconfiguration are + * handled automatically for peripherals that rely on a clock timings (timers, + * watchdogs, ...) */ void rcc_configure(enum RccPreset preset); /** - * Enables peripherals on the APB1 bus according to the given mask. - * - * @param mask the mask for the peripherals to enable + * Enables peripherals on the APB1 bus */ void rcc_enable_apb1(enum RccApb1 mask); /** - * Disables peripherals on the APB1 bus according to the given mask. - * - * @param mask the mask for the peripherals to disable + * Disables peripherals on the APB1 bus */ void rcc_disable_apb1(enum RccApb1 mask); /** - * Resets peripherals on the APB1 bus according to the given mask. - * - * @param mask the mask for the peripherals to reset + * Resets peripherals on the APB1 bus */ void rcc_reset_apb1(enum RccApb1 mask); /** - * Enables peripherals on the APB2 bus according to the given mask. - * - * @param mask the mask for the peripherals to enable + * Enables peripherals on the APB2 bus */ void rcc_enable_apb2(enum RccApb2 mask); /** - * Disables peripherals on the APB2 bus according to the given mask. - * - * @param mask the mask for the peripherals to disable + * Disables peripherals on the APB2 bus */ void rcc_disable_apb2(enum RccApb2 mask); /** - * Resets peripherals on the APB2 bus according to the given mask. - * - * @param mask the mask for the peripherals to reset + * Resets peripherals on the APB2 bus */ void rcc_reset_apb2(enum RccApb2 mask); -- 2.45.2 From 2b689c4335750ae91217dd6f47a25f5fb5e2638d Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 31 Mar 2023 14:18:48 +0200 Subject: [PATCH 10/85] Cleanup repository --- .github/ISSUE_TEMPLATE/bug_report.md | 27 - .github/ISSUE_TEMPLATE/feature_request.md | 20 - target.h | 10642 -------------------- 3 files changed, 10689 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug_report.md delete mode 100644 .github/ISSUE_TEMPLATE/feature_request.md delete mode 100644 target.h diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md deleted file mode 100644 index ff4a22a..0000000 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ /dev/null @@ -1,27 +0,0 @@ ---- -name: Bug report -about: Create a report to help us improve -title: "[BUG]" -labels: bug -assignees: Steins7 - ---- - -**Describe the bug** -A clear and concise description of what the bug is. - -**To Reproduce** -Steps to reproduce the behavior: -1. Code -2. Specific Hardware used -3. OS and toolchain -4. Conditions for the bug to appear - -**Expected behavior** -A clear and concise description of what you expected to happen. - -**Screenshots** -If applicable, add screenshots to help explain your problem. - -**Additional context** -Add any other context about the problem here. diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md deleted file mode 100644 index 97b15b8..0000000 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ /dev/null @@ -1,20 +0,0 @@ ---- -name: Feature request -about: Suggest an idea for this project -title: "[FEATURE]" -labels: enhancement -assignees: Steins7 - ---- - -**Is your feature request related to a problem? Please describe.** -A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] - -**Describe the solution you'd like** -A clear and concise description of what you want to happen. - -**Describe alternatives you've considered** -A clear and concise description of any alternative solutions or features you've considered. - -**Additional context** -Add any other context or screenshots about the feature request here. diff --git a/target.h b/target.h deleted file mode 100644 index fe33bd0..0000000 --- a/target.h +++ /dev/null @@ -1,10642 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f103xb.h - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f103xb - * @{ - */ - -#ifndef __STM32F103xB_H -#define __STM32F103xB_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ -#define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "cmsis/core_cm3.h" -#include "system_stm32f1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ - __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ - uint32_t RESERVED[16]; - __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ -} ADC_Common_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t DR1; - __IO uint32_t DR2; - __IO uint32_t DR3; - __IO uint32_t DR4; - __IO uint32_t DR5; - __IO uint32_t DR6; - __IO uint32_t DR7; - __IO uint32_t DR8; - __IO uint32_t DR9; - __IO uint32_t DR10; - __IO uint32_t RTCCR; - __IO uint32_t CR; - __IO uint32_t CSR; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t OAR1; - __IO uint32_t OAR2; - __IO uint32_t DR; - __IO uint32_t SR1; - __IO uint32_t SR2; - __IO uint32_t CCR; - __IO uint32_t TRISE; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t CRH; - __IO uint32_t CRL; - __IO uint32_t PRLH; - __IO uint32_t PRLL; - __IO uint32_t DIVH; - __IO uint32_t DIVL; - __IO uint32_t CNTH; - __IO uint32_t CNTL; - __IO uint32_t ALRH; - __IO uint32_t ALRL; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SR; - __IO uint32_t DR; - __IO uint32_t CRCPR; - __IO uint32_t RXCRCR; - __IO uint32_t TXCRCR; - __IO uint32_t I2SCFGR; -} SPI_TypeDef; - -/** - * @brief TIM Timers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; - - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ - -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ -} USB_TypeDef; - - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ -#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ -#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) -#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) -#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) -#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) - -#define SDIO_BASE (PERIPH_BASE + 0x00018000U) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ -#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ -#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ -#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ - - - -#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ - -/* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ - - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define USB ((USB_TypeDef *)USB_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define SDIO ((SDIO_TypeDef *)SDIO_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) - - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) -#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) -#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS_Pos (0U) -#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ -#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS_Pos (1U) -#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ -#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF_Pos (2U) -#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ -#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF_Pos (3U) -#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ -#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ -#define PWR_CR_PVDE_Pos (4U) -#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ -#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS_Pos (5U) -#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ -#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ -#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ -#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ -#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ -#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ -#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ -#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ -#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ -#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ -#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ - -/* Legacy defines */ -#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 -#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 -#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 -#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 -#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 -#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 -#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 -#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 - -#define PWR_CR_DBP_Pos (8U) -#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ -#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF_Pos (0U) -#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ -#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ -#define PWR_CSR_SBF_Pos (1U) -#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ -#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ -#define PWR_CSR_PVDO_Pos (2U) -#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ -#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D_Pos (0U) -#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D_Pos (0U) -#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D_Pos (0U) -#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D_Pos (0U) -#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D_Pos (0U) -#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D_Pos (0U) -#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D_Pos (0U) -#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D_Pos (0U) -#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D_Pos (0U) -#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D_Pos (0U) -#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ - -#define RTC_BKP_NUMBER 10 - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL_Pos (0U) -#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ -#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ -#define BKP_RTCCR_CCO_Pos (7U) -#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ -#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE_Pos (8U) -#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ -#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS_Pos (9U) -#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ -#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE_Pos (0U) -#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ -#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ -#define BKP_CR_TPAL_Pos (1U) -#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ -#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE_Pos (0U) -#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ -#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ -#define BKP_CSR_CTI_Pos (1U) -#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ -#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE_Pos (2U) -#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ -#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF_Pos (8U) -#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ -#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ -#define BKP_CSR_TIF_Pos (9U) -#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ -#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION_Pos (0U) -#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY_Pos (1U) -#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM_Pos (3U) -#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ -#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL_Pos (8U) -#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ -#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON_Pos (16U) -#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ -#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY_Pos (17U) -#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ -#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP_Pos (18U) -#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ -#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON_Pos (19U) -#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ -#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ -#define RCC_CR_PLLON_Pos (24U) -#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ -#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ -#define RCC_CR_PLLRDY_Pos (25U) -#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ -#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ - - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW_Pos (0U) -#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ -#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ -#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ - -#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS_Pos (2U) -#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ -#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ -#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ - -#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE_Pos (4U) -#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ -#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ -#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ -#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ -#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ - -#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_Pos (8U) -#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ -#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ -#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ -#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ - -#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_Pos (11U) -#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ -#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ -#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ -#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ - -#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_Pos (14U) -#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ -#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ -#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ - -#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC_Pos (16U) -#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ -#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE_Pos (17U) -#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ -#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL_Pos (18U) -#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ -#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ - -#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ - -#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3_Pos (18U) -#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4_Pos (19U) -#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5_Pos (18U) -#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ -#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6_Pos (20U) -#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7_Pos (18U) -#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ -#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8_Pos (19U) -#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ -#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9_Pos (18U) -#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ -#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10_Pos (21U) -#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ -#define RCC_CFGR_PLLMULL11_Pos (18U) -#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ -#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12_Pos (19U) -#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ -#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13_Pos (18U) -#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ -#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14_Pos (20U) -#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ -#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15_Pos (18U) -#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ -#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16_Pos (19U) -#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ -#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ -#define RCC_CFGR_USBPRE_Pos (22U) -#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ -#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ - -/*!< MCO configuration */ -#define RCC_CFGR_MCO_Pos (24U) -#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ -#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ -#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ -#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ - -#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ - - /* Reference defines */ - #define RCC_CFGR_MCOSEL RCC_CFGR_MCO - #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 - #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 - #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 - #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK - #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK - #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI - #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE - #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF_Pos (0U) -#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF_Pos (1U) -#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF_Pos (2U) -#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF_Pos (3U) -#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF_Pos (4U) -#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ -#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF_Pos (7U) -#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ -#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE_Pos (8U) -#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ -#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE_Pos (9U) -#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ -#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE_Pos (10U) -#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ -#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE_Pos (11U) -#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ -#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE_Pos (12U) -#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ -#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC_Pos (16U) -#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ -#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC_Pos (17U) -#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ -#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC_Pos (18U) -#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ -#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC_Pos (19U) -#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ -#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC_Pos (20U) -#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ -#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC_Pos (23U) -#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ -#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ - - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST_Pos (0U) -#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST_Pos (2U) -#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ -#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST_Pos (3U) -#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ -#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST_Pos (4U) -#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ -#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST_Pos (5U) -#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ -#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST_Pos (9U) -#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ - -#define RCC_APB2RSTR_ADC2RST_Pos (10U) -#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ -#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ - -#define RCC_APB2RSTR_TIM1RST_Pos (11U) -#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST_Pos (12U) -#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST_Pos (14U) -#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ - - -#define RCC_APB2RSTR_IOPERST_Pos (6U) -#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ -#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ - - - - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST_Pos (0U) -#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST_Pos (1U) -#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST_Pos (11U) -#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST_Pos (17U) -#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST_Pos (21U) -#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ - -#define RCC_APB1RSTR_CAN1RST_Pos (25U) -#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ - -#define RCC_APB1RSTR_BKPRST_Pos (27U) -#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST_Pos (28U) -#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ - -#define RCC_APB1RSTR_TIM4RST_Pos (2U) -#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ -#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ -#define RCC_APB1RSTR_SPI2RST_Pos (14U) -#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ -#define RCC_APB1RSTR_USART3RST_Pos (18U) -#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ -#define RCC_APB1RSTR_I2C2RST_Pos (22U) -#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ - -#define RCC_APB1RSTR_USBRST_Pos (23U) -#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ - - - - - - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN_Pos (0U) -#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ -#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN_Pos (2U) -#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ -#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN_Pos (4U) -#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ -#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN_Pos (6U) -#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ -#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ - - - - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN_Pos (0U) -#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ -#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN_Pos (2U) -#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ -#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN_Pos (3U) -#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ -#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN_Pos (4U) -#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ -#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN_Pos (5U) -#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ -#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN_Pos (9U) -#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ -#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ - -#define RCC_APB2ENR_ADC2EN_Pos (10U) -#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ -#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ - -#define RCC_APB2ENR_TIM1EN_Pos (11U) -#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ -#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN_Pos (12U) -#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ -#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN_Pos (14U) -#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ -#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ - - -#define RCC_APB2ENR_IOPEEN_Pos (6U) -#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ -#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ - - - - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN_Pos (0U) -#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ -#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN_Pos (1U) -#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ -#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN_Pos (11U) -#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ -#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN_Pos (17U) -#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ -#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN_Pos (21U) -#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ -#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ - -#define RCC_APB1ENR_CAN1EN_Pos (25U) -#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ -#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ - -#define RCC_APB1ENR_BKPEN_Pos (27U) -#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ -#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN_Pos (28U) -#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ -#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ - -#define RCC_APB1ENR_TIM4EN_Pos (2U) -#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ -#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ -#define RCC_APB1ENR_SPI2EN_Pos (14U) -#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ -#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ -#define RCC_APB1ENR_USART3EN_Pos (18U) -#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ -#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ -#define RCC_APB1ENR_I2C2EN_Pos (22U) -#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ -#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ - -#define RCC_APB1ENR_USBEN_Pos (23U) -#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ -#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ - - - - - - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY_Pos (1U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP_Pos (2U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL_Pos (8U) -#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ -#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN_Pos (15U) -#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ -#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ -#define RCC_BDCR_BDRST_Pos (16U) -#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION_Pos (0U) -#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY_Pos (1U) -#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF_Pos (24U) -#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ -#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF_Pos (26U) -#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ -#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF_Pos (27U) -#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ -#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF_Pos (28U) -#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ -#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF_Pos (29U) -#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ -#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF_Pos (30U) -#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ -#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF_Pos (31U) -#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ -#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ - - - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE_Pos (0U) -#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0_Pos (0U) -#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_CRL_MODE1_Pos (4U) -#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ -#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ -#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ - -#define GPIO_CRL_MODE2_Pos (8U) -#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ -#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ -#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ - -#define GPIO_CRL_MODE3_Pos (12U) -#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ -#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ -#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ - -#define GPIO_CRL_MODE4_Pos (16U) -#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ -#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ -#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ - -#define GPIO_CRL_MODE5_Pos (20U) -#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ -#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ -#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ - -#define GPIO_CRL_MODE6_Pos (24U) -#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ -#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ -#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ - -#define GPIO_CRL_MODE7_Pos (28U) -#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ -#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ -#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ - -#define GPIO_CRL_CNF_Pos (2U) -#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0_Pos (2U) -#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ -#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ -#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ - -#define GPIO_CRL_CNF1_Pos (6U) -#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ -#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ -#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ - -#define GPIO_CRL_CNF2_Pos (10U) -#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ -#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ -#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ - -#define GPIO_CRL_CNF3_Pos (14U) -#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ -#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ -#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ - -#define GPIO_CRL_CNF4_Pos (18U) -#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ -#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ -#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ - -#define GPIO_CRL_CNF5_Pos (22U) -#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ -#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ -#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ - -#define GPIO_CRL_CNF6_Pos (26U) -#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ -#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ -#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ - -#define GPIO_CRL_CNF7_Pos (30U) -#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ -#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ -#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE_Pos (0U) -#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8_Pos (0U) -#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ -#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ -#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ - -#define GPIO_CRH_MODE9_Pos (4U) -#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ -#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ -#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ - -#define GPIO_CRH_MODE10_Pos (8U) -#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ -#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ -#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ - -#define GPIO_CRH_MODE11_Pos (12U) -#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ -#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ -#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ - -#define GPIO_CRH_MODE12_Pos (16U) -#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ -#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ -#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ - -#define GPIO_CRH_MODE13_Pos (20U) -#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ -#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ -#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ - -#define GPIO_CRH_MODE14_Pos (24U) -#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ -#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ -#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ - -#define GPIO_CRH_MODE15_Pos (28U) -#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ -#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ -#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ - -#define GPIO_CRH_CNF_Pos (2U) -#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8_Pos (2U) -#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ -#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ -#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ - -#define GPIO_CRH_CNF9_Pos (6U) -#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ -#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ -#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ - -#define GPIO_CRH_CNF10_Pos (10U) -#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ -#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ -#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ - -#define GPIO_CRH_CNF11_Pos (14U) -#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ -#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ -#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ - -#define GPIO_CRH_CNF12_Pos (18U) -#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ -#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ -#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ - -#define GPIO_CRH_CNF13_Pos (22U) -#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ -#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ -#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ - -#define GPIO_CRH_CNF14_Pos (26U) -#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ -#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ -#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ - -#define GPIO_CRH_CNF15_Pos (30U) -#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ -#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ -#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0_Pos (0U) -#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1_Pos (1U) -#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2_Pos (2U) -#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3_Pos (3U) -#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4_Pos (4U) -#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5_Pos (5U) -#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6_Pos (6U) -#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7_Pos (7U) -#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8_Pos (8U) -#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9_Pos (9U) -#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10_Pos (10U) -#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11_Pos (11U) -#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12_Pos (12U) -#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13_Pos (13U) -#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14_Pos (14U) -#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15_Pos (15U) -#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0_Pos (0U) -#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1_Pos (1U) -#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2_Pos (2U) -#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3_Pos (3U) -#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4_Pos (4U) -#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5_Pos (5U) -#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6_Pos (6U) -#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7_Pos (7U) -#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8_Pos (8U) -#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9_Pos (9U) -#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10_Pos (10U) -#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11_Pos (11U) -#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12_Pos (12U) -#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13_Pos (13U) -#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14_Pos (14U) -#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15_Pos (15U) -#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0_Pos (0U) -#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ -#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1_Pos (1U) -#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ -#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2_Pos (2U) -#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ -#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3_Pos (3U) -#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ -#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4_Pos (4U) -#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ -#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5_Pos (5U) -#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ -#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6_Pos (6U) -#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ -#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7_Pos (7U) -#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ -#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8_Pos (8U) -#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ -#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9_Pos (9U) -#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ -#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10_Pos (10U) -#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ -#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11_Pos (11U) -#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ -#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12_Pos (12U) -#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ -#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13_Pos (13U) -#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ -#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14_Pos (14U) -#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ -#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15_Pos (15U) -#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ -#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0_Pos (16U) -#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ -#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1_Pos (17U) -#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ -#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2_Pos (18U) -#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ -#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3_Pos (19U) -#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ -#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4_Pos (20U) -#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ -#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5_Pos (21U) -#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ -#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6_Pos (22U) -#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ -#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7_Pos (23U) -#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ -#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8_Pos (24U) -#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ -#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9_Pos (25U) -#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ -#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10_Pos (26U) -#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ -#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11_Pos (27U) -#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ -#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12_Pos (28U) -#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ -#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13_Pos (29U) -#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ -#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14_Pos (30U) -#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ -#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15_Pos (31U) -#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ -#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ -#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ -#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ -#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ -#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ -#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ -#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ -#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ -#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ -#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ -#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ -#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ -#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ -#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ -#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ -#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ -#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0_Pos (0U) -#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ -#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1_Pos (1U) -#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ -#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2_Pos (2U) -#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ -#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3_Pos (3U) -#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ -#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4_Pos (4U) -#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ -#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5_Pos (5U) -#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ -#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6_Pos (6U) -#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ -#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7_Pos (7U) -#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ -#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8_Pos (8U) -#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ -#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9_Pos (9U) -#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ -#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10_Pos (10U) -#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ -#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11_Pos (11U) -#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ -#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12_Pos (12U) -#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ -#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13_Pos (13U) -#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ -#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14_Pos (14U) -#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ -#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15_Pos (15U) -#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ -#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK_Pos (16U) -#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ -#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN_Pos (0U) -#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1_Pos (0U) -#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2_Pos (1U) -#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3_Pos (0U) -#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ -#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4_Pos (2U) -#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5_Pos (0U) -#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ -#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6_Pos (1U) -#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ -#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7_Pos (0U) -#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ -#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8_Pos (3U) -#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ -#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9_Pos (0U) -#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ -#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10_Pos (1U) -#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ -#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11_Pos (0U) -#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ -#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12_Pos (2U) -#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ -#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13_Pos (0U) -#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ -#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14_Pos (1U) -#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ -#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15_Pos (0U) -#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT_Pos (4U) -#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ -#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB_Pos (4U) -#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC_Pos (5U) -#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD_Pos (4U) -#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE_Pos (6U) -#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ - -#define AFIO_EVCR_EVOE_Pos (7U) -#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ -#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP_Pos (0U) -#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ -#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP_Pos (1U) -#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ -#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP_Pos (2U) -#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ -#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP_Pos (3U) -#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ -#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ -#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP_Pos (12U) -#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ -#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ -#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) -#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP_Pos (15U) -#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ -#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ -#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ - -#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) -#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ - - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0_Pos (0U) -#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1_Pos (4U) -#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2_Pos (8U) -#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3_Pos (12U) -#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) -#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) -#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) -#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) -#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4_Pos (0U) -#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5_Pos (4U) -#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6_Pos (8U) -#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7_Pos (12U) -#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) -#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) -#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) -#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) -#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8_Pos (0U) -#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9_Pos (4U) -#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10_Pos (8U) -#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11_Pos (12U) -#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) -#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) -#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) -#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) -#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12_Pos (0U) -#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13_Pos (4U) -#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14_Pos (8U) -#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15_Pos (12U) -#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) -#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) -#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) -#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) -#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ - -/****************** Bit definition for AFIO_MAPR2 register ******************/ - - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0_Pos (0U) -#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1_Pos (1U) -#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2_Pos (2U) -#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3_Pos (3U) -#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4_Pos (4U) -#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5_Pos (5U) -#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6_Pos (6U) -#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7_Pos (7U) -#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8_Pos (8U) -#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9_Pos (9U) -#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10_Pos (10U) -#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11_Pos (11U) -#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12_Pos (12U) -#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13_Pos (13U) -#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14_Pos (14U) -#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15_Pos (15U) -#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16_Pos (16U) -#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17_Pos (17U) -#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) -#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ - -/* References Defines */ -#define EXTI_IMR_IM0 EXTI_IMR_MR0 -#define EXTI_IMR_IM1 EXTI_IMR_MR1 -#define EXTI_IMR_IM2 EXTI_IMR_MR2 -#define EXTI_IMR_IM3 EXTI_IMR_MR3 -#define EXTI_IMR_IM4 EXTI_IMR_MR4 -#define EXTI_IMR_IM5 EXTI_IMR_MR5 -#define EXTI_IMR_IM6 EXTI_IMR_MR6 -#define EXTI_IMR_IM7 EXTI_IMR_MR7 -#define EXTI_IMR_IM8 EXTI_IMR_MR8 -#define EXTI_IMR_IM9 EXTI_IMR_MR9 -#define EXTI_IMR_IM10 EXTI_IMR_MR10 -#define EXTI_IMR_IM11 EXTI_IMR_MR11 -#define EXTI_IMR_IM12 EXTI_IMR_MR12 -#define EXTI_IMR_IM13 EXTI_IMR_MR13 -#define EXTI_IMR_IM14 EXTI_IMR_MR14 -#define EXTI_IMR_IM15 EXTI_IMR_MR15 -#define EXTI_IMR_IM16 EXTI_IMR_MR16 -#define EXTI_IMR_IM17 EXTI_IMR_MR17 -#define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0_Pos (0U) -#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1_Pos (1U) -#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2_Pos (2U) -#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3_Pos (3U) -#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4_Pos (4U) -#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5_Pos (5U) -#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6_Pos (6U) -#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7_Pos (7U) -#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8_Pos (8U) -#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9_Pos (9U) -#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10_Pos (10U) -#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11_Pos (11U) -#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12_Pos (12U) -#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13_Pos (13U) -#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14_Pos (14U) -#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15_Pos (15U) -#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16_Pos (16U) -#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17_Pos (17U) -#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) -#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ - -/* References Defines */ -#define EXTI_EMR_EM0 EXTI_EMR_MR0 -#define EXTI_EMR_EM1 EXTI_EMR_MR1 -#define EXTI_EMR_EM2 EXTI_EMR_MR2 -#define EXTI_EMR_EM3 EXTI_EMR_MR3 -#define EXTI_EMR_EM4 EXTI_EMR_MR4 -#define EXTI_EMR_EM5 EXTI_EMR_MR5 -#define EXTI_EMR_EM6 EXTI_EMR_MR6 -#define EXTI_EMR_EM7 EXTI_EMR_MR7 -#define EXTI_EMR_EM8 EXTI_EMR_MR8 -#define EXTI_EMR_EM9 EXTI_EMR_MR9 -#define EXTI_EMR_EM10 EXTI_EMR_MR10 -#define EXTI_EMR_EM11 EXTI_EMR_MR11 -#define EXTI_EMR_EM12 EXTI_EMR_MR12 -#define EXTI_EMR_EM13 EXTI_EMR_MR13 -#define EXTI_EMR_EM14 EXTI_EMR_MR14 -#define EXTI_EMR_EM15 EXTI_EMR_MR15 -#define EXTI_EMR_EM16 EXTI_EMR_MR16 -#define EXTI_EMR_EM17 EXTI_EMR_MR17 -#define EXTI_EMR_EM18 EXTI_EMR_MR18 - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0_Pos (0U) -#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1_Pos (1U) -#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2_Pos (2U) -#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3_Pos (3U) -#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4_Pos (4U) -#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5_Pos (5U) -#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6_Pos (6U) -#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7_Pos (7U) -#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8_Pos (8U) -#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9_Pos (9U) -#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10_Pos (10U) -#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11_Pos (11U) -#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12_Pos (12U) -#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13_Pos (13U) -#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14_Pos (14U) -#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15_Pos (15U) -#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16_Pos (16U) -#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17_Pos (17U) -#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) -#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ - -/* References Defines */ -#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 -#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 -#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 -#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 -#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 -#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 -#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 -#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 -#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 -#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 -#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 -#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 -#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 -#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 -#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 -#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 -#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 -#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 -#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0_Pos (0U) -#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1_Pos (1U) -#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2_Pos (2U) -#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3_Pos (3U) -#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4_Pos (4U) -#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5_Pos (5U) -#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6_Pos (6U) -#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7_Pos (7U) -#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8_Pos (8U) -#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9_Pos (9U) -#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10_Pos (10U) -#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11_Pos (11U) -#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12_Pos (12U) -#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13_Pos (13U) -#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14_Pos (14U) -#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15_Pos (15U) -#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16_Pos (16U) -#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17_Pos (17U) -#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) -#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ - -/* References Defines */ -#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 -#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 -#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 -#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 -#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 -#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 -#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 -#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 -#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 -#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 -#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 -#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 -#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 -#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 -#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 -#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 -#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 -#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 -#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0_Pos (0U) -#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ -#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1_Pos (1U) -#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ -#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2_Pos (2U) -#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ -#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3_Pos (3U) -#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ -#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4_Pos (4U) -#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ -#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5_Pos (5U) -#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ -#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6_Pos (6U) -#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ -#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7_Pos (7U) -#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ -#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8_Pos (8U) -#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ -#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9_Pos (9U) -#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ -#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10_Pos (10U) -#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ -#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11_Pos (11U) -#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ -#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12_Pos (12U) -#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ -#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13_Pos (13U) -#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ -#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14_Pos (14U) -#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ -#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15_Pos (15U) -#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ -#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16_Pos (16U) -#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ -#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17_Pos (17U) -#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ -#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) -#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ -#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ - -/* References Defines */ -#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 -#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 -#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 -#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 -#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 -#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 -#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 -#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 -#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 -#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 -#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 -#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 -#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 -#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 -#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 -#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 -#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 -#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 -#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0_Pos (0U) -#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ -#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1_Pos (1U) -#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ -#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2_Pos (2U) -#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ -#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3_Pos (3U) -#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ -#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4_Pos (4U) -#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ -#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5_Pos (5U) -#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ -#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6_Pos (6U) -#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ -#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7_Pos (7U) -#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ -#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8_Pos (8U) -#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ -#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9_Pos (9U) -#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ -#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10_Pos (10U) -#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ -#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11_Pos (11U) -#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ -#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12_Pos (12U) -#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ -#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13_Pos (13U) -#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ -#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14_Pos (14U) -#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ -#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15_Pos (15U) -#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ -#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16_Pos (16U) -#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ -#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17_Pos (17U) -#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ -#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) -#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ -#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ - -/* References Defines */ -#define EXTI_PR_PIF0 EXTI_PR_PR0 -#define EXTI_PR_PIF1 EXTI_PR_PR1 -#define EXTI_PR_PIF2 EXTI_PR_PR2 -#define EXTI_PR_PIF3 EXTI_PR_PR3 -#define EXTI_PR_PIF4 EXTI_PR_PR4 -#define EXTI_PR_PIF5 EXTI_PR_PR5 -#define EXTI_PR_PIF6 EXTI_PR_PR6 -#define EXTI_PR_PIF7 EXTI_PR_PR7 -#define EXTI_PR_PIF8 EXTI_PR_PR8 -#define EXTI_PR_PIF9 EXTI_PR_PR9 -#define EXTI_PR_PIF10 EXTI_PR_PR10 -#define EXTI_PR_PIF11 EXTI_PR_PR11 -#define EXTI_PR_PIF12 EXTI_PR_PR12 -#define EXTI_PR_PIF13 EXTI_PR_PR13 -#define EXTI_PR_PIF14 EXTI_PR_PR14 -#define EXTI_PR_PIF15 EXTI_PR_PR15 -#define EXTI_PR_PIF16 EXTI_PR_PR16 -#define EXTI_PR_PIF17 EXTI_PR_PR17 -#define EXTI_PR_PIF18 EXTI_PR_PR18 - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1_Pos (0U) -#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ -#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1_Pos (1U) -#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ -#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1_Pos (2U) -#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ -#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1_Pos (3U) -#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ -#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2_Pos (4U) -#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ -#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2_Pos (5U) -#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ -#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2_Pos (6U) -#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ -#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2_Pos (7U) -#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ -#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3_Pos (8U) -#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ -#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3_Pos (9U) -#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ -#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3_Pos (10U) -#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ -#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3_Pos (11U) -#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ -#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4_Pos (12U) -#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ -#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4_Pos (13U) -#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ -#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4_Pos (14U) -#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ -#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4_Pos (15U) -#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ -#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5_Pos (16U) -#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ -#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5_Pos (17U) -#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ -#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5_Pos (18U) -#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ -#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5_Pos (19U) -#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ -#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6_Pos (20U) -#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ -#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6_Pos (21U) -#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ -#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6_Pos (22U) -#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ -#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6_Pos (23U) -#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ -#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7_Pos (24U) -#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ -#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7_Pos (25U) -#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ -#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7_Pos (26U) -#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ -#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7_Pos (27U) -#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ -#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1_Pos (0U) -#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ -#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1_Pos (1U) -#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ -#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1_Pos (2U) -#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ -#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1_Pos (3U) -#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ -#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2_Pos (4U) -#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ -#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2_Pos (5U) -#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ -#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2_Pos (6U) -#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ -#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2_Pos (7U) -#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ -#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3_Pos (8U) -#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ -#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3_Pos (9U) -#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ -#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3_Pos (10U) -#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ -#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3_Pos (11U) -#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ -#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) -#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) -#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) -#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) -#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5_Pos (16U) -#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ -#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5_Pos (17U) -#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ -#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5_Pos (18U) -#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ -#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5_Pos (19U) -#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ -#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6_Pos (20U) -#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ -#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6_Pos (21U) -#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ -#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6_Pos (22U) -#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ -#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6_Pos (23U) -#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ -#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7_Pos (24U) -#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ -#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7_Pos (25U) -#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ -#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7_Pos (26U) -#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ -#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7_Pos (27U) -#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ -#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR register *******************/ -#define DMA_CCR_EN_Pos (0U) -#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ -#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_TCIE_Pos (1U) -#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ -#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (2U) -#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ -#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE_Pos (3U) -#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ -#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR_Pos (4U) -#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ -#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ -#define DMA_CCR_CIRC_Pos (5U) -#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ -#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ -#define DMA_CCR_PINC_Pos (6U) -#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ -#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ -#define DMA_CCR_MINC_Pos (7U) -#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ -#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ - -#define DMA_CCR_PSIZE_Pos (8U) -#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ -#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ -#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ - -#define DMA_CCR_MSIZE_Pos (10U) -#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ -#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ -#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ - -#define DMA_CCR_PL_Pos (12U) -#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ -#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ -#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ - -#define DMA_CCR_MEM2MEM_Pos (14U) -#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ -#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CNDTR register ******************/ -#define DMA_CNDTR_NDT_Pos (0U) -#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ -#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR register *******************/ -#define DMA_CPAR_PA_Pos (0U) -#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR register *******************/ -#define DMA_CMAR_MA_Pos (0U) -#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) - */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) -#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ -#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) -#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ -#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) -#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ -#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) -#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ -#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) -#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ -#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ - -/* Legacy defines */ -#define ADC_SR_EOC (ADC_SR_EOS) -#define ADC_SR_JEOC (ADC_SR_JEOS) - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) -#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ -#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ -#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ -#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ -#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ -#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ - -#define ADC_CR1_EOSIE_Pos (5U) -#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ -#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) -#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ -#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) -#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ -#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) -#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ -#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) -#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ -#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) -#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ -#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) -#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ -#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) -#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ -#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ - -#define ADC_CR1_DISCNUM_Pos (13U) -#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ -#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ -#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ -#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ - -#define ADC_CR1_DUALMOD_Pos (16U) -#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ -#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ -#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ -#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ -#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ -#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ - -#define ADC_CR1_JAWDEN_Pos (22U) -#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ -#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) -#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ -#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ - -/* Legacy defines */ -#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) -#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) -#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ -#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) -#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ -#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) -#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ -#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) -#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ -#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) -#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ -#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) -#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ -#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CR2_JEXTSEL_Pos (12U) -#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ -#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ -#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ -#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ - -#define ADC_CR2_JEXTTRIG_Pos (15U) -#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ - -#define ADC_CR2_EXTSEL_Pos (17U) -#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ -#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ -#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ -#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ - -#define ADC_CR2_EXTTRIG_Pos (20U) -#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ -#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) -#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ -#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) -#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ -#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) -#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ -#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) -#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP11_Pos (3U) -#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP12_Pos (6U) -#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP13_Pos (9U) -#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP14_Pos (12U) -#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP15_Pos (15U) -#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP16_Pos (18U) -#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP17_Pos (21U) -#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) -#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP1_Pos (3U) -#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP2_Pos (6U) -#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP3_Pos (9U) -#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP4_Pos (12U) -#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP5_Pos (15U) -#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP6_Pos (18U) -#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP7_Pos (21U) -#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP8_Pos (24U) -#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP9_Pos (27U) -#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) -#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) -#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) -#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) -#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) -#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ -#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) -#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ -#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) -#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ -#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ - -#define ADC_SQR1_SQ14_Pos (5U) -#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ -#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ -#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ - -#define ADC_SQR1_SQ15_Pos (10U) -#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ -#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ -#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ - -#define ADC_SQR1_SQ16_Pos (15U) -#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ -#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ -#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ - -#define ADC_SQR1_L_Pos (20U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ8_Pos (5U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ - -#define ADC_SQR2_SQ9_Pos (10U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ - -#define ADC_SQR2_SQ10_Pos (15U) -#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ -#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ -#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ - -#define ADC_SQR2_SQ11_Pos (20U) -#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ -#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ -#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ - -#define ADC_SQR2_SQ12_Pos (25U) -#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ -#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ -#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) -#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ2_Pos (5U) -#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ -#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ -#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ - -#define ADC_SQR3_SQ3_Pos (10U) -#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ -#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ - -#define ADC_SQR3_SQ4_Pos (15U) -#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ -#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ -#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ - -#define ADC_SQR3_SQ5_Pos (20U) -#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ -#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ -#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ - -#define ADC_SQR3_SQ6_Pos (25U) -#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ -#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ -#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ - -#define ADC_JSQR_JSQ2_Pos (5U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ - -#define ADC_JSQR_JSQ3_Pos (10U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ - -#define ADC_JSQR_JSQ4_Pos (15U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JL_Pos (20U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) -#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) -#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ -#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ - - -/*****************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/*****************************************************************************/ -/******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) -#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ -#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! Date: Fri, 31 Mar 2023 23:22:11 +0200 Subject: [PATCH 11/85] Implement AHB peripherals control functions --- drivers/rcc.c | 11 +++++++++++ drivers/rcc.h | 24 ++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/rcc.c b/drivers/rcc.c index 4af833b..7f0e4f8 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -14,6 +14,7 @@ //--local definitions----------------------------------------------------------- +#define AHB_MASK 0x00000557 #define APB1_MASK 0x3afec9ff #define APB2_MASK 0x0038fffd @@ -56,6 +57,16 @@ void rcc_configure(enum RccPreset preset) regs->APB2ENR = apb2_enr; } +void rcc_enable_ahb(enum RccAhb mask) +{ + regs->AHBENR.word |= mask & AHB_MASK; +} + +void rcc_disable_ahb(enum RccAhb mask) +{ + regs->AHBENR.word &= !(mask & AHB_MASK); +} + void rcc_enable_apb1(enum RccApb1 mask) { regs->APB1ENR.word |= mask & APB1_MASK; diff --git a/drivers/rcc.h b/drivers/rcc.h index b3ccc6e..74d651a 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -23,6 +23,20 @@ enum RccPreset { RCC_PRESET_SPEED, //highest clocks, uses 8MHz HSE if available }; +/** + * Available peripherals on the AHB bus. Note that some of these peripherals + * may not be availables on all chips + */ +enum RccAhb { + RCC_AHB_DMA1 = (0x1 << 0), + RCC_AHB_DMA2 = (0x1 << 1), + RCC_AHB_SRAM = (0x1 << 2), + RCC_AHB_FLITF = (0x1 << 4), + RCC_AHB_CRC = (0x1 << 6), + RCC_AHB_FSMC = (0x1 << 8), + RCC_AHB_SDIO = (0x1 << 10), +}; + /** * Available peripherals on the APB1 bus. Note that some of these peripherals * may not be availables on all chips @@ -89,6 +103,16 @@ enum RccApb2 { */ void rcc_configure(enum RccPreset preset); +/** + * Enables peripherals on the AHB bus + */ +void rcc_enable_ahb(enum RccAhb mask); + +/** + * Disables peripherals on the AHB bus + */ +void rcc_disable_ahb(enum RccAhb mask); + /** * Enables peripherals on the APB1 bus */ -- 2.45.2 From c10ef4d2f10bdc823b677c29d924e09e19eb95af Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 31 Mar 2023 23:32:43 +0200 Subject: [PATCH 12/85] Merge peripheral control functions The functions are very simple and their number complicates the API more than anything, so we better merge them --- drivers/rcc.c | 44 +++++++++++++------------------------------- drivers/rcc.h | 48 +++++++++++++++++------------------------------- 2 files changed, 30 insertions(+), 62 deletions(-) diff --git a/drivers/rcc.c b/drivers/rcc.c index 7f0e4f8..65c7fcc 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -57,44 +57,26 @@ void rcc_configure(enum RccPreset preset) regs->APB2ENR = apb2_enr; } -void rcc_enable_ahb(enum RccAhb mask) +void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask, + enum RccApb2 apb2_mask) { - regs->AHBENR.word |= mask & AHB_MASK; + regs->AHBENR.word |= ahb_mask & AHB_MASK; + regs->APB1ENR.word |= apb1_mask & APB1_MASK; + regs->APB2ENR.word |= apb2_mask & APB2_MASK; } -void rcc_disable_ahb(enum RccAhb mask) +void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask, + enum RccApb2 apb2_mask) { - regs->AHBENR.word &= !(mask & AHB_MASK); + regs->AHBENR.word &= !(ahb_mask & AHB_MASK); + regs->APB1ENR.word &= !(apb1_mask & APB1_MASK); + regs->APB2ENR.word &= !(apb2_mask & APB2_MASK); } -void rcc_enable_apb1(enum RccApb1 mask) +void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask) { - regs->APB1ENR.word |= mask & APB1_MASK; -} - -void rcc_disable_apb1(enum RccApb1 mask) -{ - regs->APB1ENR.word &= !(mask & APB1_MASK); -} - -void rcc_reset_apb1(enum RccApb1 mask) -{ - regs->APB1RSTR.word &= !(mask & APB1_MASK); -} - -void rcc_enable_apb2(enum RccApb2 mask) -{ - regs->APB2ENR.word |= mask & APB2_MASK; -} - -void rcc_disable_apb2(enum RccApb2 mask) -{ - regs->APB2ENR.word &= !(mask & APB2_MASK); -} - -void rcc_reset_apb2(enum RccApb2 mask) -{ - regs->APB2RSTR.word &= !(mask & APB2_MASK); + regs->APB1RSTR.word &= !(apb1_mask & APB1_MASK); + regs->APB2RSTR.word &= !(apb2_mask & APB2_MASK); } diff --git a/drivers/rcc.h b/drivers/rcc.h index 74d651a..9869e06 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -28,6 +28,7 @@ enum RccPreset { * may not be availables on all chips */ enum RccAhb { + RCC_AHB_NONE = 0, RCC_AHB_DMA1 = (0x1 << 0), RCC_AHB_DMA2 = (0x1 << 1), RCC_AHB_SRAM = (0x1 << 2), @@ -42,6 +43,7 @@ enum RccAhb { * may not be availables on all chips */ enum RccApb1 { + RCC_APB1_NONE = 0, RCC_APB1_TIM2 = (0x1 << 0), RCC_APB1_TIM3 = (0x1 << 1), RCC_APB1_TIM4 = (0x1 << 2), @@ -72,6 +74,7 @@ enum RccApb1 { * may not be available on all chips */ enum RccApb2 { + RCC_APB2_NONE = 0, RCC_APB2_AFOI = (0x1 << 0), RCC_APB2_IOPA = (0x1 << 2), RCC_APB2_IOPB = (0x1 << 3), @@ -104,44 +107,27 @@ enum RccApb2 { void rcc_configure(enum RccPreset preset); /** - * Enables peripherals on the AHB bus + * Enables peripherals on the different buses. The enums values can used as + * masks to enable multiple peripherals at the same time. Invalid values will be + * ignored. */ -void rcc_enable_ahb(enum RccAhb mask); +void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask, + enum RccApb2 apb2_mask); /** - * Disables peripherals on the AHB bus + * Disables peripherals on the different buses. The enums values can used as + * masks to disable multiple peripherals at the same time. Invalid values will + * be ignored. */ -void rcc_disable_ahb(enum RccAhb mask); +void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask, + enum RccApb2 apb2_mask); /** - * Enables peripherals on the APB1 bus + * Resets peripherals on the different buses. The enums values can used as + * masks to reset multiple peripherals at the same time. Invalid values will + * be ignored. */ -void rcc_enable_apb1(enum RccApb1 mask); - -/** - * Disables peripherals on the APB1 bus - */ -void rcc_disable_apb1(enum RccApb1 mask); - -/** - * Resets peripherals on the APB1 bus - */ -void rcc_reset_apb1(enum RccApb1 mask); - -/** - * Enables peripherals on the APB2 bus - */ -void rcc_enable_apb2(enum RccApb2 mask); - -/** - * Disables peripherals on the APB2 bus - */ -void rcc_disable_apb2(enum RccApb2 mask); - -/** - * Resets peripherals on the APB2 bus - */ -void rcc_reset_apb2(enum RccApb2 mask); +void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask); #endif //_RCC_H_ -- 2.45.2 From 8ff2cabeab8d49cd959d8bda6ed38bd106a68591 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Thu, 27 Apr 2023 21:03:25 +0200 Subject: [PATCH 13/85] Add cortex_m3 doc --- doc/cortex_m3.pdf | Bin 0 -> 2098835 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 doc/cortex_m3.pdf diff --git a/doc/cortex_m3.pdf b/doc/cortex_m3.pdf new file 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z@1UOUI@72lSG7yqyf5!1YW8_rs4cy?S!eAEUghYqu-M|Tlj+pyH>Zn8`VYYr-R?J2Swnx0bjPJfh3Caj z&A}ZX3amOX)iJsc7vtvaupx5ii|6I8Mp)$xH(}18c5rQ=vgcy&D}P0z*S~ujVd#KFd5n9! zmok<4(&6%b6qr3nOq}RQmzTEu;PTuu4}7TOc;SccsWjm)NHTh{EU296Q+@JYHbmyD zPGry4nNcePu%`9PV_=DS!IJ9&i*MI=j(PW z!KYb!OB$U)eM;8!u58MCsjMqgsDz<=-s1nC5BJ-zKm6_QKmYp4ci;W-FaP+*Z=Z^K zc*>`L`QxAe>C=Dz?&r^b`sSz4zy0y2Z-4&c!(V^6yejT%*_(g*@yl<2{N~H=zf(;7 z(^o(L^@k5Xef#+@AAb4p*^fW!B=FgfU;QKv?U&F0`u%_W@z4MH%RfGKeE;vc|Ms{4 p`T73);`{GE`LEx8`1QB{{`KcyKH-b!Px;d)fB3^c|Lebe^1oL|85sZo literal 0 HcmV?d00001 -- 2.45.2 From 691b360eb1b885e0d0631a916fcf6b9c9ffc6407 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Thu, 27 Apr 2023 21:06:09 +0200 Subject: [PATCH 14/85] Create nvic's register map --- drivers/nvic_regs.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 drivers/nvic_regs.h diff --git a/drivers/nvic_regs.h b/drivers/nvic_regs.h new file mode 100644 index 0000000..7d9d02f --- /dev/null +++ b/drivers/nvic_regs.h @@ -0,0 +1,39 @@ +/** @file nvic_regs.h + * Module defining the Nested Vector Interrupt Controller (NVIC) registers. + * + * Mainly made to be used by the nvic module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _NVIC_REGS_H_ +#define _NVIC_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define NVIC1_BASE_ADDRESS 0xE000E100 +#define NVIC2_BASE_ADDRESS 0xE000EF00 + +struct __attribute__((packed)) NVIC1 { + uint32_t ISERX[3]; + uint32_t ICERX[3]; + uint32_t ISPRX[3]; + uint32_t ICPRX[3]; + uint32_t IABRX[3]; + uint32_t IPRX[20]; +}; + +struct __attribute__((packed)) NVIC2 { + uint32_t INTID; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_NVIC_REGS_H_ + -- 2.45.2 From 661f4a0ae53637baa30933cf32c1be4fcbabd9da Mon Sep 17 00:00:00 2001 From: Steins7 Date: Thu, 27 Apr 2023 21:12:05 +0200 Subject: [PATCH 15/85] Implement nvic's control functions --- drivers/nvic.c | 87 ++++++++++++++++++++++++++++++++++ drivers/nvic.h | 125 +++++++++++++++++++++++++++++++++++++++++++++++++ startup.s | 113 ++++++++++++++++++++++++++++++++------------ 3 files changed, 294 insertions(+), 31 deletions(-) create mode 100644 drivers/nvic.c create mode 100644 drivers/nvic.h diff --git a/drivers/nvic.c b/drivers/nvic.c new file mode 100644 index 0000000..b4849e4 --- /dev/null +++ b/drivers/nvic.c @@ -0,0 +1,87 @@ +/** @file nvic.c + * Module handling the Nested Vector Interrupt Controller (NVIC) + * + * The module provides functions to configure the different interrupts and + * their priority suiing the NVIC's interface + */ + +//--includes-------------------------------------------------------------------- + +#include "nvic.h" +#include "nvic_regs.h" + + +//--local definitions----------------------------------------------------------- + +/** + * NVIC's register are only accessible by 32 bits words, and data is stored + * accors 3 consecutive registers. This macro sets the right bit from the + * right register based on the IRQ number + */ +#define set_bit(reg, irq) \ + do { \ + uint8_t n = irq / 32; \ + uint8_t r = irq - n * 32; \ + regs->reg[n] |= (0x1 << r); \ + } while (0) + +/** + * NVIC's register are only accessible by 32 bits words, and data is stored + * accors 3 consecutive registers. This macro fetches the right bit from the + * right register based on the IRQ number + */ +#define get_bit(reg, irq, res) \ + do { \ + uint8_t n = irq / 32; \ + uint8_t r = irq - n * 32; \ + res = 0 != (regs->reg[n] | (0x1 << r)); \ + } while (0) + + +//--local variables------------------------------------------------------------- + +static volatile struct NVIC1* regs = (struct NVIC1*)NVIC1_BASE_ADDRESS; + + +//--public functions------------------------------------------------------------ + +void nvic_enable(enum NvicIrq irq) +{ + set_bit(ISERX, irq); +} + +void nvic_disable(enum NvicIrq irq) +{ + set_bit(ICERX, irq); +} + +void nvic_clear_pending(enum NvicIrq irq) +{ + set_bit(ICPRX, irq); +} + +void nvic_set_priority(enum NvicIrq irq, uint8_t priority) +{ + uint8_t n = irq / 4; + uint8_t r = (irq - n * 4); //get the division's reminder + r *= 8; //mul by 8 since each 'slot' is 8 bits + r += 4; //add 4 since we only write to the upper 4 bits + regs->IPRX[n] &= ~(0x0F << r); + regs->IPRX[n] |= (priority & 0x0F) << r; +} + +void nvic_set_pending(enum NvicIrq irq) +{ + set_bit(ISPRX, irq); +} + +bool nvic_is_pending(enum NvicIrq irq) +{ + bool res = false; + get_bit(ISPRX, irq, res); + return res; +} + + +//--local functions------------------------------------------------------------- + diff --git a/drivers/nvic.h b/drivers/nvic.h new file mode 100644 index 0000000..38386b0 --- /dev/null +++ b/drivers/nvic.h @@ -0,0 +1,125 @@ +/** @file nvic.h + * Module handling the Nested Vector Interrupt Controller (NVIC) + * + * The module provides functions to configure the different interrupts and + * their priority suiing the NVIC's interface + */ + +#ifndef _NVIC_H_ +#define _NVIC_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" +#include "stdbool.h" + + +//--type definitions------------------------------------------------------------ + +/** + * Available System IRQs. This does not include CPU's IRQs + */ +enum NvicIrq { + NVIC_IRQ_WWDG = 0, + NVIC_IRQ_PVD, + NVIC_IRQ_TAMPER, + NVIC_IRQ_RTC, + NVIC_IRQ_FLASH, + NVIC_IRQ_RCC, + NVIC_IRQ_EXTI0, + NVIC_IRQ_EXTI1, + NVIC_IRQ_EXTI2, + NVIC_IRQ_EXTI3, + NVIC_IRQ_EXTI4, + NVIC_IRQ_DMA1_CHANNEL1, + NVIC_IRQ_DMA1_CHANNEL2, + NVIC_IRQ_DMA1_CHANNEL3, + NVIC_IRQ_DMA1_CHANNEL4, + NVIC_IRQ_DMA1_CHANNEL5, + NVIC_IRQ_DMA1_CHANNEL6, + NVIC_IRQ_DMA1_CHANNEL7, + NVIC_IRQ_ADC1_2, + NVIC_IRQ_HP_CAN_TX, + NVIC_IRQ_LP_CAN_RX0, + NVIC_IRQ_CAN_RX1, + NVIC_IRQ_CAN_SCE, + NVIC_IRQ_EXTI9_5, + NVIC_IRQ_TIM1_BRK, + NVIC_IRQ_TIM1_UP, + NVIC_IRQ_TIM1_TRG_COM, + NVIC_IRQ_TIM1_CC, + NVIC_IRQ_TIM2, + NVIC_IRQ_TIM3, + NVIC_IRQ_TIM4, + NVIC_IRQ_I2C1_EVENT, + NVIC_IRQ_I2C1_ERROR, + NVIC_IRQ_I2C2_EVENT, + NVIC_IRQ_I2C2_ERROR, + NVIC_IRQ_SPI1, + NVIC_IRQ_SPI2, + NVIC_IRQ_USART1, + NVIC_IRQ_USART2, + NVIC_IRQ_USART3, + NVIC_IRQ_EXTI15_10, + NVIC_IRQ_RTC_ALARM, + NVIC_IRQ_USB_WAKEUP, + NVIC_IRQ_TIM8_BRK, + NVIC_IRQ_TIM8_UP, + NVIC_IRQ_TIM8_TRG_COM, + NVIC_IRQ_TIM8_CC, + NVIC_IRQ_ADC3, + NVIC_IRQ_FSMC, + NVIC_IRQ_SDIO, + NVIC_IRQ_TIM5, + NVIC_IRQ_SPI3, + NVIC_IRQ_UART4, + NVIC_IRQ_UART5, + NVIC_IRQ_TIM6, + NVIC_IRQ_TIM7, + NVIC_IRQ_DMA2_CHANNEL1, + NVIC_IRQ_DMA2_CHANNEL2, + NVIC_IRQ_DMA2_CHANNEL3, + NVIC_IRQ_DMA2_CHANNEL4_5, +}; + + +//--functions------------------------------------------------------------------- + +/** + * Enables the selected IRQ + */ +void nvic_enable(enum NvicIrq irq); + +/** + * Disables the selected IRQ + */ +void nvic_disable(enum NvicIrq irq); + +/** + * Clears the pending state of an IRQ. Should be called when reaching an IRQ + * handler so that the IRQ isn't triggered again when exiting the handler + */ +void nvic_clear_pending(enum NvicIrq irq); + +/** + * Sets the priority for the selected IRQ. The lower the priority value, the + * higher the effective priority. Valid priority values range from 0 to 15. Any + * higher value will be ignored. When multiple IRQs with the same priority are + * triggered, they will be serviced from the lowest ID to the highest + */ +void nvic_set_priority(enum NvicIrq irq, uint8_t priority); + +/** + * Sets the selected IRQ's pending state. If the IRQ is active, it will be + * triggered + */ +void nvic_set_pending(enum NvicIrq irq); + +/** + * Returns wether the selected IRQ is currently pending or not + */ +bool nvic_is_pending(enum NvicIrq irq); + + +#endif //_RCC_H_ + diff --git a/startup.s b/startup.s index 3d4080e..3a3b5a1 100644 --- a/startup.s +++ b/startup.s @@ -99,13 +99,13 @@ vector_table: .word hdr_exti2 .word hdr_exti3 .word hdr_exti4 - .word hdr_dma_channel1 - .word hdr_dma_channel2 - .word hdr_dma_channel3 - .word hdr_dma_channel4 - .word hdr_dma_channel5 - .word hdr_dma_channel6 - .word hdr_dma_channel7 + .word hdr_dma1_channel1 + .word hdr_dma1_channel2 + .word hdr_dma1_channel3 + .word hdr_dma1_channel4 + .word hdr_dma1_channel5 + .word hdr_dma1_channel6 + .word hdr_dma1_channel7 .word hdr_adc1_2 .word hdr_hp_can_tx .word hdr_lp_can_rx0 @@ -131,23 +131,23 @@ vector_table: .word hdr_exti15_10 .word hdr_rtc_alarm .word hdr_usb_wakeup - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 + .word hdr_tim8_brk + .word hdr_tim8_up + .word hdr_tim8_trg_com + .word hdr_tim8_cc + .word hdr_adc3 + .word hdr_fsmc + .word hdr_sdio + .word hdr_tim5 + .word hdr_spi3 + .word hdr_uart4 + .word hdr_uart5 + .word hdr_tim6 + .word hdr_tim7 + .word hdr_dma2_channel1 + .word hdr_dma2_channel2 + .word hdr_dma2_channel3 + .word hdr_dma2_channel4_5 //--Weak definitions------------------------------------------------------------ @@ -211,25 +211,25 @@ vector_table: .weak hdr_exti4 .thumb_set hdr_exti4, hdr_default - .weak hdr_dma_channel1 + .weak hdr_dma1_channel1 .thumb_set hdr_dma_channel1, hdr_default - .weak hdr_dma_channel2 + .weak hdr_dma1_channel2 .thumb_set hdr_dma_channel2, hdr_default - .weak hdr_dma_channel3 + .weak hdr_dma1_channel3 .thumb_set hdr_dma_channel3, hdr_default - .weak hdr_dma_channel4 + .weak hdr_dma1_channel4 .thumb_set hdr_dma_channel4, hdr_default - .weak hdr_dma_channel5 + .weak hdr_dma1_channel5 .thumb_set hdr_dma_channel5, hdr_default - .weak hdr_dma_channel6 + .weak hdr_dma1_channel6 .thumb_set hdr_dma_channel6, hdr_default - .weak hdr_dma_channel7 + .weak hdr_dma1_channel7 .thumb_set hdr_dma_channel7, hdr_default .weak hdr_adc1_2 @@ -307,3 +307,54 @@ vector_table: .weak hdr_usb_wakeup .thumb_set hdr_usb_wakeup, hdr_default + .weak hdr_tim8_brk + .thumb_set hdr_tim8_brk, hdr_default + + .weak hdr_tim8_up + .thumb_set hdr_tim8_up, hdr_default + + .weak hdr_tim8_trg_com + .thumb_set hdr_tim8_trg_com, hdr_default + + .weak hdr_tim8_cc + .thumb_set hdr_tim8_cc, hdr_default + + .weak hdr_adc3 + .thumb_set hdr_adc3, hdr_default + + .weak hdr_fsmc + .thumb_set hdr_fsmc, hdr_default + + .weak hdr_sdio + .thumb_set hdr_sdio, hdr_default + + .weak hdr_tim5 + .thumb_set hdr_tim5, hdr_default + + .weak hdr_spi3 + .thumb_set hdr_spi3, hdr_default + + .weak hdr_uart4 + .thumb_set hdr_uart4, hdr_default + + .weak hdr_uart5 + .thumb_set hdr_uart5, hdr_default + + .weak hdr_tim6 + .thumb_set hdr_tim6, hdr_default + + .weak hdr_tim7 + .thumb_set hdr_tim7, hdr_default + + .weak hdr_dma2_channel1 + .thumb_set hdr_dma_channel1, hdr_default + + .weak hdr_dma2_channel2 + .thumb_set hdr_dma_channel2, hdr_default + + .weak hdr_dma2_channel3 + .thumb_set hdr_dma_channel3, hdr_default + + .weak hdr_dma2_channel4_5 + .thumb_set hdr_dma_channel4_5, hdr_default + -- 2.45.2 From 1d8ccfdfca39334f585eafdfa9d18db6ac7333d9 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 7 May 2023 19:28:01 +0200 Subject: [PATCH 16/85] Fix rcc enum --- drivers/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rcc.h b/drivers/rcc.h index 9869e06..61a5307 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -75,7 +75,7 @@ enum RccApb1 { */ enum RccApb2 { RCC_APB2_NONE = 0, - RCC_APB2_AFOI = (0x1 << 0), + RCC_APB2_AFIO = (0x1 << 0), RCC_APB2_IOPA = (0x1 << 2), RCC_APB2_IOPB = (0x1 << 3), RCC_APB2_IOPC = (0x1 << 4), -- 2.45.2 From 16fbf892baf51be4582bf66723ec713dd72ff548 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 20:52:18 +0200 Subject: [PATCH 17/85] Fix bitwise negations using the boolean operator --- drivers/flash.c | 2 +- drivers/rcc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/flash.c b/drivers/flash.c index a49df48..3219253 100644 --- a/drivers/flash.c +++ b/drivers/flash.c @@ -28,7 +28,7 @@ static volatile struct FLASH* regs = (struct FLASH*)FLASH_BASE_ADDRESS; void flash_configure(enum FlashPreset preset) { //restore default configuration - regs->ACR.word &= !0x3f; + regs->ACR.word &= ~0x3f; regs->ACR.word |= 0x30; //apply new configuration diff --git a/drivers/rcc.c b/drivers/rcc.c index 65c7fcc..c4c7bb0 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -94,7 +94,7 @@ static void apply_default_preset(void) while (regs->CR.HSIRDY != 0x1); //set HSI as main clock source and disable prescalers - regs->CFGR.word &= !0x077fff3; + regs->CFGR.word &= ~0x077fff3; //disable all options regs->CR.HSITRIM = 0x10; -- 2.45.2 From 2f40111dbb2f9d06ec86cf30b951ba5e00ed28e0 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 20:53:30 +0200 Subject: [PATCH 18/85] Create gpio's register map --- drivers/gpio_regs.h | 215 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 drivers/gpio_regs.h diff --git a/drivers/gpio_regs.h b/drivers/gpio_regs.h new file mode 100644 index 0000000..5ab539b --- /dev/null +++ b/drivers/gpio_regs.h @@ -0,0 +1,215 @@ +/** @file gpio_regs.h + * Module defining the GPIO registers. + * + * Mainly made to be used by the gpio module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define GPIO_BASE_ADDRESS 0x40010800 + +union GPIO_CRL { + struct __attribute__((packed)) { + uint32_t MODE0:2; + uint32_t CNF0:2; + uint32_t MODE1:2; + uint32_t CNF1:2; + uint32_t MODE2:2; + uint32_t CNF2:2; + uint32_t MODE3:2; + uint32_t CNF3:2; + uint32_t MODE4:2; + uint32_t CNF4:2; + uint32_t MODE5:2; + uint32_t CNF5:2; + uint32_t MODE6:2; + uint32_t CNF6:2; + uint32_t MODE7:2; + uint32_t CNF7:2; + }; + uint32_t word; +}; + +union GPIO_CRH { + struct __attribute__((packed)) { + uint32_t MODE8:2; + uint32_t CNF8:2; + uint32_t MODE9:2; + uint32_t CNF9:2; + uint32_t MODE10:2; + uint32_t CNF10:2; + uint32_t MODE11:2; + uint32_t CNF11:2; + uint32_t MODE12:2; + uint32_t CNF12:2; + uint32_t MODE13:2; + uint32_t CNF13:2; + uint32_t MODE14:2; + uint32_t CNF14:2; + uint32_t MODE15:2; + uint32_t CNF15:2; + }; + uint32_t word; +}; + +union GPIO_IDR { + struct __attribute__((packed)) { + uint32_t IDR0:1; + uint32_t IDR1:1; + uint32_t IDR2:1; + uint32_t IDR3:1; + uint32_t IDR4:1; + uint32_t IDR5:1; + uint32_t IDR6:1; + uint32_t IDR7:1; + uint32_t IDR8:1; + uint32_t IDR9:1; + uint32_t IDR10:1; + uint32_t IDR11:1; + uint32_t IDR12:1; + uint32_t IDR13:1; + uint32_t IDR14:1; + uint32_t IDR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_ODR { + struct __attribute__((packed)) { + uint32_t ODR0:1; + uint32_t ODR1:1; + uint32_t ODR2:1; + uint32_t ODR3:1; + uint32_t ODR4:1; + uint32_t ODR5:1; + uint32_t ODR6:1; + uint32_t ODR7:1; + uint32_t ODR8:1; + uint32_t ODR9:1; + uint32_t ODR10:1; + uint32_t ODR11:1; + uint32_t ODR12:1; + uint32_t ODR13:1; + uint32_t ODR14:1; + uint32_t ODR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_BSRR { + struct __attribute__((packed)) { + uint32_t BS0:1; + uint32_t BS1:1; + uint32_t BS2:1; + uint32_t BS3:1; + uint32_t BS4:1; + uint32_t BS5:1; + uint32_t BS6:1; + uint32_t BS7:1; + uint32_t BS8:1; + uint32_t BS9:1; + uint32_t BS10:1; + uint32_t BS11:1; + uint32_t BS12:1; + uint32_t BS13:1; + uint32_t BS14:1; + uint32_t BS15:1; + uint32_t BR0:1; + uint32_t BR1:1; + uint32_t BR2:1; + uint32_t BR3:1; + uint32_t BR4:1; + uint32_t BR5:1; + uint32_t BR6:1; + uint32_t BR7:1; + uint32_t BR8:1; + uint32_t BR9:1; + uint32_t BR10:1; + uint32_t BR11:1; + uint32_t BR12:1; + uint32_t BR13:1; + uint32_t BR14:1; + uint32_t BR15:1; + }; + uint32_t word; +}; + +union GPIO_BRR { + struct __attribute__((packed)) { + uint32_t BR0:1; + uint32_t BR1:1; + uint32_t BR2:1; + uint32_t BR3:1; + uint32_t BR4:1; + uint32_t BR5:1; + uint32_t BR6:1; + uint32_t BR7:1; + uint32_t BR8:1; + uint32_t BR9:1; + uint32_t BR10:1; + uint32_t BR11:1; + uint32_t BR12:1; + uint32_t BR13:1; + uint32_t BR14:1; + uint32_t BR15:1; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union GPIO_LCKK { + struct __attribute__((packed)) { + uint32_t LCK0:1; + uint32_t LCK1:1; + uint32_t LCK2:1; + uint32_t LCK3:1; + uint32_t LCK4:1; + uint32_t LCK5:1; + uint32_t LCK6:1; + uint32_t LCK7:1; + uint32_t LCK8:1; + uint32_t LCK9:1; + uint32_t LCK10:1; + uint32_t LCK11:1; + uint32_t LCK12:1; + uint32_t LCK13:1; + uint32_t LCK14:1; + uint32_t LCK15:1; + uint32_t LCKK:1; + uint32_t reserved1:15; + }; + uint32_t word; +}; + +struct __attribute__((packed)) GPIO_PORT { + union GPIO_CRL CRL; + union GPIO_CRH CRH; + union GPIO_IDR IDR; + union GPIO_ODR ODR; + union GPIO_BSRR BSRR; + union GPIO_BRR BRR; + union GPIO_LCKK LCKK; + uint32_t reserved1[249]; +}; + +struct __attribute__((packed)) GPIO { + struct GPIO_PORT PORTS[7]; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_GPIO_REGS_H_ + -- 2.45.2 From c44dc87f43b2d3aa97915f4b73544604474ad95e Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 20:54:50 +0200 Subject: [PATCH 19/85] Implement gpio's control functions --- drivers/gpio.c | 87 +++++++++++++++++++++++++++++++++++++ drivers/gpio.h | 116 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 203 insertions(+) create mode 100644 drivers/gpio.c create mode 100644 drivers/gpio.h diff --git a/drivers/gpio.c b/drivers/gpio.c new file mode 100644 index 0000000..409347d --- /dev/null +++ b/drivers/gpio.c @@ -0,0 +1,87 @@ +/** @file gpio.c + * Module handling General Purpose Input/Output (GPIO) pins + * + * The module provides functions to configure the gpio pins and read from/ + * write to them + */ + +//--includes-------------------------------------------------------------------- + +#include "gpio.h" +#include "gpio_regs.h" + +#include "rcc.h" + + +//--local definitions----------------------------------------------------------- + +static volatile struct GPIO* regs = (struct GPIO*)GPIO_BASE_ADDRESS; + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +/** + * Use the provided mask to generate its equivalent with 3 bits of padding + * between each initial bit. This new mask matches the registers layout and + * allow for direct application of the mode and config. Outputs are disabled + * prior to confiiguration to avoid any glitches. The relevant clocks are + * automatically enabled for the ports used + */ +void gpio_configure(enum GpioPort port, enum GpioPin pin_mask, + enum GpioMode mode, enum GpioConfig config) +{ + //ensure gpio port is enabled + rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_IOPA << port); + + //reset outputs before configuring anything + regs->PORTS[port].BRR.word |= pin_mask; + + //clear config for selected port, then apply new config, 8 first pins + uint32_t mask = 0; + for (uint8_t i=0; i<8; ++i) + { + if (pin_mask & (0x1 << i)) + { + mask |= 0x1 << (i * 4); + } + } + regs->PORTS[port].CRL.word &= ~(0xF * mask); + regs->PORTS[port].CRL.word |= (config << 2) | (mode << 0) * mask; + + //clear config for selected port, then apply new config, 8 last pins + mask = 0; + pin_mask = pin_mask >> 8; + for (uint8_t i=0; i<8; ++i) + { + if (pin_mask & (0x1 << i)) + { + mask |= 0x1 << (i * 4); + } + } + regs->PORTS[port].CRH.word &= ~(0xF * mask); + regs->PORTS[port].CRH.word |= (config << 2) | (mode << 0) * mask; +} + +void gpio_reset(enum GpioPort port, enum GpioPin pin_mask) +{ + gpio_configure(port, pin_mask, GPIO_MODE_INPUT, GPIO_CONFIG_IN_FLOATING); +} + +void gpio_write(enum GpioPort port, enum GpioPin pin_mask, bool value) +{ + if (value) { + regs->PORTS[port].BSRR.word |= pin_mask; + } else { + regs->PORTS[port].BRR.word |= pin_mask; + } +} + +bool gpio_read(enum GpioPort port, enum GpioPin pin_mask) +{ + return (regs->PORTS[port].IDR.word & pin_mask) == pin_mask; +} + + +//--local functions------------------------------------------------------------- diff --git a/drivers/gpio.h b/drivers/gpio.h new file mode 100644 index 0000000..36b2b75 --- /dev/null +++ b/drivers/gpio.h @@ -0,0 +1,116 @@ +/** @file gpio.h + * Module handling General Purpose Input/Output (GPIO) pins + * + * The module provides functions to configure the gpio pins and read from/ + * write to them + */ + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" +#include "stdbool.h" + + +//--type definitions------------------------------------------------------------ + +/** + * Available GPIO ports. Note that not all ports may be available for a + * particular chip + */ +enum GpioPort { + GPIO_PORT_A = 0, + GPIO_PORT_B, + GPIO_PORT_C, + GPIO_PORT_D, + GPIO_PORT_E, + GPIO_PORT_F, + GPIO_PORT_G, +}; + +/** + * Availables pin for a particular port. Note that all ports available may not + * have all the pins listed here and that some pins may be used by defaut (jtag, + * ...) + */ +enum GpioPin { + GPIO_PIN_0 = (0x1 << 0), + GPIO_PIN_1 = (0x1 << 1), + GPIO_PIN_2 = (0x1 << 2), + GPIO_PIN_3 = (0x1 << 3), + GPIO_PIN_4 = (0x1 << 4), + GPIO_PIN_5 = (0x1 << 5), + GPIO_PIN_6 = (0x1 << 6), + GPIO_PIN_7 = (0x1 << 7), + GPIO_PIN_8 = (0x1 << 8), + GPIO_PIN_9 = (0x1 << 9), + GPIO_PIN_10 = (0x1 << 10), + GPIO_PIN_11 = (0x1 << 11), + GPIO_PIN_12 = (0x1 << 12), + GPIO_PIN_13 = (0x1 << 13), + GPIO_PIN_14 = (0x1 << 14), + GPIO_PIN_15 = (0x1 << 15), +}; + +/** + * Available modes for a pin. To have a pin in both modes simultaneously, see + * push-pull configuration in input mode + */ +enum GpioMode { + GPIO_MODE_INPUT = 0, + GPIO_MODE_OUTPUT, //10MHz max + GPIO_MODE_OUTPUT_SLOW, //2MHz max + GPIO_MODE_OUTPUT_FAST, //50MHz max +}; + +/** + * Available configurations for a pin. Some configurations onlly apply in input + * mode (denoted "IN") while others only apply in output mode (denoted "OUT") + */ +enum GpioConfig { + GPIO_CONFIG_IN_ANALOG = 0, + GPIO_CONFIG_IN_FLOATING, + GPIO_CONFIG_IN_PUSH_PULL, //use gpio_write() to configure pull_up/down + GPIO_CONFIG_OUT_PUSH_PULL = 0, + GPIO_CONFIG_OUT_OPEN_DRAIN, + GPIO_CONFIG_OUT_ALT_PUSH_PULL, + GPIO_CONFIG_OUT_ALT_OPEN_DRAIN, +}; + + +//--functions------------------------------------------------------------------- + +/** + * Configures gpio pins on a single port. The GpioPin enum can be used as mask + * to configure multiple pins at the same time. Before configuring a pin, make + * sure it isn't used somewhere else (peripherals, jtag, ...). After + * configuration, the selected output pins are set to output 0V + */ +void gpio_configure(enum GpioPort port, enum GpioPin pin_mask, + enum GpioMode mode, enum GpioConfig config); + +/** + * Resets gpio pins on a single port. The GpioPin enum can be used as mask + * to reset multiple pins at the same time. This is a simple wrapper over + * gpio_configure(), setting the selected ports as floating input + */ +void gpio_reset(enum GpioPort port, enum GpioPin pin_mask); + +/** + * Write a value to output gpios on a single port. The GpioPin enum can be used + * as mask to reset multiple pins at the same time. In push-pull input mode, + * configure the pull up/down. Has no effect otherwise + */ +void gpio_write(enum GpioPort port, enum GpioPin pin_mask, bool value); + +/** + * Reads the value of gpios on a single port. The GpioPin enum can be used + * as mask to read multiple pins at the same time. For output pins, reads the + * pin state. Returns true if all selected ports are high + */ +bool gpio_read(enum GpioPort port, enum GpioPin pin_mask); + + +#endif //_RCC_H_ -- 2.45.2 From 0034dea7747f8ab384df09f01708bbe9bc6582df Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 21:03:52 +0200 Subject: [PATCH 20/85] Make gpio writes atomic --- drivers/gpio.c | 6 +++--- drivers/gpio.h | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpio.c b/drivers/gpio.c index 409347d..be603b4 100644 --- a/drivers/gpio.c +++ b/drivers/gpio.c @@ -36,7 +36,7 @@ void gpio_configure(enum GpioPort port, enum GpioPin pin_mask, rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_IOPA << port); //reset outputs before configuring anything - regs->PORTS[port].BRR.word |= pin_mask; + regs->PORTS[port].BRR.word = pin_mask; //clear config for selected port, then apply new config, 8 first pins uint32_t mask = 0; @@ -72,9 +72,9 @@ void gpio_reset(enum GpioPort port, enum GpioPin pin_mask) void gpio_write(enum GpioPort port, enum GpioPin pin_mask, bool value) { if (value) { - regs->PORTS[port].BSRR.word |= pin_mask; + regs->PORTS[port].BSRR.word = pin_mask; } else { - regs->PORTS[port].BRR.word |= pin_mask; + regs->PORTS[port].BRR.word = pin_mask; } } diff --git a/drivers/gpio.h b/drivers/gpio.h index 36b2b75..9e5c2a5 100644 --- a/drivers/gpio.h +++ b/drivers/gpio.h @@ -101,7 +101,8 @@ void gpio_reset(enum GpioPort port, enum GpioPin pin_mask); /** * Write a value to output gpios on a single port. The GpioPin enum can be used * as mask to reset multiple pins at the same time. In push-pull input mode, - * configure the pull up/down. Has no effect otherwise + * configure the pull up/down. Has no effect otherwise. Writes are atomic + * operations */ void gpio_write(enum GpioPort port, enum GpioPin pin_mask, bool value); -- 2.45.2 From f0da0cd05c62092f03c0a501872a0058e188fff7 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 21:18:28 +0200 Subject: [PATCH 21/85] Fix gpio configuration mask not properly applied --- drivers/gpio.c | 5 +++-- drivers/gpio.h | 8 +++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpio.c b/drivers/gpio.c index be603b4..5ef4cd1 100644 --- a/drivers/gpio.c +++ b/drivers/gpio.c @@ -48,7 +48,7 @@ void gpio_configure(enum GpioPort port, enum GpioPin pin_mask, } } regs->PORTS[port].CRL.word &= ~(0xF * mask); - regs->PORTS[port].CRL.word |= (config << 2) | (mode << 0) * mask; + regs->PORTS[port].CRL.word |= ((config << 2) | (mode << 0)) * mask; //clear config for selected port, then apply new config, 8 last pins mask = 0; @@ -61,7 +61,7 @@ void gpio_configure(enum GpioPort port, enum GpioPin pin_mask, } } regs->PORTS[port].CRH.word &= ~(0xF * mask); - regs->PORTS[port].CRH.word |= (config << 2) | (mode << 0) * mask; + regs->PORTS[port].CRH.word |= ((config << 2) | (mode << 0)) * mask; } void gpio_reset(enum GpioPort port, enum GpioPin pin_mask) @@ -85,3 +85,4 @@ bool gpio_read(enum GpioPort port, enum GpioPin pin_mask) //--local functions------------------------------------------------------------- + diff --git a/drivers/gpio.h b/drivers/gpio.h index 9e5c2a5..7a12484 100644 --- a/drivers/gpio.h +++ b/drivers/gpio.h @@ -55,8 +55,9 @@ enum GpioPin { }; /** - * Available modes for a pin. To have a pin in both modes simultaneously, see - * push-pull configuration in input mode + * Available modes for a pin. To have a pin in both modes simultaneously, use + * push-pull configuration in input mode but note that the power may be + * limited */ enum GpioMode { GPIO_MODE_INPUT = 0, @@ -66,7 +67,7 @@ enum GpioMode { }; /** - * Available configurations for a pin. Some configurations onlly apply in input + * Available configurations for a pin. Some configurations only apply in input * mode (denoted "IN") while others only apply in output mode (denoted "OUT") */ enum GpioConfig { @@ -115,3 +116,4 @@ bool gpio_read(enum GpioPort port, enum GpioPin pin_mask); #endif //_RCC_H_ + -- 2.45.2 From d9170ee902a58a027f4ea32b254b78228ba55b34 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 8 May 2023 21:28:30 +0200 Subject: [PATCH 22/85] Updated module documentation --- doc/modules.drawio | 322 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 322 insertions(+) create mode 100644 doc/modules.drawio diff --git a/doc/modules.drawio b/doc/modules.drawio new file mode 100644 index 0000000..cc1209c --- /dev/null +++ b/doc/modules.drawio @@ -0,0 +1,322 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.45.2 From 8dc58b674785caa40953922d844f13f72d735a43 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 13:21:26 +0200 Subject: [PATCH 23/85] Add peripheral-wide reset function for gpios --- drivers/gpio.c | 11 +++++++++-- drivers/gpio.h | 8 +++++++- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpio.c b/drivers/gpio.c index 5ef4cd1..d1a7922 100644 --- a/drivers/gpio.c +++ b/drivers/gpio.c @@ -15,11 +15,11 @@ //--local definitions----------------------------------------------------------- +//--local variables------------------------------------------------------------- + static volatile struct GPIO* regs = (struct GPIO*)GPIO_BASE_ADDRESS; -//--local variables------------------------------------------------------------- - //--public functions------------------------------------------------------------ /** @@ -83,6 +83,13 @@ bool gpio_read(enum GpioPort port, enum GpioPin pin_mask) return (regs->PORTS[port].IDR.word & pin_mask) == pin_mask; } +void gpio_reset_peripheral(void) +{ + rcc_disable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_IOPA | RCC_APB2_IOPB + | RCC_APB2_IOPC | RCC_APB2_IOPD | RCC_APB2_IOPE | RCC_APB2_IOPF + | RCC_APB2_IOPG); +} + //--local functions------------------------------------------------------------- diff --git a/drivers/gpio.h b/drivers/gpio.h index 7a12484..6453764 100644 --- a/drivers/gpio.h +++ b/drivers/gpio.h @@ -114,6 +114,12 @@ void gpio_write(enum GpioPort port, enum GpioPin pin_mask, bool value); */ bool gpio_read(enum GpioPort port, enum GpioPin pin_mask); +/** + * Resets all gpios and disable all ports. The gpio peripherals are returned to + * their reset configuration and their respective clocks disabled + */ +void gpio_reset_peripheral(void); -#endif //_RCC_H_ + +#endif //_GPIO_H_ -- 2.45.2 From a99b4ad0dee8e62cdb10453e10b3e21729f00f9c Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 14:17:03 +0200 Subject: [PATCH 24/85] Create exti's register map --- drivers/exti_regs.h | 190 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 drivers/exti_regs.h diff --git a/drivers/exti_regs.h b/drivers/exti_regs.h new file mode 100644 index 0000000..c5d884f --- /dev/null +++ b/drivers/exti_regs.h @@ -0,0 +1,190 @@ +/** @file exti_regs.h + * Module defining the EXTI registers + * + * Mainly made to be used by the exti module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _EXTI_REGS_H_ +#define _EXTI_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define EXTI_BASE_ADDRESS 0x40010400 + +union EXTI_IMR { + struct __attribute__((packed)) { + uint32_t MR0:1; + uint32_t MR1:1; + uint32_t MR2:1; + uint32_t MR3:1; + uint32_t MR4:1; + uint32_t MR5:1; + uint32_t MR6:1; + uint32_t MR7:1; + uint32_t MR8:1; + uint32_t MR9:1; + uint32_t MR10:1; + uint32_t MR11:1; + uint32_t MR12:1; + uint32_t MR13:1; + uint32_t MR14:1; + uint32_t MR15:1; + uint32_t MR16:1; + uint32_t MR17:1; + uint32_t MR18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +union EXTI_EMR { + struct __attribute__((packed)) { + uint32_t MR0:1; + uint32_t MR1:1; + uint32_t MR2:1; + uint32_t MR3:1; + uint32_t MR4:1; + uint32_t MR5:1; + uint32_t MR6:1; + uint32_t MR7:1; + uint32_t MR8:1; + uint32_t MR9:1; + uint32_t MR10:1; + uint32_t MR11:1; + uint32_t MR12:1; + uint32_t MR13:1; + uint32_t MR14:1; + uint32_t MR15:1; + uint32_t MR16:1; + uint32_t MR17:1; + uint32_t MR18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +union EXTI_RTSR { + struct __attribute__((packed)) { + uint32_t TR0:1; + uint32_t TR1:1; + uint32_t TR2:1; + uint32_t TR3:1; + uint32_t TR4:1; + uint32_t TR5:1; + uint32_t TR6:1; + uint32_t TR7:1; + uint32_t TR8:1; + uint32_t TR9:1; + uint32_t TR10:1; + uint32_t TR11:1; + uint32_t TR12:1; + uint32_t TR13:1; + uint32_t TR14:1; + uint32_t TR15:1; + uint32_t TR16:1; + uint32_t TR17:1; + uint32_t TR18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +union EXTI_FTSR { + struct __attribute__((packed)) { + uint32_t TR0:1; + uint32_t TR1:1; + uint32_t TR2:1; + uint32_t TR3:1; + uint32_t TR4:1; + uint32_t TR5:1; + uint32_t TR6:1; + uint32_t TR7:1; + uint32_t TR8:1; + uint32_t TR9:1; + uint32_t TR10:1; + uint32_t TR11:1; + uint32_t TR12:1; + uint32_t TR13:1; + uint32_t TR14:1; + uint32_t TR15:1; + uint32_t TR16:1; + uint32_t TR17:1; + uint32_t TR18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +union EXTI_SWIER { + struct __attribute__((packed)) { + uint32_t SWIER0:1; + uint32_t SWIER1:1; + uint32_t SWIER2:1; + uint32_t SWIER3:1; + uint32_t SWIER4:1; + uint32_t SWIER5:1; + uint32_t SWIER6:1; + uint32_t SWIER7:1; + uint32_t SWIER8:1; + uint32_t SWIER9:1; + uint32_t SWIER10:1; + uint32_t SWIER11:1; + uint32_t SWIER12:1; + uint32_t SWIER13:1; + uint32_t SWIER14:1; + uint32_t SWIER15:1; + uint32_t SWIER16:1; + uint32_t SWIER17:1; + uint32_t SWIER18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +union EXTI_PR { + struct __attribute__((packed)) { + uint32_t PR0:1; + uint32_t PR1:1; + uint32_t PR2:1; + uint32_t PR3:1; + uint32_t PR4:1; + uint32_t PR5:1; + uint32_t PR6:1; + uint32_t PR7:1; + uint32_t PR8:1; + uint32_t PR9:1; + uint32_t PR10:1; + uint32_t PR11:1; + uint32_t PR12:1; + uint32_t PR13:1; + uint32_t PR14:1; + uint32_t PR15:1; + uint32_t PR16:1; + uint32_t PR17:1; + uint32_t PR18:1; + uint32_t reserved1:13; + }; + uint32_t word; +}; + +struct __attribute__((packed)) EXTI { + union EXTI_IMR IMR; + union EXTI_EMR EMR; + union EXTI_RTSR RTSR; + union EXTI_FTSR FTSR; + union EXTI_SWIER SWIER; + union EXTI_PR PR; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_EXTI_REGS_H_ + -- 2.45.2 From c7deded9b24e72c7ed7aa434f3eef7163becc6c5 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 14:17:32 +0200 Subject: [PATCH 25/85] Implement exti's control functions --- drivers/exti.c | 267 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/exti.h | 108 ++++++++++++++++++++ 2 files changed, 375 insertions(+) create mode 100644 drivers/exti.c create mode 100644 drivers/exti.h diff --git a/drivers/exti.c b/drivers/exti.c new file mode 100644 index 0000000..3556864 --- /dev/null +++ b/drivers/exti.c @@ -0,0 +1,267 @@ +/** @file exti.c + * Module handling EXTernal Interrupt lines + * + * The module provides functions to configure the exti lines to generate events + * or interrupts + */ + +//--includes-------------------------------------------------------------------- + +#include "exti.h" +#include "exti_regs.h" + +#include "nvic.h" + + +//--local definitions----------------------------------------------------------- + +//--local variables------------------------------------------------------------- + +static volatile struct EXTI* regs = (struct EXTI*)EXTI_BASE_ADDRESS; +static ExtiCallback callbacks[19]; + + +//--public functions------------------------------------------------------------ + +void exti_configure(enum ExtiLine line_mask, enum GpioPort port, + enum ExtiConfig config_mask, ExtiCallback callback) +{ + exti_reset(line_mask); + +#warning "configure ports mapping" + + //configure edge detections + if (config_mask & EXTI_CONFIG_RISING_EDGE) { + regs->RTSR.word |= line_mask; + } else { + regs->RTSR.word &= ~line_mask; + } + + if (config_mask & EXTI_CONFIG_FALLING_EDGE) { + regs->FTSR.word |= line_mask; + } else { + regs->FTSR.word &= ~line_mask; + } + + //reconfigure events/irqs + regs->EMR.word |= line_mask; + if (callback) { + //register callbacks for each line selected + for (uint8_t i = 0; i < 16; ++i) { + if (line_mask & (0x1 << i)) { + callbacks[i] = callback; + } + } + + //enable interrupts lines in nvic + for (uint8_t i = 0; i < 5; ++i) { + if (line_mask & (0x1 << i)) { + nvic_enable(NVIC_IRQ_EXTI0 + i); + } + } + if (line_mask & 0x3e0) { + nvic_enable(NVIC_IRQ_EXTI9_5); + } + if (line_mask & 0x7c00) { + nvic_enable(NVIC_IRQ_EXTI15_10); + } + + //enable irqs in last to avoid triggers during config + regs->IMR.word |= line_mask; + } +} + +void exti_reset(enum ExtiLine line_mask) +{ + //disable events/irqs + regs->IMR.word &= ~line_mask; + regs->EMR.word &= ~line_mask; + + //clear any pending bits + regs->PR.word |= line_mask; + + //disable interrupts lines in nvic + for (uint8_t i = 0; i < 5; ++i) { + if (line_mask & (0x1 << i)) { + nvic_enable(NVIC_IRQ_EXTI0 + i); + } + } + if (line_mask & 0x3e0) { + nvic_enable(NVIC_IRQ_EXTI9_5); + } + if (line_mask & 0x7c00) { + nvic_enable(NVIC_IRQ_EXTI15_10); + } +} + +void exti_configure_specific(enum ExtiLineSpecific line_mask, + enum ExtiConfig config_mask, ExtiCallback callback) +{ + //reset is identical to normal lines + exti_reset_specific(line_mask); + + //configure edge detections + if (config_mask & EXTI_CONFIG_RISING_EDGE) { + regs->RTSR.word |= line_mask; + } else { + regs->RTSR.word &= ~line_mask; + } + + if (config_mask & EXTI_CONFIG_FALLING_EDGE) { + regs->FTSR.word |= line_mask; + } else { + regs->FTSR.word &= ~line_mask; + } + + //reconfigure events/irqs + regs->EMR.word |= line_mask; + if (callback) { + //register callbacks for each line selected + for (uint8_t i = 0; i < 16; ++i) { + if (line_mask & (0x1 << i)) { + callbacks[i] = callback; + } + } + + //enable interrupts lines in nvic + if (line_mask & EXTI_LINE_PVD) { + nvic_enable(NVIC_IRQ_PVD); + } + if (line_mask & EXTI_LINE_RTC) { + nvic_enable(NVIC_IRQ_RTC_ALARM); + } + if (line_mask & EXTI_LINE_USB) { + nvic_enable(NVIC_IRQ_USB_WAKEUP); + } + + //enable irqs in last to avoid triggers during config + regs->IMR.word |= line_mask; + } +} + +void exti_reset_specific(enum ExtiLineSpecific line_mask) +{ + //disable events/irqs + regs->IMR.word &= ~line_mask; + regs->EMR.word &= ~line_mask; + + //clear any pending bits + regs->PR.word |= line_mask; + + //disable interrupts lines in nvic + if (line_mask & EXTI_LINE_PVD) { + nvic_disable(NVIC_IRQ_PVD); + } + if (line_mask & EXTI_LINE_RTC) { + nvic_disable(NVIC_IRQ_RTC_ALARM); + } + if (line_mask & EXTI_LINE_USB) { + nvic_disable(NVIC_IRQ_USB_WAKEUP); + } +} + +void exti_reset_peripheral(void) +{ + //reset peripheral config + regs->IMR.word = 0; + regs->EMR.word = 0; + regs->RTSR.word = 0; + regs->FTSR.word = 0; + regs->SWIER.word = 0; + regs->PR.word = 0; + + //disable interrupts in nvic + for (uint8_t i = 0; i < 5; ++i) { + nvic_enable(NVIC_IRQ_EXTI0 + i); + } + nvic_enable(NVIC_IRQ_EXTI9_5); + nvic_enable(NVIC_IRQ_EXTI15_10); + nvic_disable(NVIC_IRQ_PVD); + nvic_disable(NVIC_IRQ_RTC_ALARM); + nvic_disable(NVIC_IRQ_USB_WAKEUP); + +#warning "reset afio lines" +} + +//--local functions------------------------------------------------------------- + +//--ISRs ----------------------------------------------------------------------- + +void hdr_exti0(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI0); + regs->PR.PR0 = 1; + callbacks[0](); +} + +void hdr_exti1(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI1); + regs->PR.PR1 = 1; + callbacks[1](); +} + +void hdr_exti2(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI2); + regs->PR.PR2 = 1; + callbacks[2](); +} + +void hdr_exti3(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI3); + regs->PR.PR3 = 1; + callbacks[3](); +} + +void hdr_exti4(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI4); + regs->PR.PR4 = 1; + callbacks[4](); +} + +void hdr_exti9_5(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI9_5); + for (uint8_t i = 5; i < 10; ++i) { + if (regs->PR.word & (0x1 << i)) { + regs->PR.word |= 0x1 << i; + callbacks[i](); + } + } +} + +void hdr_exti15_10(void) +{ + nvic_clear_pending(NVIC_IRQ_EXTI15_10); + for (uint8_t i = 10; i < 16; ++i) { + if (regs->PR.word & (0x1 << i)) { + regs->PR.word |= 0x1 << i; + callbacks[i](); + } + } +} + +void hdr_pvd(void) +{ + nvic_clear_pending(NVIC_IRQ_PVD); + regs->PR.PR16 = 1; + callbacks[16](); +} + +void hdr_rtc_alarm(void) +{ + nvic_clear_pending(NVIC_IRQ_RTC_ALARM); + regs->PR.PR17 = 1; + callbacks[17](); +} + +void hdr_usb_wakeup(void) +{ + nvic_clear_pending(NVIC_IRQ_USB_WAKEUP); + regs->PR.PR18 = 1; + callbacks[18](); +} + diff --git a/drivers/exti.h b/drivers/exti.h new file mode 100644 index 0000000..f942c20 --- /dev/null +++ b/drivers/exti.h @@ -0,0 +1,108 @@ +/** @file exti.h + * Module handling EXTernal Interrupt lines + * + * The module provides functions to configure the exti lines to generate events + * or interrupts + */ + +#ifndef _EXTI_H_ +#define _EXTI_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" +#include "stdbool.h" + +#include "gpio.h" + + +//--type definitions------------------------------------------------------------ + +/** + * Available exti lines. These lines correspond to gpios + */ +enum ExtiLine { + EXTI_LINE_0 = (0x1 << 0), + EXTI_LINE_1 = (0x1 << 1), + EXTI_LINE_2 = (0x1 << 2), + EXTI_LINE_3 = (0x1 << 3), + EXTI_LINE_4 = (0x1 << 4), + EXTI_LINE_5 = (0x1 << 5), + EXTI_LINE_6 = (0x1 << 6), + EXTI_LINE_7 = (0x1 << 7), + EXTI_LINE_8 = (0x1 << 8), + EXTI_LINE_9 = (0x1 << 9), + EXTI_LINE_10 = (0x1 << 10), + EXTI_LINE_11 = (0x1 << 11), + EXTI_LINE_12 = (0x1 << 12), + EXTI_LINE_13 = (0x1 << 13), + EXTI_LINE_14 = (0x1 << 14), + EXTI_LINE_15 = (0x1 << 15), +}; + +/** + * Available exti lines. These lines correspond to specific peripherals + */ +enum ExtiLineSpecific { + EXTI_LINE_PVD = (0x1 << 16), + EXTI_LINE_RTC = (0x1 << 17), + EXTI_LINE_USB = (0x1 << 18), +}; + +/** + * Available configurations for exti lines. These configurations apply to both + * regular and specific lines and can be used together on a single line + */ +enum ExtiConfig { + EXTI_CONFIG_RISING_EDGE, + EXTI_CONFIG_FALLING_EDGE, +}; + +typedef void (*ExtiCallback)(void); + + +//--functions------------------------------------------------------------------- + +/** + * Configure lines on a single GPIO port. The ExtiLine enum can be used as a + * mask to configure multiple lines at the same time. Every line can only be + * configured for a single port, reconfiguring it will override the previous + * configuration. Each line is linked to the pins of the same id (ex : pin 1 for + * exti 1). When possible, it is recommanded to use the lowest id possible for + * better performance. The ExtiConfig enum can be used as mask. If no callback + * is specified, the interrupt won't be enabled, but an event will still be sent + * to wake the cpu up + */ +void exti_configure(enum ExtiLine line_mask, enum GpioPort port, + enum ExtiConfig config_mask, ExtiCallback callback); + +/** + * Resets lines. The ExtiLine enum can be used as a mask to configure multiple + * lines at the same time + */ +void exti_reset(enum ExtiLine line_mask); + +/** + * Configure lines for specific, non-gpio peripherals. The ExtiLineSpecific enum + * can be used as a mask to configure multiple lines at the same time. The + * ExtiConfig enum can be used as mask. If no callback is specified, the + * interrupt won't be enabled, but an event will still be sent to wake the cpu + * up + */ +void exti_configure_specific(enum ExtiLineSpecific line_mask, + enum ExtiConfig config_mask, ExtiCallback callback); + +/** + * Resets lines for specific, non-gpio peripherals. The ExtiLineSpecific enum + * can be used as a mask to configure multiple lines at the same time. + */ +void exti_reset_specific(enum ExtiLineSpecific line_mask); + +/** + * Resets all lines. The exti peripheral is returned to its reset configuration + */ +void exti_reset_peripheral(void); + + +#endif //_EXTI_H_ + -- 2.45.2 From 9052aac1b3f6a0ce4e70409956bd2e773b2b26af Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 15:42:11 +0200 Subject: [PATCH 26/85] Create afio's register map --- drivers/afio_regs.h | 125 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 drivers/afio_regs.h diff --git a/drivers/afio_regs.h b/drivers/afio_regs.h new file mode 100644 index 0000000..55bdde0 --- /dev/null +++ b/drivers/afio_regs.h @@ -0,0 +1,125 @@ +/** @file afio_regs.h + * Module defining the AFIO registers. + * + * Mainly made to be used by the afio module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _IO_REGS_H_ +#define _IO_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define AFIO_BASE_ADDRESS 0x40010000 + +union EVCR { + struct __attribute__((packed)) { + uint32_t PIN:4; + uint32_t PORT:3; + uint32_t EVOE:1; + uint32_t reserved1:24; + }; + uint32_t word; +}; + +union MAPR { + struct __attribute__((packed)) { + uint32_t SPI1_REMAP:1; + uint32_t I2C1_REMAP:1; + uint32_t USART1_REMAP:1; + uint32_t USART2_REMAP:1; + uint32_t USART3_REMAP:2; + uint32_t TIM1_REMAP:2; + uint32_t TIM2_REMAP:2; + uint32_t TIM3_REMAP:2; + uint32_t TIM4_REMAP:1; + uint32_t CAN_REMAP:2; + uint32_t PD01_REMAP:1; + uint32_t TIM5CH4_REMAP:1; + uint32_t ADC1_ETRGINJ_REMAP:1; + uint32_t ADC1_ETRGREG_REMAP:1; + uint32_t ADC2_ETRGINJ_REMAP:1; + uint32_t ADC2_ETRGREG_REMAP:1; + uint32_t reserved1:3; + uint32_t SWJ_CFG:3; + uint32_t reserved2:5; + }; + uint32_t word; +}; + +union EXTICR1 { + struct __attribute__((packed)) { + uint32_t EXTI0:4; + uint32_t EXTI1:4; + uint32_t EXTI2:4; + uint32_t EXTI3:4; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union EXTICR2 { + struct __attribute__((packed)) { + uint32_t EXTI4:4; + uint32_t EXTI5:4; + uint32_t EXTI6:4; + uint32_t EXTI7:4; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union EXTICR3 { + struct __attribute__((packed)) { + uint32_t EXTI8:4; + uint32_t EXTI9:4; + uint32_t EXTI10:4; + uint32_t EXTI11:4; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union EXTICR4 { + struct __attribute__((packed)) { + uint32_t EXTI12:4; + uint32_t EXTI13:4; + uint32_t EXTI14:4; + uint32_t EXTI15:4; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union MAPR2 { + struct __attribute__((packed)) { + uint32_t reserved1:5; + uint32_t TIM9_REMAP:1; + uint32_t TIM10_REMAP:1; + uint32_t TIM11_REMAP:1; + uint32_t TIM13_REMAP:1; + uint32_t TIM14_REMAP:1; + uint32_t FSMC_NADV:1; + uint32_t reserved2:21; + }; + uint32_t word; +}; + +struct __attribute__((packed)) AFIO { + union EVCR EVCR; + union MAPR MAPR; + union EXTICR1 EXTICR1; + union EXTICR2 EXTICR2; + union EXTICR3 EXTICR3; + union EXTICR4 EXTICR4; + union MAPR2 MAPR2; +}; + +#endif //_AFIO_REGS_H_ + -- 2.45.2 From 3906a79315372b660abf3b2ac436eada00f89b52 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 15:42:38 +0200 Subject: [PATCH 27/85] Implement afio's control functions --- drivers/afio.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/afio.h | 26 +++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 drivers/afio.c create mode 100644 drivers/afio.h diff --git a/drivers/afio.c b/drivers/afio.c new file mode 100644 index 0000000..688bc20 --- /dev/null +++ b/drivers/afio.c @@ -0,0 +1,63 @@ +/** @file afio.c + * Module handling Alternate Functions for Inputs/Outputs + * + * The module provides functions to remap ios to diverse peripherals + */ + +//--includes-------------------------------------------------------------------- + +#include "afio.h" +#include "afio_regs.h" + +#include "rcc.h" + + +//--local definitions----------------------------------------------------------- + +//--local variables------------------------------------------------------------- + +static volatile struct AFIO* regs = (struct AFIO*)AFIO_BASE_ADDRESS; + + +//--public functions------------------------------------------------------------ + +void afio_map_exti(enum ExtiLine line_mask, enum GpioPort port) +{ + //ensure afio peripheral is enabled + rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_AFIO); + + for (uint8_t i = 0; i < 4; ++i) { + if (line_mask & (0x1 << i)) { + regs->EXTICR1.word &= ~(0xF << (4 * i)); + regs->EXTICR1.word |= (port << (4 * i)); + } + } + + line_mask = line_mask >> 4; + for (uint8_t i = 0; i < 4; ++i) { + if (line_mask & (0x1 << i)) { + regs->EXTICR2.word &= ~(0xF << (4 * i)); + regs->EXTICR2.word |= (port << (4 * i)); + } + } + + line_mask = line_mask >> 4; + for (uint8_t i = 0; i < 4; ++i) { + if (line_mask & (0x1 << i)) { + regs->EXTICR3.word &= ~(0xF << (4 * i)); + regs->EXTICR3.word |= (port << (4 * i)); + } + } + + line_mask = line_mask >> 4; + for (uint8_t i = 0; i < 4; ++i) { + if (line_mask & (0x1 << i)) { + regs->EXTICR4.word &= ~(0xF << (4 * i)); + regs->EXTICR4.word |= (port << (4 * i)); + } + } +} + + +//--local functions------------------------------------------------------------- + diff --git a/drivers/afio.h b/drivers/afio.h new file mode 100644 index 0000000..961390c --- /dev/null +++ b/drivers/afio.h @@ -0,0 +1,26 @@ +/** @file afio.h + * Module handling Alternate Functions for Inputs/Outputs + * + * The module provides functions to remap ios to diverse peripherals + */ + +#ifndef _AFIO_H_ +#define _AFIO_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" +#include "stdbool.h" + +#include "exti.h" + + +//--type definitions------------------------------------------------------------ + +//--functions------------------------------------------------------------------- + +void afio_map_exti(enum ExtiLine line_mask, enum GpioPort port); + + +#endif //_AFIO_H_ + -- 2.45.2 From 245b9238e92383540301d399db0196384e83aede Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 15:42:59 +0200 Subject: [PATCH 28/85] Finish exti's implementation --- drivers/exti.c | 13 ++++++++----- drivers/exti.h | 4 ++-- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/exti.c b/drivers/exti.c index 3556864..4f518e1 100644 --- a/drivers/exti.c +++ b/drivers/exti.c @@ -11,6 +11,7 @@ #include "exti_regs.h" #include "nvic.h" +#include "afio.h" //--local definitions----------------------------------------------------------- @@ -28,7 +29,7 @@ void exti_configure(enum ExtiLine line_mask, enum GpioPort port, { exti_reset(line_mask); -#warning "configure ports mapping" + afio_map_exti(line_mask, port); //configure edge detections if (config_mask & EXTI_CONFIG_RISING_EDGE) { @@ -83,15 +84,17 @@ void exti_reset(enum ExtiLine line_mask) //disable interrupts lines in nvic for (uint8_t i = 0; i < 5; ++i) { if (line_mask & (0x1 << i)) { - nvic_enable(NVIC_IRQ_EXTI0 + i); + nvic_disable(NVIC_IRQ_EXTI0 + i); } } if (line_mask & 0x3e0) { - nvic_enable(NVIC_IRQ_EXTI9_5); + nvic_disable(NVIC_IRQ_EXTI9_5); } if (line_mask & 0x7c00) { - nvic_enable(NVIC_IRQ_EXTI15_10); + nvic_disable(NVIC_IRQ_EXTI15_10); } + + afio_map_exti(0xFFFF, 0x0); } void exti_configure_specific(enum ExtiLineSpecific line_mask, @@ -180,7 +183,7 @@ void exti_reset_peripheral(void) nvic_disable(NVIC_IRQ_RTC_ALARM); nvic_disable(NVIC_IRQ_USB_WAKEUP); -#warning "reset afio lines" + afio_map_exti(0xFFFF, 0x0); } //--local functions------------------------------------------------------------- diff --git a/drivers/exti.h b/drivers/exti.h index f942c20..d2c5089 100644 --- a/drivers/exti.h +++ b/drivers/exti.h @@ -54,8 +54,8 @@ enum ExtiLineSpecific { * regular and specific lines and can be used together on a single line */ enum ExtiConfig { - EXTI_CONFIG_RISING_EDGE, - EXTI_CONFIG_FALLING_EDGE, + EXTI_CONFIG_RISING_EDGE = (0x1 << 0), + EXTI_CONFIG_FALLING_EDGE = (0x1 << 1), }; typedef void (*ExtiCallback)(void); -- 2.45.2 From db5180d3e7c0ad05c30050ccfe33ca22a4630052 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 15:48:07 +0200 Subject: [PATCH 29/85] Document afio function --- drivers/afio.h | 7 +++++++ drivers/exti.h | 5 ++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/afio.h b/drivers/afio.h index 961390c..f1a06de 100644 --- a/drivers/afio.h +++ b/drivers/afio.h @@ -19,6 +19,13 @@ //--functions------------------------------------------------------------------- +/** + * Maps the exti lines to gpio ports. The ExtiLine enum can be used as a + * mask to configure multiple lines at the same time. This function is used by + * the exti module to configure its line and calling it directly should should + * thus normaly not be needed. It could however still be usefull when wanting to + * change the port linked to an exti without reconfiguring it entirely + */ void afio_map_exti(enum ExtiLine line_mask, enum GpioPort port); diff --git a/drivers/exti.h b/drivers/exti.h index d2c5089..3349aca 100644 --- a/drivers/exti.h +++ b/drivers/exti.h @@ -71,7 +71,10 @@ typedef void (*ExtiCallback)(void); * exti 1). When possible, it is recommanded to use the lowest id possible for * better performance. The ExtiConfig enum can be used as mask. If no callback * is specified, the interrupt won't be enabled, but an event will still be sent - * to wake the cpu up + * to wake the cpu up. + * + * Note: wich port is linked to a line can be changed atfer the fact using + * afio_map_exti() */ void exti_configure(enum ExtiLine line_mask, enum GpioPort port, enum ExtiConfig config_mask, ExtiCallback callback); -- 2.45.2 From 3b4536bea20ccad856bead28030971e9aa38ff94 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 13 May 2023 15:50:13 +0200 Subject: [PATCH 30/85] Upddate module documentation --- doc/modules.drawio | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/doc/modules.drawio b/doc/modules.drawio index cc1209c..100992c 100644 --- a/doc/modules.drawio +++ b/doc/modules.drawio @@ -1,4 +1,4 @@ - + @@ -41,7 +41,7 @@ - + @@ -61,6 +61,9 @@ + + + @@ -169,7 +172,7 @@ - + @@ -286,35 +289,41 @@ - - + + - + - + - + - + - + - - + + - - + + - - + + - - + + + + + + + + -- 2.45.2 From aeba78cfccdb22a24929b0effc5f3dc3d369c6e1 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Thu, 18 May 2023 13:49:53 +0200 Subject: [PATCH 31/85] Create usart's register map --- drivers/usart_regs.h | 137 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 drivers/usart_regs.h diff --git a/drivers/usart_regs.h b/drivers/usart_regs.h new file mode 100644 index 0000000..3e66200 --- /dev/null +++ b/drivers/usart_regs.h @@ -0,0 +1,137 @@ +/** @file usart_regs.h + * Module defining the USART registers. + * + * Mainly made to be used by the usart module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _USART_REGS_H_ +#define _USART_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define USART1_BASE_ADDRESS 0x40013800 +#define USART2_BASE_ADDRESS 0x40004400 +#define USART3_BASE_ADDRESS 0x40004800 + +union USART_SR { + struct __attribute__((packed)) { + uint32_t PE:1; + uint32_t FE:1; + uint32_t NE:1; + uint32_t ORE:1; + uint32_t IDLE:1; + uint32_t RXNE:1; + uint32_t TC:1; + uint32_t TXE:1; + uint32_t LBD:1; + uint32_t CTS:1; + uint32_t reserved1:22; + }; + uint32_t word; +}; + +union USART_DR { + struct __attribute__((packed)) { + uint32_t DR:9; + uint32_t reserved1:23; + }; + uint32_t word; +}; + +union USART_BRR { + struct __attribute__((packed)) { + uint32_t DIV_Fraction:4; + uint32_t DIV_Mantissa:12; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +union USART_CR1 { + struct __attribute__((packed)) { + uint32_t SBK:1; + uint32_t RWU:1; + uint32_t RE:1; + uint32_t TE:1; + uint32_t IDLEIE:1; + uint32_t RXNEIE:1; + uint32_t TCIE:1; + uint32_t TXEIE:1; + uint32_t PEI:1; + uint32_t PS:1; + uint32_t PCE:1; + uint32_t WAKE:1; + uint32_t M:1; + uint32_t UE:1; + uint32_t reserved1:18; + }; + uint32_t word; +}; + +union USART_CR2 { + struct __attribute__((packed)) { + uint32_t ADD:4; + uint32_t reserved1:1; + uint32_t LBDL:1; + uint32_t LBDIE:1; + uint32_t reserved2:1; + uint32_t LBCL:1; + uint32_t CPHA:1; + uint32_t CPOL:1; + uint32_t CLKEN:1; + uint32_t STOP:2; + uint32_t LINEN:1; + uint32_t reserved3:17; + }; + uint32_t word; +}; + +union USART_CR3 { + struct __attribute__((packed)) { + uint32_t EIE:1; + uint32_t IREN:1; + uint32_t IRLP:1; + uint32_t HDSEL:1; + uint32_t NACK:1; + uint32_t SCEN:1; + uint32_t DMAR:1; + uint32_t DMAT:1; + uint32_t RTSE:1; + uint32_t CTSE:1; + uint32_t CTSIE:1; + uint32_t reserved3:21; + }; + uint32_t word; +}; + +union USART_GTPR { + struct __attribute__((packed)) { + uint32_t PSC:8; + uint32_t GT:8; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +struct __attribute__((packed)) USART { + union USART_SR SR; + union USART_DR DR; + union USART_BRR BRR; + union USART_CR1 CR1; + union USART_CR2 CR2; + union USART_CR3 CR3; + union USART_GTPR GTPR; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_USART_REGS_H_ + -- 2.45.2 From c1b3f0d073fc6b8cfa57a636c6ab45583bee1776 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 5 Jul 2023 22:20:53 +0200 Subject: [PATCH 32/85] Replace rcc's bitfields with macros Bitfields can use byte acces, which the bus doesn't permit. When that happens, the bus adds extra bytes to form a word, modifying fields that shouldn't be. Bitfields can be kept for debug and read, but writes must be done though masks --- drivers/rcc.c | 64 ++++++++++----- drivers/rcc.h | 8 ++ drivers/rcc_regs.h | 191 +++++++++++++++++++++++++++++++++++++++++++++ drivers/reg.h | 15 ++++ 4 files changed, 258 insertions(+), 20 deletions(-) create mode 100644 drivers/reg.h diff --git a/drivers/rcc.c b/drivers/rcc.c index c4c7bb0..20dfcff 100644 --- a/drivers/rcc.c +++ b/drivers/rcc.c @@ -25,6 +25,7 @@ static void apply_speed_preset(void); //--local variables------------------------------------------------------------- static volatile struct RCC* regs = (struct RCC*)RCC_BASE_ADDRESS; +static enum RccPreset current_preset = RCC_PRESET_DEFAULT; //--public functions------------------------------------------------------------ @@ -44,9 +45,11 @@ void rcc_configure(enum RccPreset preset) switch (preset) { case RCC_PRESET_DEFAULT: apply_default_preset(); + current_preset = RCC_PRESET_DEFAULT; break; case RCC_PRESET_SPEED: apply_speed_preset(); + current_preset = RCC_PRESET_SPEED; break; default: break; @@ -79,6 +82,26 @@ void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask) regs->APB2RSTR.word &= !(apb2_mask & APB2_MASK); } +void rcc_get_clocks(struct RccClocks* clocks) +{ + switch (current_preset) + { + case RCC_PRESET_DEFAULT: + clocks->ahb_freq = 8000000; + clocks->apb1_freq = 8000000; + clocks->apb2_freq = 8000000; + break; + case RCC_PRESET_SPEED: + clocks->ahb_freq = 72000000; + clocks->apb1_freq = 36000000; + clocks->apb2_freq = 72000000; + break; + default: + //TODO hardfault + break; + } +} + //--local functions------------------------------------------------------------- @@ -90,25 +113,26 @@ void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask) static void apply_default_preset(void) { //ensures HSI is enabled - regs->CR.HSION = 0x1; + reg_set(regs->CR, RCC_CR_HSION); while (regs->CR.HSIRDY != 0x1); //set HSI as main clock source and disable prescalers regs->CFGR.word &= ~0x077fff3; //disable all options - regs->CR.HSITRIM = 0x10; - regs->CR.HSEON = 0x0; - regs->CR.HSEBYP = 0x0; - regs->CR.CCSON = 0x0; - regs->CR.PLLON = 0x0; + reg_reset(regs->CR, RCC_CR_HSITRIM); + reg_write(regs->CR, RCC_CR_HSITRIM, 0x10); + reg_reset(regs->CR, RCC_CR_HSEON); + reg_reset(regs->CR, RCC_CR_HSEBYP); + reg_reset(regs->CR, RCC_CR_CCSON); + reg_reset(regs->CR, RCC_CR_PLLON); //disable all interrupts - regs->CIR.LSIRDYIE = 0x0; - regs->CIR.LSERDYIE = 0x0; - regs->CIR.HSIRDYIE = 0x0; - regs->CIR.HSERDYIE = 0x0; - regs->CIR.PLLRDYIE = 0x0; + reg_reset(regs->CIR, RCC_CIR_LSIRDYIE); + reg_reset(regs->CIR, RCC_CIR_LSERDYIE); + reg_reset(regs->CIR, RCC_CIR_HSIRDYIE); + reg_reset(regs->CIR, RCC_CIR_HSERDYIE); + reg_reset(regs->CIR, RCC_CIR_PLLRDYIE); //reconfigure flash flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED); @@ -125,35 +149,35 @@ static void apply_speed_preset(void) apply_default_preset(); //try enabling HSE, fallback to HSI if HSE fails - regs->CR.HSEON = 0x1; + reg_set(regs->CR, RCC_CR_HSEON); for (uint32_t i=0; i<1000; ++i) { __asm__("nop"); } if (regs->CR.HSERDY == 0x1) { - regs->CFGR.PLLSCR = 0x1; + reg_set(regs->CFGR, RCC_CFGR_PLLSCR); } else { - regs->CR.HSEON = 0; + reg_reset(regs->CR, RCC_CR_HSEON); } //configure PLL, fallback to HSI if PLL fails - regs->CFGR.PLLMUL = 0x7; //PLL x9 - regs->CR.PLLON = 0x1; + reg_write(regs->CFGR, RCC_CFGR_PLLMUL, 0x7); //PLL x9 + reg_set(regs->CR, RCC_CR_PLLON); for (uint32_t i=0; i<1000; ++i) { __asm__("nop"); } if (regs->CR.PLLRDY != 0x1) { - regs->CR.PLLON = 0x0; + reg_reset(regs->CR, RCC_CR_PLLON); return; //clock low enough, no need for prescalers } //configure prescalers - regs->CFGR.PPRE1 = 0x4; // /2 - regs->CFGR.ADCPRE = 0x2; // /6 + reg_write(regs->CFGR, RCC_CFGR_PPRE1, 0x4); // /2 + reg_write(regs->CFGR, RCC_CFGR_ADCPRE, 0x2); // /6 //reconfigure flash flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED); //switch to PLL output - regs->CFGR.SW = 0x2; + reg_write(regs->CFGR, RCC_CFGR_SW, 0x2); } diff --git a/drivers/rcc.h b/drivers/rcc.h index 61a5307..770b7a0 100644 --- a/drivers/rcc.h +++ b/drivers/rcc.h @@ -95,6 +95,12 @@ enum RccApb2 { RCC_APB2_TIM11 = (0x1 << 21), }; +struct RccClocks { + uint32_t ahb_freq; + uint32_t apb1_freq; + uint32_t apb2_freq; +}; + //--functions------------------------------------------------------------------- @@ -129,6 +135,8 @@ void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask, */ void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask); +void rcc_get_clocks(struct RccClocks* clocks); + #endif //_RCC_H_ diff --git a/drivers/rcc_regs.h b/drivers/rcc_regs.h index 047f7e9..44f7eff 100644 --- a/drivers/rcc_regs.h +++ b/drivers/rcc_regs.h @@ -11,6 +11,8 @@ //--includes-------------------------------------------------------------------- +#include "reg.h" + #include "stdint.h" @@ -37,6 +39,20 @@ union RCC_CR { uint32_t word; }; +#define RCC_CR_HSION reg_def( 0, 1) +#define RCC_CR_HSIRDY reg_def( 1, 1) +#define RCC_CR_reserved1 reg_def( 2, 1) +#define RCC_CR_HSITRIM reg_def( 3, 5) +#define RCC_CR_HSICAL reg_def( 8, 8) +#define RCC_CR_HSEON reg_def(16, 1) +#define RCC_CR_HSERDY reg_def(17, 1) +#define RCC_CR_HSEBYP reg_def(18, 1) +#define RCC_CR_CCSON reg_def(19, 1) +#define RCC_CR_reserved2 reg_def(20, 4) +#define RCC_CR_PLLON reg_def(24, 1) +#define RCC_CR_PLLRDY reg_def(25, 1) +#define RCC_CR_reserved3 reg_def(26, 6) + union RCC_CFGR { struct __attribute__((packed)) { uint32_t SW:2; @@ -56,6 +72,20 @@ union RCC_CFGR { uint32_t word; }; +#define RCC_CFGR_SW reg_def( 0, 2) +#define RCC_CFGR_SWS reg_def( 2, 2) +#define RCC_CFGR_HPRE reg_def( 4, 4) +#define RCC_CFGR_PPRE1 reg_def( 8, 3) +#define RCC_CFGR_PPRE2 reg_def(11, 3) +#define RCC_CFGR_ADCPRE reg_def(14, 2) +#define RCC_CFGR_PLLSCR reg_def(16, 1) +#define RCC_CFGR_PLLXTPRE reg_def(17, 1) +#define RCC_CFGR_PLLMUL reg_def(18, 4) +#define RCC_CFGR_USBPRE reg_def(22, 1) +#define RCC_CFGR_reserved1 reg_def(23, 1) +#define RCC_CFGR_MCO reg_def(24, 3) +#define RCC_CFGR_reserved2 reg_def(27, 5) + union RCC_CIR { struct __attribute__((packed)) { uint32_t LSIRDYF:1; @@ -83,6 +113,28 @@ union RCC_CIR { uint32_t word; }; +#define RCC_CIR_LSIRDYF reg_def( 0, 1) +#define RCC_CIR_LSERDYF reg_def( 1, 1) +#define RCC_CIR_HSIRDYF reg_def( 2, 1) +#define RCC_CIR_HSERDYF reg_def( 3, 1) +#define RCC_CIR_PLLRDYF reg_def( 4, 1) +#define RCC_CIR_reserved1 reg_def( 5, 2) +#define RCC_CIR_CSSF reg_def( 7, 1) +#define RCC_CIR_LSIRDYIE reg_def( 8, 1) +#define RCC_CIR_LSERDYIE reg_def( 9, 1) +#define RCC_CIR_HSIRDYIE reg_def(10, 1) +#define RCC_CIR_HSERDYIE reg_def(11, 1) +#define RCC_CIR_PLLRDYIE reg_def(12, 1) +#define RCC_CIR_RSE2 reg_def(13, 3) +#define RCC_CIR_LSIRDYC reg_def(16, 1) +#define RCC_CIR_LSERDYC reg_def(17, 1) +#define RCC_CIR_HSIRDYC reg_def(18, 1) +#define RCC_CIR_HSERDYC reg_def(19, 1) +#define RCC_CIR_PLLRDYC reg_def(20, 1) +#define RCC_CIR_reserved3 reg_def(21, 2) +#define RCC_CIR_CSSC reg_def(23, 1) +#define RCC_CIR_reserved4 reg_def(24, 8) + union RCC_APB2RSTR { struct __attribute__((packed)) { uint32_t AFIORST:1; @@ -110,6 +162,28 @@ union RCC_APB2RSTR { uint32_t word; }; +#define RCC_APB2RSTR_AFIORST reg_def( 0, 1) +#define RCC_APB2RSTR_reserved1 reg_def( 1, 1) +#define RCC_APB2RSTR_IOPARST reg_def( 2, 1) +#define RCC_APB2RSTR_IOPBRST reg_def( 3, 1) +#define RCC_APB2RSTR_IOPCRST reg_def( 4, 1) +#define RCC_APB2RSTR_IOPDRST reg_def( 5, 1) +#define RCC_APB2RSTR_IOPERST reg_def( 6, 1) +#define RCC_APB2RSTR_IOPFRST reg_def( 7, 1) +#define RCC_APB2RSTR_IOPGRST reg_def( 8, 1) +#define RCC_APB2RSTR_ADC1RST reg_def( 9, 1) +#define RCC_APB2RSTR_ACD2RST reg_def(10, 1) +#define RCC_APB2RSTR_TIM1RST reg_def(11, 1) +#define RCC_APB2RSTR_SPI1RST reg_def(12, 1) +#define RCC_APB2RSTR_TIM8RST reg_def(13, 1) +#define RCC_APB2RSTR_USART1RST reg_def(14, 1) +#define RCC_APB2RSTR_ADC3RST reg_def(15, 1) +#define RCC_APB2RSTR_reserved2 reg_def(16, 3) +#define RCC_APB2RSTR_TIM9RST reg_def(19, 1) +#define RCC_APB2RSTR_TIM10RST reg_def(20, 1) +#define RCC_APB2RSTR_TIM11RST reg_def(21, 1) +#define RCC_APB2RSTR_reserved3 reg_def(22, 10) + union RCC_APB1RSTR { struct __attribute__((packed)) { uint32_t TIM2RST:1; @@ -145,6 +219,36 @@ union RCC_APB1RSTR { uint32_t word; }; +#define RCC_APB1RSTR_TIM2RST reg_def( 0, 1) +#define RCC_APB1RSTR_TIM3RST reg_def( 1, 1) +#define RCC_APB1RSTR_TIM4RST reg_def( 2, 1) +#define RCC_APB1RSTR_TIM5RST reg_def( 3, 1) +#define RCC_APB1RSTR_TIM6RST reg_def( 4, 1) +#define RCC_APB1RSTR_TIM7RST reg_def( 5, 1) +#define RCC_APB1RSTR_TIM12RST reg_def( 6, 1) +#define RCC_APB1RSTR_TIM13RST reg_def( 7, 1) +#define RCC_APB1RSTR_TIM14RST reg_def( 8, 1) +#define RCC_APB1RSTR_reserved1 reg_def( 9, 2) +#define RCC_APB1RSTR_WWDGRST reg_def(11, 1) +#define RCC_APB1RSTR_reserved2 reg_def(12, 2) +#define RCC_APB1RSTR_SPI2RST reg_def(14, 1) +#define RCC_APB1RSTR_SPI3RST reg_def(15, 1) +#define RCC_APB1RSTR_reserved3 reg_def(16, 1) +#define RCC_APB1RSTR_USART2RST reg_def(17, 1) +#define RCC_APB1RSTR_USART3RST reg_def(18, 1) +#define RCC_APB1RSTR_UART4RST reg_def(19, 1) +#define RCC_APB1RSTR_UART5RST reg_def(20, 1) +#define RCC_APB1RSTR_I2C12RST reg_def(21, 1) +#define RCC_APB1RSTR_I2C2RST reg_def(22, 1) +#define RCC_APB1RSTR_USB2RST reg_def(23, 1) +#define RCC_APB1RSTR_reserved4 reg_def(24, 1) +#define RCC_APB1RSTR_CANRST reg_def(25, 1) +#define RCC_APB1RSTR_reserved5 reg_def(26, 1) +#define RCC_APB1RSTR_BKPRST reg_def(27, 1) +#define RCC_APB1RSTR_PWRRST reg_def(28, 1) +#define RCC_APB1RSTR_DACRST reg_def(29, 1) +#define RCC_APB1RSTR_reserved6 reg_def(30, 2) + union RCC_AHBENR { struct __attribute__((packed)) { uint32_t DMA1EN:1; @@ -163,6 +267,19 @@ union RCC_AHBENR { uint32_t word; }; +#define RCC_AHBENR_DMA1EN reg_def( 0, 1) +#define RCC_AHBENR_DMA2EN reg_def( 1, 1) +#define RCC_AHBENR_SRAMEN reg_def( 2, 1) +#define RCC_AHBENR_reserved1 reg_def( 3, 1) +#define RCC_AHBENR_FLITFEN reg_def( 4, 1) +#define RCC_AHBENR_reserved2 reg_def( 5, 1) +#define RCC_AHBENR_CRCEN reg_def( 6, 1) +#define RCC_AHBENR_reserved3 reg_def( 7, 1) +#define RCC_AHBENR_FSMCEN reg_def( 8, 1) +#define RCC_AHBENR_reserved4 reg_def( 9, 1) +#define RCC_AHBENR_SDIOEN reg_def(10, 1) +#define RCC_AHBENR_reserved5 reg_def(11, 21) + union RCC_APB2ENR { struct __attribute__((packed)) { uint32_t AFIOEN:1; @@ -190,6 +307,28 @@ union RCC_APB2ENR { uint32_t word; }; +#define RCC_APB2ENR_AFIOEN reg_def( 0, 1) +#define RCC_APB2ENR_reserved1 reg_def( 1, 1) +#define RCC_APB2ENR_IOPAEN reg_def( 2, 1) +#define RCC_APB2ENR_IOPBEN reg_def( 3, 1) +#define RCC_APB2ENR_IOPCEN reg_def( 4, 1) +#define RCC_APB2ENR_IOPDEN reg_def( 5, 1) +#define RCC_APB2ENR_IOPEEN reg_def( 6, 1) +#define RCC_APB2ENR_IOPFEN reg_def( 7, 1) +#define RCC_APB2ENR_IOPGEN reg_def( 8, 1) +#define RCC_APB2ENR_ADC1EN reg_def( 9, 1) +#define RCC_APB2ENR_ACD2EN reg_def(10, 1) +#define RCC_APB2ENR_TIM1EN reg_def(11, 1) +#define RCC_APB2ENR_SPI1EN reg_def(12, 1) +#define RCC_APB2ENR_TIM8EN reg_def(13, 1) +#define RCC_APB2ENR_USART1EN reg_def(14, 1) +#define RCC_APB2ENR_ADC3EN reg_def(15, 1) +#define RCC_APB2ENR_reserved2 reg_def(16, 3) +#define RCC_APB2ENR_TIM9EN reg_def(19, 1) +#define RCC_APB2ENR_TIM10EN reg_def(20, 1) +#define RCC_APB2ENR_TIM11EN reg_def(21, 1) +#define RCC_APB2ENR_reserved3 reg_def(22, 10) + union RCC_APB1ENR { struct __attribute__((packed)) { uint32_t TIM2EN:1; @@ -225,6 +364,36 @@ union RCC_APB1ENR { uint32_t word; }; +#define RCC_APB1ENR_TIM2EN reg_def( 0, 1) +#define RCC_APB1ENR_TIM3EN reg_def( 1, 1) +#define RCC_APB1ENR_TIM4EN reg_def( 2, 1) +#define RCC_APB1ENR_TIM5EN reg_def( 3, 1) +#define RCC_APB1ENR_TIM6EN reg_def( 4, 1) +#define RCC_APB1ENR_TIM7EN reg_def( 5, 1) +#define RCC_APB1ENR_TIM12EN reg_def( 6, 1) +#define RCC_APB1ENR_TIM13EN reg_def( 7, 1) +#define RCC_APB1ENR_TIM14EN reg_def( 8, 1) +#define RCC_APB1ENR_reserved1 reg_def( 9, 2) +#define RCC_APB1ENR_WWDGEN reg_def(11, 1) +#define RCC_APB1ENR_reserved reg_def(12, 2) +#define RCC_APB1ENR_SPI2EN reg_def(14, 1) +#define RCC_APB1ENR_SPI3EN reg_def(15, 1) +#define RCC_APB1ENR_reserved2 reg_def(16, 1) +#define RCC_APB1ENR_USART2EN reg_def(17, 1) +#define RCC_APB1ENR_USART3EN reg_def(18, 1) +#define RCC_APB1ENR_UART4EN reg_def(19, 1) +#define RCC_APB1ENR_UART5EN reg_def(20, 1) +#define RCC_APB1ENR_I2C12EN reg_def(21, 1) +#define RCC_APB1ENR_I2C2EN reg_def(22, 1) +#define RCC_APB1ENR_USB2EN reg_def(23, 1) +#define RCC_APB1ENR_reserved3 reg_def(24, 1) +#define RCC_APB1ENR_CANEN reg_def(25, 1) +#define RCC_APB1ENR_reserved4 reg_def(26, 1) +#define RCC_APB1ENR_BKPEN reg_def(27, 1) +#define RCC_APB1ENR_PWREN reg_def(28, 1) +#define RCC_APB1ENR_DACEN reg_def(29, 1) +#define RCC_APB1ENR_reserved5 reg_def(30, 2) + union RCC_BDCR { struct __attribute__((packed)) { uint32_t LSEON:1; @@ -240,6 +409,16 @@ union RCC_BDCR { uint32_t word; }; +#define RCC_BDCR_LSEON reg_def( 0, 1) +#define RCC_BDCR_LSERDY reg_def( 1, 1) +#define RCC_BDCR_LSEBYP reg_def( 2, 1) +#define RCC_BDCR_reserved1 reg_def( 3, 5) +#define RCC_BDCR_RTCSEL reg_def( 8, 2) +#define RCC_BDCR_reserved2 reg_def(10, 5) +#define RCC_BDCR_RTCEN reg_def(15, 1) +#define RCC_BDCR_BDRST reg_def(16, 1) +#define RCC_BDCR_reserved3 reg_def(17, 15) + union RCC_CSR { struct __attribute__((packed)) { uint32_t LSION:1; @@ -257,6 +436,18 @@ union RCC_CSR { uint32_t word; }; +#define RCC_CSR_LSION reg_def( 0, 1) +#define RCC_CSR_LSIRDY reg_def( 1, 1) +#define RCC_CSR_reserved1 reg_def( 2, 22) +#define RCC_CSR_RMVF reg_def(24, 1) +#define RCC_CSR_reserved2 reg_def(25, 1) +#define RCC_CSR_PINRSTF reg_def(26, 1) +#define RCC_CSR_PORRSTF reg_def(27, 1) +#define RCC_CSR_SFTRSTF reg_def(28, 1) +#define RCC_CSR_IWDGRSTF reg_def(29, 1) +#define RCC_CSR_WWDGRSTF reg_def(30, 1) +#define RCC_CSR_LPWRSTF reg_def(31, 1) + struct __attribute__((packed)) RCC { union RCC_CR CR; union RCC_CFGR CFGR; diff --git a/drivers/reg.h b/drivers/reg.h new file mode 100644 index 0000000..05cdc19 --- /dev/null +++ b/drivers/reg.h @@ -0,0 +1,15 @@ + +#define reg_def(pos, size) pos, (((0x1 << size) - 1) << pos) + +#define reg_set(reg, field) _reg_set(reg, field) +#define _reg_set(reg, pos, mask) do { reg.word |= mask; } while (false) + +#define reg_reset(reg, field) _reg_reset(reg, field) +#define _reg_reset(reg, pos, mask) do { reg.word &= ~mask; } while (false) + +#define reg_write(reg, field, value) _reg_write(reg, field, value) +#define _reg_write(reg, pos, mask, value) \ +do { \ + reg.word |= value << pos; \ +} while (false) \ + -- 2.45.2 From 97069790281b4bbe3b9b0968d5cdd747e0158988 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 5 Jul 2023 22:23:31 +0200 Subject: [PATCH 33/85] Apply new mask system to usart's regs --- drivers/usart_regs.h | 67 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/usart_regs.h b/drivers/usart_regs.h index 3e66200..863ae1d 100644 --- a/drivers/usart_regs.h +++ b/drivers/usart_regs.h @@ -11,6 +11,8 @@ //--includes-------------------------------------------------------------------- +#include "reg.h" + #include "stdint.h" @@ -37,6 +39,18 @@ union USART_SR { uint32_t word; }; +#define USART_SR_PE reg_def( 0, 1) +#define USART_SR_FE reg_def( 1, 1) +#define USART_SR_NE reg_def( 2, 1) +#define USART_SR_ORE reg_def( 3, 1) +#define USART_SR_IDLE reg_def( 4, 1) +#define USART_SR_RXNE reg_def( 5, 1) +#define USART_SR_TC reg_def( 6, 1) +#define USART_SR_TXE reg_def( 7, 1) +#define USART_SR_LBD reg_def( 8, 1) +#define USART_SR_CTS reg_def( 9, 1) +#define USART_SR_reserved1 reg_def(10, 22) + union USART_DR { struct __attribute__((packed)) { uint32_t DR:9; @@ -45,6 +59,9 @@ union USART_DR { uint32_t word; }; +#define USART_DR_DR reg_def( 0, 9) +#define USART_DR_reserved1 reg_def( 9, 23) + union USART_BRR { struct __attribute__((packed)) { uint32_t DIV_Fraction:4; @@ -54,6 +71,10 @@ union USART_BRR { uint32_t word; }; +#define USART_BRR_DIV_Fraction reg_def( 0, 4) +#define USART_BRR_DIV_Mantissa reg_def( 4, 12) +#define USART_BRR_reserved1 reg_def(16, 16) + union USART_CR1 { struct __attribute__((packed)) { uint32_t SBK:1; @@ -75,6 +96,22 @@ union USART_CR1 { uint32_t word; }; +#define USART_CR1_SBK reg_def( 0, 1) +#define USART_CR1_RWU reg_def( 1, 1) +#define USART_CR1_RE reg_def( 2, 1) +#define USART_CR1_TE reg_def( 3, 1) +#define USART_CR1_IDLEIE reg_def( 4, 1) +#define USART_CR1_RXNEIE reg_def( 5, 1) +#define USART_CR1_TCIE reg_def( 6, 1) +#define USART_CR1_TXEIE reg_def( 7, 1) +#define USART_CR1_PEI reg_def( 8, 1) +#define USART_CR1_PS reg_def( 9, 1) +#define USART_CR1_PCE reg_def(10, 1) +#define USART_CR1_WAKE reg_def(11, 1) +#define USART_CR1_M reg_def(12, 1) +#define USART_CR1_UE reg_def(13, 1) +#define USART_CR1_reserved1 reg_def(14, 18) + union USART_CR2 { struct __attribute__((packed)) { uint32_t ADD:4; @@ -93,6 +130,19 @@ union USART_CR2 { uint32_t word; }; +#define USART_CR2_ADD reg_def( 0, 4) +#define USART_CR2_reserved1 reg_def( 4, 1) +#define USART_CR2_LBDL reg_def( 5, 1) +#define USART_CR2_LBDIE reg_def( 6, 1) +#define USART_CR2_reserved2 reg_def( 7, 1) +#define USART_CR2_LBCL reg_def( 8, 1) +#define USART_CR2_CPHA reg_def( 9, 1) +#define USART_CR2_CPOL reg_def(10, 1) +#define USART_CR2_CLKEN reg_def(11, 1) +#define USART_CR2_STOP reg_def(12, 2) +#define USART_CR2_LINEN reg_def(14, 1) +#define USART_CR2_reserved3 reg_def(15, 17) + union USART_CR3 { struct __attribute__((packed)) { uint32_t EIE:1; @@ -111,6 +161,19 @@ union USART_CR3 { uint32_t word; }; +#define UART_CR3_EIE reg_def( 0, 1) +#define UART_CR3_IREN reg_def( 1, 1) +#define UART_CR3_IRLP reg_def( 2, 1) +#define UART_CR3_HDSEL reg_def( 3, 1) +#define UART_CR3_NACK reg_def( 4, 1) +#define UART_CR3_SCEN reg_def( 5, 1) +#define UART_CR3_DMAR reg_def( 6, 1) +#define UART_CR3_DMAT reg_def( 7, 1) +#define UART_CR3_RTSE reg_def( 8, 1) +#define UART_CR3_CTSE reg_def( 9, 1) +#define UART_CR3_CTSIE reg_def(10, 1) +#define UART_CR3_reserved3 reg_def(11, 21) + union USART_GTPR { struct __attribute__((packed)) { uint32_t PSC:8; @@ -120,6 +183,10 @@ union USART_GTPR { uint32_t word; }; +#define USART_GTPR_PSC reg_def( 0, 8) +#define USART_GTPR_GT reg_def( 8, 8) +#define USART_GTPR_reserved1 reg_def(16, 16) + struct __attribute__((packed)) USART { union USART_SR SR; union USART_DR DR; -- 2.45.2 From c8040cf62f71a4d87dd2a2c107331686f3e7e490 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 5 Jul 2023 22:24:02 +0200 Subject: [PATCH 34/85] Implement usart's basic function This code doesn't work quite right yet, must most of the control system is in place --- drivers/usart.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usart.h | 51 +++++++++++++++ 2 files changed, 220 insertions(+) create mode 100644 drivers/usart.c create mode 100644 drivers/usart.h diff --git a/drivers/usart.c b/drivers/usart.c new file mode 100644 index 0000000..4822784 --- /dev/null +++ b/drivers/usart.c @@ -0,0 +1,169 @@ +/** @file usart.c + * Module handling Universal Synchronous/Asynchronous Receiver/Transmitter + * + * The module provides functions to configure the usarts and read/write from/to + * it + */ + +//--includes-------------------------------------------------------------------- + +#include "usart.h" +#include "usart_regs.h" +#include "reg.h" + +#include "rcc.h" + + +//--local definitions----------------------------------------------------------- + +static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; +static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; +static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; + +void configure_usart(volatile struct USART* regs, enum UsartConfig config); +void configure_baudrate(volatile struct USART* regs, uint32_t clock, + uint32_t baudrate); + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +void usart_configure(enum UsartPeriph periph, enum UsartConfig config, + uint32_t baudrate) +{ + struct RccClocks clocks; + rcc_get_clocks(&clocks); + + switch (periph) { + case USART_PERIPH_1: + rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); + configure_baudrate(usart1, clocks.apb2_freq, baudrate); + configure_usart(usart1, config); + break; + case USART_PERIPH_2: + rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); + configure_baudrate(usart2, clocks.apb1_freq, baudrate); + configure_usart(usart2, config); + break; + case USART_PERIPH_3: + rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE); + configure_baudrate(usart3, clocks.apb1_freq, baudrate); + configure_usart(usart3, config); + break; + default: + break; + } +} + +uint8_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) +{ + switch (periph) { + case USART_PERIPH_1: + if (usart1->SR.TXE) { + reg_write(usart1->DR, USART_DR_DR, byte); + return 0; + } else { + return 1; + } + + case USART_PERIPH_2: + case USART_PERIPH_3: + default: + break; + } + + return 1; +} + +//--local functions------------------------------------------------------------- + +void configure_usart(volatile struct USART* regs, enum UsartConfig config) +{ + //configure parity + switch (config) + { + case USART_CONFIG_7E1: + case USART_CONFIG_8E1: + case USART_CONFIG_7E2: + case USART_CONFIG_8E2: + reg_set(regs->CR1, USART_CR1_PCE); + reg_reset(regs->CR1, USART_CR1_PS); + break; + case USART_CONFIG_7O1: + case USART_CONFIG_7O2: + case USART_CONFIG_8O1: + case USART_CONFIG_8O2: + reg_set(regs->CR1, USART_CR1_PCE); + reg_set(regs->CR1, USART_CR1_PS); + break; + case USART_CONFIG_8N1: + case USART_CONFIG_8N2: + reg_reset(regs->CR1, USART_CR1_PCE); + break; + default: + break; + } + + //configure bit number + switch (config) + { + case USART_CONFIG_7E1: + case USART_CONFIG_7E2: + case USART_CONFIG_7O1: + case USART_CONFIG_7O2: + case USART_CONFIG_8N1: + case USART_CONFIG_8N2: + reg_reset(regs->CR1, USART_CR1_M); + break; + case USART_CONFIG_8E2: + case USART_CONFIG_8E1: + case USART_CONFIG_8O1: + case USART_CONFIG_8O2: + reg_set(regs->CR1, USART_CR1_M); + break; + default: + break; + } + + //configure stop bits + switch (config) + { + case USART_CONFIG_7E1: + case USART_CONFIG_7O1: + case USART_CONFIG_8N1: + case USART_CONFIG_8E1: + case USART_CONFIG_8O1: + reg_reset(regs->CR2, USART_CR2_STOP); + break; + case USART_CONFIG_7E2: + case USART_CONFIG_7O2: + case USART_CONFIG_8N2: + case USART_CONFIG_8E2: + case USART_CONFIG_8O2: + reg_reset(regs->CR2, USART_CR2_STOP); + reg_write(regs->CR2, USART_CR2_STOP, 2); + break; + default: + break; + } + + //enable Rx/Tx + reg_set(regs->CR1, USART_CR1_TE); + reg_set(regs->CR1, USART_CR1_RE); + reg_set(regs->CR1, USART_CR1_UE); +} + +void configure_baudrate(volatile struct USART* regs, uint32_t clock, + uint32_t baudrate) +{ + uint32_t mantissa = clock / (baudrate * 16); + uint32_t factor = clock / baudrate; + volatile uint32_t divider = factor - (mantissa * 16); + + reg_reset(regs->BRR, USART_BRR_DIV_Mantissa); + reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF); + reg_reset(regs->BRR, USART_BRR_DIV_Fraction); + reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); +} + diff --git a/drivers/usart.h b/drivers/usart.h new file mode 100644 index 0000000..8c15f2a --- /dev/null +++ b/drivers/usart.h @@ -0,0 +1,51 @@ +/** @file usart.h + * Module handling Universal Synchronous/Asynchronous Receiver/Transmitter + * + * The module provides functions to configure the usarts and read/write from/to + * it + */ + +#ifndef _USART_H_ +#define _USART_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +enum UsartPeriph { + USART_PERIPH_1, + USART_PERIPH_2, + USART_PERIPH_3, +}; + +enum UsartConfig { + USART_CONFIG_7E1, + USART_CONFIG_7E2, + USART_CONFIG_7O1, + USART_CONFIG_7O2, + USART_CONFIG_8N1, + USART_CONFIG_8N2, + USART_CONFIG_8E1, + USART_CONFIG_8E2, + USART_CONFIG_8O1, + USART_CONFIG_8O2, +}; + + +//--functions------------------------------------------------------------------- + +void usart_configure(enum UsartPeriph periph, enum UsartConfig config, + uint32_t baudrate); + +void usart_reset(enum UsartPeriph periph); + +uint8_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); + +uint8_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); + + +#endif //_USART_H_ + -- 2.45.2 From 073be3f980871890eb123ed1c87d7df5644392f8 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 5 Jul 2023 22:51:31 +0200 Subject: [PATCH 35/85] Fix macro parameter --- drivers/reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reg.h b/drivers/reg.h index 05cdc19..5334e18 100644 --- a/drivers/reg.h +++ b/drivers/reg.h @@ -7,7 +7,7 @@ #define reg_reset(reg, field) _reg_reset(reg, field) #define _reg_reset(reg, pos, mask) do { reg.word &= ~mask; } while (false) -#define reg_write(reg, field, value) _reg_write(reg, field, value) +#define reg_write(reg, field, value) _reg_write(reg, field, (value)) #define _reg_write(reg, pos, mask, value) \ do { \ reg.word |= value << pos; \ -- 2.45.2 From 26bb798b7969af4ce0539639d0e419b11e008723 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 5 Jul 2023 23:05:03 +0200 Subject: [PATCH 36/85] Add usart's read function --- drivers/usart.c | 61 +++++++++++++++++++++++++++++++++++++------------ drivers/usart.h | 4 ++-- 2 files changed, 48 insertions(+), 17 deletions(-) diff --git a/drivers/usart.c b/drivers/usart.c index 4822784..017df30 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -23,6 +23,7 @@ static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; void configure_usart(volatile struct USART* regs, enum UsartConfig config); void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); +uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs); //--local variables------------------------------------------------------------- @@ -56,24 +57,34 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, } } -uint8_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) +uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { - switch (periph) { - case USART_PERIPH_1: - if (usart1->SR.TXE) { - reg_write(usart1->DR, USART_DR_DR, byte); - return 0; - } else { - return 1; - } - - case USART_PERIPH_2: - case USART_PERIPH_3: - default: - break; + volatile struct USART* regs; + if (periph_regs(periph, ®s)) { + return 1; } - return 1; + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + return 0; + } else { + return 1; + } +} + +uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) +{ + volatile struct USART* regs; + if (periph_regs(periph, ®s)) { + return 1; + } + + if (regs->SR.RXNE) { + *byte = regs->DR.DR; + return 0; + } else { + return 1; + } } //--local functions------------------------------------------------------------- @@ -167,3 +178,23 @@ void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } +uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs) +{ + switch (periph) { + case USART_PERIPH_1: + *regs = usart1; + break; + case USART_PERIPH_2: + *regs = usart2; + break; + case USART_PERIPH_3: + *regs = usart3; + break; + default: + return 1; + break; + } + + return 0; +} + diff --git a/drivers/usart.h b/drivers/usart.h index 8c15f2a..c5845c1 100644 --- a/drivers/usart.h +++ b/drivers/usart.h @@ -42,9 +42,9 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, void usart_reset(enum UsartPeriph periph); -uint8_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); +uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); -uint8_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); +uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); #endif //_USART_H_ -- 2.45.2 From ebe30a4a7aa64dcf98d196bea51839da462e2fa5 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 7 Jul 2023 17:41:18 +0200 Subject: [PATCH 37/85] Replace exti's bitfields with macros --- drivers/exti.c | 16 +++--- drivers/exti_regs.h | 128 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 8 deletions(-) diff --git a/drivers/exti.c b/drivers/exti.c index 4f518e1..1139105 100644 --- a/drivers/exti.c +++ b/drivers/exti.c @@ -193,35 +193,35 @@ void exti_reset_peripheral(void) void hdr_exti0(void) { nvic_clear_pending(NVIC_IRQ_EXTI0); - regs->PR.PR0 = 1; + reg_set(regs->PR, EXTI_PR_PR0); callbacks[0](); } void hdr_exti1(void) { nvic_clear_pending(NVIC_IRQ_EXTI1); - regs->PR.PR1 = 1; + reg_set(regs->PR, EXTI_PR_PR1); callbacks[1](); } void hdr_exti2(void) { nvic_clear_pending(NVIC_IRQ_EXTI2); - regs->PR.PR2 = 1; + reg_set(regs->PR, EXTI_PR_PR2); callbacks[2](); } void hdr_exti3(void) { nvic_clear_pending(NVIC_IRQ_EXTI3); - regs->PR.PR3 = 1; + reg_set(regs->PR, EXTI_PR_PR3); callbacks[3](); } void hdr_exti4(void) { nvic_clear_pending(NVIC_IRQ_EXTI4); - regs->PR.PR4 = 1; + reg_set(regs->PR, EXTI_PR_PR4); callbacks[4](); } @@ -250,21 +250,21 @@ void hdr_exti15_10(void) void hdr_pvd(void) { nvic_clear_pending(NVIC_IRQ_PVD); - regs->PR.PR16 = 1; + reg_set(regs->PR, EXTI_PR_PR16); callbacks[16](); } void hdr_rtc_alarm(void) { nvic_clear_pending(NVIC_IRQ_RTC_ALARM); - regs->PR.PR17 = 1; + reg_set(regs->PR, EXTI_PR_PR17); callbacks[17](); } void hdr_usb_wakeup(void) { nvic_clear_pending(NVIC_IRQ_USB_WAKEUP); - regs->PR.PR18 = 1; + reg_set(regs->PR, EXTI_PR_PR18); callbacks[18](); } diff --git a/drivers/exti_regs.h b/drivers/exti_regs.h index c5d884f..74c0ddd 100644 --- a/drivers/exti_regs.h +++ b/drivers/exti_regs.h @@ -11,6 +11,8 @@ //--includes-------------------------------------------------------------------- +#include "reg.h" + #include "stdint.h" @@ -44,6 +46,27 @@ union EXTI_IMR { uint32_t word; }; +#define EXTI_IMR_MR0 reg_def( 0, 1) +#define EXTI_IMR_MR1 reg_def( 1, 1) +#define EXTI_IMR_MR2 reg_def( 2, 1) +#define EXTI_IMR_MR3 reg_def( 3, 1) +#define EXTI_IMR_MR4 reg_def( 4, 1) +#define EXTI_IMR_MR5 reg_def( 5, 1) +#define EXTI_IMR_MR6 reg_def( 6, 1) +#define EXTI_IMR_MR7 reg_def( 7, 1) +#define EXTI_IMR_MR8 reg_def( 8, 1) +#define EXTI_IMR_MR9 reg_def( 9, 1) +#define EXTI_IMR_MR10 reg_def(10, 1) +#define EXTI_IMR_MR11 reg_def(11, 1) +#define EXTI_IMR_MR12 reg_def(12, 1) +#define EXTI_IMR_MR13 reg_def(13, 1) +#define EXTI_IMR_MR14 reg_def(14, 1) +#define EXTI_IMR_MR15 reg_def(15, 1) +#define EXTI_IMR_MR16 reg_def(16, 1) +#define EXTI_IMR_MR17 reg_def(17, 1) +#define EXTI_IMR_MR18 reg_def(18, 1) +#define EXTI_IMR_reserved1 reg_def(19, 13) + union EXTI_EMR { struct __attribute__((packed)) { uint32_t MR0:1; @@ -70,6 +93,27 @@ union EXTI_EMR { uint32_t word; }; +#define EXTI_EMR_MR0 reg_def( 0, 1) +#define EXTI_EMR_MR1 reg_def( 1, 1) +#define EXTI_EMR_MR2 reg_def( 2, 1) +#define EXTI_EMR_MR3 reg_def( 3, 1) +#define EXTI_EMR_MR4 reg_def( 4, 1) +#define EXTI_EMR_MR5 reg_def( 5, 1) +#define EXTI_EMR_MR6 reg_def( 6, 1) +#define EXTI_EMR_MR7 reg_def( 7, 1) +#define EXTI_EMR_MR8 reg_def( 8, 1) +#define EXTI_EMR_MR9 reg_def( 9, 1) +#define EXTI_EMR_MR10 reg_def(10, 1) +#define EXTI_EMR_MR11 reg_def(11, 1) +#define EXTI_EMR_MR12 reg_def(12, 1) +#define EXTI_EMR_MR13 reg_def(13, 1) +#define EXTI_EMR_MR14 reg_def(14, 1) +#define EXTI_EMR_MR15 reg_def(15, 1) +#define EXTI_EMR_MR16 reg_def(16, 1) +#define EXTI_EMR_MR17 reg_def(17, 1) +#define EXTI_EMR_MR18 reg_def(18, 1) +#define EXTI_EMR_reserved1 reg_def(19, 13) + union EXTI_RTSR { struct __attribute__((packed)) { uint32_t TR0:1; @@ -96,6 +140,27 @@ union EXTI_RTSR { uint32_t word; }; +#define EXTI_RTSR_TR0 reg_def( 0, 1) +#define EXTI_RTSR_TR1 reg_def( 1, 1) +#define EXTI_RTSR_TR2 reg_def( 2, 1) +#define EXTI_RTSR_TR3 reg_def( 3, 1) +#define EXTI_RTSR_TR4 reg_def( 4, 1) +#define EXTI_RTSR_TR5 reg_def( 5, 1) +#define EXTI_RTSR_TR6 reg_def( 6, 1) +#define EXTI_RTSR_TR7 reg_def( 7, 1) +#define EXTI_RTSR_TR8 reg_def( 8, 1) +#define EXTI_RTSR_TR9 reg_def( 9, 1) +#define EXTI_RTSR_TR10 reg_def(10, 1) +#define EXTI_RTSR_TR11 reg_def(11, 1) +#define EXTI_RTSR_TR12 reg_def(12, 1) +#define EXTI_RTSR_TR13 reg_def(13, 1) +#define EXTI_RTSR_TR14 reg_def(14, 1) +#define EXTI_RTSR_TR15 reg_def(15, 1) +#define EXTI_RTSR_TR16 reg_def(16, 1) +#define EXTI_RTSR_TR17 reg_def(17, 1) +#define EXTI_RTSR_TR18 reg_def(18, 1) +#define EXTI_RTSR_reserved1 reg_def(19, 13) + union EXTI_FTSR { struct __attribute__((packed)) { uint32_t TR0:1; @@ -122,6 +187,27 @@ union EXTI_FTSR { uint32_t word; }; +#define EXTI_FTSR_TR0 reg_def( 0, 1) +#define EXTI_FTSR_TR1 reg_def( 1, 1) +#define EXTI_FTSR_TR2 reg_def( 2, 1) +#define EXTI_FTSR_TR3 reg_def( 3, 1) +#define EXTI_FTSR_TR4 reg_def( 4, 1) +#define EXTI_FTSR_TR5 reg_def( 5, 1) +#define EXTI_FTSR_TR6 reg_def( 6, 1) +#define EXTI_FTSR_TR7 reg_def( 7, 1) +#define EXTI_FTSR_TR8 reg_def( 8, 1) +#define EXTI_FTSR_TR9 reg_def( 9, 1) +#define EXTI_FTSR_TR10 reg_def(10, 1) +#define EXTI_FTSR_TR11 reg_def(11, 1) +#define EXTI_FTSR_TR12 reg_def(12, 1) +#define EXTI_FTSR_TR13 reg_def(13, 1) +#define EXTI_FTSR_TR14 reg_def(14, 1) +#define EXTI_FTSR_TR15 reg_def(15, 1) +#define EXTI_FTSR_TR16 reg_def(16, 1) +#define EXTI_FTSR_TR17 reg_def(17, 1) +#define EXTI_FTSR_TR18 reg_def(18, 1) +#define EXTI_FTSR_reserved1 reg_def(19, 13) + union EXTI_SWIER { struct __attribute__((packed)) { uint32_t SWIER0:1; @@ -148,6 +234,27 @@ union EXTI_SWIER { uint32_t word; }; +#define EXTI_SWIER_SWIER0 reg_def( 0, 1) +#define EXTI_SWIER_SWIER1 reg_def( 1, 1) +#define EXTI_SWIER_SWIER2 reg_def( 2, 1) +#define EXTI_SWIER_SWIER3 reg_def( 3, 1) +#define EXTI_SWIER_SWIER4 reg_def( 4, 1) +#define EXTI_SWIER_SWIER5 reg_def( 5, 1) +#define EXTI_SWIER_SWIER6 reg_def( 6, 1) +#define EXTI_SWIER_SWIER7 reg_def( 7, 1) +#define EXTI_SWIER_SWIER8 reg_def( 8, 1) +#define EXTI_SWIER_SWIER9 reg_def( 9, 1) +#define EXTI_SWIER_SWIER10 reg_def(10, 1) +#define EXTI_SWIER_SWIER11 reg_def(11, 1) +#define EXTI_SWIER_SWIER12 reg_def(12, 1) +#define EXTI_SWIER_SWIER13 reg_def(13, 1) +#define EXTI_SWIER_SWIER14 reg_def(14, 1) +#define EXTI_SWIER_SWIER15 reg_def(15, 1) +#define EXTI_SWIER_SWIER16 reg_def(16, 1) +#define EXTI_SWIER_SWIER17 reg_def(17, 1) +#define EXTI_SWIER_SWIER18 reg_def(18, 1) +#define EXTI_SWIER_reserved1 reg_def(19, 13) + union EXTI_PR { struct __attribute__((packed)) { uint32_t PR0:1; @@ -174,6 +281,27 @@ union EXTI_PR { uint32_t word; }; +#define EXTI_PR_PR0 reg_def( 0, 1) +#define EXTI_PR_PR1 reg_def( 1, 1) +#define EXTI_PR_PR2 reg_def( 2, 1) +#define EXTI_PR_PR3 reg_def( 3, 1) +#define EXTI_PR_PR4 reg_def( 4, 1) +#define EXTI_PR_PR5 reg_def( 5, 1) +#define EXTI_PR_PR6 reg_def( 6, 1) +#define EXTI_PR_PR7 reg_def( 7, 1) +#define EXTI_PR_PR8 reg_def( 8, 1) +#define EXTI_PR_PR9 reg_def( 9, 1) +#define EXTI_PR_PR10 reg_def(10, 1) +#define EXTI_PR_PR11 reg_def(11, 1) +#define EXTI_PR_PR12 reg_def(12, 1) +#define EXTI_PR_PR13 reg_def(13, 1) +#define EXTI_PR_PR14 reg_def(14, 1) +#define EXTI_PR_PR15 reg_def(15, 1) +#define EXTI_PR_PR16 reg_def(16, 1) +#define EXTI_PR_PR17 reg_def(17, 1) +#define EXTI_PR_PR18 reg_def(18, 1) +#define EXTI_PR_reserved1 reg_def(19, 13) + struct __attribute__((packed)) EXTI { union EXTI_IMR IMR; union EXTI_EMR EMR; -- 2.45.2 From dfccfd9591b68a961b325766fcd889d115629a9d Mon Sep 17 00:00:00 2001 From: Steins7 Date: Fri, 7 Jul 2023 17:46:04 +0200 Subject: [PATCH 38/85] Replace flash's bitfields with macros --- drivers/flash.c | 8 +++++--- drivers/flash_regs.h | 8 ++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/flash.c b/drivers/flash.c index 3219253..3378d06 100644 --- a/drivers/flash.c +++ b/drivers/flash.c @@ -34,13 +34,15 @@ void flash_configure(enum FlashPreset preset) //apply new configuration switch (preset) { case FLASH_PRESET_LOW_CLOCK_SPEED: - regs->ACR.HLFCYA = 0x1; //half cycle for power saving + reg_set(regs->ACR, FLASH_ACR_HLFCYA); //half cycle for power saving break; case FLASH_PRESET_MEDIUM_CLOCK_SPEED: - regs->ACR.LATENCY = 0x1; + reg_reset(regs->ACR, FLASH_ACR_LATENCY); + reg_write(regs->ACR, FLASH_ACR_LATENCY, 0x1); break; case FLASH_PRESET_HIGH_CLOCK_SPEED: - regs->ACR.LATENCY = 0x2; + reg_reset(regs->ACR, FLASH_ACR_LATENCY); + reg_write(regs->ACR, FLASH_ACR_LATENCY, 0x2); break; default: break; diff --git a/drivers/flash_regs.h b/drivers/flash_regs.h index 26f4593..de1068a 100644 --- a/drivers/flash_regs.h +++ b/drivers/flash_regs.h @@ -11,6 +11,8 @@ //--includes-------------------------------------------------------------------- +#include "reg.h" + #include "stdint.h" @@ -29,6 +31,12 @@ union FLASH_ACR { uint32_t word; }; +#define FLASH_ACR_LATENCY reg_def(0, 3) +#define FLASH_ACR_HLFCYA reg_def(3, 1) +#define FLASH_ACR_PRFTBE reg_def(4, 1) +#define FLASH_ACR_PRFTBS reg_def(5, 1) +#define FLASH_ACR_reserved1 reg_def(6, 26) + union FLASH_KEYR { struct __attribute__((packed)) { uint32_t reserved1; //TODO -- 2.45.2 From 6ddc2266e157ac36101e9e46b0407ded5d6344d4 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:13:05 +0200 Subject: [PATCH 39/85] Create dma's register map --- drivers/dma_regs.h | 216 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 drivers/dma_regs.h diff --git a/drivers/dma_regs.h b/drivers/dma_regs.h new file mode 100644 index 0000000..bfbb8f9 --- /dev/null +++ b/drivers/dma_regs.h @@ -0,0 +1,216 @@ +/** @file dma_regs.h + * Module defining the DMA registers. + * + * Mainly made to be used by the dma module. It is recommanded to go through + * the functions provided by that module instead of directly using the registers + * defined here. + */ + +#ifndef _DMA_REGS_H_ +#define _DMA_REGS_H_ + +//--includes-------------------------------------------------------------------- + +#include "reg.h" + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +#define DMA1_BASE_ADDRESS 0x40020000 +#define DMA2_BASE_ADDRESS 0x40020400 + +union DMA_ISR { + struct __attribute__((packed)) { + uint32_t GIF1:1; + uint32_t TCIF1:1; + uint32_t HTIF1:1; + uint32_t TEIF1:1; + uint32_t GIF2:1; + uint32_t TCIF2:1; + uint32_t HTIF2:1; + uint32_t TEIF2:1; + uint32_t GIF3:1; + uint32_t TCIF3:1; + uint32_t HTIF3:1; + uint32_t TEIF3:1; + uint32_t GIF4:1; + uint32_t TCIF4:1; + uint32_t HTIF4:1; + uint32_t TEIF4:1; + uint32_t GIF5:1; + uint32_t TCIF5:1; + uint32_t HTIF5:1; + uint32_t TEIF5:1; + uint32_t GIF6:1; + uint32_t TCIF6:1; + uint32_t HTIF6:1; + uint32_t TEIF6:1; + uint32_t GIF7:1; + uint32_t TCIF7:1; + uint32_t HTIF7:1; + uint32_t TEIF7:1; + uint32_t reserved1:4; + }; + uint32_t word; +}; + +#define DMA_ISR_GIF1 reg_def( 0, 1) +#define DMA_ISR_TCIF1 reg_def( 1, 1) +#define DMA_ISR_HTIF1 reg_def( 2, 1) +#define DMA_ISR_TEIF1 reg_def( 3, 1) +#define DMA_ISR_GIF2 reg_def( 4, 1) +#define DMA_ISR_TCIF2 reg_def( 5, 1) +#define DMA_ISR_HTIF2 reg_def( 6, 1) +#define DMA_ISR_TEIF2 reg_def( 7, 1) +#define DMA_ISR_GIF3 reg_def( 8, 1) +#define DMA_ISR_TCIF3 reg_def( 9, 1) +#define DMA_ISR_HTIF3 reg_def(10, 1) +#define DMA_ISR_TEIF3 reg_def(11, 1) +#define DMA_ISR_GIF4 reg_def(12, 1) +#define DMA_ISR_TCIF4 reg_def(13, 1) +#define DMA_ISR_HTIF4 reg_def(14, 1) +#define DMA_ISR_TEIF4 reg_def(15, 1) +#define DMA_ISR_GIF5 reg_def(16, 1) +#define DMA_ISR_TCIF5 reg_def(17, 1) +#define DMA_ISR_HTIF5 reg_def(18, 1) +#define DMA_ISR_TEIF5 reg_def(19, 1) +#define DMA_ISR_GIF6 reg_def(20, 1) +#define DMA_ISR_TCIF6 reg_def(21, 1) +#define DMA_ISR_HTIF6 reg_def(22, 1) +#define DMA_ISR_TEIF6 reg_def(23, 1) +#define DMA_ISR_GIF7 reg_def(24, 1) +#define DMA_ISR_TCIF7 reg_def(25, 1) +#define DMA_ISR_HTIF7 reg_def(26, 1) +#define DMA_ISR_TEIF7 reg_def(27, 1) +#define DMA_ISR_reserved1 reg_def(28, 4) + +union DMA_IFCR { + struct __attribute__((packed)) { + uint32_t CGIF1:1; + uint32_t CTCIF1:1; + uint32_t CHTIF1:1; + uint32_t CTEIF1:1; + uint32_t CGIF2:1; + uint32_t CTCIF2:1; + uint32_t CHTIF2:1; + uint32_t CTEIF2:1; + uint32_t CGIF3:1; + uint32_t CTCIF3:1; + uint32_t CHTIF3:1; + uint32_t CTEIF3:1; + uint32_t CGIF4:1; + uint32_t CTCIF4:1; + uint32_t CHTIF4:1; + uint32_t CTEIF4:1; + uint32_t CGIF5:1; + uint32_t CTCIF5:1; + uint32_t CHTIF5:1; + uint32_t CTEIF5:1; + uint32_t CGIF6:1; + uint32_t CTCIF6:1; + uint32_t CHTIF6:1; + uint32_t CTEIF6:1; + uint32_t CGIF7:1; + uint32_t CTCIF7:1; + uint32_t CHTIF7:1; + uint32_t CTEIF7:1; + uint32_t reserved1:4; + }; + uint32_t word; +}; + +#define DMA_IFCR_CGIF1 reg_def( 0, 1) +#define DMA_IFCR_CTCIF1 reg_def( 1, 1) +#define DMA_IFCR_CHTIF1 reg_def( 2, 1) +#define DMA_IFCR_CTEIF1 reg_def( 3, 1) +#define DMA_IFCR_CGIF2 reg_def( 4, 1) +#define DMA_IFCR_CTCIF2 reg_def( 5, 1) +#define DMA_IFCR_CHTIF2 reg_def( 6, 1) +#define DMA_IFCR_CTEIF2 reg_def( 7, 1) +#define DMA_IFCR_CGIF3 reg_def( 8, 1) +#define DMA_IFCR_CTCIF3 reg_def( 9, 1) +#define DMA_IFCR_CHTIF3 reg_def(10, 1) +#define DMA_IFCR_CTEIF3 reg_def(11, 1) +#define DMA_IFCR_CGIF4 reg_def(12, 1) +#define DMA_IFCR_CTCIF4 reg_def(13, 1) +#define DMA_IFCR_CHTIF4 reg_def(14, 1) +#define DMA_IFCR_CTEIF4 reg_def(15, 1) +#define DMA_IFCR_CGIF5 reg_def(16, 1) +#define DMA_IFCR_CTCIF5 reg_def(17, 1) +#define DMA_IFCR_CHTIF5 reg_def(18, 1) +#define DMA_IFCR_CTEIF5 reg_def(19, 1) +#define DMA_IFCR_CGIF6 reg_def(20, 1) +#define DMA_IFCR_CTCIF6 reg_def(21, 1) +#define DMA_IFCR_CHTIF6 reg_def(22, 1) +#define DMA_IFCR_CTEIF6 reg_def(23, 1) +#define DMA_IFCR_CGIF7 reg_def(24, 1) +#define DMA_IFCR_CTCIF7 reg_def(25, 1) +#define DMA_IFCR_CHTIF7 reg_def(26, 1) +#define DMA_IFCR_CTEIF7 reg_def(27, 1) +#define DMA_IFCR_reserved1 reg_def(28, 4) + +union DMA_CCR { + struct __attribute__((packed)) { + uint32_t EN:1; + uint32_t TCIE:1; + uint32_t HTIE:1; + uint32_t TEIE:1; + uint32_t DIR:1; + uint32_t CIRC:1; + uint32_t PINC:1; + uint32_t MINC:1; + uint32_t PSIZE:2; + uint32_t MSIZE:2; + uint32_t PL:2; + uint32_t MEM2MEM:1; + uint32_t reserved1:17; + }; + uint32_t word; +}; + +#define DMA_CCR_EN reg_def( 0, 1) +#define DMA_CCR_TCIE reg_def( 1, 1) +#define DMA_CCR_HTIE reg_def( 2, 1) +#define DMA_CCR_TEIE reg_def( 3, 1) +#define DMA_CCR_DIR reg_def( 4, 1) +#define DMA_CCR_CIRC reg_def( 5, 1) +#define DMA_CCR_PINC reg_def( 6, 1) +#define DMA_CCR_MINC reg_def( 7, 1) +#define DMA_CCR_PSIZE reg_def( 8, 2) +#define DMA_CCR_MSIZE reg_def(10, 2) +#define DMA_CCR_PL reg_def(12, 2) +#define DMA_CCR_MEM2MEM reg_def(14, 1) +#define DMA_CCR_reserved1 reg_def(15, 17) + +union DMA_CNDTR { + struct __attribute__((packed)) { + uint32_t NDT:16; + uint32_t reserved1:16; + }; + uint32_t word; +}; + +#define DMA_CNDTR_NDT reg_def( 0, 16) +#define DMA_CNDTR_reserved1 reg_def(16, 16) + +struct __attribute__((packed)) DMA_CHANNEL { + union DMA_CCR CCR; + union DMA_CNDTR CNDTR; + uint32_t CPAR; + uint32_t CMAR; + uint32_t reserved1; +}; + +struct __attribute__((packed)) DMA { + union DMA_ISR ISR; + union DMA_IFCR IFCR; + struct DMA_CHANNEL CHANNELS[7]; +}; + + +//--functions------------------------------------------------------------------- + +#endif //_DMA_REGS_H_ + -- 2.45.2 From 45452ce49ec94eabe7a7d988915001e6ecae7797 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:13:36 +0200 Subject: [PATCH 40/85] Implement dma's basic functions --- drivers/dma.c | 246 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/dma.h | 99 ++++++++++++++++++++ 2 files changed, 345 insertions(+) create mode 100644 drivers/dma.c create mode 100644 drivers/dma.h diff --git a/drivers/dma.c b/drivers/dma.c new file mode 100644 index 0000000..0e7f98f --- /dev/null +++ b/drivers/dma.c @@ -0,0 +1,246 @@ +/** @file dma.h + * Module handling Direct Memory Access controller + * + * The module provides functions to configure the dma channels and controller + * transfers + */ + +//--includes-------------------------------------------------------------------- + +#include "dma.h" +#include "dma_regs.h" + +#include "nvic.h" +#include "rcc.h" + + +//--local definitions----------------------------------------------------------- + +static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, + enum DmaConfig config_mask, void* periph, void* mem, + uint16_t size); +static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs); + + +//--local variables------------------------------------------------------------- + +static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS; +static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS; +static DmaCallback dm1_callbacks[7]; +static DmaCallback dm2_callbacks[5]; + + +//--public functions------------------------------------------------------------ + +void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, + enum DmaConfig config_mask, void* periph, void* mem, + uint16_t size, DmaCallback callback) +{ + //reset peripheral first, to ensure proper configuration + dma_reset(dma, channel); + + switch (dma) { + case DMA_PERIPH_1: + rcc_enable(RCC_AHB_DMA1, RCC_APB1_NONE, RCC_APB2_NONE); + configure_dma(dma1, channel, config_mask, periph, mem, size); + if (callback) { + dm1_callbacks[channel] = callback; + nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + } + break; + case DMA_PERIPH_2: + rcc_enable(RCC_AHB_DMA2, RCC_APB1_NONE, RCC_APB2_NONE); + configure_dma(dma2, channel, config_mask, periph, mem, size); + if (callback) { + dm2_callbacks[channel] = callback; + nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + } + break; + default: + break; + } +} + +void dma_reset(enum DmaPeriph dma, enum DmaChannel channel) +{ + volatile struct DMA* periph; + + //first, disable IRQs + switch (dma) { + case DMA_PERIPH_1: + periph = dma1; + nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + break; + case DMA_PERIPH_2: + periph = dma2; + nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + break; + default: + return; + break; + } + + //then, set all registers to reset value + volatile struct DMA_CHANNEL* regs = &periph->CHANNELS[channel]; + regs->CCR.word = 0; + regs->CNDTR.word = 0; + regs->CMAR = 0; + regs->CPAR = 0; +} + + +//--local functions------------------------------------------------------------- + +static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, + enum DmaConfig config_mask, void* periph, void* mem, + uint16_t size) +{ + volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; + + //registers should already be at reset value, apply new config + regs->CCR.word = config_mask; + reg_write(regs->CNDTR, DMA_CNDTR_NDT, size); + regs->CPAR = (uint32_t)periph; + regs->CMAR = (uint32_t)mem; + + //only enable channel when everything is configured + reg_set(regs->CCR, DMA_CCR_EN); +} + +static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs) +{ + switch (periph) { + case DMA_PERIPH_1: + *regs = dma1; + break; + case DMA_PERIPH_2: + *regs = dma2; + break; + default: + return 1; + break; + } + + return 0; +} + + +//--ISRs------------------------------------------------------------------------ + +void hdr_dma1_channel1(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL1); + + enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF1); + + dm1_callbacks[0](src); +} + +void hdr_dma1_channel2(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL2); + + enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF2); + + dm1_callbacks[1](src); +} + +void hdr_dma1_channel3(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL3); + + enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF3); + + dm1_callbacks[2](src); +} + +void hdr_dma1_channel4(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL4); + + enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF4); + + dm1_callbacks[3](src); +} + +void hdr_dma1_channel5(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL5); + + enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF5); + + dm1_callbacks[4](src); +} + +void hdr_dma1_channel6(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL6); + + enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF6); + + dm1_callbacks[5](src); +} + +void hdr_dma1_channel7(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL7); + + enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7; + reg_set(dma1->IFCR, DMA_IFCR_CGIF7); + + dm1_callbacks[6](src); +} + +void hdr_dma2_channel1(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL1); + + enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7; + reg_set(dma2->IFCR, DMA_IFCR_CGIF1); + + dm1_callbacks[0](src); +} + +void hdr_dma2_channel2(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL2); + + enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7; + reg_set(dma2->IFCR, DMA_IFCR_CGIF2); + + dm2_callbacks[1](src); +} + +void hdr_dma2_channel3(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL3); + + enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7; + reg_set(dma2->IFCR, DMA_IFCR_CGIF3); + + dm2_callbacks[2](src); +} + +void hdr_dma2_channel4_5(void) +{ + nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL4_5); + + enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7; + if (src != 0) { + reg_set(dma2->IFCR, DMA_IFCR_CGIF4); + dm1_callbacks[3](src); + } + + src = (dma2->IFCR.word >> 17) & 0x7; + if (src != 0) { + reg_set(dma2->IFCR, DMA_IFCR_CGIF5); + dm1_callbacks[4](src); + } +} + diff --git a/drivers/dma.h b/drivers/dma.h new file mode 100644 index 0000000..05f471e --- /dev/null +++ b/drivers/dma.h @@ -0,0 +1,99 @@ +/** @file dma.h + * Module handling Direct Memory Access controller + * + * The module provides functions to configure the dma channels and controller + * transfers + */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +//--includes-------------------------------------------------------------------- + +#include "stdint.h" + + +//--type definitions------------------------------------------------------------ + +enum DmaPeriph { + DMA_PERIPH_1, + DMA_PERIPH_2, +}; + +enum DmaChannel { + DMA_CHANNEL_1 = 0, + DMA_CHANNEL_2, + DMA_CHANNEL_3, + DMA_CHANNEL_4, + DMA_CHANNEL_5, + DMA_CHANNEL_6, //not available for DMA 2 + DMA_CHANNEL_7, //not available for DMA 2 +}; + +enum DmaConfig { + DMA_CONFIG_IRQ_COMPLETE = (0x1 << 1), + DMA_CONFIG_IRQ_HALF = (0x1 << 2), + DMA_CONFIG_IRQ_ERROR = (0x1 << 3), + DMA_CONFIG_FROM_MEM = (0x1 << 4), + DMA_CONFIG_FROM_PERIPH = (0x0 << 4), + DMA_CONFIG_CIRCULAR = (0x1 << 5), + DMA_CONFIG_INC_PERIPH = (0x1 << 6), + DMA_CONFIG_INC_MEM = (0x1 << 7), + DMA_CONFIG_PSIZE_8BITS = (0x0 << 8), + DMA_CONFIG_PSIZE_16BITS = (0x1 << 8), + DMA_CONFIG_PSIZE_32BITS = (0x2 << 8), + DMA_CONFIG_MSIZE_8BITS = (0x0 << 10), + DMA_CONFIG_MSIZE_16BITS = (0x1 << 10), + DMA_CONFIG_MSIZE_32BITS = (0x2 << 10), + DMA_CONFIG_PRIO_LOW = (0x0 << 12), + DMA_CONFIG_PRIO_MEDIUM = (0x1 << 12), + DMA_CONFIG_PRIO_HIGH = (0x2 << 12), + DMA_CONFIG_PRIO_VHIGH = (0x3 << 12), +}; + +enum DmaConfigM2M { + DMA_CONFIG_M2M_IRQ_COMPLETE = (0x1 << 1), + DMA_CONFIG_M2M_IRQ_HALF = (0x1 << 2), + DMA_CONFIG_M2M_IRQ_ERROR = (0x1 << 3), + DMA_CONFIG_M2M_INC_SRC = (0x1 << 6), + DMA_CONFIG_M2M_INC_DEST = (0x1 << 7), + DMA_CONFIG_M2M_SSIZE_8BITS = (0x0 << 8), + DMA_CONFIG_M2M_SSIZE_16BITS = (0x1 << 8), + DMA_CONFIG_M2M_SSIZE_32BITS = (0x2 << 8), + DMA_CONFIG_M2M_DSIZE_8BITS = (0x0 << 10), + DMA_CONFIG_M2M_DSIZE_16BITS = (0x1 << 10), + DMA_CONFIG_M2M_DSIZE_32BITS = (0x2 << 10), + DMA_CONFIG_M2M_PRIO_LOW = (0x0 << 12), + DMA_CONFIG_M2M_PRIO_MEDIUM = (0x1 << 12), + DMA_CONFIG_M2M_PRIO_HIGH = (0x2 << 12), + DMA_CONFIG_M2M_PRIO_VHIGH = (0x3 << 12), +}; + +enum DmaIRQSource { + DMA_IRQ_SOURCE_COMPLETE = (0x1 << 1), + DMA_IRQ_SOURCE_HALF = (0x1 << 2), + DMA_IQR_SOURCE_ERROR = (0x2 << 3), +}; + +typedef void (*DmaCallback)(enum DmaIRQSource); + + +//--functions------------------------------------------------------------------- + +void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, + enum DmaConfig config_mask, void* periph, void* mem, + uint16_t size, DmaCallback callback); + +void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, + enum DmaConfigM2M config_mask, const void* src, void* dest, + uint16_t size, DmaCallback callback); + +void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); + +void dma_enable(enum DmaPeriph dma, enum DmaChannel channel); + +void dma_disable(enum DmaPeriph dma, enum DmaChannel channel); + + +#endif //_DMA_H_ + -- 2.45.2 From 12c0b16b3955270eb8fac9ddef53b2861971a33c Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:14:46 +0200 Subject: [PATCH 41/85] Cosmetic fixes --- drivers/afio_regs.h | 4 ++-- drivers/exti.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/afio_regs.h b/drivers/afio_regs.h index 55bdde0..aa34561 100644 --- a/drivers/afio_regs.h +++ b/drivers/afio_regs.h @@ -6,8 +6,8 @@ * defined here. */ -#ifndef _IO_REGS_H_ -#define _IO_REGS_H_ +#ifndef _AFIO_REGS_H_ +#define _AFIO_REGS_H_ //--includes-------------------------------------------------------------------- diff --git a/drivers/exti.c b/drivers/exti.c index 1139105..686f37f 100644 --- a/drivers/exti.c +++ b/drivers/exti.c @@ -188,7 +188,7 @@ void exti_reset_peripheral(void) //--local functions------------------------------------------------------------- -//--ISRs ----------------------------------------------------------------------- +//--ISRs------------------------------------------------------------------------ void hdr_exti0(void) { -- 2.45.2 From 43cdb55c4867a75a0f990632cb5ef4c612fe4694 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:29:07 +0200 Subject: [PATCH 42/85] Cleanup dma's configuration code --- drivers/dma.c | 96 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 62 insertions(+), 34 deletions(-) diff --git a/drivers/dma.c b/drivers/dma.c index 0e7f98f..1cb0f03 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -13,21 +13,22 @@ #include "nvic.h" #include "rcc.h" +#include "stddef.h" + //--local definitions----------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, enum DmaConfig config_mask, void* periph, void* mem, uint16_t size); -static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs); //--local variables------------------------------------------------------------- static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS; static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS; -static DmaCallback dm1_callbacks[7]; -static DmaCallback dm2_callbacks[5]; +static DmaCallback dma1_callbacks[7]; +static DmaCallback dma2_callbacks[5]; //--public functions------------------------------------------------------------ @@ -44,7 +45,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, rcc_enable(RCC_AHB_DMA1, RCC_APB1_NONE, RCC_APB2_NONE); configure_dma(dma1, channel, config_mask, periph, mem, size); if (callback) { - dm1_callbacks[channel] = callback; + dma1_callbacks[channel] = callback; nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); } break; @@ -52,7 +53,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, rcc_enable(RCC_AHB_DMA2, RCC_APB1_NONE, RCC_APB2_NONE); configure_dma(dma2, channel, config_mask, periph, mem, size); if (callback) { - dm2_callbacks[channel] = callback; + dma2_callbacks[channel] = callback; nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); } break; @@ -69,10 +70,12 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel) switch (dma) { case DMA_PERIPH_1: periph = dma1; + dma1_callbacks[channel] = NULL; nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); break; case DMA_PERIPH_2: periph = dma2; + dma2_callbacks[channel] = NULL; nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); break; default: @@ -88,6 +91,48 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel) regs->CPAR = 0; } +void dma_enable(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + reg_set(dma1->CHANNELS[channel].CCR, DMA_CCR_EN); + if (dma1_callbacks[channel]) { + nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + } + break; + case DMA_PERIPH_2: + reg_set(dma2->CHANNELS[channel].CCR, DMA_CCR_EN); + if (dma2_callbacks[channel]) { + nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + } + break; + default: + return; + break; + } +} + +void dma_disable(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + reg_reset(dma1->CHANNELS[channel].CCR, DMA_CCR_EN); + if (dma1_callbacks[channel]) { + nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + } + break; + case DMA_PERIPH_2: + reg_reset(dma2->CHANNELS[channel].CCR, DMA_CCR_EN); + if (dma2_callbacks[channel]) { + nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + } + break; + default: + return; + break; + } +} + //--local functions------------------------------------------------------------- @@ -107,23 +152,6 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, reg_set(regs->CCR, DMA_CCR_EN); } -static uint32_t periph_regs(enum DmaPeriph periph, volatile struct DMA** regs) -{ - switch (periph) { - case DMA_PERIPH_1: - *regs = dma1; - break; - case DMA_PERIPH_2: - *regs = dma2; - break; - default: - return 1; - break; - } - - return 0; -} - //--ISRs------------------------------------------------------------------------ @@ -134,7 +162,7 @@ void hdr_dma1_channel1(void) enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF1); - dm1_callbacks[0](src); + dma1_callbacks[0](src); } void hdr_dma1_channel2(void) @@ -144,7 +172,7 @@ void hdr_dma1_channel2(void) enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF2); - dm1_callbacks[1](src); + dma1_callbacks[1](src); } void hdr_dma1_channel3(void) @@ -154,7 +182,7 @@ void hdr_dma1_channel3(void) enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF3); - dm1_callbacks[2](src); + dma1_callbacks[2](src); } void hdr_dma1_channel4(void) @@ -164,7 +192,7 @@ void hdr_dma1_channel4(void) enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF4); - dm1_callbacks[3](src); + dma1_callbacks[3](src); } void hdr_dma1_channel5(void) @@ -174,7 +202,7 @@ void hdr_dma1_channel5(void) enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF5); - dm1_callbacks[4](src); + dma1_callbacks[4](src); } void hdr_dma1_channel6(void) @@ -184,7 +212,7 @@ void hdr_dma1_channel6(void) enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF6); - dm1_callbacks[5](src); + dma1_callbacks[5](src); } void hdr_dma1_channel7(void) @@ -194,7 +222,7 @@ void hdr_dma1_channel7(void) enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF7); - dm1_callbacks[6](src); + dma1_callbacks[6](src); } void hdr_dma2_channel1(void) @@ -204,7 +232,7 @@ void hdr_dma2_channel1(void) enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF1); - dm1_callbacks[0](src); + dma1_callbacks[0](src); } void hdr_dma2_channel2(void) @@ -214,7 +242,7 @@ void hdr_dma2_channel2(void) enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF2); - dm2_callbacks[1](src); + dma2_callbacks[1](src); } void hdr_dma2_channel3(void) @@ -224,7 +252,7 @@ void hdr_dma2_channel3(void) enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF3); - dm2_callbacks[2](src); + dma2_callbacks[2](src); } void hdr_dma2_channel4_5(void) @@ -234,13 +262,13 @@ void hdr_dma2_channel4_5(void) enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7; if (src != 0) { reg_set(dma2->IFCR, DMA_IFCR_CGIF4); - dm1_callbacks[3](src); + dma1_callbacks[3](src); } src = (dma2->IFCR.word >> 17) & 0x7; if (src != 0) { reg_set(dma2->IFCR, DMA_IFCR_CGIF5); - dm1_callbacks[4](src); + dma1_callbacks[4](src); } } -- 2.45.2 From c571343de19281f92938cd0cd3659cff6f3f80f0 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:29:43 +0200 Subject: [PATCH 43/85] Fix usart's regs typo --- drivers/usart_regs.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/usart_regs.h b/drivers/usart_regs.h index 863ae1d..2c84cc3 100644 --- a/drivers/usart_regs.h +++ b/drivers/usart_regs.h @@ -161,18 +161,18 @@ union USART_CR3 { uint32_t word; }; -#define UART_CR3_EIE reg_def( 0, 1) -#define UART_CR3_IREN reg_def( 1, 1) -#define UART_CR3_IRLP reg_def( 2, 1) -#define UART_CR3_HDSEL reg_def( 3, 1) -#define UART_CR3_NACK reg_def( 4, 1) -#define UART_CR3_SCEN reg_def( 5, 1) -#define UART_CR3_DMAR reg_def( 6, 1) -#define UART_CR3_DMAT reg_def( 7, 1) -#define UART_CR3_RTSE reg_def( 8, 1) -#define UART_CR3_CTSE reg_def( 9, 1) -#define UART_CR3_CTSIE reg_def(10, 1) -#define UART_CR3_reserved3 reg_def(11, 21) +#define USART_CR3_EIE reg_def( 0, 1) +#define USART_CR3_IREN reg_def( 1, 1) +#define USART_CR3_IRLP reg_def( 2, 1) +#define USART_CR3_HDSEL reg_def( 3, 1) +#define USART_CR3_NACK reg_def( 4, 1) +#define USART_CR3_SCEN reg_def( 5, 1) +#define USART_CR3_DMAR reg_def( 6, 1) +#define USART_CR3_DMAT reg_def( 7, 1) +#define USART_CR3_RTSE reg_def( 8, 1) +#define USART_CR3_CTSE reg_def( 9, 1) +#define USART_CR3_CTSIE reg_def(10, 1) +#define USART_CR3_reserved3 reg_def(11, 21) union USART_GTPR { struct __attribute__((packed)) { @@ -187,7 +187,7 @@ union USART_GTPR { #define USART_GTPR_GT reg_def( 8, 8) #define USART_GTPR_reserved1 reg_def(16, 16) -struct __attribute__((packed)) USART { +struct USART { union USART_SR SR; union USART_DR DR; union USART_BRR BRR; -- 2.45.2 From 46776ebfd3dc074d674a71a546662402406e96de Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 10 Jul 2023 11:30:51 +0200 Subject: [PATCH 44/85] Configure usart's rx with dma --- drivers/usart.c | 86 ++++++++++++++++++++++++++++++++++++++++++------- drivers/usart.h | 6 ++++ 2 files changed, 80 insertions(+), 12 deletions(-) diff --git a/drivers/usart.c b/drivers/usart.c index 017df30..0b8406c 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -12,6 +12,9 @@ #include "reg.h" #include "rcc.h" +#include "dma.h" + +#include "stddef.h" //--local definitions----------------------------------------------------------- @@ -20,14 +23,23 @@ static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; -void configure_usart(volatile struct USART* regs, enum UsartConfig config); -void configure_baudrate(volatile struct USART* regs, uint32_t clock, +static void configure_usart(volatile struct USART* regs, + enum UsartConfig config); +static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs); +static uint32_t periph_regs(enum UsartPeriph periph, + volatile struct USART** regs); +static uint32_t read_from_buffer(volatile uint8_t* buffer, + enum DmaChannel channel, uint8_t* byte); + +static void usart1_rx_callback(enum DmaIRQSource src); //--local variables------------------------------------------------------------- +static volatile uint8_t* usart1_rx_buffer; + + //--public functions------------------------------------------------------------ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, @@ -75,21 +87,58 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { volatile struct USART* regs; - if (periph_regs(periph, ®s)) { - return 1; + volatile uint8_t* buffer; + enum DmaChannel dma_channel; + + switch (periph) { + case USART_PERIPH_1: + regs = usart1; + buffer = usart1_rx_buffer; + dma_channel = DMA_CHANNEL_5; + break; + case USART_PERIPH_2: + case USART_PERIPH_3: + default: + return 1; + break; } - if (regs->SR.RXNE) { - *byte = regs->DR.DR; - return 0; + if (buffer) { + return read_from_buffer(buffer, dma_channel, byte); } else { - return 1; + if (regs->SR.RXNE) { + *byte = regs->DR.DR; + return 0; + } else { + return 1; + } + } +} + +void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, + uint16_t size) +{ + switch (periph) { + case USART_PERIPH_1: + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_5, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS + | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer, + size, usart1_rx_callback); + usart1_rx_buffer = buffer; + reg_set(usart1->CR3, USART_CR3_DMAR); + break; + case USART_PERIPH_2: + break; + case USART_PERIPH_3: + break; } } //--local functions------------------------------------------------------------- -void configure_usart(volatile struct USART* regs, enum UsartConfig config) +static void configure_usart(volatile struct USART* regs, enum UsartConfig config) { //configure parity switch (config) @@ -165,7 +214,7 @@ void configure_usart(volatile struct USART* regs, enum UsartConfig config) reg_set(regs->CR1, USART_CR1_UE); } -void configure_baudrate(volatile struct USART* regs, uint32_t clock, +static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate) { uint32_t mantissa = clock / (baudrate * 16); @@ -178,7 +227,7 @@ void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } -uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs) +static uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs) { switch (periph) { case USART_PERIPH_1: @@ -198,3 +247,16 @@ uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs) return 0; } +static uint32_t read_from_buffer(volatile uint8_t* buffer, + enum DmaChannel channel, uint8_t* byte) +{ + +} + +//--callbacks------------------------------------------------------------------- + +static void usart1_rx_callback(enum DmaIRQSource src) +{ + +} + diff --git a/drivers/usart.h b/drivers/usart.h index c5845c1..ed68b3f 100644 --- a/drivers/usart.h +++ b/drivers/usart.h @@ -46,6 +46,12 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); +void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t* buffer, + uint16_t size); + +void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, + uint16_t size); + #endif //_USART_H_ -- 2.45.2 From f89fe12298046dd95f46da32c7bbd2fd340ea282 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Tue, 11 Jul 2023 11:44:54 +0200 Subject: [PATCH 45/85] Add circular rx buffer management --- drivers/dma.c | 14 ++++++++++++++ drivers/dma.h | 2 ++ drivers/usart.c | 51 ++++++++++++++++++++++++++++++++++++++----------- 3 files changed, 56 insertions(+), 11 deletions(-) diff --git a/drivers/dma.c b/drivers/dma.c index 1cb0f03..1fef4c8 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -133,6 +133,20 @@ void dma_disable(enum DmaPeriph dma, enum DmaChannel channel) } } +uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + return dma1->CHANNELS[channel].CNDTR.NDT; + break; + case DMA_PERIPH_2: + return dma2->CHANNELS[channel].CNDTR.NDT; + break; + default: + return 0; + break; + } +} //--local functions------------------------------------------------------------- diff --git a/drivers/dma.h b/drivers/dma.h index 05f471e..b5a2159 100644 --- a/drivers/dma.h +++ b/drivers/dma.h @@ -94,6 +94,8 @@ void dma_enable(enum DmaPeriph dma, enum DmaChannel channel); void dma_disable(enum DmaPeriph dma, enum DmaChannel channel); +uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channe); + #endif //_DMA_H_ diff --git a/drivers/usart.c b/drivers/usart.c index 0b8406c..7567c87 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -19,9 +19,12 @@ //--local definitions----------------------------------------------------------- -static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; -static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; -static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; +struct CircularBuffer { + volatile uint8_t* buffer; + uint16_t size; + uint16_t begin; + bool dmaLooped; +}; static void configure_usart(volatile struct USART* regs, enum UsartConfig config); @@ -29,7 +32,7 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); static uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs); -static uint32_t read_from_buffer(volatile uint8_t* buffer, +static uint32_t read_from_buffer(struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte); static void usart1_rx_callback(enum DmaIRQSource src); @@ -37,7 +40,11 @@ static void usart1_rx_callback(enum DmaIRQSource src); //--local variables------------------------------------------------------------- -static volatile uint8_t* usart1_rx_buffer; +static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; +static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; +static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; + +static struct CircularBuffer usart1_rx_buffer; //--public functions------------------------------------------------------------ @@ -87,13 +94,13 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { volatile struct USART* regs; - volatile uint8_t* buffer; + struct CircularBuffer* buffer; enum DmaChannel dma_channel; switch (periph) { case USART_PERIPH_1: regs = usart1; - buffer = usart1_rx_buffer; + buffer = &usart1_rx_buffer; dma_channel = DMA_CHANNEL_5; break; case USART_PERIPH_2: @@ -103,7 +110,7 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) break; } - if (buffer) { + if (buffer->buffer) { return read_from_buffer(buffer, dma_channel, byte); } else { if (regs->SR.RXNE) { @@ -126,7 +133,10 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer, size, usart1_rx_callback); - usart1_rx_buffer = buffer; + usart1_rx_buffer.buffer = buffer; + usart1_rx_buffer.size = size; + usart1_rx_buffer.begin = 0; + usart1_rx_buffer.dmaLooped = false; reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: @@ -140,6 +150,7 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, static void configure_usart(volatile struct USART* regs, enum UsartConfig config) { + usart1_rx_buffer.buffer = NULL; //configure parity switch (config) { @@ -247,16 +258,34 @@ static uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** reg return 0; } -static uint32_t read_from_buffer(volatile uint8_t* buffer, +static uint32_t read_from_buffer(struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte) { + uint16_t end = buffer->size - dma_get_remaining(DMA_PERIPH_1, channel); + if ((end > buffer->begin) && buffer->dmaLooped) { + //TODO overflow + buffer->begin = end; + } else if ((buffer->begin == end) && !buffer->dmaLooped) { + //TODO no data + return 1; + } + + *byte = buffer->buffer[buffer->begin]; + ++buffer->begin; + if (buffer->begin >= buffer->size) { + buffer->begin = 0; + buffer->dmaLooped = false; + } + + return 0; } //--callbacks------------------------------------------------------------------- static void usart1_rx_callback(enum DmaIRQSource src) { - + (void)src; //only transfer complete expected + usart1_rx_buffer.dmaLooped = true; } -- 2.45.2 From 6269cf969ab0a2e037fa79837a681a22dbedeefa Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 13 Sep 2023 21:56:30 +0200 Subject: [PATCH 46/85] Add critical section functions for DMAs --- drivers/dma.c | 30 ++++++++++++++++++++++++++++++ drivers/dma.h | 4 ++++ 2 files changed, 34 insertions(+) diff --git a/drivers/dma.c b/drivers/dma.c index 1fef4c8..bd6a3a6 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -91,6 +91,21 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel) regs->CPAR = 0; } +void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + break; + case DMA_PERIPH_2: + nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + break; + default: + return; + break; + } +} + void dma_enable(enum DmaPeriph dma, enum DmaChannel channel) { switch (dma) { @@ -112,6 +127,21 @@ void dma_enable(enum DmaPeriph dma, enum DmaChannel channel) } } +void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + break; + case DMA_PERIPH_2: + nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + break; + default: + return; + break; + } +} + void dma_disable(enum DmaPeriph dma, enum DmaChannel channel) { switch (dma) { diff --git a/drivers/dma.h b/drivers/dma.h index b5a2159..893c14f 100644 --- a/drivers/dma.h +++ b/drivers/dma.h @@ -90,8 +90,12 @@ void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); +void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel); + void dma_enable(enum DmaPeriph dma, enum DmaChannel channel); +void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel); + void dma_disable(enum DmaPeriph dma, enum DmaChannel channel); uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channe); -- 2.45.2 From a66e5733e1c3abbc2928a3faa6de47e887274299 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 13 Sep 2023 21:57:13 +0200 Subject: [PATCH 47/85] First try at implementing USART's TX Unbuffered writes are working as intented. Buffering still needs work --- drivers/usart.c | 193 +++++++++++++++++++++++++++++++++++++++++------- drivers/usart.h | 4 +- 2 files changed, 168 insertions(+), 29 deletions(-) diff --git a/drivers/usart.c b/drivers/usart.c index 7567c87..e317567 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -8,6 +8,7 @@ //--includes-------------------------------------------------------------------- #include "usart.h" +#include "nvic.h" #include "usart_regs.h" #include "reg.h" @@ -26,15 +27,28 @@ struct CircularBuffer { bool dmaLooped; }; +struct FragmentedBuffer { + uint8_t** buffers; + uint16_t buffer_size; + uint16_t byte_index; + uint8_t buffer_nb; + uint8_t free_buffer_nb; + uint8_t buffer_index; + uint8_t dma_buffer_index; +}; + static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -static uint32_t periph_regs(enum UsartPeriph periph, - volatile struct USART** regs); -static uint32_t read_from_buffer(struct CircularBuffer* buffer, +static uint32_t write_byte(volatile struct USART* regs, uint8_t byte); +static uint32_t write_to_buffer(volatile struct USART* regs, + volatile struct FragmentedBuffer *buffer, enum DmaChannel channel, + uint8_t byte); +static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte); +static void usart1_tx_callback(enum DmaIRQSource src); static void usart1_rx_callback(enum DmaIRQSource src); @@ -44,7 +58,8 @@ static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; -static struct CircularBuffer usart1_rx_buffer; +static volatile struct CircularBuffer usart1_rx_buffer; +static volatile struct FragmentedBuffer usart1_tx_buffer; //--public functions------------------------------------------------------------ @@ -60,6 +75,7 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); + usart1_tx_buffer.buffers = NULL; break; case USART_PERIPH_2: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); @@ -79,22 +95,35 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; - if (periph_regs(periph, ®s)) { - return 1; + volatile struct FragmentedBuffer* buffer; + enum DmaChannel dma_channel; + + switch (periph) { + case USART_PERIPH_1: + regs = usart1; + buffer = &usart1_tx_buffer; + dma_channel = DMA_CHANNEL_4; + break; + case USART_PERIPH_2: + case USART_PERIPH_3: + default: + return 1; + break; } - if (regs->SR.TXE) { + if (buffer->buffers) { + return write_to_buffer(regs, buffer, dma_channel, byte); + } else { + while (regs->SR.TXE == 0) {} reg_write(regs->DR, USART_DR_DR, byte); return 0; - } else { - return 1; } } uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { volatile struct USART* regs; - struct CircularBuffer* buffer; + volatile struct CircularBuffer* buffer; enum DmaChannel dma_channel; switch (periph) { @@ -122,6 +151,32 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) } } +void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, + uint16_t buffer_size, uint8_t buffer_nb) +{ + volatile struct FragmentedBuffer* buffer = NULL; + switch (periph) { + case USART_PERIPH_1: + buffer = &usart1_tx_buffer; + break; + case USART_PERIPH_2: + break; + case USART_PERIPH_3: + break; + } + +#warning "check for null ptr" + +// for (uint8_t i = 0; i < sizeof(struct FragmentedBuffer); ++i) +// { +// ((uint8_t*)(&buffer))[i] = 0; +// } + buffer->buffers = buffers; + buffer->buffer_size = buffer_size; + buffer->buffer_nb = buffer_nb; + buffer->free_buffer_nb = buffer_nb; +} + void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, uint16_t size) { @@ -148,9 +203,9 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, //--local functions------------------------------------------------------------- -static void configure_usart(volatile struct USART* regs, enum UsartConfig config) +static void configure_usart(volatile struct USART* regs, + enum UsartConfig config) { - usart1_rx_buffer.buffer = NULL; //configure parity switch (config) { @@ -238,27 +293,55 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } -static uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs) +static uint32_t write_byte(volatile struct USART* regs, uint8_t byte) { - switch (periph) { - case USART_PERIPH_1: - *regs = usart1; - break; - case USART_PERIPH_2: - *regs = usart2; - break; - case USART_PERIPH_3: - *regs = usart3; - break; - default: - return 1; - break; + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + reg_reset(regs->CR3, USART_CR3_DMAT); + reg_set(regs->CR1, USART_CR1_TXEIE); + nvic_enable(NVIC_IRQ_USART1); + return 0; + } else { + return 1; + } +} + +static uint32_t write_to_buffer(volatile struct USART *regs, + volatile struct FragmentedBuffer *buffer, enum DmaChannel channel, + uint8_t byte) +{ + //if the tx register is empty, there is no need to go through the dma + if (!write_byte(regs, byte)) { + //TODO enable IRQ + return 0; } + //if the current buffer is full, we need to switch it with an empty one + if (buffer->byte_index >= buffer->buffer_size) { + + //if all buffer full, simply wait for the DMA to empty one + while (buffer->free_buffer_nb == 0) {} + dma_enter_critical(DMA_PERIPH_1, channel); + + ++buffer->buffer_index; + if (buffer->buffer_index >= buffer->buffer_nb) { + buffer->buffer_index = 0; + } + --buffer->free_buffer_nb; + + buffer->byte_index = 0; + } else { + dma_enter_critical(DMA_PERIPH_1, channel); + } + + buffer->buffers[buffer->buffer_index][buffer->byte_index] = byte; + ++buffer->byte_index; + + dma_exit_critical(DMA_PERIPH_1, channel); return 0; } -static uint32_t read_from_buffer(struct CircularBuffer* buffer, +static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte) { uint16_t end = buffer->size - dma_get_remaining(DMA_PERIPH_1, channel); @@ -283,9 +366,65 @@ static uint32_t read_from_buffer(struct CircularBuffer* buffer, //--callbacks------------------------------------------------------------------- +static void usart1_tx_callback(enum DmaIRQSource src) +{ + (void)src; //only transfer complete expected + volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; + + ++buffer->dma_buffer_index; + if (buffer->dma_buffer_index >= buffer->buffer_nb) { + buffer->dma_buffer_index = 0; + } + ++buffer->free_buffer_nb; + + //no more data to send, stop here + if (buffer->dma_buffer_index == buffer->buffer_index + && buffer->byte_index == 0) { + return; + } + + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS + | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, + (void*)&usart1->DR, + (void*)&buffer->buffers[buffer->dma_buffer_index], + buffer->byte_index, + usart1_tx_callback); +} + static void usart1_rx_callback(enum DmaIRQSource src) { (void)src; //only transfer complete expected usart1_rx_buffer.dmaLooped = true; } + +//--ISRs------------------------------------------------------------------------ + +void hdr_usart1(void) +{ + nvic_clear_pending(NVIC_IRQ_USART1); + + volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; + + //no more data to send, stop here + if (buffer->dma_buffer_index == buffer->buffer_index + && buffer->byte_index == 0) { + return; + } + + reg_set(usart1->CR3, USART_CR3_DMAT); + reg_reset(usart1->CR1, USART_CR1_TXEIE); + nvic_disable(NVIC_IRQ_USART1); + + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS + | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, + (void*)&usart1->DR, + (void*)&buffer->buffers[buffer->dma_buffer_index], + buffer->byte_index, + usart1_tx_callback); +} + diff --git a/drivers/usart.h b/drivers/usart.h index ed68b3f..c854c77 100644 --- a/drivers/usart.h +++ b/drivers/usart.h @@ -46,8 +46,8 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); -void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t* buffer, - uint16_t size); +void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, + uint16_t buffer_size, uint8_t buffer_nb); void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, uint16_t size); -- 2.45.2 From fdc5f381f8313c11e5e4b4d3c30005ce9256119f Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 17:15:49 +0200 Subject: [PATCH 48/85] Got USART's TX via DMA working as intended For now, USART's writes are blocking. This should be left to the application to decide --- drivers/usart.c | 42 ++++++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/usart.c b/drivers/usart.c index e317567..f6ae0a3 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -167,14 +167,13 @@ void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, #warning "check for null ptr" -// for (uint8_t i = 0; i < sizeof(struct FragmentedBuffer); ++i) -// { -// ((uint8_t*)(&buffer))[i] = 0; -// } buffer->buffers = buffers; buffer->buffer_size = buffer_size; + buffer->byte_index = 0; buffer->buffer_nb = buffer_nb; - buffer->free_buffer_nb = buffer_nb; + buffer->free_buffer_nb = buffer_nb - 1; + buffer->buffer_index = 0; + buffer->dma_buffer_index = 0; } void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, @@ -312,14 +311,16 @@ static uint32_t write_to_buffer(volatile struct USART *regs, { //if the tx register is empty, there is no need to go through the dma if (!write_byte(regs, byte)) { - //TODO enable IRQ return 0; } + dma_enter_critical(DMA_PERIPH_1, channel); + //if the current buffer is full, we need to switch it with an empty one if (buffer->byte_index >= buffer->buffer_size) { //if all buffer full, simply wait for the DMA to empty one + dma_exit_critical(DMA_PERIPH_1, channel); while (buffer->free_buffer_nb == 0) {} dma_enter_critical(DMA_PERIPH_1, channel); @@ -388,9 +389,18 @@ static void usart1_tx_callback(enum DmaIRQSource src) | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, - (void*)&buffer->buffers[buffer->dma_buffer_index], + (void*)buffer->buffers[buffer->dma_buffer_index], buffer->byte_index, usart1_tx_callback); + + if (buffer->dma_buffer_index == buffer->buffer_index) + { + ++buffer->buffer_index; + if (buffer->buffer_index >= buffer->buffer_nb) { + buffer->buffer_index = 0; + } + buffer->byte_index = 0; + } } static void usart1_rx_callback(enum DmaIRQSource src) @@ -405,6 +415,9 @@ static void usart1_rx_callback(enum DmaIRQSource src) void hdr_usart1(void) { nvic_clear_pending(NVIC_IRQ_USART1); + nvic_disable(NVIC_IRQ_USART1); + reg_reset(usart1->CR1, USART_CR1_TXEIE); + reg_set(usart1->CR3, USART_CR3_DMAT); volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; @@ -414,17 +427,22 @@ void hdr_usart1(void) return; } - reg_set(usart1->CR3, USART_CR3_DMAT); - reg_reset(usart1->CR1, USART_CR1_TXEIE); - nvic_disable(NVIC_IRQ_USART1); - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, - (void*)&buffer->buffers[buffer->dma_buffer_index], + (void*)buffer->buffers[buffer->dma_buffer_index], buffer->byte_index, usart1_tx_callback); + + if (buffer->dma_buffer_index == buffer->buffer_index) + { + ++buffer->buffer_index; + if (buffer->buffer_index >= buffer->buffer_nb) { + buffer->buffer_index = 0; + } + buffer->byte_index = 0; + } } -- 2.45.2 From b9285f2ab9de4faee148b88abbbe3dd314d3a065 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 17:38:13 +0200 Subject: [PATCH 49/85] Document USART's private functions --- drivers/usart.c | 62 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/usart.c b/drivers/usart.c index f6ae0a3..87cd5f3 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -21,20 +21,20 @@ //--local definitions----------------------------------------------------------- struct CircularBuffer { - volatile uint8_t* buffer; - uint16_t size; - uint16_t begin; - bool dmaLooped; + volatile uint8_t* buffer; //the buffer to use as a circular buffer + uint16_t size; //the size of the buffer + uint16_t begin; //pointer to the current begin of the buffer + bool dmaLooped; //whether the DMA looped or not (buffer overflow) }; struct FragmentedBuffer { - uint8_t** buffers; - uint16_t buffer_size; - uint16_t byte_index; - uint8_t buffer_nb; - uint8_t free_buffer_nb; - uint8_t buffer_index; - uint8_t dma_buffer_index; + uint8_t** buffers; //list of buffers to write to + uint16_t buffer_size; //size of a single buffer + uint16_t byte_index; //index of the current byte in the current buffer + uint8_t buffer_nb; //total number of buffers + uint8_t free_buffer_nb; //number of buffers not currently used + uint8_t buffer_index; //index of the current buffer + uint8_t dma_buffer_index; //index of the DMA's current buffer }; static void configure_usart(volatile struct USART* regs, @@ -202,6 +202,10 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, //--local functions------------------------------------------------------------- +/** + * Apply the given configuration to the given registers. Generic version of + * usart_configure() + */ static void configure_usart(volatile struct USART* regs, enum UsartConfig config) { @@ -279,6 +283,11 @@ static void configure_usart(volatile struct USART* regs, reg_set(regs->CR1, USART_CR1_UE); } +/** + * Configure the given registers with the given baudrate. Baudrate is dependant + * on the peripheric's clock and may not be exact due to precision errors (see + * table 192 in documentation) + */ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate) { @@ -292,10 +301,17 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } +/** + * Non-blocking write to the given USART. Will return 0 if the write was + * successfull, 1 otherwise. If the write is successfull, the tranfer complete + * IRQ is enabled and the DMA disabled + */ static uint32_t write_byte(volatile struct USART* regs, uint8_t byte) { + //write if TX register empty if (regs->SR.TXE) { reg_write(regs->DR, USART_DR_DR, byte); + //enable IRQ, disable DMA reg_reset(regs->CR3, USART_CR3_DMAT); reg_set(regs->CR1, USART_CR1_TXEIE); nvic_enable(NVIC_IRQ_USART1); @@ -305,6 +321,10 @@ static uint32_t write_byte(volatile struct USART* regs, uint8_t byte) } } +/** + * Writes the given byte to the given UART, using a FragmentedBuffer and a DMA + * to bufferize the write if the peripheral is already busy. + */ static uint32_t write_to_buffer(volatile struct USART *regs, volatile struct FragmentedBuffer *buffer, enum DmaChannel channel, uint8_t byte) @@ -335,6 +355,7 @@ static uint32_t write_to_buffer(volatile struct USART *regs, dma_enter_critical(DMA_PERIPH_1, channel); } + //write the byte buffer->buffers[buffer->buffer_index][buffer->byte_index] = byte; ++buffer->byte_index; @@ -342,11 +363,17 @@ static uint32_t write_to_buffer(volatile struct USART *regs, return 0; } +/** + * Reads the oldest byte from the given CircularBuffer if any. Returns 0 if the + * read was successfull, 1 otherwise + */ static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte) { + //retreive the current end of the buffer based on the DMA's progress uint16_t end = buffer->size - dma_get_remaining(DMA_PERIPH_1, channel); + //check for bytes to read and overflow if ((end > buffer->begin) && buffer->dmaLooped) { //TODO overflow buffer->begin = end; @@ -355,6 +382,7 @@ static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, return 1; } + //read the oldest byte and advance the buffer *byte = buffer->buffer[buffer->begin]; ++buffer->begin; if (buffer->begin >= buffer->size) { @@ -367,11 +395,16 @@ static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, //--callbacks------------------------------------------------------------------- +/** + * Callback called on DMA TX tranfert's completion. Checks for any remaining + * data to send. If any, starts a new transfer, else stop the DMA + */ static void usart1_tx_callback(enum DmaIRQSource src) { (void)src; //only transfer complete expected volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; + //increment DMA's buffer since the last once has already been sent ++buffer->dma_buffer_index; if (buffer->dma_buffer_index >= buffer->buffer_nb) { buffer->dma_buffer_index = 0; @@ -384,6 +417,7 @@ static void usart1_tx_callback(enum DmaIRQSource src) return; } + //else start a new transfer dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS @@ -393,6 +427,8 @@ static void usart1_tx_callback(enum DmaIRQSource src) buffer->byte_index, usart1_tx_callback); + //if the newly transfering buffer was being written to, switch the current + //buffer. Since we just ended a transfer, the next buffer should be empty if (buffer->dma_buffer_index == buffer->buffer_index) { ++buffer->buffer_index; @@ -403,6 +439,10 @@ static void usart1_tx_callback(enum DmaIRQSource src) } } +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ static void usart1_rx_callback(enum DmaIRQSource src) { (void)src; //only transfer complete expected -- 2.45.2 From 9f2b337abfd0946315304ba3e0c5e668e67f4700 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 18:15:44 +0200 Subject: [PATCH 50/85] Add additionnal param to DMA callbacks This parameter is necessary for DMA tools to be implemented with minimal flash usage as it allow the use of a single callback function for all purposes instead of the need to add separate callback functions --- drivers/dma.c | 30 +++++++++++++++++------------- drivers/dma.h | 6 +++--- 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/dma.c b/drivers/dma.c index bd6a3a6..fd3153f 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -28,14 +28,16 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS; static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS; static DmaCallback dma1_callbacks[7]; +static void* dma1_cb_params[7]; static DmaCallback dma2_callbacks[5]; +static void* dma2_cb_params[5]; //--public functions------------------------------------------------------------ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config_mask, void* periph, void* mem, - uint16_t size, DmaCallback callback) + uint16_t size, DmaCallback callback, void* cb_param) { //reset peripheral first, to ensure proper configuration dma_reset(dma, channel); @@ -46,6 +48,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, configure_dma(dma1, channel, config_mask, periph, mem, size); if (callback) { dma1_callbacks[channel] = callback; + dma1_cb_params[channel] = cb_param; nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); } break; @@ -54,6 +57,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, configure_dma(dma2, channel, config_mask, periph, mem, size); if (callback) { dma2_callbacks[channel] = callback; + dma2_cb_params[channel] = cb_param; nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); } break; @@ -206,7 +210,7 @@ void hdr_dma1_channel1(void) enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF1); - dma1_callbacks[0](src); + dma1_callbacks[0](src, dma1_cb_params[0]); } void hdr_dma1_channel2(void) @@ -216,7 +220,7 @@ void hdr_dma1_channel2(void) enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF2); - dma1_callbacks[1](src); + dma1_callbacks[1](src, dma1_cb_params[1]); } void hdr_dma1_channel3(void) @@ -226,7 +230,7 @@ void hdr_dma1_channel3(void) enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF3); - dma1_callbacks[2](src); + dma1_callbacks[2](src, dma1_cb_params[2]); } void hdr_dma1_channel4(void) @@ -236,7 +240,7 @@ void hdr_dma1_channel4(void) enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF4); - dma1_callbacks[3](src); + dma1_callbacks[3](src, dma1_cb_params[3]); } void hdr_dma1_channel5(void) @@ -246,7 +250,7 @@ void hdr_dma1_channel5(void) enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF5); - dma1_callbacks[4](src); + dma1_callbacks[4](src, dma1_cb_params[4]); } void hdr_dma1_channel6(void) @@ -256,7 +260,7 @@ void hdr_dma1_channel6(void) enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF6); - dma1_callbacks[5](src); + dma1_callbacks[5](src, dma1_cb_params[5]); } void hdr_dma1_channel7(void) @@ -266,7 +270,7 @@ void hdr_dma1_channel7(void) enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7; reg_set(dma1->IFCR, DMA_IFCR_CGIF7); - dma1_callbacks[6](src); + dma1_callbacks[6](src, dma1_cb_params[6]); } void hdr_dma2_channel1(void) @@ -276,7 +280,7 @@ void hdr_dma2_channel1(void) enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF1); - dma1_callbacks[0](src); + dma2_callbacks[0](src, dma2_cb_params[0]); } void hdr_dma2_channel2(void) @@ -286,7 +290,7 @@ void hdr_dma2_channel2(void) enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF2); - dma2_callbacks[1](src); + dma2_callbacks[1](src, dma2_cb_params[1]); } void hdr_dma2_channel3(void) @@ -296,7 +300,7 @@ void hdr_dma2_channel3(void) enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7; reg_set(dma2->IFCR, DMA_IFCR_CGIF3); - dma2_callbacks[2](src); + dma2_callbacks[2](src, dma2_cb_params[2]); } void hdr_dma2_channel4_5(void) @@ -306,13 +310,13 @@ void hdr_dma2_channel4_5(void) enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7; if (src != 0) { reg_set(dma2->IFCR, DMA_IFCR_CGIF4); - dma1_callbacks[3](src); + dma1_callbacks[3](src, dma2_cb_params[3]); } src = (dma2->IFCR.word >> 17) & 0x7; if (src != 0) { reg_set(dma2->IFCR, DMA_IFCR_CGIF5); - dma1_callbacks[4](src); + dma1_callbacks[4](src, dma2_cb_params[4]); } } diff --git a/drivers/dma.h b/drivers/dma.h index 893c14f..d2c7b54 100644 --- a/drivers/dma.h +++ b/drivers/dma.h @@ -75,18 +75,18 @@ enum DmaIRQSource { DMA_IQR_SOURCE_ERROR = (0x2 << 3), }; -typedef void (*DmaCallback)(enum DmaIRQSource); +typedef void (*DmaCallback)(enum DmaIRQSource, void* param); //--functions------------------------------------------------------------------- void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config_mask, void* periph, void* mem, - uint16_t size, DmaCallback callback); + uint16_t size, DmaCallback callback, void* cb_param); void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfigM2M config_mask, const void* src, void* dest, - uint16_t size, DmaCallback callback); + uint16_t size, DmaCallback callback, void* cb_param); void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); -- 2.45.2 From dac751e46640d4c7e9501b6c0ecc05fe5ce5b565 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 18:53:50 +0200 Subject: [PATCH 51/85] Move DMA's tx buffer to a separate module --- drivers/dma.c | 12 +-- drivers/dma.h | 6 +- drivers/dma_mbuf.c | 125 ++++++++++++++++++++++++++++++++ drivers/dma_mbuf.h | 49 +++++++++++++ drivers/usart.c | 177 +++++++-------------------------------------- 5 files changed, 208 insertions(+), 161 deletions(-) create mode 100644 drivers/dma_mbuf.c create mode 100644 drivers/dma_mbuf.h diff --git a/drivers/dma.c b/drivers/dma.c index fd3153f..0cc80fe 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -19,7 +19,7 @@ //--local definitions----------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, void* mem, uint16_t size); @@ -28,16 +28,16 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS; static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS; static DmaCallback dma1_callbacks[7]; -static void* dma1_cb_params[7]; +static volatile void* dma1_cb_params[7]; static DmaCallback dma2_callbacks[5]; -static void* dma2_cb_params[5]; +static volatile void* dma2_cb_params[5]; //--public functions------------------------------------------------------------ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, void* periph, void* mem, - uint16_t size, DmaCallback callback, void* cb_param) + enum DmaConfig config_mask, volatile void* periph, void* mem, + uint16_t size, DmaCallback callback, volatile void* cb_param) { //reset peripheral first, to ensure proper configuration dma_reset(dma, channel); @@ -185,7 +185,7 @@ uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) //--local functions------------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, void* mem, uint16_t size) { volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; diff --git a/drivers/dma.h b/drivers/dma.h index d2c7b54..14746f6 100644 --- a/drivers/dma.h +++ b/drivers/dma.h @@ -75,14 +75,14 @@ enum DmaIRQSource { DMA_IQR_SOURCE_ERROR = (0x2 << 3), }; -typedef void (*DmaCallback)(enum DmaIRQSource, void* param); +typedef void (*DmaCallback)(enum DmaIRQSource, volatile void* param); //--functions------------------------------------------------------------------- void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, void* periph, void* mem, - uint16_t size, DmaCallback callback, void* cb_param); + enum DmaConfig config_mask, volatile void* periph, void* mem, + uint16_t size, DmaCallback callback, volatile void* cb_param); void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfigM2M config_mask, const void* src, void* dest, diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c new file mode 100644 index 0000000..66c3520 --- /dev/null +++ b/drivers/dma_mbuf.c @@ -0,0 +1,125 @@ +/** @file dma_mbuf.c + * Module handling Direct Memory Access controller's TX functions + * + * The module provides convenient tools to send data to a peripheral or memory + * area in a buffered, non-blocking way + */ + +//--includes-------------------------------------------------------------------- + +#include "dma_mbuf.h" + + +//--local definitions----------------------------------------------------------- + +static void mbuf_callback(enum DmaIRQSource src, volatile void* param); + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, + volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config) +{ + #warning "check for null ptr" + + buffer->buffers = buffers; + buffer->dest = dest; + + buffer->buffer_size = buffer_size; + buffer->byte_index = 0; + + buffer->buffer_nb = buffer_nb; + buffer->free_buffer_nb = buffer_nb - 1; + buffer->buffer_index = 0; + buffer->dma_buffer_index = 0; + + buffer->dma = dma; + buffer->channel = channel; + buffer->config = config; +} + +uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, + uint8_t byte) +{ + dma_enter_critical(buffer->dma, buffer->channel); + + //if the current buffer is full, we need to switch it with an empty one + if (buffer->byte_index >= buffer->buffer_size) { + + //if all buffer full, simply wait for the DMA to empty one + dma_exit_critical(buffer->dma, buffer->channel); + while (buffer->free_buffer_nb == 0) {} + dma_enter_critical(buffer->dma, buffer->channel); + + ++buffer->buffer_index; + if (buffer->buffer_index >= buffer->buffer_nb) { + buffer->buffer_index = 0; + } + --buffer->free_buffer_nb; + + buffer->byte_index = 0; + } else { + dma_enter_critical(buffer->dma, buffer->channel); + } + + //write the byte + uint8_t** buffers = (uint8_t**)buffer->buffers; + buffers[buffer->buffer_index][buffer->byte_index] = byte; + ++buffer->byte_index; + + dma_exit_critical(DMA_PERIPH_1, buffer->channel); + return 0; +} + +void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer) +{ + //no more data to send, stop here + if (buffer->dma_buffer_index == buffer->buffer_index + && buffer->byte_index == 0) { + return; + } + + //else start a new transfer + dma_configure(buffer->dma, buffer->channel, buffer->config, buffer->dest, + buffer->buffers[buffer->dma_buffer_index], + buffer->byte_index, mbuf_callback, buffer); + + //if the newly transfering buffer was being written to, switch the current + //buffer. Since we just ended a transfer, the next buffer should be empty + if (buffer->dma_buffer_index == buffer->buffer_index) + { + ++buffer->buffer_index; + if (buffer->buffer_index >= buffer->buffer_nb) { + buffer->buffer_index = 0; + } + buffer->byte_index = 0; + } + + return; +} + + +//--local functions------------------------------------------------------------- + +/** + * Callback called on DMA TX tranfert's completion. Checks for any remaining + * data to send. If any, starts a new transfer, else stop the DMA + */ +static void mbuf_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + volatile struct DmaMultiBuffer* buffer = param; + + //increment DMA's buffer since the last once has already been sent + ++buffer->dma_buffer_index; + if (buffer->dma_buffer_index >= buffer->buffer_nb) { + buffer->dma_buffer_index = 0; + } + ++buffer->free_buffer_nb; + + dma_mbuf_refresh(param); +} + diff --git a/drivers/dma_mbuf.h b/drivers/dma_mbuf.h new file mode 100644 index 0000000..b14ba12 --- /dev/null +++ b/drivers/dma_mbuf.h @@ -0,0 +1,49 @@ +/** @file dma_mbuf.h + * Module handling Direct Memory Access controller's TX functions + * + * The module provides convenient tools to send data to a peripheral in a + * buffered, non-blocking way + */ + +#ifndef _DMA_MBUF_H_ +#define _DMA_MBUF_H_ + +//--includes-------------------------------------------------------------------- + +#include "dma.h" + + +//--type definitions------------------------------------------------------------ + +struct DmaMultiBuffer { + void** buffers; //list of buffers to write to + volatile void* dest; //destination peripheral register + + uint16_t buffer_size; //size of a single buffer + uint16_t byte_index; //index of the current byte in the current buffer + + uint8_t buffer_nb; //total number of buffers + uint8_t free_buffer_nb; //number of buffers not currently used + uint8_t buffer_index; //index of the current buffer + uint8_t dma_buffer_index; //index of the DMA's current buffer + + enum DmaPeriph dma; //DMA peripheral, must correspond to peripheral + enum DmaChannel channel; //DMA channel, must correspond to peripheral + enum DmaConfig config; //DMA config, must correspond to peripheral +}; + + +//--functions------------------------------------------------------------------- + +void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, + volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config); + +uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, + uint8_t byte); + +void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer); + + +#endif //_DMA_MBUF_H_ + diff --git a/drivers/usart.c b/drivers/usart.c index 87cd5f3..2224845 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -14,12 +14,18 @@ #include "rcc.h" #include "dma.h" +#include "dma_mbuf.h" #include "stddef.h" //--local definitions----------------------------------------------------------- +#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ + | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW) + + struct CircularBuffer { volatile uint8_t* buffer; //the buffer to use as a circular buffer uint16_t size; //the size of the buffer @@ -27,29 +33,16 @@ struct CircularBuffer { bool dmaLooped; //whether the DMA looped or not (buffer overflow) }; -struct FragmentedBuffer { - uint8_t** buffers; //list of buffers to write to - uint16_t buffer_size; //size of a single buffer - uint16_t byte_index; //index of the current byte in the current buffer - uint8_t buffer_nb; //total number of buffers - uint8_t free_buffer_nb; //number of buffers not currently used - uint8_t buffer_index; //index of the current buffer - uint8_t dma_buffer_index; //index of the DMA's current buffer -}; - static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -static uint32_t write_byte(volatile struct USART* regs, uint8_t byte); static uint32_t write_to_buffer(volatile struct USART* regs, - volatile struct FragmentedBuffer *buffer, enum DmaChannel channel, - uint8_t byte); + volatile struct DmaMultiBuffer *buffer, uint8_t byte); static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte); -static void usart1_tx_callback(enum DmaIRQSource src); -static void usart1_rx_callback(enum DmaIRQSource src); +static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param); //--local variables------------------------------------------------------------- @@ -59,7 +52,7 @@ static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; static volatile struct CircularBuffer usart1_rx_buffer; -static volatile struct FragmentedBuffer usart1_tx_buffer; +static volatile struct DmaMultiBuffer usart1_tx_buffer; //--public functions------------------------------------------------------------ @@ -95,14 +88,12 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; - volatile struct FragmentedBuffer* buffer; - enum DmaChannel dma_channel; + volatile struct DmaMultiBuffer* buffer; switch (periph) { case USART_PERIPH_1: regs = usart1; buffer = &usart1_tx_buffer; - dma_channel = DMA_CHANNEL_4; break; case USART_PERIPH_2: case USART_PERIPH_3: @@ -112,7 +103,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) } if (buffer->buffers) { - return write_to_buffer(regs, buffer, dma_channel, byte); + return write_to_buffer(regs, buffer, byte); } else { while (regs->SR.TXE == 0) {} reg_write(regs->DR, USART_DR_DR, byte); @@ -154,26 +145,17 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, uint16_t buffer_size, uint8_t buffer_nb) { - volatile struct FragmentedBuffer* buffer = NULL; switch (periph) { case USART_PERIPH_1: - buffer = &usart1_tx_buffer; + dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR, + buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4, + DMA_CONFIG); break; case USART_PERIPH_2: break; case USART_PERIPH_3: break; } - -#warning "check for null ptr" - - buffer->buffers = buffers; - buffer->buffer_size = buffer_size; - buffer->byte_index = 0; - buffer->buffer_nb = buffer_nb; - buffer->free_buffer_nb = buffer_nb - 1; - buffer->buffer_index = 0; - buffer->dma_buffer_index = 0; } void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, @@ -186,7 +168,7 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer, - size, usart1_rx_callback); + size, usart1_rx_callback, NULL); usart1_rx_buffer.buffer = buffer; usart1_rx_buffer.size = size; usart1_rx_buffer.begin = 0; @@ -302,13 +284,13 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, } /** - * Non-blocking write to the given USART. Will return 0 if the write was - * successfull, 1 otherwise. If the write is successfull, the tranfer complete - * IRQ is enabled and the DMA disabled + * Writes the given byte to the given UART, using a FragmentedBuffer and a DMA + * to bufferize the write if the peripheral is already busy. */ -static uint32_t write_byte(volatile struct USART* regs, uint8_t byte) +static uint32_t write_to_buffer(volatile struct USART* regs, + volatile struct DmaMultiBuffer* buffer, uint8_t byte) { - //write if TX register empty + //if the tx register is empty, there is no need to go through the dma if (regs->SR.TXE) { reg_write(regs->DR, USART_DR_DR, byte); //enable IRQ, disable DMA @@ -316,51 +298,9 @@ static uint32_t write_byte(volatile struct USART* regs, uint8_t byte) reg_set(regs->CR1, USART_CR1_TXEIE); nvic_enable(NVIC_IRQ_USART1); return 0; - } else { - return 1; - } -} - -/** - * Writes the given byte to the given UART, using a FragmentedBuffer and a DMA - * to bufferize the write if the peripheral is already busy. - */ -static uint32_t write_to_buffer(volatile struct USART *regs, - volatile struct FragmentedBuffer *buffer, enum DmaChannel channel, - uint8_t byte) -{ - //if the tx register is empty, there is no need to go through the dma - if (!write_byte(regs, byte)) { - return 0; } - dma_enter_critical(DMA_PERIPH_1, channel); - - //if the current buffer is full, we need to switch it with an empty one - if (buffer->byte_index >= buffer->buffer_size) { - - //if all buffer full, simply wait for the DMA to empty one - dma_exit_critical(DMA_PERIPH_1, channel); - while (buffer->free_buffer_nb == 0) {} - dma_enter_critical(DMA_PERIPH_1, channel); - - ++buffer->buffer_index; - if (buffer->buffer_index >= buffer->buffer_nb) { - buffer->buffer_index = 0; - } - --buffer->free_buffer_nb; - - buffer->byte_index = 0; - } else { - dma_enter_critical(DMA_PERIPH_1, channel); - } - - //write the byte - buffer->buffers[buffer->buffer_index][buffer->byte_index] = byte; - ++buffer->byte_index; - - dma_exit_critical(DMA_PERIPH_1, channel); - return 0; + return dma_mbuf_write_byte(buffer, byte); } /** @@ -393,57 +333,13 @@ static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, return 0; } -//--callbacks------------------------------------------------------------------- - -/** - * Callback called on DMA TX tranfert's completion. Checks for any remaining - * data to send. If any, starts a new transfer, else stop the DMA - */ -static void usart1_tx_callback(enum DmaIRQSource src) -{ - (void)src; //only transfer complete expected - volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; - - //increment DMA's buffer since the last once has already been sent - ++buffer->dma_buffer_index; - if (buffer->dma_buffer_index >= buffer->buffer_nb) { - buffer->dma_buffer_index = 0; - } - ++buffer->free_buffer_nb; - - //no more data to send, stop here - if (buffer->dma_buffer_index == buffer->buffer_index - && buffer->byte_index == 0) { - return; - } - - //else start a new transfer - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, - DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS - | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, - (void*)&usart1->DR, - (void*)buffer->buffers[buffer->dma_buffer_index], - buffer->byte_index, - usart1_tx_callback); - - //if the newly transfering buffer was being written to, switch the current - //buffer. Since we just ended a transfer, the next buffer should be empty - if (buffer->dma_buffer_index == buffer->buffer_index) - { - ++buffer->buffer_index; - if (buffer->buffer_index >= buffer->buffer_nb) { - buffer->buffer_index = 0; - } - buffer->byte_index = 0; - } -} +//--allbacks------------------------------------------------------------------- /** * Callback called on DMA RX tranfert's completion. Sets a flag needed to * properly handle the circular buffer */ -static void usart1_rx_callback(enum DmaIRQSource src) +static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param) { (void)src; //only transfer complete expected usart1_rx_buffer.dmaLooped = true; @@ -454,35 +350,12 @@ static void usart1_rx_callback(enum DmaIRQSource src) void hdr_usart1(void) { + //disable the interrupt. It will be reenabled on a write if needed nvic_clear_pending(NVIC_IRQ_USART1); nvic_disable(NVIC_IRQ_USART1); reg_reset(usart1->CR1, USART_CR1_TXEIE); reg_set(usart1->CR3, USART_CR3_DMAT); - volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer; - - //no more data to send, stop here - if (buffer->dma_buffer_index == buffer->buffer_index - && buffer->byte_index == 0) { - return; - } - - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4, - DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS - | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW, - (void*)&usart1->DR, - (void*)buffer->buffers[buffer->dma_buffer_index], - buffer->byte_index, - usart1_tx_callback); - - if (buffer->dma_buffer_index == buffer->buffer_index) - { - ++buffer->buffer_index; - if (buffer->buffer_index >= buffer->buffer_nb) { - buffer->buffer_index = 0; - } - buffer->byte_index = 0; - } + dma_mbuf_refresh(&usart1_tx_buffer); } -- 2.45.2 From 7a660c29d21052acd90f4cf9287319986c4085eb Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 23:40:36 +0200 Subject: [PATCH 52/85] Implement and validate all USARTs --- drivers/dma_mbuf.c | 2 +- drivers/usart.c | 135 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 113 insertions(+), 24 deletions(-) diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c index 66c3520..68462a7 100644 --- a/drivers/dma_mbuf.c +++ b/drivers/dma_mbuf.c @@ -70,7 +70,7 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, buffers[buffer->buffer_index][buffer->byte_index] = byte; ++buffer->byte_index; - dma_exit_critical(DMA_PERIPH_1, buffer->channel); + dma_exit_critical(buffer->dma, buffer->channel); return 0; } diff --git a/drivers/usart.c b/drivers/usart.c index 2224845..e5b8491 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -37,12 +37,12 @@ static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -static uint32_t write_to_buffer(volatile struct USART* regs, - volatile struct DmaMultiBuffer *buffer, uint8_t byte); static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, enum DmaChannel channel, uint8_t* byte); static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param); +static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param); +static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param); //--local variables------------------------------------------------------------- @@ -53,6 +53,10 @@ static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; static volatile struct CircularBuffer usart1_rx_buffer; static volatile struct DmaMultiBuffer usart1_tx_buffer; +static volatile struct CircularBuffer usart2_rx_buffer; +static volatile struct DmaMultiBuffer usart2_tx_buffer; +static volatile struct CircularBuffer usart3_rx_buffer; +static volatile struct DmaMultiBuffer usart3_tx_buffer; //--public functions------------------------------------------------------------ @@ -69,16 +73,21 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); usart1_tx_buffer.buffers = NULL; + usart1_rx_buffer.buffer = NULL; break; case USART_PERIPH_2: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); configure_baudrate(usart2, clocks.apb1_freq, baudrate); configure_usart(usart2, config); + usart2_tx_buffer.buffers = NULL; + usart2_rx_buffer.buffer = NULL; break; case USART_PERIPH_3: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE); configure_baudrate(usart3, clocks.apb1_freq, baudrate); configure_usart(usart3, config); + usart3_tx_buffer.buffers = NULL; + usart3_rx_buffer.buffer = NULL; break; default: break; @@ -89,21 +98,41 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; volatile struct DmaMultiBuffer* buffer; + enum NvicIrq irq; switch (periph) { case USART_PERIPH_1: regs = usart1; buffer = &usart1_tx_buffer; + irq = NVIC_IRQ_USART1; break; case USART_PERIPH_2: + regs = usart2; + buffer = &usart2_tx_buffer; + irq = NVIC_IRQ_USART2; + break; case USART_PERIPH_3: + regs = usart3; + buffer = &usart3_tx_buffer; + irq = NVIC_IRQ_USART3; + break; default: return 1; break; } if (buffer->buffers) { - return write_to_buffer(regs, buffer, byte); + //if the tx register is empty, there is no need to go through the dma + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + //enable IRQ, disable DMA + reg_reset(regs->CR3, USART_CR3_DMAT); + reg_set(regs->CR1, USART_CR1_TXEIE); + nvic_enable(irq); + return 0; + } else { + return dma_mbuf_write_byte(buffer, byte); + } } else { while (regs->SR.TXE == 0) {} reg_write(regs->DR, USART_DR_DR, byte); @@ -124,7 +153,15 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) dma_channel = DMA_CHANNEL_5; break; case USART_PERIPH_2: + regs = usart2; + buffer = &usart2_rx_buffer; + dma_channel = DMA_CHANNEL_6; + break; case USART_PERIPH_3: + regs = usart3; + buffer = &usart3_rx_buffer; + dma_channel = DMA_CHANNEL_3; + break; default: return 1; break; @@ -152,8 +189,14 @@ void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, DMA_CONFIG); break; case USART_PERIPH_2: + dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR, + buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7, + DMA_CONFIG); break; case USART_PERIPH_3: + dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR, + buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2, + DMA_CONFIG); break; } } @@ -176,8 +219,32 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_6, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS + | DMA_CONFIG_PRIO_LOW, (void*)&usart2->DR, buffer, + size, usart2_rx_callback, NULL); + usart2_rx_buffer.buffer = buffer; + usart2_rx_buffer.size = size; + usart2_rx_buffer.begin = 0; + usart2_rx_buffer.dmaLooped = false; + reg_set(usart2->CR3, USART_CR3_DMAR); break; + case USART_PERIPH_3: + dma_configure(DMA_PERIPH_1, DMA_CHANNEL_3, + DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS + | DMA_CONFIG_PRIO_LOW, (void*)&usart3->DR, buffer, + size, usart3_rx_callback, NULL); + usart3_rx_buffer.buffer = buffer; + usart3_rx_buffer.size = size; + usart3_rx_buffer.begin = 0; + usart3_rx_buffer.dmaLooped = false; + reg_set(usart3->CR3, USART_CR3_DMAR); + break; } } @@ -283,26 +350,6 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } -/** - * Writes the given byte to the given UART, using a FragmentedBuffer and a DMA - * to bufferize the write if the peripheral is already busy. - */ -static uint32_t write_to_buffer(volatile struct USART* regs, - volatile struct DmaMultiBuffer* buffer, uint8_t byte) -{ - //if the tx register is empty, there is no need to go through the dma - if (regs->SR.TXE) { - reg_write(regs->DR, USART_DR_DR, byte); - //enable IRQ, disable DMA - reg_reset(regs->CR3, USART_CR3_DMAT); - reg_set(regs->CR1, USART_CR1_TXEIE); - nvic_enable(NVIC_IRQ_USART1); - return 0; - } - - return dma_mbuf_write_byte(buffer, byte); -} - /** * Reads the oldest byte from the given CircularBuffer if any. Returns 0 if the * read was successfull, 1 otherwise @@ -345,6 +392,26 @@ static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param) usart1_rx_buffer.dmaLooped = true; } +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ +static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + usart2_rx_buffer.dmaLooped = true; +} + +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ +static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + usart3_rx_buffer.dmaLooped = true; +} + //--ISRs------------------------------------------------------------------------ @@ -359,3 +426,25 @@ void hdr_usart1(void) dma_mbuf_refresh(&usart1_tx_buffer); } +void hdr_usart2(void) +{ + //disable the interrupt. It will be reenabled on a write if needed + nvic_clear_pending(NVIC_IRQ_USART2); + nvic_disable(NVIC_IRQ_USART2); + reg_reset(usart2->CR1, USART_CR1_TXEIE); + reg_set(usart2->CR3, USART_CR3_DMAT); + + dma_mbuf_refresh(&usart2_tx_buffer); +} + +void hdr_usart3(void) +{ + //disable the interrupt. It will be reenabled on a write if needed + nvic_clear_pending(NVIC_IRQ_USART3); + nvic_disable(NVIC_IRQ_USART3); + reg_reset(usart3->CR1, USART_CR1_TXEIE); + reg_set(usart3->CR3, USART_CR3_DMAT); + + dma_mbuf_refresh(&usart3_tx_buffer); +} + -- 2.45.2 From 256e3f30ab581a0ee1684244b0dbc4af77270dcf Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 16 Sep 2023 23:50:13 +0200 Subject: [PATCH 53/85] Make USART writes non-blocking The application should be the one to decide if a write should be blocking or not --- drivers/dma_mbuf.c | 11 +++++------ drivers/usart.c | 10 +++++++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c index 68462a7..47bb2cc 100644 --- a/drivers/dma_mbuf.c +++ b/drivers/dma_mbuf.c @@ -49,10 +49,11 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, //if the current buffer is full, we need to switch it with an empty one if (buffer->byte_index >= buffer->buffer_size) { - //if all buffer full, simply wait for the DMA to empty one - dma_exit_critical(buffer->dma, buffer->channel); - while (buffer->free_buffer_nb == 0) {} - dma_enter_critical(buffer->dma, buffer->channel); + //if all buffer full, give up + if (buffer->free_buffer_nb == 0) { + dma_exit_critical(buffer->dma, buffer->channel); + return 1; + } ++buffer->buffer_index; if (buffer->buffer_index >= buffer->buffer_nb) { @@ -61,8 +62,6 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, --buffer->free_buffer_nb; buffer->byte_index = 0; - } else { - dma_enter_critical(buffer->dma, buffer->channel); } //write the byte diff --git a/drivers/usart.c b/drivers/usart.c index e5b8491..05e0cc8 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -134,9 +134,13 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) return dma_mbuf_write_byte(buffer, byte); } } else { - while (regs->SR.TXE == 0) {} - reg_write(regs->DR, USART_DR_DR, byte); - return 0; + //only write data if the tx register it empty, give up otherwise + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + return 0; + } else { + return 1; + } } } -- 2.45.2 From e2adf48f820c9961c549a981a124f178528d309e Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 17 Sep 2023 00:04:06 +0200 Subject: [PATCH 54/85] Document dma multibuffer module --- drivers/dma_mbuf.c | 8 ++++---- drivers/dma_mbuf.h | 36 +++++++++++++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c index 47bb2cc..c6257a4 100644 --- a/drivers/dma_mbuf.c +++ b/drivers/dma_mbuf.c @@ -1,8 +1,8 @@ -/** @file dma_mbuf.c - * Module handling Direct Memory Access controller's TX functions +/** @file dma_mbuf.h + * Module handling Direct Memory Access controller's multibuffer system * - * The module provides convenient tools to send data to a peripheral or memory - * area in a buffered, non-blocking way + * The module provides a convenient tool to send data to a peripheral in a + * buffered, low-altency, low-cpu usage, non-blocking way */ //--includes-------------------------------------------------------------------- diff --git a/drivers/dma_mbuf.h b/drivers/dma_mbuf.h index b14ba12..37163ae 100644 --- a/drivers/dma_mbuf.h +++ b/drivers/dma_mbuf.h @@ -1,8 +1,8 @@ /** @file dma_mbuf.h - * Module handling Direct Memory Access controller's TX functions + * Module handling Direct Memory Access controller's multibuffer system * - * The module provides convenient tools to send data to a peripheral in a - * buffered, non-blocking way + * The module provides a convenient tool to send data to a peripheral in a + * buffered, low-altency, low-cpu usage, non-blocking way */ #ifndef _DMA_MBUF_H_ @@ -15,6 +15,11 @@ //--type definitions------------------------------------------------------------ +/** + * Struct used by the multibuffer system. This system allows bufferized writes + * to a peripheral with no latency, minimal cpu usage and customisable buffer + * sizes + */ struct DmaMultiBuffer { void** buffers; //list of buffers to write to volatile void* dest; //destination peripheral register @@ -35,13 +40,38 @@ struct DmaMultiBuffer { //--functions------------------------------------------------------------------- +/** + * Configure a DMA multibuffer for a single DMA channel. A list of buffers is + * used to allow concurent write and DMA tranfers to the specified destination + * wich must be a peripheral. The exact DMA configuration to use is also given + * as parameters. The peripheral's specific configuration must be handled + * separately. + * + * This system needs to be started manually: dma_mbuf_refresh() should be called + * whenever a DMA transfer can be started. This can be done manually after + * filling up the buffer. Transfers will then automatically be started as long + * as there are bytes in the buffer. See the usart module for an usage exemple + */ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config); +/** + * Write the given byte to the given buffer. Returns 0 if the write operation + * was successfull, 1 otherwise. The function is non-blocking. + * + * Note: calling this function will not trigger a DMA transfer, see + * dma_mbuf_refresh() to do that + */ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, uint8_t byte); +/** + * Refresh the buffer state, checking for bytes to send and triggering a DMA + * transfer if necessary. Should be called for the first transfer, any remaining + * transfer will be handled automatically until there are no bytes left in the + * buffer + */ void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer); -- 2.45.2 From d84d9cef83f4883b810e11231dfc129696d8a16b Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 17 Sep 2023 17:36:24 +0200 Subject: [PATCH 55/85] Move DMA's rx buffer to a separate module --- drivers/dma.c | 6 +- drivers/dma.h | 2 +- drivers/dma_cbuf.c | 85 +++++++++++++++++++++++++++ drivers/dma_cbuf.h | 44 ++++++++++++++ drivers/usart.c | 142 ++++++++------------------------------------- 5 files changed, 156 insertions(+), 123 deletions(-) create mode 100644 drivers/dma_cbuf.c create mode 100644 drivers/dma_cbuf.h diff --git a/drivers/dma.c b/drivers/dma.c index 0cc80fe..f13f9f1 100644 --- a/drivers/dma.c +++ b/drivers/dma.c @@ -19,7 +19,7 @@ //--local definitions----------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, volatile void* mem, uint16_t size); @@ -36,7 +36,7 @@ static volatile void* dma2_cb_params[5]; //--public functions------------------------------------------------------------ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, volatile void* mem, uint16_t size, DmaCallback callback, volatile void* cb_param) { //reset peripheral first, to ensure proper configuration @@ -185,7 +185,7 @@ uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) //--local functions------------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, volatile void* mem, uint16_t size) { volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; diff --git a/drivers/dma.h b/drivers/dma.h index 14746f6..309f797 100644 --- a/drivers/dma.h +++ b/drivers/dma.h @@ -81,7 +81,7 @@ typedef void (*DmaCallback)(enum DmaIRQSource, volatile void* param); //--functions------------------------------------------------------------------- void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, void* mem, + enum DmaConfig config_mask, volatile void* periph, volatile void* mem, uint16_t size, DmaCallback callback, volatile void* cb_param); void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, diff --git a/drivers/dma_cbuf.c b/drivers/dma_cbuf.c new file mode 100644 index 0000000..52796a2 --- /dev/null +++ b/drivers/dma_cbuf.c @@ -0,0 +1,85 @@ +/** @file dma_cbuf.c + * Module handling Direct Memory Access controller's circular system + * + * The module provides a convenient tool to receive data from a peripheral in a + * buffered, low-latency, low-cpu usage, non-blocking way + */ + +//--includes-------------------------------------------------------------------- + +#include "dma_cbuf.h" + + +//--local definitions----------------------------------------------------------- + +static void cbuf_callback(enum DmaIRQSource src, volatile void* param); + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, + volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config) +{ + #warning "check for null ptr" + + buffer->buffer = raw_buffer; + buffer->src = src; + + buffer->size = buffer_size; + buffer->begin = 0; + + buffer->dma = dma; + buffer->channel = channel; + buffer->config = config; + + buffer->dma_looped = false; + + dma_configure(buffer->dma, buffer->channel, buffer->config, buffer->src, + buffer->buffer, buffer->size, cbuf_callback, buffer); +} + +uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, + uint8_t* byte) +{ + //retreive the current end of the buffer based on the DMA's progress + uint16_t end = buffer->size + - dma_get_remaining(buffer->dma, buffer->channel); + + //check for bytes to read and overflow + if ((end > buffer->begin) && buffer->dma_looped) { + //TODO overflow + buffer->begin = end; + } else if ((buffer->begin == end) && !buffer->dma_looped) { + //TODO no data + return 1; + } + + //read the oldest byte and advance the buffer + uint8_t* raw_buffer = (uint8_t*)buffer->buffer; + *byte = raw_buffer[buffer->begin]; + ++buffer->begin; + if (buffer->begin >= buffer->size) { + buffer->begin = 0; + buffer->dma_looped = false; + } + + return 0; +} + +//--local functions------------------------------------------------------------- + +/** + * Callback called on DMA RX tranfert's completion. Sets a flag needed to + * properly handle the circular buffer + */ +static void cbuf_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + volatile struct DmaCircBuffer* buffer = param; + buffer->dma_looped = true; +} + + diff --git a/drivers/dma_cbuf.h b/drivers/dma_cbuf.h new file mode 100644 index 0000000..d28a438 --- /dev/null +++ b/drivers/dma_cbuf.h @@ -0,0 +1,44 @@ +/** @file dma_cbuf.h + * Module handling Direct Memory Access controller's circular system + * + * The module provides a convenient tool to receive data from a peripheral in a + * buffered, low-latency, low-cpu usage, non-blocking way + */ + +#ifndef _DMA_CBUF_H_ +#define _DMA_CBUF_H_ + +//--includes-------------------------------------------------------------------- + +#include "dma.h" + + +//--type definitions------------------------------------------------------------ + +struct DmaCircBuffer { + volatile void* buffer; //the buffer to use as a circular buffer + volatile void* src; //source peripheral register + + uint16_t size; //the size of the buffer + uint16_t begin; //pointer to the current begin of the buffer + + enum DmaPeriph dma; //DMA peripheral, must correspond to peripheral + enum DmaChannel channel; //DMA channel, must correspond to peripheral + enum DmaConfig config; //DMA config, must correspond to peripheral + + bool dma_looped; //whether the DMA looped or not (buffer overflow) +}; + + +//--functions------------------------------------------------------------------- + +void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, + volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config); + +uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, + uint8_t* byte); + + +#endif //_DMA_CBUF_H_ + diff --git a/drivers/usart.c b/drivers/usart.c index 05e0cc8..c0f84c8 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -15,34 +15,27 @@ #include "rcc.h" #include "dma.h" #include "dma_mbuf.h" +#include "dma_cbuf.h" #include "stddef.h" //--local definitions----------------------------------------------------------- -#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ - | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW) +#define DMA_TX_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ + | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW) +#define DMA_RX_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH \ + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM \ + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS \ + | DMA_CONFIG_PRIO_LOW) -struct CircularBuffer { - volatile uint8_t* buffer; //the buffer to use as a circular buffer - uint16_t size; //the size of the buffer - uint16_t begin; //pointer to the current begin of the buffer - bool dmaLooped; //whether the DMA looped or not (buffer overflow) -}; static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); -static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, - enum DmaChannel channel, uint8_t* byte); - -static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param); -static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param); -static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param); //--local variables------------------------------------------------------------- @@ -51,11 +44,11 @@ static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; -static volatile struct CircularBuffer usart1_rx_buffer; +static volatile struct DmaCircBuffer usart1_rx_buffer; static volatile struct DmaMultiBuffer usart1_tx_buffer; -static volatile struct CircularBuffer usart2_rx_buffer; +static volatile struct DmaCircBuffer usart2_rx_buffer; static volatile struct DmaMultiBuffer usart2_tx_buffer; -static volatile struct CircularBuffer usart3_rx_buffer; +static volatile struct DmaCircBuffer usart3_rx_buffer; static volatile struct DmaMultiBuffer usart3_tx_buffer; @@ -72,6 +65,7 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); +#warning "fix zeroed variables init" usart1_tx_buffer.buffers = NULL; usart1_rx_buffer.buffer = NULL; break; @@ -147,24 +141,20 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { volatile struct USART* regs; - volatile struct CircularBuffer* buffer; - enum DmaChannel dma_channel; + volatile struct DmaCircBuffer* buffer; switch (periph) { case USART_PERIPH_1: regs = usart1; buffer = &usart1_rx_buffer; - dma_channel = DMA_CHANNEL_5; break; case USART_PERIPH_2: regs = usart2; buffer = &usart2_rx_buffer; - dma_channel = DMA_CHANNEL_6; break; case USART_PERIPH_3: regs = usart3; buffer = &usart3_rx_buffer; - dma_channel = DMA_CHANNEL_3; break; default: return 1; @@ -172,7 +162,7 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) } if (buffer->buffer) { - return read_from_buffer(buffer, dma_channel, byte); + return dma_cbuf_read_byte(buffer, byte); } else { if (regs->SR.RXNE) { *byte = regs->DR.DR; @@ -190,17 +180,17 @@ void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, case USART_PERIPH_1: dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4, - DMA_CONFIG); + DMA_TX_CONFIG); break; case USART_PERIPH_2: dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7, - DMA_CONFIG); + DMA_TX_CONFIG); break; case USART_PERIPH_3: dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2, - DMA_CONFIG); + DMA_TX_CONFIG); break; } } @@ -210,43 +200,19 @@ void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, { switch (periph) { case USART_PERIPH_1: - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_5, - DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH - | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM - | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS - | DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer, - size, usart1_rx_callback, NULL); - usart1_rx_buffer.buffer = buffer; - usart1_rx_buffer.size = size; - usart1_rx_buffer.begin = 0; - usart1_rx_buffer.dmaLooped = false; + dma_cbuf_configure(&usart1_rx_buffer, buffer, (void*)&usart1->DR, + size, DMA_PERIPH_1, DMA_CHANNEL_5, DMA_RX_CONFIG); reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_6, - DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH - | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM - | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS - | DMA_CONFIG_PRIO_LOW, (void*)&usart2->DR, buffer, - size, usart2_rx_callback, NULL); - usart2_rx_buffer.buffer = buffer; - usart2_rx_buffer.size = size; - usart2_rx_buffer.begin = 0; - usart2_rx_buffer.dmaLooped = false; + dma_cbuf_configure(&usart2_rx_buffer, buffer, (void*)&usart2->DR, + size, DMA_PERIPH_1, DMA_CHANNEL_6, DMA_RX_CONFIG); reg_set(usart2->CR3, USART_CR3_DMAR); break; case USART_PERIPH_3: - dma_configure(DMA_PERIPH_1, DMA_CHANNEL_3, - DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH - | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM - | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS - | DMA_CONFIG_PRIO_LOW, (void*)&usart3->DR, buffer, - size, usart3_rx_callback, NULL); - usart3_rx_buffer.buffer = buffer; - usart3_rx_buffer.size = size; - usart3_rx_buffer.begin = 0; - usart3_rx_buffer.dmaLooped = false; + dma_cbuf_configure(&usart3_rx_buffer, buffer, (void*)&usart3->DR, + size, DMA_PERIPH_1, DMA_CHANNEL_3, DMA_RX_CONFIG); reg_set(usart3->CR3, USART_CR3_DMAR); break; @@ -354,68 +320,6 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } -/** - * Reads the oldest byte from the given CircularBuffer if any. Returns 0 if the - * read was successfull, 1 otherwise - */ -static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer, - enum DmaChannel channel, uint8_t* byte) -{ - //retreive the current end of the buffer based on the DMA's progress - uint16_t end = buffer->size - dma_get_remaining(DMA_PERIPH_1, channel); - - //check for bytes to read and overflow - if ((end > buffer->begin) && buffer->dmaLooped) { - //TODO overflow - buffer->begin = end; - } else if ((buffer->begin == end) && !buffer->dmaLooped) { - //TODO no data - return 1; - } - - //read the oldest byte and advance the buffer - *byte = buffer->buffer[buffer->begin]; - ++buffer->begin; - if (buffer->begin >= buffer->size) { - buffer->begin = 0; - buffer->dmaLooped = false; - } - - return 0; -} - -//--allbacks------------------------------------------------------------------- - -/** - * Callback called on DMA RX tranfert's completion. Sets a flag needed to - * properly handle the circular buffer - */ -static void usart1_rx_callback(enum DmaIRQSource src, volatile void* param) -{ - (void)src; //only transfer complete expected - usart1_rx_buffer.dmaLooped = true; -} - -/** - * Callback called on DMA RX tranfert's completion. Sets a flag needed to - * properly handle the circular buffer - */ -static void usart2_rx_callback(enum DmaIRQSource src, volatile void* param) -{ - (void)src; //only transfer complete expected - usart2_rx_buffer.dmaLooped = true; -} - -/** - * Callback called on DMA RX tranfert's completion. Sets a flag needed to - * properly handle the circular buffer - */ -static void usart3_rx_callback(enum DmaIRQSource src, volatile void* param) -{ - (void)src; //only transfer complete expected - usart3_rx_buffer.dmaLooped = true; -} - //--ISRs------------------------------------------------------------------------ -- 2.45.2 From 4464156981efead7775bdd288b66fdc0d589f5b4 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 17 Sep 2023 17:52:14 +0200 Subject: [PATCH 56/85] Move DMA config to buffers Control over most parameters is not needed since they cannot change for the buffer to work as expected. Only the priority should be adjustable --- drivers/dma_cbuf.c | 8 ++++++-- drivers/dma_cbuf.h | 2 +- drivers/dma_mbuf.c | 8 ++++++-- drivers/dma_mbuf.h | 7 +++---- drivers/usart.c | 26 ++++++++------------------ drivers/usart.h | 6 ++++-- 6 files changed, 28 insertions(+), 29 deletions(-) diff --git a/drivers/dma_cbuf.c b/drivers/dma_cbuf.c index 52796a2..f324d20 100644 --- a/drivers/dma_cbuf.c +++ b/drivers/dma_cbuf.c @@ -12,6 +12,10 @@ //--local definitions----------------------------------------------------------- +#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH \ + | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM \ + | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS) + static void cbuf_callback(enum DmaIRQSource src, volatile void* param); @@ -21,7 +25,7 @@ static void cbuf_callback(enum DmaIRQSource src, volatile void* param); void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config) + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority) { #warning "check for null ptr" @@ -33,7 +37,7 @@ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, buffer->dma = dma; buffer->channel = channel; - buffer->config = config; + buffer->config = DMA_CONFIG | priority; buffer->dma_looped = false; diff --git a/drivers/dma_cbuf.h b/drivers/dma_cbuf.h index d28a438..12ca678 100644 --- a/drivers/dma_cbuf.h +++ b/drivers/dma_cbuf.h @@ -34,7 +34,7 @@ struct DmaCircBuffer { void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config); + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority); uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, uint8_t* byte); diff --git a/drivers/dma_mbuf.c b/drivers/dma_mbuf.c index c6257a4..dbbea46 100644 --- a/drivers/dma_mbuf.c +++ b/drivers/dma_mbuf.c @@ -12,6 +12,10 @@ //--local definitions----------------------------------------------------------- +#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ + | DMA_CONFIG_MSIZE_8BITS) + static void mbuf_callback(enum DmaIRQSource src, volatile void* param); @@ -21,7 +25,7 @@ static void mbuf_callback(enum DmaIRQSource src, volatile void* param); void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config) + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority) { #warning "check for null ptr" @@ -38,7 +42,7 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, buffer->dma = dma; buffer->channel = channel; - buffer->config = config; + buffer->config = DMA_CONFIG | priority; } uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, diff --git a/drivers/dma_mbuf.h b/drivers/dma_mbuf.h index 37163ae..b50b3af 100644 --- a/drivers/dma_mbuf.h +++ b/drivers/dma_mbuf.h @@ -43,9 +43,8 @@ struct DmaMultiBuffer { /** * Configure a DMA multibuffer for a single DMA channel. A list of buffers is * used to allow concurent write and DMA tranfers to the specified destination - * wich must be a peripheral. The exact DMA configuration to use is also given - * as parameters. The peripheral's specific configuration must be handled - * separately. + * wich must be a peripheral. The DMA's priority is also given as parameters. + * The peripheral's specific configuration must be handled separately. * * This system needs to be started manually: dma_mbuf_refresh() should be called * whenever a DMA transfer can be started. This can be done manually after @@ -54,7 +53,7 @@ struct DmaMultiBuffer { */ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config); + enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority); /** * Write the given byte to the given buffer. Returns 0 if the write operation diff --git a/drivers/usart.c b/drivers/usart.c index c0f84c8..800235b 100644 --- a/drivers/usart.c +++ b/drivers/usart.c @@ -22,16 +22,6 @@ //--local definitions----------------------------------------------------------- -#define DMA_TX_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ - | DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW) - -#define DMA_RX_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH \ - | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM \ - | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS \ - | DMA_CONFIG_PRIO_LOW) - - static void configure_usart(volatile struct USART* regs, enum UsartConfig config); static void configure_baudrate(volatile struct USART* regs, uint32_t clock, @@ -174,45 +164,45 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) } void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, - uint16_t buffer_size, uint8_t buffer_nb) + uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority) { switch (periph) { case USART_PERIPH_1: dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4, - DMA_TX_CONFIG); + priority); break; case USART_PERIPH_2: dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7, - DMA_TX_CONFIG); + priority); break; case USART_PERIPH_3: dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR, buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2, - DMA_TX_CONFIG); + priority); break; } } void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, - uint16_t size) + uint16_t size, enum DmaConfig priority) { switch (periph) { case USART_PERIPH_1: dma_cbuf_configure(&usart1_rx_buffer, buffer, (void*)&usart1->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_5, DMA_RX_CONFIG); + size, DMA_PERIPH_1, DMA_CHANNEL_5, priority); reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: dma_cbuf_configure(&usart2_rx_buffer, buffer, (void*)&usart2->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_6, DMA_RX_CONFIG); + size, DMA_PERIPH_1, DMA_CHANNEL_6, priority); reg_set(usart2->CR3, USART_CR3_DMAR); break; case USART_PERIPH_3: dma_cbuf_configure(&usart3_rx_buffer, buffer, (void*)&usart3->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_3, DMA_RX_CONFIG); + size, DMA_PERIPH_1, DMA_CHANNEL_3, priority); reg_set(usart3->CR3, USART_CR3_DMAR); break; diff --git a/drivers/usart.h b/drivers/usart.h index c854c77..8739e63 100644 --- a/drivers/usart.h +++ b/drivers/usart.h @@ -10,6 +10,8 @@ //--includes-------------------------------------------------------------------- +#include "dma.h" + #include "stdint.h" @@ -47,10 +49,10 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, - uint16_t buffer_size, uint8_t buffer_nb); + uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority); void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, - uint16_t size); + uint16_t size, enum DmaConfig priority); #endif //_USART_H_ -- 2.45.2 From 086f9155f793cc3683af6abb37f1bc7fc0442551 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 18 Sep 2023 11:45:12 +0200 Subject: [PATCH 57/85] Fix RAM initialisation The reset handler is responsible for loading the variables default values. This includes variables initialized to 0, although they are handed through bss and not data --- linker.ld | 3 +++ startup.s | 24 ++++++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/linker.ld b/linker.ld index 4f30b65..55cadad 100644 --- a/linker.ld +++ b/linker.ld @@ -64,7 +64,10 @@ SECTIONS .bss : { . = ALIGN(4); + _sbss = .; *(.bss) + . = ALIGN(4); + _ebss = .; } > RAM /* memory space allocated to stack. The stack is situated at the very end of diff --git a/startup.s b/startup.s index 3a3b5a1..8f48739 100644 --- a/startup.s +++ b/startup.s @@ -34,19 +34,35 @@ hdr_reset: ldr r1, = _sdata ldr r2, = _edata subs r2, r2, r1 - bcc startup_init_end + bcc data_init_end ldr r3, = _sromdata movs r0, #0 -startup_init_loop: +data_init_loop: ldr r4, [r3, r0] str r4, [r1, r0] adds r0, r0, #4 cmp r0, r2 - bcc startup_init_loop + bcc data_init_loop -startup_init_end: +data_init_end: +//initialize RAM to zero + ldr r1, = _sbss + ldr r2, = _ebss + subs r2, r2, r1 + bcc bss_init_end + movs r3, #0 + + movs r0, #0 + +bss_init_loop: + str r3, [r1, r0] + adds r0, r0, #4 + cmp r0, r2 + bcc bss_init_loop + +bss_init_end: b main b hdr_reset -- 2.45.2 From a7099d5dfd25be443f12b2be42ed74114e9f8cd0 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Thu, 21 Sep 2023 20:41:50 +0200 Subject: [PATCH 58/85] Rename drivers folder to drv --- {drivers => drv}/afio.c | 0 {drivers => drv}/afio.h | 0 {drivers => drv}/afio_regs.h | 0 {drivers => drv}/dma.c | 0 {drivers => drv}/dma.h | 0 {drivers => drv}/dma_cbuf.c | 0 {drivers => drv}/dma_cbuf.h | 14 ++++++++++++++ {drivers => drv}/dma_mbuf.c | 0 {drivers => drv}/dma_mbuf.h | 0 {drivers => drv}/dma_regs.h | 0 {drivers => drv}/exti.c | 0 {drivers => drv}/exti.h | 0 {drivers => drv}/exti_regs.h | 0 {drivers => drv}/flash.c | 0 {drivers => drv}/flash.h | 0 {drivers => drv}/flash_regs.h | 0 {drivers => drv}/gpio.c | 0 {drivers => drv}/gpio.h | 0 {drivers => drv}/gpio_regs.h | 0 {drivers => drv}/nvic.c | 0 {drivers => drv}/nvic.h | 0 {drivers => drv}/nvic_regs.h | 0 {drivers => drv}/rcc.c | 0 {drivers => drv}/rcc.h | 0 {drivers => drv}/rcc_regs.h | 0 {drivers => drv}/reg.h | 0 {drivers => drv}/usart.c | 0 {drivers => drv}/usart.h | 0 {drivers => drv}/usart_regs.h | 0 29 files changed, 14 insertions(+) rename {drivers => drv}/afio.c (100%) rename {drivers => drv}/afio.h (100%) rename {drivers => drv}/afio_regs.h (100%) rename {drivers => drv}/dma.c (100%) rename {drivers => drv}/dma.h (100%) rename {drivers => drv}/dma_cbuf.c (100%) rename {drivers => drv}/dma_cbuf.h (70%) rename {drivers => drv}/dma_mbuf.c (100%) rename {drivers => drv}/dma_mbuf.h (100%) rename {drivers => drv}/dma_regs.h (100%) rename {drivers => drv}/exti.c (100%) rename {drivers => drv}/exti.h (100%) rename {drivers => drv}/exti_regs.h (100%) rename {drivers => drv}/flash.c (100%) rename {drivers => drv}/flash.h (100%) rename {drivers => drv}/flash_regs.h (100%) rename {drivers => drv}/gpio.c (100%) rename {drivers => drv}/gpio.h (100%) rename {drivers => drv}/gpio_regs.h (100%) rename {drivers => drv}/nvic.c (100%) rename {drivers => drv}/nvic.h (100%) rename {drivers => drv}/nvic_regs.h (100%) rename {drivers => drv}/rcc.c (100%) rename {drivers => drv}/rcc.h (100%) rename {drivers => drv}/rcc_regs.h (100%) rename {drivers => drv}/reg.h (100%) rename {drivers => drv}/usart.c (100%) rename {drivers => drv}/usart.h (100%) rename {drivers => drv}/usart_regs.h (100%) diff --git a/drivers/afio.c b/drv/afio.c similarity index 100% rename from drivers/afio.c rename to drv/afio.c diff --git a/drivers/afio.h b/drv/afio.h similarity index 100% rename from drivers/afio.h rename to drv/afio.h diff --git a/drivers/afio_regs.h b/drv/afio_regs.h similarity index 100% rename from drivers/afio_regs.h rename to drv/afio_regs.h diff --git a/drivers/dma.c b/drv/dma.c similarity index 100% rename from drivers/dma.c rename to drv/dma.c diff --git a/drivers/dma.h b/drv/dma.h similarity index 100% rename from drivers/dma.h rename to drv/dma.h diff --git a/drivers/dma_cbuf.c b/drv/dma_cbuf.c similarity index 100% rename from drivers/dma_cbuf.c rename to drv/dma_cbuf.c diff --git a/drivers/dma_cbuf.h b/drv/dma_cbuf.h similarity index 70% rename from drivers/dma_cbuf.h rename to drv/dma_cbuf.h index 12ca678..4221f14 100644 --- a/drivers/dma_cbuf.h +++ b/drv/dma_cbuf.h @@ -15,6 +15,11 @@ //--type definitions------------------------------------------------------------ +/** + * Struct used by the circular buffer system. This system allows bufferized + * reads to a peripheral with no latency, minimal cpu usage and customisable + * buffer sizes + */ struct DmaCircBuffer { volatile void* buffer; //the buffer to use as a circular buffer volatile void* src; //source peripheral register @@ -32,6 +37,15 @@ struct DmaCircBuffer { //--functions------------------------------------------------------------------- +/** + * Configure a DMA circular buffer for a single DMA channel. A standard buffer + * is used a base to construct a circular buffer, supplied in data by DMA + * tranfers from a peripheral. The DMA's priority is given as parameters. + * The peripheral's specific configuration must be handled separately. + * + * Once this function is called, the system will start running right away and + * will stay running until manually stopped + */ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority); diff --git a/drivers/dma_mbuf.c b/drv/dma_mbuf.c similarity index 100% rename from drivers/dma_mbuf.c rename to drv/dma_mbuf.c diff --git a/drivers/dma_mbuf.h b/drv/dma_mbuf.h similarity index 100% rename from drivers/dma_mbuf.h rename to drv/dma_mbuf.h diff --git a/drivers/dma_regs.h b/drv/dma_regs.h similarity index 100% rename from drivers/dma_regs.h rename to drv/dma_regs.h diff --git a/drivers/exti.c b/drv/exti.c similarity index 100% rename from drivers/exti.c rename to drv/exti.c diff --git a/drivers/exti.h b/drv/exti.h similarity index 100% rename from drivers/exti.h rename to drv/exti.h diff --git a/drivers/exti_regs.h b/drv/exti_regs.h similarity index 100% rename from drivers/exti_regs.h rename to drv/exti_regs.h diff --git a/drivers/flash.c b/drv/flash.c similarity index 100% rename from drivers/flash.c rename to drv/flash.c diff --git a/drivers/flash.h b/drv/flash.h similarity index 100% rename from drivers/flash.h rename to drv/flash.h diff --git a/drivers/flash_regs.h b/drv/flash_regs.h similarity index 100% rename from drivers/flash_regs.h rename to drv/flash_regs.h diff --git a/drivers/gpio.c b/drv/gpio.c similarity index 100% rename from drivers/gpio.c rename to drv/gpio.c diff --git a/drivers/gpio.h b/drv/gpio.h similarity index 100% rename from drivers/gpio.h rename to drv/gpio.h diff --git a/drivers/gpio_regs.h b/drv/gpio_regs.h similarity index 100% rename from drivers/gpio_regs.h rename to drv/gpio_regs.h diff --git a/drivers/nvic.c b/drv/nvic.c similarity index 100% rename from drivers/nvic.c rename to drv/nvic.c diff --git a/drivers/nvic.h b/drv/nvic.h similarity index 100% rename from drivers/nvic.h rename to drv/nvic.h diff --git a/drivers/nvic_regs.h b/drv/nvic_regs.h similarity index 100% rename from drivers/nvic_regs.h rename to drv/nvic_regs.h diff --git a/drivers/rcc.c b/drv/rcc.c similarity index 100% rename from drivers/rcc.c rename to drv/rcc.c diff --git a/drivers/rcc.h b/drv/rcc.h similarity index 100% rename from drivers/rcc.h rename to drv/rcc.h diff --git a/drivers/rcc_regs.h b/drv/rcc_regs.h similarity index 100% rename from drivers/rcc_regs.h rename to drv/rcc_regs.h diff --git a/drivers/reg.h b/drv/reg.h similarity index 100% rename from drivers/reg.h rename to drv/reg.h diff --git a/drivers/usart.c b/drv/usart.c similarity index 100% rename from drivers/usart.c rename to drv/usart.c diff --git a/drivers/usart.h b/drv/usart.h similarity index 100% rename from drivers/usart.h rename to drv/usart.h diff --git a/drivers/usart_regs.h b/drv/usart_regs.h similarity index 100% rename from drivers/usart_regs.h rename to drv/usart_regs.h -- 2.45.2 From dbfba205204cd17dd641edcfb5c74148ddceb26c Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 18:33:20 +0200 Subject: [PATCH 59/85] Temporary fix for mbuf's byte index Each buffer should use its own byte index since the value would otherwise be overwritten when writing to other buffers --- drv/dma_mbuf.c | 30 +++++++++++++++++++++--------- drv/dma_mbuf.h | 1 - 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drv/dma_mbuf.c b/drv/dma_mbuf.c index dbbea46..dd7a3cc 100644 --- a/drv/dma_mbuf.c +++ b/drv/dma_mbuf.c @@ -18,6 +18,9 @@ static void mbuf_callback(enum DmaIRQSource src, volatile void* param); +#define byte_index (((uint8_t**)buffer->buffers)[buffer->buffer_index][buffer->buffer_size + 1]) +#define dma_byte_index (((uint8_t**)buffer->buffers)[buffer->dma_buffer_index][buffer->buffer_size + 1]) + //--local variables------------------------------------------------------------- @@ -32,8 +35,7 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, buffer->buffers = buffers; buffer->dest = dest; - buffer->buffer_size = buffer_size; - buffer->byte_index = 0; + buffer->buffer_size = buffer_size - 2; buffer->buffer_nb = buffer_nb; buffer->free_buffer_nb = buffer_nb - 1; @@ -43,6 +45,12 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, buffer->dma = dma; buffer->channel = channel; buffer->config = DMA_CONFIG | priority; + + for (uint8_t i=0; ibuffer_nb; ++i) { + for (uint16_t j=0; jbuffer_size + 2; ++j) { + ((uint8_t**)buffer->buffers)[i][j] = 0; + } + } } uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, @@ -51,7 +59,8 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, dma_enter_critical(buffer->dma, buffer->channel); //if the current buffer is full, we need to switch it with an empty one - if (buffer->byte_index >= buffer->buffer_size) { + volatile uint16_t index = byte_index; + if (byte_index >= buffer->buffer_size) { //if all buffer full, give up if (buffer->free_buffer_nb == 0) { @@ -65,13 +74,14 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, } --buffer->free_buffer_nb; - buffer->byte_index = 0; + byte_index = 0; } //write the byte uint8_t** buffers = (uint8_t**)buffer->buffers; - buffers[buffer->buffer_index][buffer->byte_index] = byte; - ++buffer->byte_index; + buffers[buffer->buffer_index][byte_index] = byte; + ++byte_index; + ++index; dma_exit_critical(buffer->dma, buffer->channel); return 0; @@ -81,14 +91,14 @@ void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer) { //no more data to send, stop here if (buffer->dma_buffer_index == buffer->buffer_index - && buffer->byte_index == 0) { + && byte_index == 0) { return; } //else start a new transfer dma_configure(buffer->dma, buffer->channel, buffer->config, buffer->dest, buffer->buffers[buffer->dma_buffer_index], - buffer->byte_index, mbuf_callback, buffer); + dma_byte_index, mbuf_callback, buffer); //if the newly transfering buffer was being written to, switch the current //buffer. Since we just ended a transfer, the next buffer should be empty @@ -98,7 +108,9 @@ void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer) if (buffer->buffer_index >= buffer->buffer_nb) { buffer->buffer_index = 0; } - buffer->byte_index = 0; + --buffer->free_buffer_nb; + + byte_index = 0; } return; diff --git a/drv/dma_mbuf.h b/drv/dma_mbuf.h index b50b3af..f26a6d4 100644 --- a/drv/dma_mbuf.h +++ b/drv/dma_mbuf.h @@ -25,7 +25,6 @@ struct DmaMultiBuffer { volatile void* dest; //destination peripheral register uint16_t buffer_size; //size of a single buffer - uint16_t byte_index; //index of the current byte in the current buffer uint8_t buffer_nb; //total number of buffers uint8_t free_buffer_nb; //number of buffers not currently used -- 2.45.2 From 0628c4c07ce89ee8130b05b608d0c2a4b6be3a2f Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 18:35:36 +0200 Subject: [PATCH 60/85] Use TC instead of TXE Transfer Complete is preferable to TX Empty when using a DMA since we could be polling the bit between transfers. TXE would be 1 but the DMA would be transfering another at the same time. TC takes the DMA into account --- drv/usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drv/usart.c b/drv/usart.c index 800235b..4901ed2 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -107,7 +107,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) if (buffer->buffers) { //if the tx register is empty, there is no need to go through the dma - if (regs->SR.TXE) { + if (regs->SR.TC) { reg_write(regs->DR, USART_DR_DR, byte); //enable IRQ, disable DMA reg_reset(regs->CR3, USART_CR3_DMAT); -- 2.45.2 From cc54ca7ca89c08e064d87656d4fdb1083140e645 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 21:59:29 +0200 Subject: [PATCH 61/85] Improve mbuf fix Byte index is now stored on 2 bytes. Macros have been made cleaner --- drv/dma_mbuf.c | 7 +++++-- drv/dma_mbuf.h | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drv/dma_mbuf.c b/drv/dma_mbuf.c index dd7a3cc..8d10b27 100644 --- a/drv/dma_mbuf.c +++ b/drv/dma_mbuf.c @@ -18,8 +18,11 @@ static void mbuf_callback(enum DmaIRQSource src, volatile void* param); -#define byte_index (((uint8_t**)buffer->buffers)[buffer->buffer_index][buffer->buffer_size + 1]) -#define dma_byte_index (((uint8_t**)buffer->buffers)[buffer->dma_buffer_index][buffer->buffer_size + 1]) +//take last 2 bytes of a buffer and assemble them store the current byte index +#define byte_index (((uint16_t**)buffer->buffers) \ + [buffer->buffer_index][buffer->buffer_size/2]) +#define dma_byte_index (((uint16_t**)buffer->buffers) \ + [buffer->dma_buffer_index][buffer->buffer_size/2]) //--local variables------------------------------------------------------------- diff --git a/drv/dma_mbuf.h b/drv/dma_mbuf.h index f26a6d4..4ab6952 100644 --- a/drv/dma_mbuf.h +++ b/drv/dma_mbuf.h @@ -43,7 +43,8 @@ struct DmaMultiBuffer { * Configure a DMA multibuffer for a single DMA channel. A list of buffers is * used to allow concurent write and DMA tranfers to the specified destination * wich must be a peripheral. The DMA's priority is also given as parameters. - * The peripheral's specific configuration must be handled separately. + * The peripheral's specific configuration must be handled separately. 2 bytes + * are reserved in each buffer for index storage. * * This system needs to be started manually: dma_mbuf_refresh() should be called * whenever a DMA transfer can be started. This can be done manually after -- 2.45.2 From b992e2b8fb68daebd1c00c5385cce2bd53784f67 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 22:02:20 +0200 Subject: [PATCH 62/85] First implementation of debug service For now, only basic traces are implemented. The rest will follow once a printf function is implemented --- srv/debug.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++ srv/debug.h | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 srv/debug.c create mode 100644 srv/debug.h diff --git a/srv/debug.c b/srv/debug.c new file mode 100644 index 0000000..44711ac --- /dev/null +++ b/srv/debug.c @@ -0,0 +1,60 @@ +/** @file debug.c + * Module handling various debug functions + * + * The module provides a range of functions and tools to make debug more + * convenient + */ + +//--includes-------------------------------------------------------------------- + +#include "debug.h" + + +//--local definitions----------------------------------------------------------- + +#define BUFFER_SIZE 83 //80 char line + \n + 2 bytes for index +#define BUFFER_NB 3 //1 buffer in write, one in transfer and one waiting + +//--local variables------------------------------------------------------------- + +static enum UsartPeriph usart_periph; +static uint8_t tx_buffer1[BUFFER_SIZE]; +static uint8_t tx_buffer2[BUFFER_SIZE]; +static uint8_t tx_buffer3[BUFFER_SIZE]; +static uint8_t* tx_buffers[BUFFER_NB] = {tx_buffer1, tx_buffer2, tx_buffer3}; + + +//--public functions------------------------------------------------------------ + +#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR + +void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, + enum GpioPin tx_pin) +{ + usart_periph = usart; + gpio_configure(tx_port, tx_pin, GPIO_MODE_OUTPUT_FAST, + GPIO_CONFIG_OUT_ALT_PUSH_PULL); + usart_configure(usart_periph, USART_CONFIG_8N1, 1152000); + + usart_set_tx_buffer(USART_PERIPH_3, tx_buffers, BUFFER_SIZE, BUFFER_NB, + DMA_CONFIG_PRIO_LOW); + + debug_trace("\n"); + debug_trace("--------------------------------------------------------------------------------\n"); + debug_trace("starting debug software\n"); + debug_trace("compiled on " __DATE__ " at " __TIME__ "\n"); + debug_trace("--------------------------------------------------------------------------------\n"); +} + +void _debug_trace(char* format, ...) +{ + while(*format != '\0') { + while(usart_write_byte(usart_periph, *format)) {} + ++format; + } +} + +#endif + +//--local functions------------------------------------------------------------- + diff --git a/srv/debug.h b/srv/debug.h new file mode 100644 index 0000000..cd511d6 --- /dev/null +++ b/srv/debug.h @@ -0,0 +1,59 @@ +/** @file debug.h + * Module handling various debug functions + * + * The module provides a range of functions and tools to make debug more + * convenient + */ + +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +//--includes-------------------------------------------------------------------- + +#include "../drv/usart.h" +#include "../drv/gpio.h" + +#include "stdint.h" + +#define DEBUG_TRACE 1 +#define DEBUG_WARN 0 +#define DEBUG_ERROR 0 + +//--type definitions------------------------------------------------------------ + +#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR +#define debug_init(usart, tx_port, tx_pin) _debug_init(usart, tx_port, tx_pin) +#else +#define debug_init(usart) do {} while (0) +#endif + +#if DEBUG_TRACE +#define debug_trace(format, ...) _debug_trace(format __VA_OPT__(,) __VA_ARGS__) +#else +#define debug_trace(format, ...) do {} while (0) +#endif + +#if DEBUG_WARN +#define debug_warn(format, ...) _debug_warn(format __VA_OPT__(,) __VA_ARGS__) +#else +#define debug_warn(format, ...) do {} while (0) +#endif + +#if DEBUG_ERROR +#define debug_error(format, ...) _debug_error(format __VA_OPT__(,) __VA_ARGS__) +#else +#define debug_error(format, ...) do {} while (0) +#endif + + +//--functions------------------------------------------------------------------- + +void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, + enum GpioPin tx_pin); +void _debug_trace(char* format, ...); +void _debug_warn(char* format, ...); +void _debug_error(char* format, ...); + + +#endif //_DEBUG_H_ + -- 2.45.2 From e1097048a69b77b5ce12c6d73e25df9aa2496d90 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 24 Sep 2023 22:04:38 +0200 Subject: [PATCH 63/85] RAM initialisation fixed in 086f915 --- drv/usart.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drv/usart.c b/drv/usart.c index 4901ed2..ae53d66 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -55,7 +55,6 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); -#warning "fix zeroed variables init" usart1_tx_buffer.buffers = NULL; usart1_rx_buffer.buffer = NULL; break; -- 2.45.2 From ccf36ac400e7f978ff53f25442d2599476ab761d Mon Sep 17 00:00:00 2001 From: Steins7 Date: Wed, 3 Apr 2024 22:03:15 +0200 Subject: [PATCH 64/85] Simplify dma buffers and adjust usart The dma buffer should be services that are used on top of peripherals. As such, the usart driver should'nt directly use them, this is up to the user. The multi-buffer has also been simplified since I was not satisfied with the previous implementation --- drv/dma.h | 7 ++ drv/dma_mbuf.c | 143 ---------------------------- drv/usart.c | 203 ++++++++++++++++------------------------ drv/usart.h | 9 +- {drv => srv}/dma_cbuf.c | 17 ++-- {drv => srv}/dma_cbuf.h | 14 ++- srv/dma_mbuf.c | 99 ++++++++++++++++++++ {drv => srv}/dma_mbuf.h | 28 +++--- 8 files changed, 218 insertions(+), 302 deletions(-) delete mode 100644 drv/dma_mbuf.c rename {drv => srv}/dma_cbuf.c (85%) rename {drv => srv}/dma_cbuf.h (78%) create mode 100644 srv/dma_mbuf.c rename {drv => srv}/dma_mbuf.h (68%) diff --git a/drv/dma.h b/drv/dma.h index 309f797..89d9e00 100644 --- a/drv/dma.h +++ b/drv/dma.h @@ -77,6 +77,13 @@ enum DmaIRQSource { typedef void (*DmaCallback)(enum DmaIRQSource, volatile void* param); +struct DmaParam { + void* periph; + enum DmaConfig config; //DMA config, must correspond to peripheral + enum DmaPeriph dma; //DMA peripheral, must correspond to peripheral + enum DmaChannel channel; //DMA channel, must correspond to peripheral +}; + //--functions------------------------------------------------------------------- diff --git a/drv/dma_mbuf.c b/drv/dma_mbuf.c deleted file mode 100644 index 8d10b27..0000000 --- a/drv/dma_mbuf.c +++ /dev/null @@ -1,143 +0,0 @@ -/** @file dma_mbuf.h - * Module handling Direct Memory Access controller's multibuffer system - * - * The module provides a convenient tool to send data to a peripheral in a - * buffered, low-altency, low-cpu usage, non-blocking way - */ - -//--includes-------------------------------------------------------------------- - -#include "dma_mbuf.h" - - -//--local definitions----------------------------------------------------------- - -#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ - | DMA_CONFIG_MSIZE_8BITS) - -static void mbuf_callback(enum DmaIRQSource src, volatile void* param); - -//take last 2 bytes of a buffer and assemble them store the current byte index -#define byte_index (((uint16_t**)buffer->buffers) \ - [buffer->buffer_index][buffer->buffer_size/2]) -#define dma_byte_index (((uint16_t**)buffer->buffers) \ - [buffer->dma_buffer_index][buffer->buffer_size/2]) - - -//--local variables------------------------------------------------------------- - -//--public functions------------------------------------------------------------ - -void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, - volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority) -{ - #warning "check for null ptr" - - buffer->buffers = buffers; - buffer->dest = dest; - - buffer->buffer_size = buffer_size - 2; - - buffer->buffer_nb = buffer_nb; - buffer->free_buffer_nb = buffer_nb - 1; - buffer->buffer_index = 0; - buffer->dma_buffer_index = 0; - - buffer->dma = dma; - buffer->channel = channel; - buffer->config = DMA_CONFIG | priority; - - for (uint8_t i=0; ibuffer_nb; ++i) { - for (uint16_t j=0; jbuffer_size + 2; ++j) { - ((uint8_t**)buffer->buffers)[i][j] = 0; - } - } -} - -uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, - uint8_t byte) -{ - dma_enter_critical(buffer->dma, buffer->channel); - - //if the current buffer is full, we need to switch it with an empty one - volatile uint16_t index = byte_index; - if (byte_index >= buffer->buffer_size) { - - //if all buffer full, give up - if (buffer->free_buffer_nb == 0) { - dma_exit_critical(buffer->dma, buffer->channel); - return 1; - } - - ++buffer->buffer_index; - if (buffer->buffer_index >= buffer->buffer_nb) { - buffer->buffer_index = 0; - } - --buffer->free_buffer_nb; - - byte_index = 0; - } - - //write the byte - uint8_t** buffers = (uint8_t**)buffer->buffers; - buffers[buffer->buffer_index][byte_index] = byte; - ++byte_index; - ++index; - - dma_exit_critical(buffer->dma, buffer->channel); - return 0; -} - -void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer) -{ - //no more data to send, stop here - if (buffer->dma_buffer_index == buffer->buffer_index - && byte_index == 0) { - return; - } - - //else start a new transfer - dma_configure(buffer->dma, buffer->channel, buffer->config, buffer->dest, - buffer->buffers[buffer->dma_buffer_index], - dma_byte_index, mbuf_callback, buffer); - - //if the newly transfering buffer was being written to, switch the current - //buffer. Since we just ended a transfer, the next buffer should be empty - if (buffer->dma_buffer_index == buffer->buffer_index) - { - ++buffer->buffer_index; - if (buffer->buffer_index >= buffer->buffer_nb) { - buffer->buffer_index = 0; - } - --buffer->free_buffer_nb; - - byte_index = 0; - } - - return; -} - - -//--local functions------------------------------------------------------------- - -/** - * Callback called on DMA TX tranfert's completion. Checks for any remaining - * data to send. If any, starts a new transfer, else stop the DMA - */ -static void mbuf_callback(enum DmaIRQSource src, volatile void* param) -{ - (void)src; //only transfer complete expected - volatile struct DmaMultiBuffer* buffer = param; - - //increment DMA's buffer since the last once has already been sent - ++buffer->dma_buffer_index; - if (buffer->dma_buffer_index >= buffer->buffer_nb) { - buffer->dma_buffer_index = 0; - } - ++buffer->free_buffer_nb; - - dma_mbuf_refresh(param); -} - diff --git a/drv/usart.c b/drv/usart.c index ae53d66..ae1a928 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -14,8 +14,6 @@ #include "rcc.h" #include "dma.h" -#include "dma_mbuf.h" -#include "dma_cbuf.h" #include "stddef.h" @@ -27,6 +25,8 @@ static void configure_usart(volatile struct USART* regs, static void configure_baudrate(volatile struct USART* regs, uint32_t clock, uint32_t baudrate); +#define DMA_CONFIG (DMA_CONFIG_PSIZE_8BITS) + //--local variables------------------------------------------------------------- @@ -34,12 +34,47 @@ static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; -static volatile struct DmaCircBuffer usart1_rx_buffer; -static volatile struct DmaMultiBuffer usart1_tx_buffer; -static volatile struct DmaCircBuffer usart2_rx_buffer; -static volatile struct DmaMultiBuffer usart2_tx_buffer; -static volatile struct DmaCircBuffer usart3_rx_buffer; -static volatile struct DmaMultiBuffer usart3_tx_buffer; +static const struct DmaParam usart1_rx_param = { + (void*)&usart1->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_5, +}; + +static const struct DmaParam usart2_rx_param = { + (void*)&usart2->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_6, +}; + +static const struct DmaParam usart3_rx_param = { + (void*)&usart3->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_3, +}; + +static const struct DmaParam usart1_tx_param = { + (void*)&usart1->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_4, +}; + +static const struct DmaParam usart2_tx_param = { + (void*)&usart2->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_7, +}; + +static const struct DmaParam usart3_tx_param = { + (void*)&usart3->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_2, +}; //--public functions------------------------------------------------------------ @@ -55,22 +90,16 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); configure_baudrate(usart1, clocks.apb2_freq, baudrate); configure_usart(usart1, config); - usart1_tx_buffer.buffers = NULL; - usart1_rx_buffer.buffer = NULL; break; case USART_PERIPH_2: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); configure_baudrate(usart2, clocks.apb1_freq, baudrate); configure_usart(usart2, config); - usart2_tx_buffer.buffers = NULL; - usart2_rx_buffer.buffer = NULL; break; case USART_PERIPH_3: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE); configure_baudrate(usart3, clocks.apb1_freq, baudrate); configure_usart(usart3, config); - usart3_tx_buffer.buffers = NULL; - usart3_rx_buffer.buffer = NULL; break; default: break; @@ -80,134 +109,104 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; - volatile struct DmaMultiBuffer* buffer; - enum NvicIrq irq; switch (periph) { case USART_PERIPH_1: regs = usart1; - buffer = &usart1_tx_buffer; - irq = NVIC_IRQ_USART1; break; case USART_PERIPH_2: regs = usart2; - buffer = &usart2_tx_buffer; - irq = NVIC_IRQ_USART2; break; case USART_PERIPH_3: regs = usart3; - buffer = &usart3_tx_buffer; - irq = NVIC_IRQ_USART3; break; default: return 1; break; } - if (buffer->buffers) { - //if the tx register is empty, there is no need to go through the dma - if (regs->SR.TC) { - reg_write(regs->DR, USART_DR_DR, byte); - //enable IRQ, disable DMA - reg_reset(regs->CR3, USART_CR3_DMAT); - reg_set(regs->CR1, USART_CR1_TXEIE); - nvic_enable(irq); - return 0; - } else { - return dma_mbuf_write_byte(buffer, byte); - } + //only write data if the tx register it empty, give up otherwise + if (regs->SR.TXE) { + reg_write(regs->DR, USART_DR_DR, byte); + return 0; } else { - //only write data if the tx register it empty, give up otherwise - if (regs->SR.TXE) { - reg_write(regs->DR, USART_DR_DR, byte); - return 0; - } else { - return 1; - } + return 1; } } uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { volatile struct USART* regs; - volatile struct DmaCircBuffer* buffer; switch (periph) { case USART_PERIPH_1: regs = usart1; - buffer = &usart1_rx_buffer; break; case USART_PERIPH_2: regs = usart2; - buffer = &usart2_rx_buffer; break; case USART_PERIPH_3: regs = usart3; - buffer = &usart3_rx_buffer; break; default: return 1; break; } - if (buffer->buffer) { - return dma_cbuf_read_byte(buffer, byte); + if (regs->SR.RXNE) { + *byte = regs->DR.DR; + return 0; } else { - if (regs->SR.RXNE) { - *byte = regs->DR.DR; - return 0; - } else { - return 1; - } + return 1; } } -void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, - uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority) +const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph) { - switch (periph) { - case USART_PERIPH_1: - dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR, - buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4, - priority); - break; - case USART_PERIPH_2: - dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR, - buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7, - priority); - break; - case USART_PERIPH_3: - dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR, - buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2, - priority); - break; - } -} + const struct DmaParam* param; -void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, - uint16_t size, enum DmaConfig priority) -{ switch (periph) { case USART_PERIPH_1: - dma_cbuf_configure(&usart1_rx_buffer, buffer, (void*)&usart1->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_5, priority); + param = &usart1_rx_param; reg_set(usart1->CR3, USART_CR3_DMAR); break; case USART_PERIPH_2: - dma_cbuf_configure(&usart2_rx_buffer, buffer, (void*)&usart2->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_6, priority); + param = &usart2_rx_param; reg_set(usart2->CR3, USART_CR3_DMAR); break; - case USART_PERIPH_3: - dma_cbuf_configure(&usart3_rx_buffer, buffer, (void*)&usart3->DR, - size, DMA_PERIPH_1, DMA_CHANNEL_3, priority); + param = &usart3_rx_param; reg_set(usart3->CR3, USART_CR3_DMAR); - break; + default: + return nullptr; } + + return param; } +const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph) +{ + const struct DmaParam* param; + + switch (periph) { + case USART_PERIPH_1: + param = &usart1_tx_param; + break; + case USART_PERIPH_2: + param = &usart2_tx_param; + break; + case USART_PERIPH_3: + param = &usart3_tx_param; + break; + default: + return nullptr; + } + + return param; +} + + //--local functions------------------------------------------------------------- /** @@ -309,39 +308,3 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF); } - -//--ISRs------------------------------------------------------------------------ - -void hdr_usart1(void) -{ - //disable the interrupt. It will be reenabled on a write if needed - nvic_clear_pending(NVIC_IRQ_USART1); - nvic_disable(NVIC_IRQ_USART1); - reg_reset(usart1->CR1, USART_CR1_TXEIE); - reg_set(usart1->CR3, USART_CR3_DMAT); - - dma_mbuf_refresh(&usart1_tx_buffer); -} - -void hdr_usart2(void) -{ - //disable the interrupt. It will be reenabled on a write if needed - nvic_clear_pending(NVIC_IRQ_USART2); - nvic_disable(NVIC_IRQ_USART2); - reg_reset(usart2->CR1, USART_CR1_TXEIE); - reg_set(usart2->CR3, USART_CR3_DMAT); - - dma_mbuf_refresh(&usart2_tx_buffer); -} - -void hdr_usart3(void) -{ - //disable the interrupt. It will be reenabled on a write if needed - nvic_clear_pending(NVIC_IRQ_USART3); - nvic_disable(NVIC_IRQ_USART3); - reg_reset(usart3->CR1, USART_CR1_TXEIE); - reg_set(usart3->CR3, USART_CR3_DMAT); - - dma_mbuf_refresh(&usart3_tx_buffer); -} - diff --git a/drv/usart.h b/drv/usart.h index 8739e63..9189d01 100644 --- a/drv/usart.h +++ b/drv/usart.h @@ -41,18 +41,13 @@ enum UsartConfig { void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t baudrate); - void usart_reset(enum UsartPeriph periph); uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); - uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); -void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers, - uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority); - -void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer, - uint16_t size, enum DmaConfig priority); +const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph); +const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph); #endif //_USART_H_ diff --git a/drv/dma_cbuf.c b/srv/dma_cbuf.c similarity index 85% rename from drv/dma_cbuf.c rename to srv/dma_cbuf.c index f324d20..e66b0e1 100644 --- a/drv/dma_cbuf.c +++ b/srv/dma_cbuf.c @@ -24,24 +24,23 @@ static void cbuf_callback(enum DmaIRQSource src, volatile void* param); //--public functions------------------------------------------------------------ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, - volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority) + const struct DmaParam* param, enum DmaConfig priority, + volatile void* raw_buffer, uint16_t buffer_size) { #warning "check for null ptr" buffer->buffer = raw_buffer; - buffer->src = src; + + buffer->param = param; + buffer->priority = priority; buffer->size = buffer_size; buffer->begin = 0; - buffer->dma = dma; - buffer->channel = channel; - buffer->config = DMA_CONFIG | priority; - buffer->dma_looped = false; - dma_configure(buffer->dma, buffer->channel, buffer->config, buffer->src, + dma_configure(buffer->param->dma, buffer->param->channel, + buffer->param->config, buffer->param->periph, buffer->buffer, buffer->size, cbuf_callback, buffer); } @@ -50,7 +49,7 @@ uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, { //retreive the current end of the buffer based on the DMA's progress uint16_t end = buffer->size - - dma_get_remaining(buffer->dma, buffer->channel); + - dma_get_remaining(buffer->param->dma, buffer->param->channel); //check for bytes to read and overflow if ((end > buffer->begin) && buffer->dma_looped) { diff --git a/drv/dma_cbuf.h b/srv/dma_cbuf.h similarity index 78% rename from drv/dma_cbuf.h rename to srv/dma_cbuf.h index 4221f14..606829e 100644 --- a/drv/dma_cbuf.h +++ b/srv/dma_cbuf.h @@ -10,7 +10,7 @@ //--includes-------------------------------------------------------------------- -#include "dma.h" +#include "../drv/dma.h" //--type definitions------------------------------------------------------------ @@ -22,15 +22,13 @@ */ struct DmaCircBuffer { volatile void* buffer; //the buffer to use as a circular buffer - volatile void* src; //source peripheral register + + const struct DmaParam* param; + enum DmaConfig priority; //DMA config, must correspond to peripheral uint16_t size; //the size of the buffer uint16_t begin; //pointer to the current begin of the buffer - enum DmaPeriph dma; //DMA peripheral, must correspond to peripheral - enum DmaChannel channel; //DMA channel, must correspond to peripheral - enum DmaConfig config; //DMA config, must correspond to peripheral - bool dma_looped; //whether the DMA looped or not (buffer overflow) }; @@ -47,8 +45,8 @@ struct DmaCircBuffer { * will stay running until manually stopped */ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, - volatile void* raw_buffer, volatile void* src, uint16_t buffer_size, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority); + const struct DmaParam* param, enum DmaConfig priority, + volatile void* raw_buffer, uint16_t buffer_size); uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, uint8_t* byte); diff --git a/srv/dma_mbuf.c b/srv/dma_mbuf.c new file mode 100644 index 0000000..dc6a876 --- /dev/null +++ b/srv/dma_mbuf.c @@ -0,0 +1,99 @@ +/** @file dma_mbuf.h + * Module handling Direct Memory Access controller's multibuffer system + * + * The module provides a convenient tool to send data to a peripheral in a + * buffered, low-altency, low-cpu usage, non-blocking way + */ + +//--includes-------------------------------------------------------------------- + +#include "dma_mbuf.h" + + +//--local definitions----------------------------------------------------------- + +#define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ + | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ + | DMA_CONFIG_MSIZE_8BITS) + +static void mbuf_callback(enum DmaIRQSource src, volatile void* param); + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, + const struct DmaParam* param, enum DmaConfig priority, + void* raw_buffer, uint16_t buffer_size) +{ + #warning "check for null ptr" + + buffer->raw_buffer = raw_buffer; + + buffer->param = param; + buffer->priority = priority; + + buffer->buffer_size = buffer_size / 2; + + buffer->byte_index = 0; + buffer->buffer_index = 0; + + buffer->dma_running = false; +} + +uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, + uint8_t byte) +{ + //if the current buffer is full, give up + if (buffer->byte_index >= buffer->buffer_size) { + return 1; + } + + //write the byte + buffer->raw_buffer[buffer->buffer_index * buffer->buffer_size + + buffer->byte_index] = byte; + ++buffer->byte_index; + return 0; +} + +void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) +{ + //if transfer already in progress or no data to send, don't start the + //transfer + if (buffer->dma_running || buffer->byte_index == 0) { + return; + } + + //start a new transfer + dma_configure(buffer->param->dma, buffer->param->channel, + DMA_CONFIG | buffer->param->config | buffer->priority, + buffer->param->periph, + &buffer->raw_buffer[buffer->buffer_index * buffer->buffer_size], + buffer->byte_index, mbuf_callback, buffer); + buffer->dma_running = true; + + buffer->byte_index = 0; + ++buffer->buffer_index; + if (buffer->buffer_index > 1) { + buffer->buffer_index = 0; + } + + return; +} + + +//--local functions------------------------------------------------------------- + +/** + * Callback called on DMA TX tranfert's completion. Checks for any remaining + * data to send. If any, starts a new transfer, else stop the DMA + */ +static void mbuf_callback(enum DmaIRQSource src, volatile void* param) +{ + (void)src; //only transfer complete expected + volatile struct DmaMultiBuffer* buffer = param; + + buffer->dma_running = false; +} + diff --git a/drv/dma_mbuf.h b/srv/dma_mbuf.h similarity index 68% rename from drv/dma_mbuf.h rename to srv/dma_mbuf.h index 4ab6952..966c5c1 100644 --- a/drv/dma_mbuf.h +++ b/srv/dma_mbuf.h @@ -10,7 +10,7 @@ //--includes-------------------------------------------------------------------- -#include "dma.h" +#include "../drv/dma.h" //--type definitions------------------------------------------------------------ @@ -21,19 +21,17 @@ * sizes */ struct DmaMultiBuffer { - void** buffers; //list of buffers to write to - volatile void* dest; //destination peripheral register + uint8_t* raw_buffer; - uint16_t buffer_size; //size of a single buffer + const struct DmaParam* param; + enum DmaConfig priority; - uint8_t buffer_nb; //total number of buffers - uint8_t free_buffer_nb; //number of buffers not currently used - uint8_t buffer_index; //index of the current buffer - uint8_t dma_buffer_index; //index of the DMA's current buffer + uint16_t buffer_size; - enum DmaPeriph dma; //DMA peripheral, must correspond to peripheral - enum DmaChannel channel; //DMA channel, must correspond to peripheral - enum DmaConfig config; //DMA config, must correspond to peripheral + uint8_t byte_index; + uint8_t buffer_index; + + bool dma_running; }; @@ -51,9 +49,9 @@ struct DmaMultiBuffer { * filling up the buffer. Transfers will then automatically be started as long * as there are bytes in the buffer. See the usart module for an usage exemple */ -void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, void** buffers, - volatile void* dest, uint16_t buffer_size, uint8_t buffer_nb, - enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig priority); +void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, + const struct DmaParam* param, enum DmaConfig priority, + void* raw_buffer, uint16_t buffer_size); /** * Write the given byte to the given buffer. Returns 0 if the write operation @@ -71,7 +69,7 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, * transfer will be handled automatically until there are no bytes left in the * buffer */ -void dma_mbuf_refresh(volatile struct DmaMultiBuffer* buffer); +void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer); #endif //_DMA_MBUF_H_ -- 2.45.2 From 7a19ae9223f53aec5780d66f265e5efcc9ea5773 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 16:28:08 +0200 Subject: [PATCH 65/85] Clean minor issues in startup.s --- startup.s | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/startup.s b/startup.s index 8f48739..a664898 100644 --- a/startup.s +++ b/startup.s @@ -4,7 +4,7 @@ * This startup file provides a reset handler to setup the basics for c to run * (stack pointer, static data, ...) as well as the vector table and the * differents interrupt handlers that go with it. By default, all handlers use - * the default handler wich is simply and infinite loop + * the default handler wich is simply an infinite loop */ .syntax unified @@ -25,7 +25,7 @@ */ .section .text.hdr_reset .weak hdr_reset - .type hdr_reset, %function + .type hdr_reset, %function hdr_reset: ldr r0, = _estack mov sp, r0 @@ -75,19 +75,19 @@ bss_init_end: */ .section .text.hdr_default, "ax", %progbits .weak hdr_default -hdr_default: + hdr_default: b hdr_default .size hdr_default, .-hdr_default -//--Vector table---------------------------------------------------------------- + //--Vector table---------------------------------------------------------------- .section .vector_table, "a", %progbits .type vector_table, %object .size vector_table, .-vector_table -vector_table: + vector_table: .word _estack .word hdr_reset .word hdr_nmi @@ -165,7 +165,7 @@ vector_table: .word hdr_dma2_channel3 .word hdr_dma2_channel4_5 -//--Weak definitions------------------------------------------------------------ + //--Weak definitions------------------------------------------------------------ .weak hdr_nmi .thumb_set hdr_nmi, hdr_default -- 2.45.2 From fd33003e26f23f6609d20d3371f2b618cddd7aab Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 16:29:45 +0200 Subject: [PATCH 66/85] Rework DMA buffer to work properly DMA buffers now work reliably with USART. The DMA api has changed to make it more efficient code-size-wise. This may, however, complicate things when implementating powersaving features --- drv/dma.c | 43 +++++++++++++++++++++++++------------------ drv/dma.h | 9 +++++---- drv/usart.c | 3 +++ srv/dma_cbuf.c | 16 ++++++++-------- srv/dma_cbuf.h | 6 +++--- srv/dma_mbuf.c | 19 ++++++++++--------- srv/dma_mbuf.h | 5 ++--- 7 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drv/dma.c b/drv/dma.c index f13f9f1..7fd4085 100644 --- a/drv/dma.c +++ b/drv/dma.c @@ -19,9 +19,9 @@ //--local definitions----------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, volatile void* mem, - uint16_t size); - + enum DmaConfig config_mask, volatile void* periph); +static void start_dma(volatile struct DMA* dma, enum DmaChannel channel, + volatile void* mem, uint16_t size); //--local variables------------------------------------------------------------- @@ -36,8 +36,8 @@ static volatile void* dma2_cb_params[5]; //--public functions------------------------------------------------------------ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, volatile void* mem, - uint16_t size, DmaCallback callback, volatile void* cb_param) + enum DmaConfig config_mask, volatile void* periph, + DmaCallback callback, volatile void* cb_param) { //reset peripheral first, to ensure proper configuration dma_reset(dma, channel); @@ -45,7 +45,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, switch (dma) { case DMA_PERIPH_1: rcc_enable(RCC_AHB_DMA1, RCC_APB1_NONE, RCC_APB2_NONE); - configure_dma(dma1, channel, config_mask, periph, mem, size); + configure_dma(dma1, channel, config_mask, periph); if (callback) { dma1_callbacks[channel] = callback; dma1_cb_params[channel] = cb_param; @@ -54,7 +54,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, break; case DMA_PERIPH_2: rcc_enable(RCC_AHB_DMA2, RCC_APB1_NONE, RCC_APB2_NONE); - configure_dma(dma2, channel, config_mask, periph, mem, size); + configure_dma(dma2, channel, config_mask, periph); if (callback) { dma2_callbacks[channel] = callback; dma2_cb_params[channel] = cb_param; @@ -110,20 +110,21 @@ void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel) } } -void dma_enable(enum DmaPeriph dma, enum DmaChannel channel) +void dma_start(enum DmaPeriph dma, enum DmaChannel channel, + volatile void* mem, uint16_t size) { switch (dma) { case DMA_PERIPH_1: - reg_set(dma1->CHANNELS[channel].CCR, DMA_CCR_EN); if (dma1_callbacks[channel]) { nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); } + start_dma(dma1, channel, mem, size); break; case DMA_PERIPH_2: - reg_set(dma2->CHANNELS[channel].CCR, DMA_CCR_EN); if (dma2_callbacks[channel]) { nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); } + start_dma(dma2, channel, mem, size); break; default: return; @@ -146,7 +147,7 @@ void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel) } } -void dma_disable(enum DmaPeriph dma, enum DmaChannel channel) +void dma_stop(enum DmaPeriph dma, enum DmaChannel channel) { switch (dma) { case DMA_PERIPH_1: @@ -185,21 +186,27 @@ uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) //--local functions------------------------------------------------------------- static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, volatile void* mem, - uint16_t size) + enum DmaConfig config_mask, volatile void* periph) { volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; //registers should already be at reset value, apply new config regs->CCR.word = config_mask; - reg_write(regs->CNDTR, DMA_CNDTR_NDT, size); regs->CPAR = (uint32_t)periph; - regs->CMAR = (uint32_t)mem; - - //only enable channel when everything is configured - reg_set(regs->CCR, DMA_CCR_EN); } +static void start_dma(volatile struct DMA* dma, enum DmaChannel channel, + volatile void* mem, uint16_t size) +{ + volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; + + //registers should already be configured, apply transfer config + reg_write(regs->CNDTR, DMA_CNDTR_NDT, size); + regs->CMAR = (uint32_t)mem; + + //only start transfer when everything is configured + reg_set(regs->CCR, DMA_CCR_EN); +} //--ISRs------------------------------------------------------------------------ diff --git a/drv/dma.h b/drv/dma.h index 89d9e00..1e38987 100644 --- a/drv/dma.h +++ b/drv/dma.h @@ -88,8 +88,8 @@ struct DmaParam { //--functions------------------------------------------------------------------- void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, - enum DmaConfig config_mask, volatile void* periph, volatile void* mem, - uint16_t size, DmaCallback callback, volatile void* cb_param); + enum DmaConfig config_mask, volatile void* periph, + DmaCallback callback, volatile void* cb_param); void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfigM2M config_mask, const void* src, void* dest, @@ -99,11 +99,12 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel); -void dma_enable(enum DmaPeriph dma, enum DmaChannel channel); +void dma_start(enum DmaPeriph dma, enum DmaChannel channel, + volatile void* mem, uint16_t size); void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel); -void dma_disable(enum DmaPeriph dma, enum DmaChannel channel); +void dma_stop(enum DmaPeriph dma, enum DmaChannel channel); uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channe); diff --git a/drv/usart.c b/drv/usart.c index ae1a928..578b93b 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -192,12 +192,15 @@ const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph) switch (periph) { case USART_PERIPH_1: param = &usart1_tx_param; + reg_set(usart1->CR3, USART_CR3_DMAT); break; case USART_PERIPH_2: param = &usart2_tx_param; + reg_set(usart2->CR3, USART_CR3_DMAT); break; case USART_PERIPH_3: param = &usart3_tx_param; + reg_set(usart3->CR3, USART_CR3_DMAT); break; default: return nullptr; diff --git a/srv/dma_cbuf.c b/srv/dma_cbuf.c index e66b0e1..a9277f6 100644 --- a/srv/dma_cbuf.c +++ b/srv/dma_cbuf.c @@ -31,17 +31,18 @@ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, buffer->buffer = raw_buffer; - buffer->param = param; - buffer->priority = priority; - buffer->size = buffer_size; buffer->begin = 0; + buffer->dma = param->dma; + buffer->channel = param->channel; + buffer->dma_looped = false; - dma_configure(buffer->param->dma, buffer->param->channel, - buffer->param->config, buffer->param->periph, - buffer->buffer, buffer->size, cbuf_callback, buffer); + dma_configure(buffer->dma, buffer->channel, + DMA_CONFIG | param->config | priority, + param->periph, cbuf_callback, buffer); + dma_start(buffer->dma, buffer->channel, buffer->buffer, buffer->size); } uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, @@ -49,7 +50,7 @@ uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, { //retreive the current end of the buffer based on the DMA's progress uint16_t end = buffer->size - - dma_get_remaining(buffer->param->dma, buffer->param->channel); + - dma_get_remaining(buffer->dma, buffer->channel); //check for bytes to read and overflow if ((end > buffer->begin) && buffer->dma_looped) { @@ -85,4 +86,3 @@ static void cbuf_callback(enum DmaIRQSource src, volatile void* param) buffer->dma_looped = true; } - diff --git a/srv/dma_cbuf.h b/srv/dma_cbuf.h index 606829e..7a05bbd 100644 --- a/srv/dma_cbuf.h +++ b/srv/dma_cbuf.h @@ -23,12 +23,12 @@ struct DmaCircBuffer { volatile void* buffer; //the buffer to use as a circular buffer - const struct DmaParam* param; - enum DmaConfig priority; //DMA config, must correspond to peripheral - uint16_t size; //the size of the buffer uint16_t begin; //pointer to the current begin of the buffer + enum DmaPeriph dma; + enum DmaChannel channel; + bool dma_looped; //whether the DMA looped or not (buffer overflow) }; diff --git a/srv/dma_mbuf.c b/srv/dma_mbuf.c index dc6a876..1ceaad0 100644 --- a/srv/dma_mbuf.c +++ b/srv/dma_mbuf.c @@ -31,15 +31,18 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, buffer->raw_buffer = raw_buffer; - buffer->param = param; - buffer->priority = priority; - buffer->buffer_size = buffer_size / 2; buffer->byte_index = 0; buffer->buffer_index = 0; + buffer->dma = param->dma; + buffer->channel = param->channel; buffer->dma_running = false; + + dma_configure(buffer->dma, buffer->channel, + DMA_CONFIG | param->config | priority, + param->periph, mbuf_callback, buffer); } uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, @@ -66,12 +69,10 @@ void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) } //start a new transfer - dma_configure(buffer->param->dma, buffer->param->channel, - DMA_CONFIG | buffer->param->config | buffer->priority, - buffer->param->periph, - &buffer->raw_buffer[buffer->buffer_index * buffer->buffer_size], - buffer->byte_index, mbuf_callback, buffer); buffer->dma_running = true; + dma_start(buffer->dma, buffer->channel, + &buffer->raw_buffer[buffer->buffer_index * buffer->buffer_size], + buffer->byte_index); buffer->byte_index = 0; ++buffer->buffer_index; @@ -93,7 +94,7 @@ static void mbuf_callback(enum DmaIRQSource src, volatile void* param) { (void)src; //only transfer complete expected volatile struct DmaMultiBuffer* buffer = param; - + dma_stop(buffer->dma, buffer->channel); buffer->dma_running = false; } diff --git a/srv/dma_mbuf.h b/srv/dma_mbuf.h index 966c5c1..cf44d0d 100644 --- a/srv/dma_mbuf.h +++ b/srv/dma_mbuf.h @@ -23,13 +23,12 @@ struct DmaMultiBuffer { uint8_t* raw_buffer; - const struct DmaParam* param; - enum DmaConfig priority; - uint16_t buffer_size; uint8_t byte_index; uint8_t buffer_index; + enum DmaPeriph dma; + enum DmaChannel channel; bool dma_running; }; -- 2.45.2 From 5e961b15fc28d1529029bd142d824d64e8100af7 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 16:55:31 +0200 Subject: [PATCH 67/85] Document dma_mbuf service --- srv/dma_mbuf.c | 27 ++++++++++++++++---------- srv/dma_mbuf.h | 51 +++++++++++++++++++++++++------------------------- 2 files changed, 43 insertions(+), 35 deletions(-) diff --git a/srv/dma_mbuf.c b/srv/dma_mbuf.c index 1ceaad0..4f2255c 100644 --- a/srv/dma_mbuf.c +++ b/srv/dma_mbuf.c @@ -12,9 +12,12 @@ //--local definitions----------------------------------------------------------- +/** + * DMA configuration to be used for the buffer. Additionnal configuration may be + * added by the peripherals used + */ #define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM \ - | DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS \ - | DMA_CONFIG_MSIZE_8BITS) + | DMA_CONFIG_INC_MEM | DMA_CONFIG_MSIZE_8BITS) static void mbuf_callback(enum DmaIRQSource src, volatile void* param); @@ -60,12 +63,16 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, return 0; } -void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) +uint32_t dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) { - //if transfer already in progress or no data to send, don't start the - //transfer - if (buffer->dma_running || buffer->byte_index == 0) { - return; + //no data to send, stop here + if (buffer->byte_index == 0) { + return 0; + } + + //dma already running, give up + if (buffer->dma_running) { + return 1; } //start a new transfer @@ -80,15 +87,15 @@ void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) buffer->buffer_index = 0; } - return; + return 0; } //--local functions------------------------------------------------------------- /** - * Callback called on DMA TX tranfert's completion. Checks for any remaining - * data to send. If any, starts a new transfer, else stop the DMA + * Callback called on DMA TX tranfert's completion. Stops the DMA and notifies + * the buffer that the transfer is done. */ static void mbuf_callback(enum DmaIRQSource src, volatile void* param) { diff --git a/srv/dma_mbuf.h b/srv/dma_mbuf.h index cf44d0d..b5f930c 100644 --- a/srv/dma_mbuf.h +++ b/srv/dma_mbuf.h @@ -2,7 +2,7 @@ * Module handling Direct Memory Access controller's multibuffer system * * The module provides a convenient tool to send data to a peripheral in a - * buffered, low-altency, low-cpu usage, non-blocking way + * buffered, low-latency, low-cpu usage, non-blocking way */ #ifndef _DMA_MBUF_H_ @@ -17,36 +17,38 @@ /** * Struct used by the multibuffer system. This system allows bufferized writes - * to a peripheral with no latency, minimal cpu usage and customisable buffer - * sizes + * to a peripheral with controlled latency, minimal cpu usage and customisable + * buffer size */ struct DmaMultiBuffer { - uint8_t* raw_buffer; + uint8_t* raw_buffer; //the buffer to use as a multi-buffer - uint16_t buffer_size; + uint16_t buffer_size; //the size of the buffer - uint8_t byte_index; - uint8_t buffer_index; - enum DmaPeriph dma; - enum DmaChannel channel; + uint8_t byte_index; //index of the next byte to be written + uint8_t buffer_index; //index of the buffer being written to + enum DmaPeriph dma; //DMA peripheral used for transfers + enum DmaChannel channel; //DMA channel used for transfers - bool dma_running; + bool dma_running; //whether the dam is currently running or not }; //--functions------------------------------------------------------------------- /** - * Configure a DMA multibuffer for a single DMA channel. A list of buffers is - * used to allow concurent write and DMA tranfers to the specified destination - * wich must be a peripheral. The DMA's priority is also given as parameters. - * The peripheral's specific configuration must be handled separately. 2 bytes - * are reserved in each buffer for index storage. + * Configure a DMA multibuffer for a single DMA channel. The given buffer is + * divided into 2 to allow one part to be written to while the other is being + * transfered by the DMA to a peripheral. + * The peripheral's specific configuration must be handled separately. + * Each peripheral's driver is responsible for providing the DMA configuration + * for said peripheral, though it can be manually given too. Please note that + * multiple peripherals may share the same DMA channel, which will cause issue + * when used with this buffer. * - * This system needs to be started manually: dma_mbuf_refresh() should be called - * whenever a DMA transfer can be started. This can be done manually after - * filling up the buffer. Transfers will then automatically be started as long - * as there are bytes in the buffer. See the usart module for an usage exemple + * This buffer can be written to at any given time using dma_mbuf_write_byte(), + * but its content are only written to the corresponding peripheral when + * dma_mbuf_switch() is called. */ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, const struct DmaParam* param, enum DmaConfig priority, @@ -57,18 +59,17 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, * was successfull, 1 otherwise. The function is non-blocking. * * Note: calling this function will not trigger a DMA transfer, see - * dma_mbuf_refresh() to do that + * dma_mbuf_switch() to do that */ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, uint8_t byte); /** - * Refresh the buffer state, checking for bytes to send and triggering a DMA - * transfer if necessary. Should be called for the first transfer, any remaining - * transfer will be handled automatically until there are no bytes left in the - * buffer + * Switch the buffers, triggering a DMA transfer while allowing writes to + * continue. This function may fail if a DMA transfer is already running, + * returning 1 */ -void dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer); +uint32_t dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer); #endif //_DMA_MBUF_H_ -- 2.45.2 From a1ae9042394f84f3c36c61db49b5556fac241d79 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 16:59:57 +0200 Subject: [PATCH 68/85] Document dma_cbuf service --- srv/dma_cbuf.c | 6 +++++- srv/dma_cbuf.h | 14 +++++++++++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/srv/dma_cbuf.c b/srv/dma_cbuf.c index a9277f6..22f1fe4 100644 --- a/srv/dma_cbuf.c +++ b/srv/dma_cbuf.c @@ -12,9 +12,13 @@ //--local definitions----------------------------------------------------------- +/** + * DMA configuration to be used for the buffer. Additionnal configuration may be + * added by the peripherals used + */ #define DMA_CONFIG (DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH \ | DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM \ - | DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS) + | DMA_CONFIG_MSIZE_8BITS) static void cbuf_callback(enum DmaIRQSource src, volatile void* param); diff --git a/srv/dma_cbuf.h b/srv/dma_cbuf.h index 7a05bbd..cd21f49 100644 --- a/srv/dma_cbuf.h +++ b/srv/dma_cbuf.h @@ -26,8 +26,8 @@ struct DmaCircBuffer { uint16_t size; //the size of the buffer uint16_t begin; //pointer to the current begin of the buffer - enum DmaPeriph dma; - enum DmaChannel channel; + enum DmaPeriph dma; //DMA peripheral used for transfers + enum DmaChannel channel; //DMA channel used for transfers bool dma_looped; //whether the DMA looped or not (buffer overflow) }; @@ -38,8 +38,12 @@ struct DmaCircBuffer { /** * Configure a DMA circular buffer for a single DMA channel. A standard buffer * is used a base to construct a circular buffer, supplied in data by DMA - * tranfers from a peripheral. The DMA's priority is given as parameters. + * tranfers from a peripheral. * The peripheral's specific configuration must be handled separately. + * Each peripheral's driver is responsible for providing the DMA configuration + * for said peripheral, though it can be manually given too. Please note that + * multiple peripherals may share the same DMA channel, which will cause issue + * when used with this buffer. * * Once this function is called, the system will start running right away and * will stay running until manually stopped @@ -48,6 +52,10 @@ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, const struct DmaParam* param, enum DmaConfig priority, volatile void* raw_buffer, uint16_t buffer_size); +/** + * Reads a bytes from the buffer, returning if the read operation was + * successfull, 1 otherwise. This function is non-blocking. + */ uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, uint8_t* byte); -- 2.45.2 From 85e7ad5ef1bcac5ce79f59477f85337ddde082f4 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 17:26:56 +0200 Subject: [PATCH 69/85] Document DMA driver --- drv/dma.c | 66 ++++++++++++++++++++++++++---------------------- drv/dma.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 107 insertions(+), 34 deletions(-) diff --git a/drv/dma.c b/drv/dma.c index 7fd4085..7d68b09 100644 --- a/drv/dma.c +++ b/drv/dma.c @@ -95,21 +95,6 @@ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel) regs->CPAR = 0; } -void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel) -{ - switch (dma) { - case DMA_PERIPH_1: - nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); - break; - case DMA_PERIPH_2: - nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); - break; - default: - return; - break; - } -} - void dma_start(enum DmaPeriph dma, enum DmaChannel channel, volatile void* mem, uint16_t size) { @@ -132,21 +117,6 @@ void dma_start(enum DmaPeriph dma, enum DmaChannel channel, } } -void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel) -{ - switch (dma) { - case DMA_PERIPH_1: - nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); - break; - case DMA_PERIPH_2: - nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); - break; - default: - return; - break; - } -} - void dma_stop(enum DmaPeriph dma, enum DmaChannel channel) { switch (dma) { @@ -168,6 +138,36 @@ void dma_stop(enum DmaPeriph dma, enum DmaChannel channel) } } +void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + break; + case DMA_PERIPH_2: + nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + break; + default: + return; + break; + } +} + +void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel) +{ + switch (dma) { + case DMA_PERIPH_1: + nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); + break; + case DMA_PERIPH_2: + nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); + break; + default: + return; + break; + } +} + uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) { switch (dma) { @@ -185,6 +185,9 @@ uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channel) //--local functions------------------------------------------------------------- +/** + * Applies the given configuration mask to the given DMA channel + */ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, enum DmaConfig config_mask, volatile void* periph) { @@ -195,6 +198,9 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel, regs->CPAR = (uint32_t)periph; } +/** + * Starts the given DMA channel using the given parameters + */ static void start_dma(volatile struct DMA* dma, enum DmaChannel channel, volatile void* mem, uint16_t size) { diff --git a/drv/dma.h b/drv/dma.h index 1e38987..5367530 100644 --- a/drv/dma.h +++ b/drv/dma.h @@ -15,11 +15,19 @@ //--type definitions------------------------------------------------------------ +/** + * Available DMA peripherals. Note that some of these peripherals may not be + * available on all chips + */ enum DmaPeriph { DMA_PERIPH_1, DMA_PERIPH_2, }; +/** + * Available DMA channels. Note that some of these channels may not be + * available on all chips and all DMA peripheral + */ enum DmaChannel { DMA_CHANNEL_1 = 0, DMA_CHANNEL_2, @@ -30,6 +38,9 @@ enum DmaChannel { DMA_CHANNEL_7, //not available for DMA 2 }; +/** + * Configuration options for memory-to-peripheral transfers + */ enum DmaConfig { DMA_CONFIG_IRQ_COMPLETE = (0x1 << 1), DMA_CONFIG_IRQ_HALF = (0x1 << 2), @@ -51,6 +62,9 @@ enum DmaConfig { DMA_CONFIG_PRIO_VHIGH = (0x3 << 12), }; +/** + * Configuration options for memory-to-memory transfers + */ enum DmaConfigM2M { DMA_CONFIG_M2M_IRQ_COMPLETE = (0x1 << 1), DMA_CONFIG_M2M_IRQ_HALF = (0x1 << 2), @@ -69,14 +83,25 @@ enum DmaConfigM2M { DMA_CONFIG_M2M_PRIO_VHIGH = (0x3 << 12), }; +/** + * Available sources for a DMA IRQ. These sources can be enabled independently + * in the DMA configuration. + */ enum DmaIRQSource { DMA_IRQ_SOURCE_COMPLETE = (0x1 << 1), DMA_IRQ_SOURCE_HALF = (0x1 << 2), DMA_IQR_SOURCE_ERROR = (0x2 << 3), }; +/** + * Prototype of the IRQ callbacks that the applicative code can provide + */ typedef void (*DmaCallback)(enum DmaIRQSource, volatile void* param); +/** + * Generic struct used to share DAM configs between peripheral drivers and + * services providing DMA interfaces + */ struct DmaParam { void* periph; enum DmaConfig config; //DMA config, must correspond to peripheral @@ -87,25 +112,67 @@ struct DmaParam { //--functions------------------------------------------------------------------- +/** + * Configures the given DMA channel with the provided configuration, to perform + * a transfer to or from the given peripheral register. The specified callback, + * if any, will be called on the enabled IRQ sources, with the specified + * parameter, if any. + * + * This function doesn't initiate transfers, use dma_start() for that + */ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfig config_mask, volatile void* periph, DmaCallback callback, volatile void* cb_param); +/** + * Unimplemented + */ void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, enum DmaConfigM2M config_mask, const void* src, void* dest, uint16_t size, DmaCallback callback, void* cb_param); +/** + * Resets the given DMA channel, restoring the default configuration and + * disabling it + */ void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); -void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel); - +/** + * Initiate a transfer on the given DMA channel, to or from the given memory + * address, and of the specified size. + * + * Should only be used after the channel has been configured through + * dma_configure() + * All transfers started must be eventually stopped, or the channel reset, for + * proper IRQ behavior. + */ void dma_start(enum DmaPeriph dma, enum DmaChannel channel, volatile void* mem, uint16_t size); -void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel); - +/** + * Stops a transfer on the given DMA channel. If the transfer has already + * ended, properly shutdown the channel. Configuration is not lost after calling + * this function and dma_start() may be called again + */ void dma_stop(enum DmaPeriph dma, enum DmaChannel channel); +/** + * Enters a DMA critical section, disabling the given channel's IRQs until + * dma_exit_critical() is called + */ +void dma_enter_critical(enum DmaPeriph dma, enum DmaChannel channel); + +/** + * Exists a DMA critical section previously entered through + * dma_enter_critical(). Reenables the given channel's IRQs + */ +void dma_exit_critical(enum DmaPeriph dma, enum DmaChannel channel); + +/** + * Returns the remaining number of bytes to be transmitted while a transfer is + * running. When no transfer is running, returns the number of bytes to transfer + * next + */ uint16_t dma_get_remaining(enum DmaPeriph dma, enum DmaChannel channe); -- 2.45.2 From c6da4e11d8fed20836f242962d7cc1dfc28f1795 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 22:19:19 +0200 Subject: [PATCH 70/85] Document USART driver --- drv/usart.c | 57 +++++++++++++++++++++++++-------------------------- drv/usart.h | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 30 deletions(-) diff --git a/drv/usart.c b/drv/usart.c index 578b93b..35bc779 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -8,7 +8,6 @@ //--includes-------------------------------------------------------------------- #include "usart.h" -#include "nvic.h" #include "usart_regs.h" #include "reg.h" @@ -106,6 +105,33 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, } } +uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) +{ + volatile struct USART* regs; + + switch (periph) { + case USART_PERIPH_1: + regs = usart1; + break; + case USART_PERIPH_2: + regs = usart2; + break; + case USART_PERIPH_3: + regs = usart3; + break; + default: + return 1; + break; + } + + if (regs->SR.RXNE) { + *byte = regs->DR.DR; + return 0; + } else { + return 1; + } +} + uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { volatile struct USART* regs; @@ -134,33 +160,6 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) } } -uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) -{ - volatile struct USART* regs; - - switch (periph) { - case USART_PERIPH_1: - regs = usart1; - break; - case USART_PERIPH_2: - regs = usart2; - break; - case USART_PERIPH_3: - regs = usart3; - break; - default: - return 1; - break; - } - - if (regs->SR.RXNE) { - *byte = regs->DR.DR; - return 0; - } else { - return 1; - } -} - const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph) { const struct DmaParam* param; @@ -295,7 +294,7 @@ static void configure_usart(volatile struct USART* regs, /** * Configure the given registers with the given baudrate. Baudrate is dependant - * on the peripheric's clock and may not be exact due to precision errors (see + * on the peripheral's clock and may not be exact due to precision errors (see * table 192 in documentation) */ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, diff --git a/drv/usart.h b/drv/usart.h index 9189d01..960bf47 100644 --- a/drv/usart.h +++ b/drv/usart.h @@ -17,12 +17,19 @@ //--type definitions------------------------------------------------------------ +/** + * Available USART peripherals. Note that some of these peripherals may not be + * available on all chips + */ enum UsartPeriph { USART_PERIPH_1, USART_PERIPH_2, USART_PERIPH_3, }; +/** + * Available configuration options + */ enum UsartConfig { USART_CONFIG_7E1, USART_CONFIG_7E2, @@ -39,14 +46,64 @@ enum UsartConfig { //--functions------------------------------------------------------------------- +/** + * Configures the given USART peripheral using the provided condiguration + * options and baudrate. The baudrate may be any value supported by the + * peripheral, though some may not be exact due to precision errors (see + * table 192 in documentation). The baudrate is dependant on the peripheral's + * clock and changes to the later after this function has been called will cause + * the effective baudrate to change + * + * This function doesn't configure the required ports. This should be done using + * the gpio driver: + * - Tx port should be using GPIO_CONFIG_OUT_ALT_PUSH_PULL with + * the appropriate output speed based on the baurate (see GpioMode) + * - Rx port should be using GPIO_CONFIG_IN_FLOATING in input mode + * Both ports do not need to be configured if not used (e.g. if only using Tx, + * the Rx port can be left unconfigured) + */ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t baudrate); + +/** + * Resets the given USART peripheral, applying the default configuration and + * disabling it + */ void usart_reset(enum UsartPeriph periph); -uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); +/** + * Reads a single byte to the given USART peripheral, returning 0 if + * successfull, 1 otherwise. + * + * The Rx port must be configured for this function to ever return successfully + */ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte); +/** + * Writes a single byte to the given USART peripheral, returning 0 if + * successfull, 1 otherwise. + * + * The Tx port must be configured for this function to do anything, though the + * function would still return 0 + */ +uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte); + +/** + * Configures the given USART peripheral for DMA Rx operations, returning the + * corresponding DMA parameters to be used. + * + * The DMA must be configured separately using the DMA driver or an existing + * service + */ const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph); + +/** + * Configures the given USART peripheral for DMA Rx operations, returning the + * corresponding DMA parameters to be used. + * + * The DMA must be configured separately using the DMA driver or an existing + * service + */ const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph); -- 2.45.2 From 4eec301d17de001d8d75b20adfbcb05d088aff34 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 22:56:28 +0200 Subject: [PATCH 71/85] Optimize USART driver's code size Using tables reduces code size while also improving lisibility. That is a win-win --- drv/usart.c | 183 +++++++++++++++++++--------------------------------- 1 file changed, 67 insertions(+), 116 deletions(-) diff --git a/drv/usart.c b/drv/usart.c index 35bc779..25167a2 100644 --- a/drv/usart.c +++ b/drv/usart.c @@ -29,50 +29,52 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock, //--local variables------------------------------------------------------------- -static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS; -static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS; -static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS; - -static const struct DmaParam usart1_rx_param = { - (void*)&usart1->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_5, +static volatile struct USART* const usarts[] = { + (struct USART*)USART1_BASE_ADDRESS, + (struct USART*)USART2_BASE_ADDRESS, + (struct USART*)USART3_BASE_ADDRESS, }; -static const struct DmaParam usart2_rx_param = { - (void*)&usart2->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_6, +static const struct DmaParam usarts_rx_param[] = { + { + (void*)&usarts[USART_PERIPH_1]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_5, + }, + { + (void*)&usarts[USART_PERIPH_2]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_6, + }, + { + (void*)&usarts[USART_PERIPH_3]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_3, + }, }; -static const struct DmaParam usart3_rx_param = { - (void*)&usart3->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_3, -}; - -static const struct DmaParam usart1_tx_param = { - (void*)&usart1->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_4, -}; - -static const struct DmaParam usart2_tx_param = { - (void*)&usart2->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_7, -}; - -static const struct DmaParam usart3_tx_param = { - (void*)&usart3->DR, - DMA_CONFIG, - DMA_PERIPH_1, - DMA_CHANNEL_2, +static const struct DmaParam usarts_tx_param[] = { + { + (void*)&usarts[USART_PERIPH_1]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_4, + }, + { + (void*)&usarts[USART_PERIPH_2]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_7, + }, + { + (void*)&usarts[USART_PERIPH_3]->DR, + DMA_CONFIG, + DMA_PERIPH_1, + DMA_CHANNEL_2, + }, }; @@ -87,18 +89,21 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, switch (periph) { case USART_PERIPH_1: rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART); - configure_baudrate(usart1, clocks.apb2_freq, baudrate); - configure_usart(usart1, config); + configure_baudrate(usarts[USART_PERIPH_1], clocks.apb2_freq, + baudrate); + configure_usart(usarts[USART_PERIPH_1], config); break; case USART_PERIPH_2: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE); - configure_baudrate(usart2, clocks.apb1_freq, baudrate); - configure_usart(usart2, config); + configure_baudrate(usarts[USART_PERIPH_2], clocks.apb1_freq, + baudrate); + configure_usart(usarts[USART_PERIPH_2], config); break; case USART_PERIPH_3: rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE); - configure_baudrate(usart3, clocks.apb1_freq, baudrate); - configure_usart(usart3, config); + configure_baudrate(usarts[USART_PERIPH_3], clocks.apb1_freq, + baudrate); + configure_usart(usarts[USART_PERIPH_3], config); break; default: break; @@ -107,25 +112,12 @@ void usart_configure(enum UsartPeriph periph, enum UsartConfig config, uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) { - volatile struct USART* regs; - - switch (periph) { - case USART_PERIPH_1: - regs = usart1; - break; - case USART_PERIPH_2: - regs = usart2; - break; - case USART_PERIPH_3: - regs = usart3; - break; - default: - return 1; - break; + if (periph > USART_PERIPH_3) { + return 1; } - if (regs->SR.RXNE) { - *byte = regs->DR.DR; + if (usarts[periph]->SR.RXNE) { + *byte = usarts[periph]->DR.DR; return 0; } else { return 1; @@ -134,26 +126,13 @@ uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte) uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) { - volatile struct USART* regs; - - switch (periph) { - case USART_PERIPH_1: - regs = usart1; - break; - case USART_PERIPH_2: - regs = usart2; - break; - case USART_PERIPH_3: - regs = usart3; - break; - default: - return 1; - break; + if (periph > USART_PERIPH_3) { + return 1; } //only write data if the tx register it empty, give up otherwise - if (regs->SR.TXE) { - reg_write(regs->DR, USART_DR_DR, byte); + if (usarts[periph]->SR.TXE) { + reg_write(usarts[periph]->DR, USART_DR_DR, byte); return 0; } else { return 1; @@ -162,50 +141,22 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte) const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph) { - const struct DmaParam* param; - - switch (periph) { - case USART_PERIPH_1: - param = &usart1_rx_param; - reg_set(usart1->CR3, USART_CR3_DMAR); - break; - case USART_PERIPH_2: - param = &usart2_rx_param; - reg_set(usart2->CR3, USART_CR3_DMAR); - break; - case USART_PERIPH_3: - param = &usart3_rx_param; - reg_set(usart3->CR3, USART_CR3_DMAR); - break; - default: - return nullptr; + if (periph > USART_PERIPH_3) { + return nullptr; } - return param; + reg_set(usarts[periph]->CR3, USART_CR3_DMAR); + return &usarts_rx_param[periph]; } const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph) { - const struct DmaParam* param; - - switch (periph) { - case USART_PERIPH_1: - param = &usart1_tx_param; - reg_set(usart1->CR3, USART_CR3_DMAT); - break; - case USART_PERIPH_2: - param = &usart2_tx_param; - reg_set(usart2->CR3, USART_CR3_DMAT); - break; - case USART_PERIPH_3: - param = &usart3_tx_param; - reg_set(usart3->CR3, USART_CR3_DMAT); - break; - default: - return nullptr; + if (periph > USART_PERIPH_3) { + return nullptr; } - return param; + reg_set(usarts[periph]->CR3, USART_CR3_DMAT); + return &usarts_tx_param[periph]; } -- 2.45.2 From cf077d2e51c624e76fceca0520154b5a1f48b592 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 6 Apr 2024 23:02:08 +0200 Subject: [PATCH 72/85] Fix unwanted changes --- startup.s | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/startup.s b/startup.s index a664898..cbc3e23 100644 --- a/startup.s +++ b/startup.s @@ -75,19 +75,19 @@ bss_init_end: */ .section .text.hdr_default, "ax", %progbits .weak hdr_default - hdr_default: +hdr_default: b hdr_default .size hdr_default, .-hdr_default - //--Vector table---------------------------------------------------------------- +//--Vector table---------------------------------------------------------------- .section .vector_table, "a", %progbits .type vector_table, %object .size vector_table, .-vector_table - vector_table: +vector_table: .word _estack .word hdr_reset .word hdr_nmi @@ -165,7 +165,7 @@ bss_init_end: .word hdr_dma2_channel3 .word hdr_dma2_channel4_5 - //--Weak definitions------------------------------------------------------------ +//--Weak definitions------------------------------------------------------------ .weak hdr_nmi .thumb_set hdr_nmi, hdr_default -- 2.45.2 From 0d5deffa587345edf99c9bf1c5908f5a4f6b8722 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sun, 7 Apr 2024 16:47:34 +0200 Subject: [PATCH 73/85] Update debug service to use new dma_mbuf --- srv/debug.c | 81 +++++++++++++++++++++++++++++++++++++++++------------ srv/debug.h | 3 +- 2 files changed, 64 insertions(+), 20 deletions(-) diff --git a/srv/debug.c b/srv/debug.c index 44711ac..2937fe5 100644 --- a/srv/debug.c +++ b/srv/debug.c @@ -8,20 +8,20 @@ //--includes-------------------------------------------------------------------- #include "debug.h" +#include "dma_mbuf.h" //--local definitions----------------------------------------------------------- -#define BUFFER_SIZE 83 //80 char line + \n + 2 bytes for index -#define BUFFER_NB 3 //1 buffer in write, one in transfer and one waiting +static void print_debug(char* str); + +#define BUFFER_SIZE 162 //(80 char line + \n) * 2 + //--local variables------------------------------------------------------------- -static enum UsartPeriph usart_periph; -static uint8_t tx_buffer1[BUFFER_SIZE]; -static uint8_t tx_buffer2[BUFFER_SIZE]; -static uint8_t tx_buffer3[BUFFER_SIZE]; -static uint8_t* tx_buffers[BUFFER_NB] = {tx_buffer1, tx_buffer2, tx_buffer3}; +static struct DmaMultiBuffer mbuf; +static uint8_t tx_buffer[BUFFER_SIZE]; //--public functions------------------------------------------------------------ @@ -31,30 +31,75 @@ static uint8_t* tx_buffers[BUFFER_NB] = {tx_buffer1, tx_buffer2, tx_buffer3}; void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, enum GpioPin tx_pin) { - usart_periph = usart; gpio_configure(tx_port, tx_pin, GPIO_MODE_OUTPUT_FAST, GPIO_CONFIG_OUT_ALT_PUSH_PULL); - usart_configure(usart_periph, USART_CONFIG_8N1, 1152000); - - usart_set_tx_buffer(USART_PERIPH_3, tx_buffers, BUFFER_SIZE, BUFFER_NB, - DMA_CONFIG_PRIO_LOW); + usart_configure(usart, USART_CONFIG_8N1, 1000000); + dma_mbuf_configure(&mbuf,usart_configure_tx_dma(usart), + DMA_CONFIG_PRIO_LOW, tx_buffer, BUFFER_SIZE); debug_trace("\n"); - debug_trace("--------------------------------------------------------------------------------\n"); + debug_trace("------------------------------------------------------------------------------\n"); debug_trace("starting debug software\n"); debug_trace("compiled on " __DATE__ " at " __TIME__ "\n"); - debug_trace("--------------------------------------------------------------------------------\n"); + debug_trace("------------------------------------------------------------------------------\n"); } +#endif + +#if DEBUG_TRACE + void _debug_trace(char* format, ...) { - while(*format != '\0') { - while(usart_write_byte(usart_periph, *format)) {} - ++format; - } + print_debug("T:"); + print_debug(format); + + //ensure everything is written when done + while (dma_mbuf_switch(&mbuf)) {} +} + +#endif + +#if DEBUG_WARN + +void _debug_warn(char* format, ...) +{ + print_debug("W:"); + print_debug(format); + + //ensure everything is written when done + while (dma_mbuf_switch(&mbuf)) {} +} + +#endif + +#if DEBUG_ERROR + +void _debug_error(char* format, ...) +{ + print_debug("E:"); + print_debug(format); + + //ensure everything is written when done + while (dma_mbuf_switch(&mbuf)) {} } #endif //--local functions------------------------------------------------------------- +#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR + +static void print_debug(char* str) +{ + while (*str != '\0') { + if (dma_mbuf_write_byte(&mbuf, *str)) + { + //buffer is full, wait until transfer started + while (dma_mbuf_switch(&mbuf)) {} + } + ++str; + } +} + +#endif + diff --git a/srv/debug.h b/srv/debug.h index cd511d6..b954511 100644 --- a/srv/debug.h +++ b/srv/debug.h @@ -13,12 +13,11 @@ #include "../drv/usart.h" #include "../drv/gpio.h" -#include "stdint.h" - #define DEBUG_TRACE 1 #define DEBUG_WARN 0 #define DEBUG_ERROR 0 + //--type definitions------------------------------------------------------------ #if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR -- 2.45.2 From 3dc548332ff26761cba1dbcef527f310a32467f1 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 16:54:54 +0200 Subject: [PATCH 74/85] Implement basic string formatting --- srv/debug.c | 27 +++++---- srv/format.c | 162 +++++++++++++++++++++++++++++++++++++++++++++++++++ srv/format.h | 33 +++++++++++ 3 files changed, 211 insertions(+), 11 deletions(-) create mode 100644 srv/format.c create mode 100644 srv/format.h diff --git a/srv/debug.c b/srv/debug.c index 2937fe5..00f1265 100644 --- a/srv/debug.c +++ b/srv/debug.c @@ -9,11 +9,12 @@ #include "debug.h" #include "dma_mbuf.h" +#include "format.h" //--local definitions----------------------------------------------------------- -static void print_debug(char* str); +static uint32_t write_debug(uint8_t c, void* arg); #define BUFFER_SIZE 162 //(80 char line + \n) * 2 @@ -50,8 +51,13 @@ void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, void _debug_trace(char* format, ...) { - print_debug("T:"); - print_debug(format); + write_debug('T', nullptr); + write_debug(':', nullptr); + va_list va; + va_start(va, format); + format_vfctprintf(write_debug, nullptr, format, va); + va_end(va); + write_debug('\n', nullptr); //ensure everything is written when done while (dma_mbuf_switch(&mbuf)) {} @@ -89,16 +95,15 @@ void _debug_error(char* format, ...) #if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR -static void print_debug(char* str) +static uint32_t write_debug(uint8_t c, void* arg) { - while (*str != '\0') { - if (dma_mbuf_write_byte(&mbuf, *str)) - { - //buffer is full, wait until transfer started - while (dma_mbuf_switch(&mbuf)) {} - } - ++str; + while (dma_mbuf_write_byte(&mbuf, c)) + { + //buffer is full, wait until transfer started + while (dma_mbuf_switch(&mbuf)) {} } + + return 0; } #endif diff --git a/srv/format.c b/srv/format.c new file mode 100644 index 0000000..cad9774 --- /dev/null +++ b/srv/format.c @@ -0,0 +1,162 @@ +/** @file format.c + * Module handling various formating functions + * + * The module provides a lightweight printf function and the attached tools + */ + +//--includes-------------------------------------------------------------------- + +#include "format.h" + + +//--local definitions----------------------------------------------------------- + +struct BufferArg { + char* restrict buffer; + uint32_t buffer_size; + uint32_t byte_index; +}; + +uint32_t buffer_write(uint8_t byte, void* arg); +uint32_t render_format(FormatCallback callback, void* arg, + const char* restrict format, va_list va); +uint32_t render_signed(FormatCallback callback, void* arg, + va_list va, uint8_t size, uint8_t base); +uint32_t render_unsigned(FormatCallback callback, void* arg, + va_list* va, uint8_t size, uint8_t base); + + +//--local variables------------------------------------------------------------- + +//--public functions------------------------------------------------------------ + +uint32_t format_snprintf(char* restrict buffer, uint32_t buffer_size, + const char* restrict format, ...) +{ + va_list va; + va_start(va, format); + struct BufferArg arg = { buffer, buffer_size, 0 }; + uint32_t ret = render_format(buffer_write, &arg, format, va); + va_end(va); + return ret; +} + +uint32_t format_fctprintf(FormatCallback callback, void* arg, + const char* restrict format, ...) +{ + va_list va; + va_start(va, format); + uint32_t ret = render_format(callback, arg, format, va); + va_end(va); + return ret; +} + +uint32_t format_vfctprintf(FormatCallback callback, void* arg, + const char* restrict format, va_list va) +{ + return render_format(callback, arg, format, va); +} + +//--local functions------------------------------------------------------------- + +uint32_t buffer_write(uint8_t byte, void* arg) +{ + struct BufferArg* buffer_arg = (struct BufferArg*)arg; + if (buffer_arg->byte_index >= buffer_arg->buffer_size) { + return 1; + } + + buffer_arg->buffer[buffer_arg->byte_index] = byte; + ++buffer_arg->byte_index; + return 0; +} + +uint32_t render_format(FormatCallback callback, void* arg, + const char* restrict format, va_list va) +{ + uint8_t size; + bool in_format = false; + + for (const char* c = format; *c != '\0'; ++c) { + + if (in_format) { + switch (*c) { + case '%': + callback('%', arg); + break; + case 'h': + size = size / 2; + continue; + case 'l': + size = size * 2; + continue; + case 'c': + callback((uint8_t)va_arg(va, uint32_t), arg); + break; + case 's': + { + const char* str = va_arg(va, const char*); + for (const char* c2 = str; *c2 != '\0'; ++c2) { + callback(*c2, arg); + } + } + break; + case 'i': + //render_signed(callback, arg, va, size, 10); + break; + case 'u': + render_unsigned(callback, arg, &va, size, 10); + break; + case 'x': + render_unsigned(callback, arg, &va, size, 16); + break; + default: + //TODO manage error + break; + } + } else { + switch (*c) { + case '%': + in_format = true; + size = 4; + continue; + default: + callback(*c, arg); + break; + } + } + + in_format = false; + } + + return 0; +} + +uint32_t render_unsigned(FormatCallback callback, void* arg, + va_list* va, uint8_t size, uint8_t base) +{ + uint32_t number = va_arg(*va, uint32_t); + uint32_t base_power = base; + + while (base_power <= number) { + base_power *= base; + } + + while (base_power > 1) { + base_power /= base; + + uint8_t digit = 0; + while (number >= base_power) { + number -= base_power; + ++digit; + } + + if (digit < 10) { + callback('0' + digit, arg); + } else { + callback('A' + digit - 10, arg); + } + } + + return 0; +} diff --git a/srv/format.h b/srv/format.h new file mode 100644 index 0000000..04de136 --- /dev/null +++ b/srv/format.h @@ -0,0 +1,33 @@ +/** @file format.h + * Module handling various formating functions + * + * The module provides a lightweight printf function and the attached tools + */ + +#ifndef _FORMAT_H_ +#define _FORMAT_H_ + +//--includes-------------------------------------------------------------------- + +#include +#include + + +//--type definitions------------------------------------------------------------ + +typedef uint32_t (*FormatCallback)(uint8_t byte, void* arg); + + +//--functions------------------------------------------------------------------- + +uint32_t format_snprintf(char* restrict buffer, uint32_t buffer_size, + const char* restrict format, ...); + +uint32_t format_fctprintf(FormatCallback callback, void* arg, + const char* restrict format, ...); + +uint32_t format_vfctprintf(FormatCallback callback, void* arg, + const char* restrict format, va_list va); + +#endif //_FORMAT_H_ + -- 2.45.2 From 727aadaba9a21a2ef3567f58162b16d2dd8dc9c0 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 17:04:35 +0200 Subject: [PATCH 75/85] Implement signed integer formating --- srv/format.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/srv/format.c b/srv/format.c index cad9774..11456a1 100644 --- a/srv/format.c +++ b/srv/format.c @@ -21,9 +21,9 @@ uint32_t buffer_write(uint8_t byte, void* arg); uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va); uint32_t render_signed(FormatCallback callback, void* arg, - va_list va, uint8_t size, uint8_t base); + int32_t number, uint8_t base); uint32_t render_unsigned(FormatCallback callback, void* arg, - va_list* va, uint8_t size, uint8_t base); + uint32_t number, uint8_t base); //--local variables------------------------------------------------------------- @@ -74,7 +74,6 @@ uint32_t buffer_write(uint8_t byte, void* arg) uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va) { - uint8_t size; bool in_format = false; for (const char* c = format; *c != '\0'; ++c) { @@ -84,12 +83,6 @@ uint32_t render_format(FormatCallback callback, void* arg, case '%': callback('%', arg); break; - case 'h': - size = size / 2; - continue; - case 'l': - size = size * 2; - continue; case 'c': callback((uint8_t)va_arg(va, uint32_t), arg); break; @@ -102,13 +95,13 @@ uint32_t render_format(FormatCallback callback, void* arg, } break; case 'i': - //render_signed(callback, arg, va, size, 10); + render_signed(callback, arg, va_arg(va, int32_t), 10); break; case 'u': - render_unsigned(callback, arg, &va, size, 10); + render_unsigned(callback, arg, va_arg(va, uint32_t), 10); break; case 'x': - render_unsigned(callback, arg, &va, size, 16); + render_unsigned(callback, arg, va_arg(va, uint32_t), 16); break; default: //TODO manage error @@ -118,7 +111,6 @@ uint32_t render_format(FormatCallback callback, void* arg, switch (*c) { case '%': in_format = true; - size = 4; continue; default: callback(*c, arg); @@ -132,10 +124,20 @@ uint32_t render_format(FormatCallback callback, void* arg, return 0; } -uint32_t render_unsigned(FormatCallback callback, void* arg, - va_list* va, uint8_t size, uint8_t base) +uint32_t render_signed(FormatCallback callback, void* arg, + int32_t number, uint8_t base) +{ + if (number < 0) { + callback('-', arg); + number = -number; + } + + return render_unsigned(callback, arg, (uint32_t)number, base); +} + +uint32_t render_unsigned(FormatCallback callback, void* arg, + uint32_t number, uint8_t base) { - uint32_t number = va_arg(*va, uint32_t); uint32_t base_power = base; while (base_power <= number) { -- 2.45.2 From 075d9e17a64fece09cd8ccaa3d7b2e9524ed0689 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 17:17:05 +0200 Subject: [PATCH 76/85] Changed internal functions to static --- srv/format.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/srv/format.c b/srv/format.c index 11456a1..2694d02 100644 --- a/srv/format.c +++ b/srv/format.c @@ -17,12 +17,12 @@ struct BufferArg { uint32_t byte_index; }; -uint32_t buffer_write(uint8_t byte, void* arg); -uint32_t render_format(FormatCallback callback, void* arg, +static uint32_t buffer_write(uint8_t byte, void* arg); +static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va); -uint32_t render_signed(FormatCallback callback, void* arg, +static uint32_t render_signed(FormatCallback callback, void* arg, int32_t number, uint8_t base); -uint32_t render_unsigned(FormatCallback callback, void* arg, +static uint32_t render_unsigned(FormatCallback callback, void* arg, uint32_t number, uint8_t base); @@ -59,7 +59,7 @@ uint32_t format_vfctprintf(FormatCallback callback, void* arg, //--local functions------------------------------------------------------------- -uint32_t buffer_write(uint8_t byte, void* arg) +static uint32_t buffer_write(uint8_t byte, void* arg) { struct BufferArg* buffer_arg = (struct BufferArg*)arg; if (buffer_arg->byte_index >= buffer_arg->buffer_size) { @@ -71,7 +71,7 @@ uint32_t buffer_write(uint8_t byte, void* arg) return 0; } -uint32_t render_format(FormatCallback callback, void* arg, +static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va) { bool in_format = false; @@ -124,7 +124,7 @@ uint32_t render_format(FormatCallback callback, void* arg, return 0; } -uint32_t render_signed(FormatCallback callback, void* arg, +static uint32_t render_signed(FormatCallback callback, void* arg, int32_t number, uint8_t base) { if (number < 0) { @@ -135,7 +135,7 @@ uint32_t render_signed(FormatCallback callback, void* arg, return render_unsigned(callback, arg, (uint32_t)number, base); } -uint32_t render_unsigned(FormatCallback callback, void* arg, +static uint32_t render_unsigned(FormatCallback callback, void* arg, uint32_t number, uint8_t base) { uint32_t base_power = base; -- 2.45.2 From 3bcb9c7df47938b05dbf5ac86bc81633193c6b12 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 17:17:23 +0200 Subject: [PATCH 77/85] Add error handling --- srv/format.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/srv/format.c b/srv/format.c index 2694d02..f3bc2c1 100644 --- a/srv/format.c +++ b/srv/format.c @@ -81,27 +81,37 @@ static uint32_t render_format(FormatCallback callback, void* arg, if (in_format) { switch (*c) { case '%': - callback('%', arg); + if (callback('%', arg)) return 1; break; case 'c': - callback((uint8_t)va_arg(va, uint32_t), arg); + if (callback((uint8_t)va_arg(va, uint32_t), arg)) { + return 1; + } break; case 's': { const char* str = va_arg(va, const char*); for (const char* c2 = str; *c2 != '\0'; ++c2) { - callback(*c2, arg); + if (callback(*c2, arg)) return 1; } } break; case 'i': - render_signed(callback, arg, va_arg(va, int32_t), 10); + if (render_signed(callback, arg, va_arg(va, int32_t), 10)) { + return 1; + } break; case 'u': - render_unsigned(callback, arg, va_arg(va, uint32_t), 10); + if (render_unsigned(callback, arg, + va_arg(va, uint32_t), 10)) { + return 1; + } break; case 'x': - render_unsigned(callback, arg, va_arg(va, uint32_t), 16); + if (render_unsigned(callback, arg, + va_arg(va, uint32_t), 16)) { + return 1; + } break; default: //TODO manage error @@ -113,7 +123,7 @@ static uint32_t render_format(FormatCallback callback, void* arg, in_format = true; continue; default: - callback(*c, arg); + if (callback(*c, arg)) return 1; break; } } @@ -154,9 +164,9 @@ static uint32_t render_unsigned(FormatCallback callback, void* arg, } if (digit < 10) { - callback('0' + digit, arg); + if (callback('0' + digit, arg)) return 1; } else { - callback('A' + digit - 10, arg); + if (callback('A' + digit - 10, arg)) return 1; } } -- 2.45.2 From e477055e6e3f5bf631fffdd8d0469116f1e73b77 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 22:56:49 +0200 Subject: [PATCH 78/85] Implement right-justified padding --- srv/format.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 79 insertions(+), 10 deletions(-) diff --git a/srv/format.c b/srv/format.c index f3bc2c1..ec4de76 100644 --- a/srv/format.c +++ b/srv/format.c @@ -21,9 +21,9 @@ static uint32_t buffer_write(uint8_t byte, void* arg); static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va); static uint32_t render_signed(FormatCallback callback, void* arg, - int32_t number, uint8_t base); + int32_t number, uint8_t base, uint8_t width, bool zero_padding); static uint32_t render_unsigned(FormatCallback callback, void* arg, - uint32_t number, uint8_t base); + uint32_t number, uint8_t base, uint8_t width, bool zero_padding); //--local variables------------------------------------------------------------- @@ -74,7 +74,9 @@ static uint32_t buffer_write(uint8_t byte, void* arg) static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va) { + uint8_t width = 0; bool in_format = false; + bool zero_padding = false; for (const char* c = format; *c != '\0'; ++c) { @@ -97,22 +99,40 @@ static uint32_t render_format(FormatCallback callback, void* arg, } break; case 'i': - if (render_signed(callback, arg, va_arg(va, int32_t), 10)) { + if (render_signed(callback, arg, va_arg(va, int32_t), + 10, width, zero_padding)) { return 1; } break; case 'u': - if (render_unsigned(callback, arg, - va_arg(va, uint32_t), 10)) { + if (render_unsigned(callback, arg, va_arg(va, uint32_t), + 10, width, zero_padding)) { return 1; } break; case 'x': - if (render_unsigned(callback, arg, - va_arg(va, uint32_t), 16)) { + if (render_unsigned(callback, arg, va_arg(va, uint32_t), + 16, width, zero_padding)) { return 1; } break; + case '0': + if (width == 0) { + zero_padding = true; + continue; + } + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + width *= 10; + width += (*c - '0'); + continue; default: //TODO manage error break; @@ -121,6 +141,8 @@ static uint32_t render_format(FormatCallback callback, void* arg, switch (*c) { case '%': in_format = true; + zero_padding = false; + width = 0; continue; default: if (callback(*c, arg)) return 1; @@ -135,23 +157,70 @@ static uint32_t render_format(FormatCallback callback, void* arg, } static uint32_t render_signed(FormatCallback callback, void* arg, - int32_t number, uint8_t base) + int32_t number, uint8_t base, uint8_t width, bool zero_padding) { + if (width > 0 && number < 0) { + --width; + } + + if (width > 0) { + uint32_t abs_number; + if (number < 0) { + abs_number = -number; + } else { + abs_number = number; + } + + uint32_t base_power = base; + while (width > 0 && base_power <= abs_number) { + base_power *= base; + --width; + } + if (width > 0) { + --width; + } + + while (width > 0) { + --width; + if (zero_padding) { + if (callback('0', arg)) return 1; + } else { + if (callback(' ', arg)) return 1; + } + } + } + if (number < 0) { callback('-', arg); number = -number; } - return render_unsigned(callback, arg, (uint32_t)number, base); + return render_unsigned(callback, arg, (uint32_t)number, base, 0, + zero_padding); } static uint32_t render_unsigned(FormatCallback callback, void* arg, - uint32_t number, uint8_t base) + uint32_t number, uint8_t base, uint8_t width, bool zero_padding) { uint32_t base_power = base; while (base_power <= number) { base_power *= base; + if (width > 0) { + --width; + } + } + if (width > 0) { + --width; + } + + while (width > 0) { + --width; + if (zero_padding) { + if (callback('0', arg)) return 1; + } else { + if (callback(' ', arg)) return 1; + } } while (base_power > 1) { -- 2.45.2 From 0088322ee79452dfe1c71ad8e26f0e3d5556004a Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 23:10:19 +0200 Subject: [PATCH 79/85] Fix warning --- srv/format.c | 1 + 1 file changed, 1 insertion(+) diff --git a/srv/format.c b/srv/format.c index ec4de76..baa122b 100644 --- a/srv/format.c +++ b/srv/format.c @@ -121,6 +121,7 @@ static uint32_t render_format(FormatCallback callback, void* arg, zero_padding = true; continue; } + // fall through case '1': case '2': case '3': -- 2.45.2 From 254fec4f006d6e1fee5e0d345122fd32c9230f51 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Mon, 15 Apr 2024 23:10:31 +0200 Subject: [PATCH 80/85] Disable zero padding for signed integers zero padding is mostly used with unsiged integers, and is quite difficult to properly implement for signed integers. Disbaling iti n that case seems like a good compromise --- srv/format.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/srv/format.c b/srv/format.c index baa122b..8bdcc0d 100644 --- a/srv/format.c +++ b/srv/format.c @@ -21,7 +21,7 @@ static uint32_t buffer_write(uint8_t byte, void* arg); static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va); static uint32_t render_signed(FormatCallback callback, void* arg, - int32_t number, uint8_t base, uint8_t width, bool zero_padding); + int32_t number, uint8_t base, uint8_t width); static uint32_t render_unsigned(FormatCallback callback, void* arg, uint32_t number, uint8_t base, uint8_t width, bool zero_padding); @@ -100,7 +100,7 @@ static uint32_t render_format(FormatCallback callback, void* arg, break; case 'i': if (render_signed(callback, arg, va_arg(va, int32_t), - 10, width, zero_padding)) { + 10, width)) { return 1; } break; @@ -158,7 +158,7 @@ static uint32_t render_format(FormatCallback callback, void* arg, } static uint32_t render_signed(FormatCallback callback, void* arg, - int32_t number, uint8_t base, uint8_t width, bool zero_padding) + int32_t number, uint8_t base, uint8_t width) { if (width > 0 && number < 0) { --width; @@ -183,11 +183,7 @@ static uint32_t render_signed(FormatCallback callback, void* arg, while (width > 0) { --width; - if (zero_padding) { - if (callback('0', arg)) return 1; - } else { - if (callback(' ', arg)) return 1; - } + if (callback(' ', arg)) return 1; } } @@ -196,8 +192,7 @@ static uint32_t render_signed(FormatCallback callback, void* arg, number = -number; } - return render_unsigned(callback, arg, (uint32_t)number, base, 0, - zero_padding); + return render_unsigned(callback, arg, (uint32_t)number, base, 0, false); } static uint32_t render_unsigned(FormatCallback callback, void* arg, -- 2.45.2 From 84deb788a03bfb2589c75d6cd41eb7418650d822 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 20 Apr 2024 11:37:11 +0200 Subject: [PATCH 81/85] Improve debug module architecture --- srv/debug.c | 48 +++++++++--------------------------------------- srv/debug.h | 22 ++++++++++++++-------- 2 files changed, 23 insertions(+), 47 deletions(-) diff --git a/srv/debug.c b/srv/debug.c index 00f1265..23d3794 100644 --- a/srv/debug.c +++ b/srv/debug.c @@ -11,6 +11,8 @@ #include "dma_mbuf.h" #include "format.h" +#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR + //--local definitions----------------------------------------------------------- @@ -27,8 +29,6 @@ static uint8_t tx_buffer[BUFFER_SIZE]; //--public functions------------------------------------------------------------ -#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR - void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, enum GpioPin tx_pin) { @@ -45,16 +45,12 @@ void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, debug_trace("------------------------------------------------------------------------------\n"); } -#endif - -#if DEBUG_TRACE - -void _debug_trace(char* format, ...) +void _debug_print(const char* restrict header, + const char* restrict format, ...) { - write_debug('T', nullptr); - write_debug(':', nullptr); va_list va; va_start(va, format); + format_vfctprintf(write_debug, nullptr, header, va); format_vfctprintf(write_debug, nullptr, format, va); va_end(va); write_debug('\n', nullptr); @@ -63,40 +59,13 @@ void _debug_trace(char* format, ...) while (dma_mbuf_switch(&mbuf)) {} } -#endif - -#if DEBUG_WARN - -void _debug_warn(char* format, ...) -{ - print_debug("W:"); - print_debug(format); - - //ensure everything is written when done - while (dma_mbuf_switch(&mbuf)) {} -} - -#endif - -#if DEBUG_ERROR - -void _debug_error(char* format, ...) -{ - print_debug("E:"); - print_debug(format); - - //ensure everything is written when done - while (dma_mbuf_switch(&mbuf)) {} -} - -#endif //--local functions------------------------------------------------------------- -#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR - static uint32_t write_debug(uint8_t c, void* arg) { + (void)arg; //unused, required because of FormatCallback + while (dma_mbuf_write_byte(&mbuf, c)) { //buffer is full, wait until transfer started @@ -106,5 +75,6 @@ static uint32_t write_debug(uint8_t c, void* arg) return 0; } -#endif +#endif //DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR + diff --git a/srv/debug.h b/srv/debug.h index b954511..7fcb31d 100644 --- a/srv/debug.h +++ b/srv/debug.h @@ -14,8 +14,8 @@ #include "../drv/gpio.h" #define DEBUG_TRACE 1 -#define DEBUG_WARN 0 -#define DEBUG_ERROR 0 +#define DEBUG_WARN 1 +#define DEBUG_ERROR 1 //--type definitions------------------------------------------------------------ @@ -27,19 +27,22 @@ #endif #if DEBUG_TRACE -#define debug_trace(format, ...) _debug_trace(format __VA_OPT__(,) __VA_ARGS__) +#define debug_trace(format, ...) _debug_print("T:", \ + format __VA_OPT__(,) __VA_ARGS__) #else #define debug_trace(format, ...) do {} while (0) #endif #if DEBUG_WARN -#define debug_warn(format, ...) _debug_warn(format __VA_OPT__(,) __VA_ARGS__) +#define debug_warn(format, ...) _debug_print("W:", \ + format __VA_OPT__(,) __VA_ARGS__) #else #define debug_warn(format, ...) do {} while (0) #endif #if DEBUG_ERROR -#define debug_error(format, ...) _debug_error(format __VA_OPT__(,) __VA_ARGS__) +#define debug_error(format, ...) _debug_print("E:", \ + format __VA_OPT__(,) __VA_ARGS__) #else #define debug_error(format, ...) do {} while (0) #endif @@ -47,12 +50,15 @@ //--functions------------------------------------------------------------------- +#if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR + void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, enum GpioPin tx_pin); -void _debug_trace(char* format, ...); -void _debug_warn(char* format, ...); -void _debug_error(char* format, ...); +void _debug_print(const char* restrict header, + const char* restrict format, ...); + +#endif #endif //_DEBUG_H_ -- 2.45.2 From 12800818ce40f12979c2c50da6f95fd3d3f1fff2 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 20 Apr 2024 11:44:56 +0200 Subject: [PATCH 82/85] Document debug module --- srv/debug.c | 4 +++- srv/debug.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/srv/debug.c b/srv/debug.c index 23d3794..416880c 100644 --- a/srv/debug.c +++ b/srv/debug.c @@ -62,6 +62,9 @@ void _debug_print(const char* restrict header, //--local functions------------------------------------------------------------- +/** + * Callback to use with format_vfctprintf() to print caracters to the debug port + */ static uint32_t write_debug(uint8_t c, void* arg) { (void)arg; //unused, required because of FormatCallback @@ -77,4 +80,3 @@ static uint32_t write_debug(uint8_t c, void* arg) #endif //DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR - diff --git a/srv/debug.h b/srv/debug.h index 7fcb31d..523b117 100644 --- a/srv/debug.h +++ b/srv/debug.h @@ -27,6 +27,12 @@ #endif #if DEBUG_TRACE +/** + * Prints a trace message on the debug port. This function should return + * immediately, provided that the message's length doesn't exceed 80 caracters + * and that it isn't called in very quick succession. Otherwise, it will block + * until the internal buffering system is ready to accept the message + */ #define debug_trace(format, ...) _debug_print("T:", \ format __VA_OPT__(,) __VA_ARGS__) #else @@ -34,6 +40,12 @@ #endif #if DEBUG_WARN +/** + * Prints a warning message on the debug port. This function should return + * immediately, provided that the message's length doesn't exceed 80 caracters + * and that it isn't called in very quick succession. Otherwise, it will block + * until the internal buffering system is ready to accept the message + */ #define debug_warn(format, ...) _debug_print("W:", \ format __VA_OPT__(,) __VA_ARGS__) #else @@ -41,6 +53,12 @@ #endif #if DEBUG_ERROR +/** + * Prints an error message on the debug port. This function should return + * immediately, provided that the message's length doesn't exceed 80 caracters + * and that it isn't called in very quick succession. Otherwise, it will block + * until the internal buffering system is ready to accept the message + */ #define debug_error(format, ...) _debug_print("E:", \ format __VA_OPT__(,) __VA_ARGS__) #else @@ -52,9 +70,24 @@ #if DEBUG_TRACE || DEBUG_WARN || DEBUG_ERROR +/** + * Initializes the debug system to use the given usart peripheral on the given + * tx port, printing a banner if traces are enabled. + * The usart doesn't need to be configured, neither does the tx port. + * + * This function shouldn't be called directly. Instead, use the debug_init macro + */ void _debug_init(enum UsartPeriph usart, enum GpioPort tx_port, enum GpioPin tx_pin); +/** + * Prints a debug message on the debug port with the given header. This function + * should return immediately, provided that the message's length doesn't exceed + * 80 caracters and that it isn't called in very quick succession. Otherwise, it + * will block until the internal buffering system is ready to accept the message + * + * This function shouldn't be called directly. Instead, use the debug macros + */ void _debug_print(const char* restrict header, const char* restrict format, ...); -- 2.45.2 From 26f2b4d545e486c2559a186003bdf0d12425ce03 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 20 Apr 2024 11:57:02 +0200 Subject: [PATCH 83/85] Document format module --- srv/format.c | 26 ++++++++++++++++++++++++++ srv/format.h | 24 ++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/srv/format.c b/srv/format.c index 8bdcc0d..ccf392e 100644 --- a/srv/format.c +++ b/srv/format.c @@ -57,8 +57,15 @@ uint32_t format_vfctprintf(FormatCallback callback, void* arg, return render_format(callback, arg, format, va); } + //--local functions------------------------------------------------------------- +/** + * FormatCallback to write into a regular buffer. A pointer to BufferArg shall + * be passed as arg. + * + * Returns 0 if everything went as expected, 1 otherwise + */ static uint32_t buffer_write(uint8_t byte, void* arg) { struct BufferArg* buffer_arg = (struct BufferArg*)arg; @@ -71,6 +78,12 @@ static uint32_t buffer_write(uint8_t byte, void* arg) return 0; } +/** + * Renders the given format to the output defined by the provided callback, + * formatting accordingly the provided arguments + * + * Returns 0 if everything went as expected, 1 otherwise + */ static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va) { @@ -157,6 +170,12 @@ static uint32_t render_format(FormatCallback callback, void* arg, return 0; } +/** + * Formats a signed integer and renders it to the output defined by the provided + * callback + * + * Returns 0 if everything went as expected, 1 otherwise + */ static uint32_t render_signed(FormatCallback callback, void* arg, int32_t number, uint8_t base, uint8_t width) { @@ -195,6 +214,12 @@ static uint32_t render_signed(FormatCallback callback, void* arg, return render_unsigned(callback, arg, (uint32_t)number, base, 0, false); } +/** + * Formats an unsigned integer and renders it to the output defined by the + * provided callback + * + * Returns 0 if everything went as expected, 1 otherwise + */ static uint32_t render_unsigned(FormatCallback callback, void* arg, uint32_t number, uint8_t base, uint8_t width, bool zero_padding) { @@ -237,3 +262,4 @@ static uint32_t render_unsigned(FormatCallback callback, void* arg, return 0; } + diff --git a/srv/format.h b/srv/format.h index 04de136..a735542 100644 --- a/srv/format.h +++ b/srv/format.h @@ -20,12 +20,36 @@ typedef uint32_t (*FormatCallback)(uint8_t byte, void* arg); //--functions------------------------------------------------------------------- +/** + * Custom implementation of snprintf. Print the given format into the given + * buffer with the attached arguments properly formated. + * + * This function only provided a minimal subset of the standard library's + * snprintf : %c, %s, %i, %d, %x as well as right-justified padding for %d and + * %x + * + * Returns 0 if everything went as expected, 1 otherwise + */ uint32_t format_snprintf(char* restrict buffer, uint32_t buffer_size, const char* restrict format, ...); +/** + * Custom implementation of fprintf using a callback instead of a file pointer. + * Print the given format using the given callback with the attached arguments + * properly formated. + * + * This function only provided a minimal subset of the standard library's + * snprintf : %c, %s, %i, %d, %x as well as right-justified padding for %d and + * %x + * + * Returns 0 if everything went as expected, 1 otherwise + */ uint32_t format_fctprintf(FormatCallback callback, void* arg, const char* restrict format, ...); +/** + * Variadic variation of format_fctprintf(), see the later for more information + */ uint32_t format_vfctprintf(FormatCallback callback, void* arg, const char* restrict format, va_list va); -- 2.45.2 From a20acf4031c9207f895c7ae6e04c3f75f90a2774 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 20 Apr 2024 15:20:18 +0200 Subject: [PATCH 84/85] Implement error header --- srv/error.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 srv/error.h diff --git a/srv/error.h b/srv/error.h new file mode 100644 index 0000000..2616e6b --- /dev/null +++ b/srv/error.h @@ -0,0 +1,50 @@ +/** @file error.h + * Module providing error handling macros + * + * The module implements the assert macro intended to allow catching critical + * errors during debug while having no influence in the release code as well as + * multiple tool macros to handles other kinds of errors + */ + +#ifndef _ERROR_H_ +#define _ERROR_H_ + +//--includes-------------------------------------------------------------------- + +#include "debug.h" + +#define ERROR_ASSERT 1 + + +//--type definitions------------------------------------------------------------ + +#define error_to_string(arg) #arg + +#if ERROR_ASSERT +#define error_assert(cond) \ + do { \ + if (!(cond)) { \ + debug_error("%s:l%u:%s: %s", __FILE__, __LINE__, __func__, \ + error_to_string(cond)); \ + while (true) {} \ + } \ + } while (0) +#else +#define error_assert(cond) do {} while (0) +#endif + +#if ERROR_ASSERT +#define error_trigger(msg, ...) \ + do { \ + debug_error(msg __VA_OPT__(,) __VA_ARGS__); \ + while (true) {} \ + } while (0) +#else +#define error_trigger(msg) do {} while (0) +#endif + + +//--functions------------------------------------------------------------------- + +#endif //_ERROR_H_ + -- 2.45.2 From 47a06a2a398965fcc97b8a70b05df5a732865f45 Mon Sep 17 00:00:00 2001 From: Steins7 Date: Sat, 20 Apr 2024 15:43:17 +0200 Subject: [PATCH 85/85] Add asserts in existing code --- srv/dma_cbuf.c | 10 +++++++++- srv/dma_mbuf.c | 11 ++++++++++- srv/format.c | 7 ++++++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/srv/dma_cbuf.c b/srv/dma_cbuf.c index 22f1fe4..718c4b6 100644 --- a/srv/dma_cbuf.c +++ b/srv/dma_cbuf.c @@ -8,6 +8,7 @@ //--includes-------------------------------------------------------------------- #include "dma_cbuf.h" +#include "error.h" //--local definitions----------------------------------------------------------- @@ -31,7 +32,9 @@ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, const struct DmaParam* param, enum DmaConfig priority, volatile void* raw_buffer, uint16_t buffer_size) { - #warning "check for null ptr" + error_assert(buffer != nullptr); + error_assert(param != nullptr); + error_assert(raw_buffer != nullptr); buffer->buffer = raw_buffer; @@ -52,6 +55,9 @@ void dma_cbuf_configure(volatile struct DmaCircBuffer* buffer, uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, uint8_t* byte) { + error_assert(buffer != nullptr); + error_assert(byte != nullptr); + //retreive the current end of the buffer based on the DMA's progress uint16_t end = buffer->size - dma_get_remaining(buffer->dma, buffer->channel); @@ -86,6 +92,8 @@ uint32_t dma_cbuf_read_byte(volatile struct DmaCircBuffer* buffer, static void cbuf_callback(enum DmaIRQSource src, volatile void* param) { (void)src; //only transfer complete expected + error_assert(param != nullptr); + volatile struct DmaCircBuffer* buffer = param; buffer->dma_looped = true; } diff --git a/srv/dma_mbuf.c b/srv/dma_mbuf.c index 4f2255c..a5896b6 100644 --- a/srv/dma_mbuf.c +++ b/srv/dma_mbuf.c @@ -8,6 +8,7 @@ //--includes-------------------------------------------------------------------- #include "dma_mbuf.h" +#include "error.h" //--local definitions----------------------------------------------------------- @@ -30,7 +31,9 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, const struct DmaParam* param, enum DmaConfig priority, void* raw_buffer, uint16_t buffer_size) { - #warning "check for null ptr" + error_assert(buffer != nullptr); + error_assert(param != nullptr); + error_assert(raw_buffer != nullptr); buffer->raw_buffer = raw_buffer; @@ -51,6 +54,8 @@ void dma_mbuf_configure(volatile struct DmaMultiBuffer* buffer, uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, uint8_t byte) { + error_assert(buffer != nullptr); + //if the current buffer is full, give up if (buffer->byte_index >= buffer->buffer_size) { return 1; @@ -65,6 +70,8 @@ uint32_t dma_mbuf_write_byte(volatile struct DmaMultiBuffer* buffer, uint32_t dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) { + error_assert(buffer != nullptr); + //no data to send, stop here if (buffer->byte_index == 0) { return 0; @@ -100,6 +107,8 @@ uint32_t dma_mbuf_switch(volatile struct DmaMultiBuffer* buffer) static void mbuf_callback(enum DmaIRQSource src, volatile void* param) { (void)src; //only transfer complete expected + error_assert(param != nullptr); + volatile struct DmaMultiBuffer* buffer = param; dma_stop(buffer->dma, buffer->channel); buffer->dma_running = false; diff --git a/srv/format.c b/srv/format.c index ccf392e..df78bd3 100644 --- a/srv/format.c +++ b/srv/format.c @@ -7,6 +7,7 @@ //--includes-------------------------------------------------------------------- #include "format.h" +#include "error.h" //--local definitions----------------------------------------------------------- @@ -68,6 +69,8 @@ uint32_t format_vfctprintf(FormatCallback callback, void* arg, */ static uint32_t buffer_write(uint8_t byte, void* arg) { + error_assert(arg != nullptr); + struct BufferArg* buffer_arg = (struct BufferArg*)arg; if (buffer_arg->byte_index >= buffer_arg->buffer_size) { return 1; @@ -87,6 +90,8 @@ static uint32_t buffer_write(uint8_t byte, void* arg) static uint32_t render_format(FormatCallback callback, void* arg, const char* restrict format, va_list va) { + error_assert(format != nullptr); + uint8_t width = 0; bool in_format = false; bool zero_padding = false; @@ -148,7 +153,7 @@ static uint32_t render_format(FormatCallback callback, void* arg, width += (*c - '0'); continue; default: - //TODO manage error + error_trigger("unsupported option: %c in %s", c, format); break; } } else { -- 2.45.2

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