/** @file dma_regs.h
 * Module defining the DMA registers.
 *
 * Mainly made to be used by the dma module. It is recommanded to go through
 * the functions provided by that module instead of directly using the registers
 * defined here.
 */

#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_

//--includes--------------------------------------------------------------------

#include "stdint.h"


//--type definitions------------------------------------------------------------

#define DMA1_BASE_ADDRESS 0x40020000
#define DMA2_BASE_ADDRESS 0x40020400

union DMA_ISR {
	struct {
		uint32_t GIF1:1;
		uint32_t TCIF1:1;
		uint32_t HTIF1:1;
		uint32_t TEIF1:1;
		uint32_t GIF2:1;
		uint32_t TCIF2:1;
		uint32_t HTIF2:1;
		uint32_t TEIF2:1;
		uint32_t GIF3:1;
		uint32_t TCIF3:1;
		uint32_t HTIF3:1;
		uint32_t TEIF3:1;
		uint32_t GIF4:1;
		uint32_t TCIF4:1;
		uint32_t HTIF4:1;
		uint32_t TEIF4:1;
		uint32_t GIF5:1;
		uint32_t TCIF5:1;
		uint32_t HTIF5:1;
		uint32_t TEIF5:1;
		uint32_t GIF6:1;
		uint32_t TCIF6:1;
		uint32_t HTIF6:1;
		uint32_t TEIF6:1;
		uint32_t GIF7:1;
		uint32_t TCIF7:1;
		uint32_t HTIF7:1;
		uint32_t TEIF7:1;
		uint32_t reserved1:4;
	};
	uint32_t word;
};

union DMA_IFCR {
	struct {
		uint32_t CGIF1:1;
		uint32_t CTCIF1:1;
		uint32_t CHTIF1:1;
		uint32_t CTEIF1:1;
		uint32_t CGIF2:1;
		uint32_t CTCIF2:1;
		uint32_t CHTIF2:1;
		uint32_t CTEIF2:1;
		uint32_t CGIF3:1;
		uint32_t CTCIF3:1;
		uint32_t CHTIF3:1;
		uint32_t CTEIF3:1;
		uint32_t CGIF4:1;
		uint32_t CTCIF4:1;
		uint32_t CHTIF4:1;
		uint32_t CTEIF4:1;
		uint32_t CGIF5:1;
		uint32_t CTCIF5:1;
		uint32_t CHTIF5:1;
		uint32_t CTEIF5:1;
		uint32_t CGIF6:1;
		uint32_t CTCIF6:1;
		uint32_t CHTIF6:1;
		uint32_t CTEIF6:1;
		uint32_t CGIF7:1;
		uint32_t CTCIF7:1;
		uint32_t CHTIF7:1;
		uint32_t CTEIF7:1;
		uint32_t reserved1:4;
	};
	uint32_t word;
};

union DMA_CCR {
	struct {
		uint32_t EN:1;
		uint32_t TCIE:1;
		uint32_t HTIE:1;
		uint32_t TEIE:1;
		uint32_t DIR:1;
		uint32_t CIRC:1;
		uint32_t PINC:1;
		uint32_t MINC:1;
		uint32_t PSIZE:2;
		uint32_t MSIZE:2;
		uint32_t PL:2;
		uint32_t MEM2MEM:1;
		uint32_t reserved1:17;
	};
	uint32_t word;
};

union DMA_CNDTR {
	struct {
		uint32_t NDT:16;
		uint32_t reserved1:16;
	};
	uint32_t word;
};

struct DMA_CHANNEL {
	union DMA_CCR CCR;
	union DMA_CNDTR CNDTR;
	uint32_t CPAR;
	uint32_t CMAR;
	uint32_t reserved1;
};

struct DMA {
	union DMA_ISR ISR;
	union DMA_IFCR IFCR;
	struct DMA_CHANNEL CHANNELS[7];
};


//--functions-------------------------------------------------------------------

#endif //_DMA_REGS_H_