Steins7
004b0b9a76
FUnctions need a cleanup and some details need be ironned, like the clock management since the whole backup domain must be reset to configure them
140 lines
3.2 KiB
C
140 lines
3.2 KiB
C
//--includes--------------------------------------------------------------------
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#include "rtc.h"
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#include "rtc_regs.h"
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#include "rcc.h"
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#include "pwr.h"
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#include "nvic.h"
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//--local definitions-----------------------------------------------------------
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//--local variables-------------------------------------------------------------
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static volatile struct RTC* regs = (struct RTC*)RTC_BASE_ADDRESS;
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static RtcCallback rtc_callback;
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//--public functions------------------------------------------------------------
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void rtc_configure(uint32_t period_ms, enum RtcClockSrc clock_src,
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enum RtcIrq irq_mask, uint32_t alarm_tick, RtcCallback callback)
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{
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pwr_configure_bkp_write(true);
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//start RTC
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rcc_configure_rtc(true, clock_src + 1);
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//rtc_reset();
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rcc_enable(RCC_AHB_NONE, RCC_APB1_BKP, RCC_APB2_NONE);
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//rcc_configure_rtc(false, RCC_RTC_CLOCK_SRC_NONE);
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//compute prescaler
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uint32_t prescaler = 0;
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switch (clock_src) {
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case RTC_CLOCK_SRC_LSE:
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prescaler = 32768000; //32.768kHz
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break;
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case RTC_CLOCK_SRC_LSI:
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prescaler = 40000000; //40khz
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break;
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case RTC_CLOCK_SRC_HSE:
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prescaler = 62500000; //8Mhz / 128
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break;
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default:
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return;
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}
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prescaler /= period_ms;
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//wait for registers to synchronize
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regs->CRL.RSF = 0;
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while (regs->CRL.RSF != 1) {}
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//wait for last operation to finish
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while (regs->CRL.RTOFF != 1) {}
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//enable core configuration
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regs->CRL.CNF = 1;
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//configure core registers
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regs->PRLH.PRL = prescaler >> 16;
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regs->PRLL.PRL = prescaler;
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regs->ALRH.RTC_ALR = alarm_tick >> 16;
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regs->ALRL.RTC_ALR = alarm_tick;
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//apply irq config
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regs->CRH.word |= irq_mask & 0x7;
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//disable/apply core configuration
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regs->CRL.CNF = 0;
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//wait for last operation to finish
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while (regs->CRL.RTOFF != 1) {}
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pwr_configure_bkp_write(false);
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if (callback) {
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rtc_callback = callback;
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nvic_enable(NVIC_IRQ_RTC);
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}
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}
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void rtc_reset(void)
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{
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nvic_disable(NVIC_IRQ_RTC);
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pwr_configure_bkp_write(true);
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rcc_enable(RCC_AHB_NONE, RCC_APB1_BKP, RCC_APB2_NONE);
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//wait for registers to synchronize
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regs->CRL.RSF = 0;
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//while (regs->CRL.RSF != 1) {}
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//wait for last operation to finish
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while (regs->CRL.RTOFF != 1) {}
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//clear config registers
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regs->CRH.word &= ~0x7;
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regs->CRL.word &= ~0xf;
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//enable core configuration
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regs->CRL.CNF = 1;
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//reset core registers. DIV register can be ignore since it is reset on any
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//changes of the other 2
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regs->PRLH.PRL = 0x0;
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regs->PRLL.PRL = 0x8000;
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regs->CNTH.RTC_CNT = 0x0;
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regs->CNTL.RTC_CNT = 0x0;
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//disable/apply core configuration
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regs->CRL.CNF = 0;
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//wait for last operation to finish
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while (regs->CRL.RTOFF != 1) {}
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rcc_configure_rtc(false, RCC_RTC_CLOCK_SRC_NONE);
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rcc_disable(RCC_AHB_NONE, RCC_APB1_BKP, RCC_APB2_NONE);
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pwr_configure_bkp_write(false);
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}
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uint32_t stk_read_s(void)
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{
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//wait for core registers to be synchronized, immediate most of the time
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while (regs->CRL.RSF != 1) {}
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uint32_t time = regs->CNTH.RTC_CNT << 16;
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time |= regs->CNTL.RTC_CNT << 0;
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return time;
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}
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//--local functions-------------------------------------------------------------
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void hdr_rtc(void)
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{
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nvic_clear_pending(NVIC_IRQ_RTC);
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//copy and clear and pass along src flags
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enum RtcIrq src = regs->CRL.word & 0x7;
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regs->CRL.word &= ~(0x7);
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rtc_callback(src);
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}
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