Steins7
5e4d87474a
A while back, macros had to be put in place to avoid letting the compiler directly use the bitfields. This was necessary because the compiler used strb instruction which only write bytes. On the AHB bus, byte writes are transformed into word writes by repeating the byte, which caused mayhem in the registers. After a lot of research, turns out the packed attribute stops the compiler from does optimal (word) writes and isn't needed anyway. Removing them fixes the issue
138 lines
2.3 KiB
C
138 lines
2.3 KiB
C
/** @file usart_regs.h
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* Module defining the USART registers.
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*
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* Mainly made to be used by the usart module. It is recommanded to go through
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* the functions provided by that module instead of directly using the registers
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* defined here.
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*/
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#ifndef _USART_REGS_H_
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#define _USART_REGS_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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//--type definitions------------------------------------------------------------
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#define USART1_BASE_ADDRESS 0x40013800
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#define USART2_BASE_ADDRESS 0x40004400
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#define USART3_BASE_ADDRESS 0x40004800
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union USART_SR {
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struct {
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uint32_t PE:1;
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uint32_t FE:1;
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uint32_t NE:1;
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uint32_t ORE:1;
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uint32_t IDLE:1;
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uint32_t RXNE:1;
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uint32_t TC:1;
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uint32_t TXE:1;
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uint32_t LBD:1;
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uint32_t CTS:1;
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uint32_t reserved1:22;
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};
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uint32_t word;
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};
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union USART_DR {
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struct {
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uint32_t DR:9;
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uint32_t reserved1:23;
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};
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uint32_t word;
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};
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union USART_BRR {
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struct {
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uint32_t DIV_Fraction:4;
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uint32_t DIV_Mantissa:12;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union USART_CR1 {
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struct {
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uint32_t SBK:1;
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uint32_t RWU:1;
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uint32_t RE:1;
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uint32_t TE:1;
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uint32_t IDLEIE:1;
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uint32_t RXNEIE:1;
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uint32_t TCIE:1;
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uint32_t TXEIE:1;
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uint32_t PEI:1;
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uint32_t PS:1;
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uint32_t PCE:1;
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uint32_t WAKE:1;
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uint32_t M:1;
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uint32_t UE:1;
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uint32_t reserved1:18;
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};
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uint32_t word;
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};
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union USART_CR2 {
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struct {
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uint32_t ADD:4;
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uint32_t reserved1:1;
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uint32_t LBDL:1;
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uint32_t LBDIE:1;
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uint32_t reserved2:1;
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uint32_t LBCL:1;
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uint32_t CPHA:1;
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uint32_t CPOL:1;
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uint32_t CLKEN:1;
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uint32_t STOP:2;
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uint32_t LINEN:1;
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uint32_t reserved3:17;
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};
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uint32_t word;
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};
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union USART_CR3 {
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struct {
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uint32_t EIE:1;
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uint32_t IREN:1;
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uint32_t IRLP:1;
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uint32_t HDSEL:1;
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uint32_t NACK:1;
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uint32_t SCEN:1;
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uint32_t DMAR:1;
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uint32_t DMAT:1;
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uint32_t RTSE:1;
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uint32_t CTSE:1;
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uint32_t CTSIE:1;
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uint32_t reserved3:21;
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};
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uint32_t word;
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};
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union USART_GTPR {
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struct {
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uint32_t PSC:8;
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uint32_t GT:8;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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struct USART {
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union USART_SR SR;
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union USART_DR DR;
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union USART_BRR BRR;
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union USART_CR1 CR1;
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union USART_CR2 CR2;
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union USART_CR3 CR3;
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union USART_GTPR GTPR;
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};
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//--functions-------------------------------------------------------------------
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#endif //_USART_REGS_H_
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