Steins7
4464156981
Control over most parameters is not needed since they cannot change for the buffer to work as expected. Only the priority should be adjustable
349 lines
8.8 KiB
C
349 lines
8.8 KiB
C
/** @file usart.c
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* Module handling Universal Synchronous/Asynchronous Receiver/Transmitter
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*
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* The module provides functions to configure the usarts and read/write from/to
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* it
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*/
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//--includes--------------------------------------------------------------------
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#include "usart.h"
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#include "nvic.h"
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#include "usart_regs.h"
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#include "reg.h"
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#include "rcc.h"
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#include "dma.h"
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#include "dma_mbuf.h"
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#include "dma_cbuf.h"
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#include "stddef.h"
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//--local definitions-----------------------------------------------------------
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static void configure_usart(volatile struct USART* regs,
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enum UsartConfig config);
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate);
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//--local variables-------------------------------------------------------------
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static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS;
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static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS;
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static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS;
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static volatile struct DmaCircBuffer usart1_rx_buffer;
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static volatile struct DmaMultiBuffer usart1_tx_buffer;
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static volatile struct DmaCircBuffer usart2_rx_buffer;
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static volatile struct DmaMultiBuffer usart2_tx_buffer;
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static volatile struct DmaCircBuffer usart3_rx_buffer;
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static volatile struct DmaMultiBuffer usart3_tx_buffer;
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//--public functions------------------------------------------------------------
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void usart_configure(enum UsartPeriph periph, enum UsartConfig config,
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uint32_t baudrate)
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{
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struct RccClocks clocks;
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rcc_get_clocks(&clocks);
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switch (periph) {
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case USART_PERIPH_1:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART);
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configure_baudrate(usart1, clocks.apb2_freq, baudrate);
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configure_usart(usart1, config);
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#warning "fix zeroed variables init"
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usart1_tx_buffer.buffers = NULL;
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usart1_rx_buffer.buffer = NULL;
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break;
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case USART_PERIPH_2:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE);
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configure_baudrate(usart2, clocks.apb1_freq, baudrate);
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configure_usart(usart2, config);
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usart2_tx_buffer.buffers = NULL;
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usart2_rx_buffer.buffer = NULL;
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break;
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case USART_PERIPH_3:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE);
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configure_baudrate(usart3, clocks.apb1_freq, baudrate);
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configure_usart(usart3, config);
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usart3_tx_buffer.buffers = NULL;
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usart3_rx_buffer.buffer = NULL;
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break;
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default:
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break;
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}
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}
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uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
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{
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volatile struct USART* regs;
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volatile struct DmaMultiBuffer* buffer;
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enum NvicIrq irq;
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switch (periph) {
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case USART_PERIPH_1:
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regs = usart1;
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buffer = &usart1_tx_buffer;
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irq = NVIC_IRQ_USART1;
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break;
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case USART_PERIPH_2:
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regs = usart2;
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buffer = &usart2_tx_buffer;
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irq = NVIC_IRQ_USART2;
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break;
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case USART_PERIPH_3:
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regs = usart3;
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buffer = &usart3_tx_buffer;
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irq = NVIC_IRQ_USART3;
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break;
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default:
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return 1;
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break;
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}
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if (buffer->buffers) {
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//if the tx register is empty, there is no need to go through the dma
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if (regs->SR.TXE) {
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reg_write(regs->DR, USART_DR_DR, byte);
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//enable IRQ, disable DMA
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reg_reset(regs->CR3, USART_CR3_DMAT);
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reg_set(regs->CR1, USART_CR1_TXEIE);
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nvic_enable(irq);
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return 0;
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} else {
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return dma_mbuf_write_byte(buffer, byte);
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}
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} else {
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//only write data if the tx register it empty, give up otherwise
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if (regs->SR.TXE) {
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reg_write(regs->DR, USART_DR_DR, byte);
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return 0;
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} else {
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return 1;
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}
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}
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}
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uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte)
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{
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volatile struct USART* regs;
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volatile struct DmaCircBuffer* buffer;
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switch (periph) {
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case USART_PERIPH_1:
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regs = usart1;
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buffer = &usart1_rx_buffer;
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break;
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case USART_PERIPH_2:
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regs = usart2;
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buffer = &usart2_rx_buffer;
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break;
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case USART_PERIPH_3:
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regs = usart3;
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buffer = &usart3_rx_buffer;
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break;
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default:
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return 1;
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break;
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}
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if (buffer->buffer) {
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return dma_cbuf_read_byte(buffer, byte);
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} else {
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if (regs->SR.RXNE) {
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*byte = regs->DR.DR;
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return 0;
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} else {
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return 1;
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}
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}
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}
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void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers,
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uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority)
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{
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switch (periph) {
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case USART_PERIPH_1:
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dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR,
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buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4,
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priority);
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break;
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case USART_PERIPH_2:
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dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR,
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buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7,
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priority);
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break;
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case USART_PERIPH_3:
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dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR,
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buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2,
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priority);
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break;
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}
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}
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void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer,
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uint16_t size, enum DmaConfig priority)
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{
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switch (periph) {
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case USART_PERIPH_1:
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dma_cbuf_configure(&usart1_rx_buffer, buffer, (void*)&usart1->DR,
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size, DMA_PERIPH_1, DMA_CHANNEL_5, priority);
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reg_set(usart1->CR3, USART_CR3_DMAR);
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break;
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case USART_PERIPH_2:
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dma_cbuf_configure(&usart2_rx_buffer, buffer, (void*)&usart2->DR,
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size, DMA_PERIPH_1, DMA_CHANNEL_6, priority);
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reg_set(usart2->CR3, USART_CR3_DMAR);
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break;
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case USART_PERIPH_3:
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dma_cbuf_configure(&usart3_rx_buffer, buffer, (void*)&usart3->DR,
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size, DMA_PERIPH_1, DMA_CHANNEL_3, priority);
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reg_set(usart3->CR3, USART_CR3_DMAR);
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break;
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}
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}
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//--local functions-------------------------------------------------------------
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/**
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* Apply the given configuration to the given registers. Generic version of
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* usart_configure()
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*/
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static void configure_usart(volatile struct USART* regs,
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enum UsartConfig config)
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{
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//configure parity
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_8E2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_reset(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_set(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_PCE);
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break;
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default:
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break;
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}
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//configure bit number
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_M);
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break;
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case USART_CONFIG_8E2:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_M);
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break;
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default:
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break;
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}
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//configure stop bits
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7O1:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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reg_reset(regs->CR2, USART_CR2_STOP);
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break;
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N2:
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case USART_CONFIG_8E2:
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case USART_CONFIG_8O2:
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reg_reset(regs->CR2, USART_CR2_STOP);
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reg_write(regs->CR2, USART_CR2_STOP, 2);
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break;
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default:
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break;
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}
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//enable Rx/Tx
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reg_set(regs->CR1, USART_CR1_TE);
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reg_set(regs->CR1, USART_CR1_RE);
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reg_set(regs->CR1, USART_CR1_UE);
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}
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/**
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* Configure the given registers with the given baudrate. Baudrate is dependant
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* on the peripheric's clock and may not be exact due to precision errors (see
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* table 192 in documentation)
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*/
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate)
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{
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uint32_t mantissa = clock / (baudrate * 16);
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uint32_t factor = clock / baudrate;
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volatile uint32_t divider = factor - (mantissa * 16);
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reg_reset(regs->BRR, USART_BRR_DIV_Mantissa);
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reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF);
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reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
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reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
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}
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//--ISRs------------------------------------------------------------------------
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void hdr_usart1(void)
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{
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//disable the interrupt. It will be reenabled on a write if needed
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nvic_clear_pending(NVIC_IRQ_USART1);
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nvic_disable(NVIC_IRQ_USART1);
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reg_reset(usart1->CR1, USART_CR1_TXEIE);
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reg_set(usart1->CR3, USART_CR3_DMAT);
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dma_mbuf_refresh(&usart1_tx_buffer);
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}
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void hdr_usart2(void)
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{
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//disable the interrupt. It will be reenabled on a write if needed
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nvic_clear_pending(NVIC_IRQ_USART2);
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nvic_disable(NVIC_IRQ_USART2);
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reg_reset(usart2->CR1, USART_CR1_TXEIE);
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reg_set(usart2->CR3, USART_CR3_DMAT);
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dma_mbuf_refresh(&usart2_tx_buffer);
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}
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void hdr_usart3(void)
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{
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//disable the interrupt. It will be reenabled on a write if needed
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nvic_clear_pending(NVIC_IRQ_USART3);
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nvic_disable(NVIC_IRQ_USART3);
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reg_reset(usart3->CR1, USART_CR1_TXEIE);
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reg_set(usart3->CR3, USART_CR3_DMAT);
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dma_mbuf_refresh(&usart3_tx_buffer);
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}
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