263 lines
6.1 KiB
C
263 lines
6.1 KiB
C
/** @file usart.c
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* Module handling Universal Synchronous/Asynchronous Receiver/Transmitter
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*
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* The module provides functions to configure the usarts and read/write from/to
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* it
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*/
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//--includes--------------------------------------------------------------------
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#include "usart.h"
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#include "usart_regs.h"
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#include "reg.h"
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#include "rcc.h"
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#include "dma.h"
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#include "stddef.h"
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//--local definitions-----------------------------------------------------------
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static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS;
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static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS;
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static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS;
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static void configure_usart(volatile struct USART* regs,
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enum UsartConfig config);
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate);
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static uint32_t periph_regs(enum UsartPeriph periph,
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volatile struct USART** regs);
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static uint32_t read_from_buffer(volatile uint8_t* buffer,
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enum DmaChannel channel, uint8_t* byte);
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static void usart1_rx_callback(enum DmaIRQSource src);
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//--local variables-------------------------------------------------------------
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static volatile uint8_t* usart1_rx_buffer;
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//--public functions------------------------------------------------------------
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void usart_configure(enum UsartPeriph periph, enum UsartConfig config,
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uint32_t baudrate)
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{
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struct RccClocks clocks;
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rcc_get_clocks(&clocks);
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switch (periph) {
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case USART_PERIPH_1:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART);
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configure_baudrate(usart1, clocks.apb2_freq, baudrate);
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configure_usart(usart1, config);
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break;
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case USART_PERIPH_2:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE);
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configure_baudrate(usart2, clocks.apb1_freq, baudrate);
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configure_usart(usart2, config);
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break;
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case USART_PERIPH_3:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE);
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configure_baudrate(usart3, clocks.apb1_freq, baudrate);
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configure_usart(usart3, config);
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break;
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default:
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break;
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}
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}
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uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
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{
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volatile struct USART* regs;
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if (periph_regs(periph, ®s)) {
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return 1;
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}
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if (regs->SR.TXE) {
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reg_write(regs->DR, USART_DR_DR, byte);
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return 0;
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} else {
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return 1;
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}
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}
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uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte)
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{
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volatile struct USART* regs;
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volatile uint8_t* buffer;
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enum DmaChannel dma_channel;
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switch (periph) {
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case USART_PERIPH_1:
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regs = usart1;
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buffer = usart1_rx_buffer;
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dma_channel = DMA_CHANNEL_5;
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break;
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case USART_PERIPH_2:
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case USART_PERIPH_3:
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default:
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return 1;
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break;
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}
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if (buffer) {
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return read_from_buffer(buffer, dma_channel, byte);
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} else {
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if (regs->SR.RXNE) {
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*byte = regs->DR.DR;
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return 0;
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} else {
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return 1;
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}
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}
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}
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void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer,
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uint16_t size)
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{
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switch (periph) {
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case USART_PERIPH_1:
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dma_configure(DMA_PERIPH_1, DMA_CHANNEL_5,
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DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH
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| DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM
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| DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS
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| DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer,
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size, usart1_rx_callback);
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usart1_rx_buffer = buffer;
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reg_set(usart1->CR3, USART_CR3_DMAR);
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break;
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case USART_PERIPH_2:
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break;
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case USART_PERIPH_3:
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break;
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}
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}
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//--local functions-------------------------------------------------------------
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static void configure_usart(volatile struct USART* regs, enum UsartConfig config)
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{
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//configure parity
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_8E2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_reset(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_set(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_PCE);
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break;
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default:
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break;
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}
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//configure bit number
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_M);
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break;
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case USART_CONFIG_8E2:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_M);
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break;
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default:
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break;
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}
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//configure stop bits
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7O1:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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reg_reset(regs->CR2, USART_CR2_STOP);
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break;
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N2:
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case USART_CONFIG_8E2:
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case USART_CONFIG_8O2:
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reg_reset(regs->CR2, USART_CR2_STOP);
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reg_write(regs->CR2, USART_CR2_STOP, 2);
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break;
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default:
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break;
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}
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//enable Rx/Tx
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reg_set(regs->CR1, USART_CR1_TE);
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reg_set(regs->CR1, USART_CR1_RE);
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reg_set(regs->CR1, USART_CR1_UE);
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}
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate)
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{
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uint32_t mantissa = clock / (baudrate * 16);
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uint32_t factor = clock / baudrate;
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volatile uint32_t divider = factor - (mantissa * 16);
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reg_reset(regs->BRR, USART_BRR_DIV_Mantissa);
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reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF);
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reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
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reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
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}
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static uint32_t periph_regs(enum UsartPeriph periph, volatile struct USART** regs)
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{
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switch (periph) {
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case USART_PERIPH_1:
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*regs = usart1;
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break;
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case USART_PERIPH_2:
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*regs = usart2;
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break;
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case USART_PERIPH_3:
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*regs = usart3;
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break;
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default:
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return 1;
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break;
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}
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return 0;
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}
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static uint32_t read_from_buffer(volatile uint8_t* buffer,
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enum DmaChannel channel, uint8_t* byte)
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{
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}
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//--callbacks-------------------------------------------------------------------
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static void usart1_rx_callback(enum DmaIRQSource src)
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{
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}
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