Steins7
507f1e6863
RCC's BCDR register has been moved to the BKP module since it is part of the backup circuit and thus also aboeys some restrictions access-wise
126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
/** @file bkp.c
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* Module handling the Backup (BKP) domain functionalities.
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*
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*/
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//--includes--------------------------------------------------------------------
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#include "bkp.h"
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#include "bkp_regs.h"
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#include "rcc.h"
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#include "nvic.h"
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//--local definitions-----------------------------------------------------------
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uint32_t compute_prescaler(uint32_t period_ms, enum BkpRtcClockSrc clock_src);
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//--local variables-------------------------------------------------------------
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static volatile struct BKP* bkp_regs = (struct BKP*)BKP_BASE_ADDRESS;
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static volatile struct RCC* rcc_regs = (struct RCC*)RCC_BASE_ADDRESS;
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static volatile struct RTC* rtc_regs = (struct RTC*)RTC_BASE_ADDRESS;
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static BkpRtcCallback rtc_callback;
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//--public functions------------------------------------------------------------
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void bkp_configure_rtc(uint32_t period_ms, enum BkpRtcClockSrc clock_src,
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enum BkpRtcIrq irq_mask, uint32_t alarm_tick, BkpRtcCallback callback)
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{
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rcc_enable(RCC_AHB_NONE, RCC_APB1_BKP, RCC_APB2_NONE);
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//start RTC
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rcc_regs->BDCR.RTCSEL = clock_src + 1;
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rcc_regs->BDCR.RTCEN = 1;
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//compute prescaler
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uint32_t prescaler = compute_prescaler(period_ms, clock_src);
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//wait for registers to synchronize
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rtc_regs->CRL.RSF = 0;
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while (rtc_regs->CRL.RSF != 1) {}
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//wait for last operation to finish
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while (rtc_regs->CRL.RTOFF != 1) {}
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//enable core configuration
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rtc_regs->CRL.CNF = 1;
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//configure core registers
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rtc_regs->PRLH.PRL = prescaler >> 16;
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rtc_regs->PRLL.PRL = prescaler;
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rtc_regs->ALRH.RTC_ALR = alarm_tick >> 16;
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rtc_regs->ALRL.RTC_ALR = alarm_tick;
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//apply irq config
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rtc_regs->CRH.word |= irq_mask & 0x7;
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//disable/apply core configuration
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rtc_regs->CRL.CNF = 0;
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//wait for last operation to finish
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while (rtc_regs->CRL.RTOFF != 1) {}
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if (callback) {
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rtc_callback = callback;
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nvic_enable(NVIC_IRQ_RTC);
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}
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}
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uint32_t bkp_read_rtc(void)
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{
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//wait for core registers to be synchronized, immediate most of the time
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while (rtc_regs->CRL.RSF != 1) {}
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uint32_t time = rtc_regs->CNTH.RTC_CNT << 16;
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time |= rtc_regs->CNTL.RTC_CNT << 0;
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return time;
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}
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void bkp_reset(void)
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{
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rcc_regs->BDCR.BDRST = 1;
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rcc_regs->BDCR.BDRST = 0;
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}
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//--local functions-------------------------------------------------------------
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uint32_t compute_prescaler(uint32_t period_ms, enum BkpRtcClockSrc clock_src)
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{
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uint32_t prescaler;
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switch (clock_src) {
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case BKP_RTC_CLOCK_SRC_LSE:
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prescaler = 32768000; //32.768kHz
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break;
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case BKP_RTC_CLOCK_SRC_LSI:
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prescaler = 40000000; //40khz
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break;
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case BKP_RTC_CLOCK_SRC_HSE:
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prescaler = 62500000; //8Mhz / 128
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break;
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default:
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return 0;
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}
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return prescaler / period_ms;
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}
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//--ISRs------------------------------------------------------------------------
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void hdr_rtc(void)
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{
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nvic_clear_pending(NVIC_IRQ_RTC);
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//copy and clear and pass along src flags
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enum BkpRtcIrq src = rtc_regs->CRL.word & 0x7;
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rtc_regs->CRL.word &= ~(0x7);
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rtc_callback(src);
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}
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