stm32f1xx_HBL/drv/usart.c

/** @file usart.c
 * Module handling Universal Synchronous/Asynchronous Receiver/Transmitter
 *
 * The module provides functions to configure the usarts and read/write from/to
 * it
 */

//--includes--------------------------------------------------------------------

#include "usart.h"
#include "nvic.h"
#include "usart_regs.h"
#include "reg.h"

#include "rcc.h"
#include "dma.h"

#include "stddef.h"


//--local definitions-----------------------------------------------------------

static void configure_usart(volatile struct USART* regs,
		enum UsartConfig config);
static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
		uint32_t baudrate);

#define DMA_CONFIG (DMA_CONFIG_PSIZE_8BITS)


//--local variables-------------------------------------------------------------

static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS;
static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS;
static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS;

static const struct DmaParam usart1_rx_param = {
	(void*)&usart1->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_5,
};

static const struct DmaParam usart2_rx_param = {
	(void*)&usart2->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_6,
};

static const struct DmaParam usart3_rx_param = {
	(void*)&usart3->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_3,
};

static const struct DmaParam usart1_tx_param = {
	(void*)&usart1->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_4,
};

static const struct DmaParam usart2_tx_param = {
	(void*)&usart2->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_7,
};

static const struct DmaParam usart3_tx_param = {
	(void*)&usart3->DR,
	DMA_CONFIG,
	DMA_PERIPH_1,
	DMA_CHANNEL_2,
};


//--public functions------------------------------------------------------------

void usart_configure(enum UsartPeriph periph, enum UsartConfig config,
		uint32_t baudrate)
{
	struct RccClocks clocks;
	rcc_get_clocks(&clocks);

	switch (periph) {
		case USART_PERIPH_1:
			rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART);
			configure_baudrate(usart1, clocks.apb2_freq, baudrate);
			configure_usart(usart1, config);
			break;
		case USART_PERIPH_2:
			rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE);
			configure_baudrate(usart2, clocks.apb1_freq, baudrate);
			configure_usart(usart2, config);
			break;
		case USART_PERIPH_3:
			rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE);
			configure_baudrate(usart3, clocks.apb1_freq, baudrate);
			configure_usart(usart3, config);
			break;
		default:
			break;
	}
}

uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
{
	volatile struct USART* regs;

	switch (periph) {
		case USART_PERIPH_1:
			regs = usart1;
			break;
		case USART_PERIPH_2:
			regs = usart2;
			break;
		case USART_PERIPH_3:
			regs = usart3;
			break;
		default:
			return 1;
			break;
	}

	//only write data if the tx register it empty, give up otherwise
	if (regs->SR.TXE) {
		reg_write(regs->DR, USART_DR_DR, byte);
		return 0;
	} else {
		return 1;
	}
}

uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte)
{
	volatile struct USART* regs;

	switch (periph) {
		case USART_PERIPH_1:
			regs = usart1;
			break;
		case USART_PERIPH_2:
			regs = usart2;
			break;
		case USART_PERIPH_3:
			regs = usart3;
			break;
		default:
			return 1;
			break;
	}

	if (regs->SR.RXNE) {
		*byte = regs->DR.DR;
		return 0;
	} else {
		return 1;
	}
}

const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph)
{
	const struct DmaParam* param;

	switch (periph) {
		case USART_PERIPH_1:
			param = &usart1_rx_param;
			reg_set(usart1->CR3, USART_CR3_DMAR);
			break;
		case USART_PERIPH_2:
			param = &usart2_rx_param;
			reg_set(usart2->CR3, USART_CR3_DMAR);
			break;
		case USART_PERIPH_3:
			param = &usart3_rx_param;
			reg_set(usart3->CR3, USART_CR3_DMAR);
			break;
		default:
			return nullptr;
	}

	return param;
}

const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph)
{
	const struct DmaParam* param;

	switch (periph) {
		case USART_PERIPH_1:
			param = &usart1_tx_param;
			reg_set(usart1->CR3, USART_CR3_DMAT);
			break;
		case USART_PERIPH_2:
			param = &usart2_tx_param;
			reg_set(usart2->CR3, USART_CR3_DMAT);
			break;
		case USART_PERIPH_3:
			param = &usart3_tx_param;
			reg_set(usart3->CR3, USART_CR3_DMAT);
			break;
		default:
			return nullptr;
	}

	return param;
}


//--local functions-------------------------------------------------------------

/**
 * Apply the given configuration to the given registers. Generic version of
 * usart_configure()
 */
static void configure_usart(volatile struct USART* regs,
		enum UsartConfig config)
{
	//configure parity
	switch (config)
	{
		case USART_CONFIG_7E1:
		case USART_CONFIG_8E1:
		case USART_CONFIG_7E2:
		case USART_CONFIG_8E2:
			reg_set(regs->CR1, USART_CR1_PCE);
			reg_reset(regs->CR1, USART_CR1_PS);
			break;
		case USART_CONFIG_7O1:
		case USART_CONFIG_7O2:
		case USART_CONFIG_8O1:
		case USART_CONFIG_8O2:
			reg_set(regs->CR1, USART_CR1_PCE);
			reg_set(regs->CR1, USART_CR1_PS);
			break;
		case USART_CONFIG_8N1:
		case USART_CONFIG_8N2:
			reg_reset(regs->CR1, USART_CR1_PCE);
			break;
		default:
			break;
	}

	//configure bit number
	switch (config)
	{
		case USART_CONFIG_7E1:
		case USART_CONFIG_7E2:
		case USART_CONFIG_7O1:
		case USART_CONFIG_7O2:
		case USART_CONFIG_8N1:
		case USART_CONFIG_8N2:
			reg_reset(regs->CR1, USART_CR1_M);
			break;
		case USART_CONFIG_8E2:
		case USART_CONFIG_8E1:
		case USART_CONFIG_8O1:
		case USART_CONFIG_8O2:
			reg_set(regs->CR1, USART_CR1_M);
			break;
		default:
			break;
	}

	//configure stop bits
	switch (config)
	{
		case USART_CONFIG_7E1:
		case USART_CONFIG_7O1:
		case USART_CONFIG_8N1:
		case USART_CONFIG_8E1:
		case USART_CONFIG_8O1:
			reg_reset(regs->CR2, USART_CR2_STOP);
			break;
		case USART_CONFIG_7E2:
		case USART_CONFIG_7O2:
		case USART_CONFIG_8N2:
		case USART_CONFIG_8E2:
		case USART_CONFIG_8O2:
			reg_reset(regs->CR2, USART_CR2_STOP);
			reg_write(regs->CR2, USART_CR2_STOP, 2);
			break;
		default:
			break;
	}

	//enable Rx/Tx
	reg_set(regs->CR1, USART_CR1_TE);
	reg_set(regs->CR1, USART_CR1_RE);
	reg_set(regs->CR1, USART_CR1_UE);
}

/**
 * Configure the given registers with the given baudrate. Baudrate is dependant
 * on the peripheric's clock and may not be exact due to precision errors (see
 * table 192 in documentation)
 */
static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
		uint32_t baudrate)
{
	uint32_t mantissa = clock / (baudrate * 16);
	uint32_t factor = clock / baudrate;
	volatile uint32_t divider = factor - (mantissa * 16);

	reg_reset(regs->BRR, USART_BRR_DIV_Mantissa);
	reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF);
	reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
	reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
}