Steins7
5e4d87474a
A while back, macros had to be put in place to avoid letting the compiler directly use the bitfields. This was necessary because the compiler used strb instruction which only write bytes. On the AHB bus, byte writes are transformed into word writes by repeating the byte, which caused mayhem in the registers. After a lot of research, turns out the packed attribute stops the compiler from does optimal (word) writes and isn't needed anyway. Removing them fixes the issue
138 lines
2.5 KiB
C
138 lines
2.5 KiB
C
/** @file dma_regs.h
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* Module defining the DMA registers.
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*
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* Mainly made to be used by the dma module. It is recommanded to go through
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* the functions provided by that module instead of directly using the registers
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* defined here.
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*/
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#ifndef _DMA_REGS_H_
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#define _DMA_REGS_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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//--type definitions------------------------------------------------------------
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#define DMA1_BASE_ADDRESS 0x40020000
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#define DMA2_BASE_ADDRESS 0x40020400
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union DMA_ISR {
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struct {
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uint32_t GIF1:1;
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uint32_t TCIF1:1;
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uint32_t HTIF1:1;
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uint32_t TEIF1:1;
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uint32_t GIF2:1;
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uint32_t TCIF2:1;
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uint32_t HTIF2:1;
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uint32_t TEIF2:1;
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uint32_t GIF3:1;
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uint32_t TCIF3:1;
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uint32_t HTIF3:1;
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uint32_t TEIF3:1;
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uint32_t GIF4:1;
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uint32_t TCIF4:1;
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uint32_t HTIF4:1;
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uint32_t TEIF4:1;
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uint32_t GIF5:1;
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uint32_t TCIF5:1;
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uint32_t HTIF5:1;
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uint32_t TEIF5:1;
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uint32_t GIF6:1;
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uint32_t TCIF6:1;
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uint32_t HTIF6:1;
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uint32_t TEIF6:1;
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uint32_t GIF7:1;
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uint32_t TCIF7:1;
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uint32_t HTIF7:1;
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uint32_t TEIF7:1;
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uint32_t reserved1:4;
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};
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uint32_t word;
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};
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union DMA_IFCR {
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struct {
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uint32_t CGIF1:1;
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uint32_t CTCIF1:1;
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uint32_t CHTIF1:1;
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uint32_t CTEIF1:1;
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uint32_t CGIF2:1;
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uint32_t CTCIF2:1;
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uint32_t CHTIF2:1;
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uint32_t CTEIF2:1;
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uint32_t CGIF3:1;
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uint32_t CTCIF3:1;
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uint32_t CHTIF3:1;
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uint32_t CTEIF3:1;
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uint32_t CGIF4:1;
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uint32_t CTCIF4:1;
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uint32_t CHTIF4:1;
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uint32_t CTEIF4:1;
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uint32_t CGIF5:1;
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uint32_t CTCIF5:1;
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uint32_t CHTIF5:1;
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uint32_t CTEIF5:1;
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uint32_t CGIF6:1;
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uint32_t CTCIF6:1;
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uint32_t CHTIF6:1;
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uint32_t CTEIF6:1;
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uint32_t CGIF7:1;
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uint32_t CTCIF7:1;
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uint32_t CHTIF7:1;
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uint32_t CTEIF7:1;
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uint32_t reserved1:4;
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};
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uint32_t word;
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};
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union DMA_CCR {
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struct {
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uint32_t EN:1;
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uint32_t TCIE:1;
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uint32_t HTIE:1;
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uint32_t TEIE:1;
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uint32_t DIR:1;
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uint32_t CIRC:1;
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uint32_t PINC:1;
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uint32_t MINC:1;
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uint32_t PSIZE:2;
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uint32_t MSIZE:2;
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uint32_t PL:2;
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uint32_t MEM2MEM:1;
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uint32_t reserved1:17;
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};
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uint32_t word;
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};
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union DMA_CNDTR {
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struct {
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uint32_t NDT:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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struct DMA_CHANNEL {
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union DMA_CCR CCR;
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union DMA_CNDTR CNDTR;
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uint32_t CPAR;
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uint32_t CMAR;
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uint32_t reserved1;
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};
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struct DMA {
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union DMA_ISR ISR;
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union DMA_IFCR IFCR;
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struct DMA_CHANNEL CHANNELS[7];
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};
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//--functions-------------------------------------------------------------------
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#endif //_DMA_REGS_H_
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