489 lines
13 KiB
C
489 lines
13 KiB
C
/** @file usart.c
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* Module handling Universal Synchronous/Asynchronous Receiver/Transmitter
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*
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* The module provides functions to configure the usarts and read/write from/to
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* it
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*/
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//--includes--------------------------------------------------------------------
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#include "usart.h"
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#include "nvic.h"
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#include "usart_regs.h"
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#include "reg.h"
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#include "rcc.h"
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#include "dma.h"
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#include "stddef.h"
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//--local definitions-----------------------------------------------------------
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struct CircularBuffer {
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volatile uint8_t* buffer; //the buffer to use as a circular buffer
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uint16_t size; //the size of the buffer
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uint16_t begin; //pointer to the current begin of the buffer
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bool dmaLooped; //whether the DMA looped or not (buffer overflow)
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};
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struct FragmentedBuffer {
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uint8_t** buffers; //list of buffers to write to
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uint16_t buffer_size; //size of a single buffer
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uint16_t byte_index; //index of the current byte in the current buffer
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uint8_t buffer_nb; //total number of buffers
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uint8_t free_buffer_nb; //number of buffers not currently used
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uint8_t buffer_index; //index of the current buffer
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uint8_t dma_buffer_index; //index of the DMA's current buffer
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};
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static void configure_usart(volatile struct USART* regs,
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enum UsartConfig config);
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate);
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static uint32_t write_byte(volatile struct USART* regs, uint8_t byte);
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static uint32_t write_to_buffer(volatile struct USART* regs,
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volatile struct FragmentedBuffer *buffer, enum DmaChannel channel,
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uint8_t byte);
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static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer,
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enum DmaChannel channel, uint8_t* byte);
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static void usart1_tx_callback(enum DmaIRQSource src);
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static void usart1_rx_callback(enum DmaIRQSource src);
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//--local variables-------------------------------------------------------------
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static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS;
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static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS;
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static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS;
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static volatile struct CircularBuffer usart1_rx_buffer;
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static volatile struct FragmentedBuffer usart1_tx_buffer;
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//--public functions------------------------------------------------------------
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void usart_configure(enum UsartPeriph periph, enum UsartConfig config,
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uint32_t baudrate)
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{
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struct RccClocks clocks;
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rcc_get_clocks(&clocks);
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switch (periph) {
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case USART_PERIPH_1:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART);
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configure_baudrate(usart1, clocks.apb2_freq, baudrate);
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configure_usart(usart1, config);
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usart1_tx_buffer.buffers = NULL;
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break;
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case USART_PERIPH_2:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE);
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configure_baudrate(usart2, clocks.apb1_freq, baudrate);
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configure_usart(usart2, config);
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break;
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case USART_PERIPH_3:
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rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE);
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configure_baudrate(usart3, clocks.apb1_freq, baudrate);
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configure_usart(usart3, config);
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break;
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default:
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break;
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}
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}
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uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
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{
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volatile struct USART* regs;
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volatile struct FragmentedBuffer* buffer;
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enum DmaChannel dma_channel;
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switch (periph) {
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case USART_PERIPH_1:
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regs = usart1;
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buffer = &usart1_tx_buffer;
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dma_channel = DMA_CHANNEL_4;
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break;
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case USART_PERIPH_2:
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case USART_PERIPH_3:
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default:
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return 1;
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break;
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}
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if (buffer->buffers) {
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return write_to_buffer(regs, buffer, dma_channel, byte);
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} else {
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while (regs->SR.TXE == 0) {}
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reg_write(regs->DR, USART_DR_DR, byte);
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return 0;
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}
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}
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uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte)
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{
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volatile struct USART* regs;
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volatile struct CircularBuffer* buffer;
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enum DmaChannel dma_channel;
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switch (periph) {
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case USART_PERIPH_1:
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regs = usart1;
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buffer = &usart1_rx_buffer;
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dma_channel = DMA_CHANNEL_5;
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break;
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case USART_PERIPH_2:
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case USART_PERIPH_3:
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default:
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return 1;
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break;
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}
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if (buffer->buffer) {
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return read_from_buffer(buffer, dma_channel, byte);
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} else {
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if (regs->SR.RXNE) {
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*byte = regs->DR.DR;
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return 0;
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} else {
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return 1;
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}
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}
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}
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void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers,
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uint16_t buffer_size, uint8_t buffer_nb)
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{
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volatile struct FragmentedBuffer* buffer = NULL;
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switch (periph) {
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case USART_PERIPH_1:
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buffer = &usart1_tx_buffer;
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break;
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case USART_PERIPH_2:
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break;
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case USART_PERIPH_3:
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break;
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}
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#warning "check for null ptr"
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buffer->buffers = buffers;
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buffer->buffer_size = buffer_size;
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buffer->byte_index = 0;
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buffer->buffer_nb = buffer_nb;
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buffer->free_buffer_nb = buffer_nb - 1;
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buffer->buffer_index = 0;
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buffer->dma_buffer_index = 0;
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}
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void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer,
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uint16_t size)
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{
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switch (periph) {
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case USART_PERIPH_1:
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dma_configure(DMA_PERIPH_1, DMA_CHANNEL_5,
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DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_PERIPH
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| DMA_CONFIG_CIRCULAR | DMA_CONFIG_INC_MEM
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| DMA_CONFIG_PSIZE_8BITS | DMA_CONFIG_MSIZE_8BITS
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| DMA_CONFIG_PRIO_LOW, (void*)&usart1->DR, buffer,
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size, usart1_rx_callback);
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usart1_rx_buffer.buffer = buffer;
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usart1_rx_buffer.size = size;
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usart1_rx_buffer.begin = 0;
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usart1_rx_buffer.dmaLooped = false;
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reg_set(usart1->CR3, USART_CR3_DMAR);
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break;
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case USART_PERIPH_2:
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break;
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case USART_PERIPH_3:
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break;
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}
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}
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//--local functions-------------------------------------------------------------
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/**
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* Apply the given configuration to the given registers. Generic version of
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* usart_configure()
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*/
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static void configure_usart(volatile struct USART* regs,
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enum UsartConfig config)
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{
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//configure parity
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_8E2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_reset(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_PCE);
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reg_set(regs->CR1, USART_CR1_PS);
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break;
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_PCE);
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break;
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default:
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break;
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}
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//configure bit number
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O1:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8N2:
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reg_reset(regs->CR1, USART_CR1_M);
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break;
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case USART_CONFIG_8E2:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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case USART_CONFIG_8O2:
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reg_set(regs->CR1, USART_CR1_M);
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break;
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default:
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break;
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}
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//configure stop bits
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switch (config)
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{
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case USART_CONFIG_7E1:
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case USART_CONFIG_7O1:
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case USART_CONFIG_8N1:
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case USART_CONFIG_8E1:
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case USART_CONFIG_8O1:
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reg_reset(regs->CR2, USART_CR2_STOP);
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break;
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case USART_CONFIG_7E2:
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case USART_CONFIG_7O2:
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case USART_CONFIG_8N2:
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case USART_CONFIG_8E2:
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case USART_CONFIG_8O2:
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reg_reset(regs->CR2, USART_CR2_STOP);
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reg_write(regs->CR2, USART_CR2_STOP, 2);
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break;
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default:
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break;
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}
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//enable Rx/Tx
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reg_set(regs->CR1, USART_CR1_TE);
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reg_set(regs->CR1, USART_CR1_RE);
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reg_set(regs->CR1, USART_CR1_UE);
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}
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/**
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* Configure the given registers with the given baudrate. Baudrate is dependant
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* on the peripheric's clock and may not be exact due to precision errors (see
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* table 192 in documentation)
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*/
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static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
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uint32_t baudrate)
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{
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uint32_t mantissa = clock / (baudrate * 16);
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uint32_t factor = clock / baudrate;
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volatile uint32_t divider = factor - (mantissa * 16);
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reg_reset(regs->BRR, USART_BRR_DIV_Mantissa);
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reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF);
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reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
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reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
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}
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/**
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* Non-blocking write to the given USART. Will return 0 if the write was
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* successfull, 1 otherwise. If the write is successfull, the tranfer complete
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* IRQ is enabled and the DMA disabled
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*/
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static uint32_t write_byte(volatile struct USART* regs, uint8_t byte)
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{
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//write if TX register empty
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if (regs->SR.TXE) {
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reg_write(regs->DR, USART_DR_DR, byte);
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//enable IRQ, disable DMA
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reg_reset(regs->CR3, USART_CR3_DMAT);
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reg_set(regs->CR1, USART_CR1_TXEIE);
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nvic_enable(NVIC_IRQ_USART1);
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return 0;
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} else {
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return 1;
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}
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}
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/**
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* Writes the given byte to the given UART, using a FragmentedBuffer and a DMA
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* to bufferize the write if the peripheral is already busy.
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*/
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static uint32_t write_to_buffer(volatile struct USART *regs,
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volatile struct FragmentedBuffer *buffer, enum DmaChannel channel,
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uint8_t byte)
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{
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//if the tx register is empty, there is no need to go through the dma
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if (!write_byte(regs, byte)) {
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return 0;
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}
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dma_enter_critical(DMA_PERIPH_1, channel);
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//if the current buffer is full, we need to switch it with an empty one
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if (buffer->byte_index >= buffer->buffer_size) {
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//if all buffer full, simply wait for the DMA to empty one
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dma_exit_critical(DMA_PERIPH_1, channel);
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while (buffer->free_buffer_nb == 0) {}
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dma_enter_critical(DMA_PERIPH_1, channel);
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++buffer->buffer_index;
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if (buffer->buffer_index >= buffer->buffer_nb) {
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buffer->buffer_index = 0;
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}
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--buffer->free_buffer_nb;
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buffer->byte_index = 0;
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} else {
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dma_enter_critical(DMA_PERIPH_1, channel);
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}
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//write the byte
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buffer->buffers[buffer->buffer_index][buffer->byte_index] = byte;
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++buffer->byte_index;
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dma_exit_critical(DMA_PERIPH_1, channel);
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return 0;
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}
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/**
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* Reads the oldest byte from the given CircularBuffer if any. Returns 0 if the
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* read was successfull, 1 otherwise
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*/
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static uint32_t read_from_buffer(volatile struct CircularBuffer* buffer,
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enum DmaChannel channel, uint8_t* byte)
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{
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//retreive the current end of the buffer based on the DMA's progress
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uint16_t end = buffer->size - dma_get_remaining(DMA_PERIPH_1, channel);
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//check for bytes to read and overflow
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if ((end > buffer->begin) && buffer->dmaLooped) {
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//TODO overflow
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buffer->begin = end;
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} else if ((buffer->begin == end) && !buffer->dmaLooped) {
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//TODO no data
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return 1;
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}
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//read the oldest byte and advance the buffer
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*byte = buffer->buffer[buffer->begin];
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++buffer->begin;
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if (buffer->begin >= buffer->size) {
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buffer->begin = 0;
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buffer->dmaLooped = false;
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}
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return 0;
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}
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//--callbacks-------------------------------------------------------------------
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/**
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* Callback called on DMA TX tranfert's completion. Checks for any remaining
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* data to send. If any, starts a new transfer, else stop the DMA
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*/
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static void usart1_tx_callback(enum DmaIRQSource src)
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{
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(void)src; //only transfer complete expected
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volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer;
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//increment DMA's buffer since the last once has already been sent
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++buffer->dma_buffer_index;
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if (buffer->dma_buffer_index >= buffer->buffer_nb) {
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buffer->dma_buffer_index = 0;
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}
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++buffer->free_buffer_nb;
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//no more data to send, stop here
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if (buffer->dma_buffer_index == buffer->buffer_index
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&& buffer->byte_index == 0) {
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return;
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}
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//else start a new transfer
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dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4,
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DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM
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| DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS
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| DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW,
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(void*)&usart1->DR,
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(void*)buffer->buffers[buffer->dma_buffer_index],
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buffer->byte_index,
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usart1_tx_callback);
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//if the newly transfering buffer was being written to, switch the current
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//buffer. Since we just ended a transfer, the next buffer should be empty
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if (buffer->dma_buffer_index == buffer->buffer_index)
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{
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++buffer->buffer_index;
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if (buffer->buffer_index >= buffer->buffer_nb) {
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buffer->buffer_index = 0;
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}
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buffer->byte_index = 0;
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}
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}
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/**
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* Callback called on DMA RX tranfert's completion. Sets a flag needed to
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* properly handle the circular buffer
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*/
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static void usart1_rx_callback(enum DmaIRQSource src)
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{
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(void)src; //only transfer complete expected
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usart1_rx_buffer.dmaLooped = true;
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}
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//--ISRs------------------------------------------------------------------------
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void hdr_usart1(void)
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{
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nvic_clear_pending(NVIC_IRQ_USART1);
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nvic_disable(NVIC_IRQ_USART1);
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reg_reset(usart1->CR1, USART_CR1_TXEIE);
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reg_set(usart1->CR3, USART_CR3_DMAT);
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volatile struct FragmentedBuffer* buffer = &usart1_tx_buffer;
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//no more data to send, stop here
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if (buffer->dma_buffer_index == buffer->buffer_index
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&& buffer->byte_index == 0) {
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return;
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}
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dma_configure(DMA_PERIPH_1, DMA_CHANNEL_4,
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DMA_CONFIG_IRQ_COMPLETE | DMA_CONFIG_FROM_MEM
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| DMA_CONFIG_INC_MEM | DMA_CONFIG_PSIZE_8BITS
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| DMA_CONFIG_MSIZE_8BITS | DMA_CONFIG_PRIO_LOW,
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(void*)&usart1->DR,
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(void*)buffer->buffers[buffer->dma_buffer_index],
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buffer->byte_index,
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usart1_tx_callback);
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if (buffer->dma_buffer_index == buffer->buffer_index)
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{
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++buffer->buffer_index;
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if (buffer->buffer_index >= buffer->buffer_nb) {
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buffer->buffer_index = 0;
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}
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buffer->byte_index = 0;
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}
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}
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