157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/** @file rcc.h
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* Module handling Reset and Clocks Control (RCC).
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*
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* The module provides functions to configure clocks according to presets as
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* well as to enable/disable/reset peripherals.
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*/
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#ifndef _RCC_H_
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#define _RCC_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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//--type definitions------------------------------------------------------------
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/**
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* Available clock configuration presets
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*/
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enum RccPreset {
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RCC_PRESET_DEFAULT, //sane values, identical to reset config
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RCC_PRESET_SPEED, //highest clocks, uses 8MHz HSE if available
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};
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/**
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* Available peripherals on the AHB bus. Note that some of these peripherals
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* may not be availables on all chips
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*/
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enum RccAhb {
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RCC_AHB_NONE = 0,
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RCC_AHB_DMA1 = (0x1 << 0),
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RCC_AHB_DMA2 = (0x1 << 1),
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RCC_AHB_SRAM = (0x1 << 2),
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RCC_AHB_FLITF = (0x1 << 4),
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RCC_AHB_CRC = (0x1 << 6),
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RCC_AHB_FSMC = (0x1 << 8),
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RCC_AHB_SDIO = (0x1 << 10),
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};
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/**
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* Available peripherals on the APB1 bus. Note that some of these peripherals
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* may not be availables on all chips
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*/
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enum RccApb1 {
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RCC_APB1_NONE = 0,
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RCC_APB1_TIM2 = (0x1 << 0),
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RCC_APB1_TIM3 = (0x1 << 1),
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RCC_APB1_TIM4 = (0x1 << 2),
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RCC_APB1_TIM5 = (0x1 << 3),
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RCC_APB1_TIM6 = (0x1 << 4),
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RCC_APB1_TIM7 = (0x1 << 5),
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RCC_APB1_TIM12 = (0x1 << 6),
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RCC_APB1_TIM13 = (0x1 << 7),
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RCC_APB1_TIM14 = (0x1 << 8),
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RCC_APB1_WWDG = (0x1 << 11),
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RCC_APB1_SPI2 = (0x1 << 14),
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RCC_APB1_SPI3 = (0x1 << 15),
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RCC_APB1_USART2 = (0x1 << 17),
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RCC_APB1_USART3 = (0x1 << 18),
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RCC_APB1_UART4 = (0x1 << 19),
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RCC_APB1_UART5 = (0x1 << 20),
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RCC_APB1_I2C1 = (0x1 << 21),
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RCC_APB1_I2C2 = (0x1 << 22),
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RCC_APB1_USB = (0x1 << 23),
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RCC_APB1_CAN = (0x1 << 25),
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RCC_APB1_BKP = (0x1 << 27),
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RCC_APB1_PWR = (0x1 << 28),
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RCC_APB1_DAC = (0x1 << 29),
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};
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/**
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* Available peripherals on the APB2 bus. Note that some of these peripherals
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* may not be available on all chips
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*/
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enum RccApb2 {
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RCC_APB2_NONE = 0,
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RCC_APB2_AFIO = (0x1 << 0),
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RCC_APB2_IOPA = (0x1 << 2),
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RCC_APB2_IOPB = (0x1 << 3),
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RCC_APB2_IOPC = (0x1 << 4),
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RCC_APB2_IOPD = (0x1 << 5),
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RCC_APB2_IOPE = (0x1 << 6),
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RCC_APB2_IOPF = (0x1 << 7),
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RCC_APB2_IOPG = (0x1 << 8),
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RCC_APB2_ADC1 = (0x1 << 9),
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RCC_APB2_ADC2 = (0x1 << 10),
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RCC_APB2_TIM1 = (0x1 << 11),
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RCC_APB2_SPI1 = (0x1 << 12),
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RCC_APB2_TIM8 = (0x1 << 13),
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RCC_APB2_USART = (0x1 << 14),
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RCC_APB2_ADC3 = (0x1 << 15),
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RCC_APB2_TIM9 = (0x1 << 19),
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RCC_APB2_TIM10 = (0x1 << 20),
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RCC_APB2_TIM11 = (0x1 << 21),
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};
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enum RccRtcClockSrc {
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RCC_RTC_CLOCK_SRC_NONE = 0x0,
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RCC_RTC_CLOCK_SRC_LSE = 0x1,
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RCC_RTC_CLOCK_SRC_LSI = 0x2,
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RCC_RTC_CLOCK_SRC_HSE = 0x3,
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};
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struct RccClocks {
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uint32_t ahb_freq;
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uint32_t apb1_freq;
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uint32_t apb2_freq;
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uint32_t tim_freq;
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};
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//--functions-------------------------------------------------------------------
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/**
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* Configures the clocks and buses according to the given preset. Peripheral
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* states are kept during the change and additional reconfiguration are
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* handled automatically for peripherals that rely on a clock timings (timers,
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* watchdogs, ...)
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*/
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void rcc_configure(enum RccPreset preset);
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/**
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* Configures the Low Speed Internal (LSI) oscillator for low power
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* applications.
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*/
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void rcc_configure_lsi(bool enable);
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/**
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* Enables peripherals on the different buses. The enums values can used as
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* masks to enable multiple peripherals at the same time. Invalid values will be
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* ignored.
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*/
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void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask);
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/**
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* Disables peripherals on the different buses. The enums values can used as
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* masks to disable multiple peripherals at the same time. Invalid values will
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* be ignored.
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*/
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void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask);
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/**
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* Resets peripherals on the different buses. The enums values can used as
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* masks to reset multiple peripherals at the same time. Invalid values will
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* be ignored.
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*/
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void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask);
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void rcc_get_clocks(struct RccClocks* clocks);
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#endif //_RCC_H_
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