Steins7
ca935a7650
Avoid repitions between comments and code. Additionnal usage information can be added as header comment and additionnal technical information can be added in the source file
167 lines
3.8 KiB
C
167 lines
3.8 KiB
C
/** @file rcc.c
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* Module handling Reset and Clocks Control (RCC).
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*
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* The module provides functions to configure clocks according to presets as
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* well as to enable/disable/reset peripherals.
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*/
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//--includes--------------------------------------------------------------------
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#include "rcc.h"
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#include "rcc_regs.h"
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#include "flash.h"
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//--local definitions-----------------------------------------------------------
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#define APB1_MASK 0x3afec9ff
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#define APB2_MASK 0x0038fffd
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static void apply_default_preset(void);
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static void apply_speed_preset(void);
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//--local variables-------------------------------------------------------------
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static volatile struct RCC* regs = (struct RCC*)RCC_BASE_ADDRESS;
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//--public functions------------------------------------------------------------
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/**
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* Configures the clock sources, PLL, prescalers, etc. All peripherals are
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* disabled prior to any modifications to avoid unwanted side effects.
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*/
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void rcc_configure(enum RccPreset preset)
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{
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//disable all peripherals during clock configuration
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union RCC_APB1ENR apb1_enr = regs->APB1ENR;
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regs->APB1ENR.word = 0x0;
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union RCC_APB2ENR apb2_enr = regs->APB2ENR;
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regs->APB2ENR.word = 0x0;
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switch (preset) {
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case RCC_PRESET_DEFAULT:
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apply_default_preset();
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break;
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case RCC_PRESET_SPEED:
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apply_speed_preset();
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break;
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default:
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break;
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}
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//re-enable peripherals
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regs->APB1ENR = apb1_enr;
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regs->APB2ENR = apb2_enr;
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}
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void rcc_enable_apb1(enum RccApb1 mask)
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{
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regs->APB1ENR.word |= mask & APB1_MASK;
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}
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void rcc_disable_apb1(enum RccApb1 mask)
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{
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regs->APB1ENR.word &= !(mask & APB1_MASK);
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}
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void rcc_reset_apb1(enum RccApb1 mask)
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{
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regs->APB1RSTR.word &= !(mask & APB1_MASK);
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}
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void rcc_enable_apb2(enum RccApb2 mask)
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{
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regs->APB2ENR.word |= mask & APB2_MASK;
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}
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void rcc_disable_apb2(enum RccApb2 mask)
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{
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regs->APB2ENR.word &= !(mask & APB2_MASK);
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}
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void rcc_reset_apb2(enum RccApb2 mask)
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{
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regs->APB2RSTR.word &= !(mask & APB2_MASK);
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}
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//--local functions-------------------------------------------------------------
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/**
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* Apply the default clock preset, using HSI whithout PLL or prescalers. This is
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* similar to the reset configuration. Most buses run at 8Mhz, except ADCs wich
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* run at 4Mhz, and Systick wich only reaches 1Mhz.
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*/
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static void apply_default_preset(void)
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{
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//ensures HSI is enabled
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regs->CR.HSION = 0x1;
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while (regs->CR.HSIRDY != 0x1);
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//set HSI as main clock source and disable prescalers
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regs->CFGR.word &= !0x077fff3;
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//disable all options
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regs->CR.HSITRIM = 0x10;
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regs->CR.HSEON = 0x0;
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regs->CR.HSEBYP = 0x0;
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regs->CR.CCSON = 0x0;
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regs->CR.PLLON = 0x0;
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//disable all interrupts
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regs->CIR.LSIRDYIE = 0x0;
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regs->CIR.LSERDYIE = 0x0;
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regs->CIR.HSIRDYIE = 0x0;
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regs->CIR.HSERDYIE = 0x0;
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regs->CIR.PLLRDYIE = 0x0;
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//reconfigure flash
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flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED);
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}
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/**
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* Apply the speed preset, using HSE with PLL to achieve 72MHz on AHB, APB2 and
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* timer buses. APB1 is limited to its maximum clock of 36Mhz and the ADCs run
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* at 12MHz. Systick runs at 9Mhz.
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*/
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static void apply_speed_preset(void)
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{
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//restore sane values
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apply_default_preset();
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//try enabling HSE, fallback to HSI if HSE fails
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regs->CR.HSEON = 0x1;
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for (uint32_t i=0; i<1000; ++i) {
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__asm__("nop");
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}
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if (regs->CR.HSERDY == 0x1) {
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regs->CFGR.PLLSCR = 0x1;
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} else {
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regs->CR.HSEON = 0;
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}
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//configure PLL, fallback to HSI if PLL fails
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regs->CFGR.PLLMUL = 0x7; //PLL x9
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regs->CR.PLLON = 0x1;
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for (uint32_t i=0; i<1000; ++i) {
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__asm__("nop");
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}
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if (regs->CR.PLLRDY != 0x1) {
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regs->CR.PLLON = 0x0;
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return; //clock low enough, no need for prescalers
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}
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//configure prescalers
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regs->CFGR.PPRE1 = 0x4; // /2
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regs->CFGR.ADCPRE = 0x2; // /6
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//reconfigure flash
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flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED);
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//switch to PLL output
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regs->CFGR.SW = 0x2;
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}
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