blink !

Timers are working and so are GPIOs in output mode
the program contain a basic blink cadenced on a timer IRQ

.gitignore

@@ -0,0 +1,2 @@
+bin
+.gdb_history

Makefile

@@ -0,0 +1,175 @@
+#-----------------------------------------------------------------------------
+# this GNU-makefile relies on the GCC toolchain
+
+# --- control global project settings
+# RELEASE=1 -> enable optimisation, then disable debug
+# RELEASE=0 -> disbale optimisation, then enable debug
+RELEASE=0
+
+# --- project architecture
+# program name
+EXE_PREFIX=main
+# project folders, This Makefile should be in the same folder as the SRC folder
+SRC=src
+BIN=bin
+LIB=lib
+OBJ=${BIN}/obj
+DEP=${BIN}/dep
+# code folders, in the SRC folder
+SUBFOLDERS=drivers target
+# Define linker script file here
+LDSCRIPT=${SRC}/target/STM32F103XB.ld
+
+# --- advanced config
+# List all user C define here
+UDEFS=
+# Define ASM defines here
+UADEFS=
+# List all user directories here
+UINCDIR=.
+# List the user directory to look for the libraries here
+ULIBDIR=
+
+# --- toolchain configuration
+TARGET=arm-none-eabi-
+CC=$(TARGET)gcc
+OBJCOPY=$(TARGET)objcopy
+AS=$(TARGET)gcc -x assembler-with-cpp -c
+SIZE=$(TARGET)size
+OBJDUMP=$(TARGET)objdump
+
+# --- hardware settings
+ARCH=armv7-m
+FLOAT-ABI=soft
+CPU=cortex-m3
+CPUFLAGS=-mthumb
+FPU=fpv4-sp-d16
+
+##-----------------------------------------------------------------------------
+# --- makefile pre-incantation
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS=-march=$(ARCH) -mfloat-abi=$(FLOAT-ABI) -mcpu=$(CPU) -mfpu=$(FPU) $(CPUFLAGS)
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS=-D__ASSEMBLY__
+# List all default directories to look for include files here
+DINCDIR=
+# List the default directory to look for the libraries here
+DLIBDIR=
+# List all default libraries here
+DLIBS=
+
+# --- deduce file names
+MAIN_C_FILES=${wildcard ${SRC}/${strip ${EXE_PREFIX}}*.c}
+COMMON_C_FILES=${filter-out ${MAIN_C_FILES},${wildcard *.c} \
+			   	 ${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.c}}}
+			   	 #${wildcard ${TC}*.c}}
+COMMON_ASM_FILES=${filter-out ${MAIN_CXX_FILES},${wildcard *.s} \
+				   ${foreach dir,${SUBFOLDERS},${wildcard ${SRC}/${dir}/*.s}}}
+				   #${wildcard ${TC}*.s}}
+MAIN_OBJECT_FILES=${sort ${patsubst ${SRC}/%.c,${OBJ}/%.o,${MAIN_C_FILES}}}
+COMMON_OBJECT_FILES=${sort ${patsubst ${SRC}/%.c,${OBJ}/%.o,${COMMON_C_FILES}} \
+                      ${patsubst ${SRC}/%.s,${OBJ}/%.o,${COMMON_ASM_FILES}}}
+LIBRARIES=${foreach dir,${wildcard ${LIB}/*},${wildcard ${LIB}/${dir}/*.a}}
+
+#-----------------------------------------------------------------------------
+# --- makefile incantation
+# down here is black magic, you probably don't want to modify anything
+
+DEFS  =$(DDEFS) $(UDEFS)
+ADEFS =$(DADEFS) $(UADEFS)
+ASFLAGS=$(INCDIR) $(DEFS) -Wa,--gdwarf2 $(ADEFS)
+
+ifeq (${strip ${RELEASE}},0)
+    CFLAGS=-g3 -O0
+else
+    CFLAGS=-O3
+endif
+ 
+ASFLAGS = $(INCDIR) $(DEFS) -Wa,--gdwarf2 $(ADEFS)
+CFLAGS+=-std=c17 -Wall $(DEFS) -Wextra -Warray-bounds -Wno-unused-parameter -fomit-frame-pointer
+LDFLAGS= -T$(LDSCRIPT) -lc -lgcc -lgcov -lm -Wl,-Map=$@.map,--gc-sections --specs=nosys.specs
+INC=-I${LIB}
+
+# --- Generate dependency information
+#CFLAGS += -MD -MP -MF ${DEP}/$(@F0).d
+#ASFLAGS += -MD -MP -MF ${DEP}/$(@F).d
+
+# --- folder tree
+DIR_GUARD=@mkdir -p ${@D}
+ifeq (${OS},Windows_NT)
+	DIR_GUARD=@md ${@D}
+endif
+
+# --- make rules
+all: ${BIN}/${EXE_PREFIX}.elf ${BIN}/${EXE_PREFIX}.hex ${BIN}/${EXE_PREFIX}.bin
+
+rebuild : clean all
+
+.SUFFIXES:
+.SECONDARY:
+.PHONY: all clean rebuild
+
+${BIN}/%.elf : ${MAIN_OBJECT_FILES} ${COMMON_OBJECT_FILES}
+	@echo
+	@echo ==== linking $@ ====
+	@echo ${COMMON_OBJECT_FILES}
+	@echo
+	${DIR_GUARD}
+	${CC} --verbose -o $@ ${filter-out %ld, $^} ${LIBRARIES} ${LDFLAGS}
+	${OBJDUMP} -h $@
+	${SIZE} $@
+	@${SKIP_LINE}
+
+${BIN}/%.hex : ${BIN}/%.elf
+	@echo
+	@echo ==== traducing [opt=${opt}] $< ====
+	@echo
+	${OBJCOPY} -O ihex $< $@
+
+${BIN}/%.bin : ${BIN}/%.elf
+	@echo
+	@echo ==== traducing [opt=${opt}] $< ====
+	@echo
+	${OBJCOPY} -O binary $< $@
+
+${OBJ}/%.o : ${SRC}/%.c
+	@echo
+	@echo ==== compiling [opt=${opt}] $< ====
+	@echo
+	${DIR_GUARD}
+	${CC} ${INC} -c ${CFLAGS} $< -o $@ ${LIBRARIES}
+	@${SKIP_LINE}
+
+${BIN}/%.o : ${SRC}/%.c
+	@echo
+	@echo ==== compiling [opt=${opt}] $< ====
+	@echo
+	${DIR_GUARD}
+	${CC} ${INC} -c ${CFLAGS} $< -o $@ ${LIBRARIES}
+	@${SKIP_LINE}
+
+${OBJ}/%.o : ${SRC}/%.s
+	@echo
+	@echo ==== compiling [opt=${opt}] $^ $@ ${LIBRARIES}====
+	@echo
+	${DIR_GUARD}
+	${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES} 
+	@${SKIP_LINE}
+
+${BIN}/%.o : ${SRC}/%.s
+	@echo
+	@echo ==== compiling [opt=${opt}] $^ $@ ${LIBRARIES}====
+	@echo
+	${DIR_GUARD}
+	${AS} -o ${ASFLAGS} $< -o $@ ${LIBRARIES}
+	@${SKIP_LINE}
+
+# --- remove generated files
+clean:
+	-rm -rf ${BIN}/*
+
+# Include the dependency files, should be the last of the makefile
+#
+#-include $(shell mkdir ${DEP}/ 2>/dev/null) $(wildcard ${DEP}/*)
+-include ${DEPEND_FILES}

lib/cmsis/cmsis_armcc.h

@@ -0,0 +1,869 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.5
+ * @date     14. December 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

lib/cmsis/cmsis_compiler.h

@@ -0,0 +1,271 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

lib/cmsis/cmsis_iccarm.h

@@ -0,0 +1,940 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.8
+ * @date     04. September 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

lib/cmsis/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

lib/cmsis/core_cm0.h

@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = 0x0U;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = 0x0U;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

lib/cmsis/core_cm1.h

@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

lib/cmsis/mbed_tz_context.c

@@ -0,0 +1,207 @@
+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !TARGET_TFM
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS     8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE      256U
+#endif
+
+typedef struct {
+  uint32_t sp_top;      // stack space top
+  uint32_t sp_limit;    // stack space limit
+  uint32_t sp;          // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
+static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+  uint32_t n;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+    ProcessStackInfo[n].sp = 0U;
+    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+  }
+  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+  ProcessStackFreeSlot = 0U;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  // Privileged Thread Mode using PSP
+  __set_CONTROL(0x02U);
+
+  return 1U;    // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+  uint32_t slot;
+
+  (void)module; // Ignore (fixed Stack size)
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+    return 0U;  // No slot available
+  }
+
+  slot = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+  return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+  ProcessStackInfo[slot].sp = 0U;
+
+  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = slot;
+
+  return 1U;    // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  // Setup process stack pointer and stack limit
+  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+  __set_PSP   (ProcessStackInfo[slot].sp);
+
+  return 1U;    // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+  uint32_t sp;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  sp = __get_PSP();
+  if ((sp < ProcessStackInfo[slot].sp_limit) ||
+      (sp > ProcessStackInfo[slot].sp_top)) {
+    return 0U;  // SP out of range
+  }
+  ProcessStackInfo[slot].sp = sp;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  return 1U;    // Success
+}
+#endif
+
+#endif // !TARGET_TFM

lib/cmsis/mpu_armv7.h

@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

lib/cmsis/mpu_armv8.h

@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

lib/cmsis/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

openocd

@@ -0,0 +1,3 @@
+#!/bin/bash
+openocd  -f interface/stlink-v2.cfg -f target/cs32f1x.cfg
+

src/config.h

@@ -0,0 +1,103 @@
+/****************************************************************************
+ * IRQ Priority
+ ****************************************************************************/
+#define EXTI0_IRQ_PRIORITY		8
+#define EXTI1_IRQ_PRIORITY		8
+#define EXTI2_IRQ_PRIORITY		8
+#define EXTI3_IRQ_PRIORITY		8
+#define EXTI4_IRQ_PRIORITY		8
+#define EXTI9_5_IRQ_PRIORITY	8
+#define EXTI15_10_IRQ_PRIORITY	8
+
+#define TIM2_IRQ_PRIORITY		4
+#define TIM3_IRQ_PRIORITY		4
+#define TIM4_IRQ_PRIORITY		4
+
+#define	USART1_IRQ_PRIORITY		3
+#define	USART2_IRQ_PRIORITY		3
+#define	USART6_IRQ_PRIORITY		3
+
+#define	I2C1_IRQ_PRIORITY		2
+#define	I2C1_IRQERR_PRIORITY	1
+#define	I2C2_IRQ_PRIORITY		2
+#define	I2C2_IRQERR_PRIORITY	1
+#define	I2C3_IRQ_PRIORITY		2
+#define	I2C3_IRQERR_PRIORITY	1
+
+#define SPI1_IRQ_PRIORITY		4
+#define SPI2_IRQ_PRIORITY		4
+#define SPI3_IRQ_PRIORITY		4
+#define SPI4_IRQ_PRIORITY		4
+#define SPI5_IRQ_PRIORITY		4
+
+#define ADC1_IRQ_PRIORITY		5
+
+/****************************************************************************
+ * USART Pin and use configuration 
+ ****************************************************************************/
+
+//#define USE_USART1
+//#define USART1_GPIO_PORT
+//#define USART1_GPIO_PINS
+
+// USART2: Tx --> PA2, Rx --> PA3
+//#define USE_USART2
+//#define USART2_GPIO_PORT	_GPIOA
+//#define USART2_GPIO_PINS	PIN_2|PIN_3
+
+//#define USE_USART6
+//#define USART6_GPIO_PORT
+//#define USART6_GPIO_PINS
+
+/****************************************************************************
+ *  I2C Pin and use configuration 
+ ****************************************************************************/
+
+// I2C1 : SCL --> PB8, SDA --> PB9
+//#define USE_I2C1
+//#define I2C1_GPIO_PORT		_GPIOB
+//#define I2C1_GPIO_PINS		PIN_8|PIN_9
+
+//#define USE_I2C2
+//#define I2C2_GPIO_PORT
+//#define I2C2_GPIO_PINS
+
+//#define USE_I2C3
+//#define I2C3_GPIO_PORT
+//#define I2C3_GPIO_PINS
+
+/****************************************************************************
+ *  SPI pin and use configuration 
+ ****************************************************************************/
+
+// SPI1 pins : LCD_SCK   --> D13 --> PA5 : SPI1_SCK
+//             LCD_MOSI  --> D11 --> PA7 : SPI1_MOSI
+//#define USE_SPI1
+//#define SPI1_GPIO_PORT		_GPIOA
+//#define SPI1_GPIO_PINS		PIN_5|PIN_7
+
+//#define USE_SPI2
+//#define SPI2_GPIO_PORT
+//#define SPI2_GPIO_PINS			
+
+//#define USE_SPI3
+//#define SPI3_GPIO_PORT
+//#define SPI3_GPIO_PINS			
+
+//#define USE_SPI4
+//#define SPI4_GPIO_PORT
+//#define SPI4_GPIO_PINS			
+
+//#define USE_SPI5
+//#define SPI5_GPIO_PORT
+//#define SPI5_GPIO_PINS			
+
+/****************************************************************************
+ *  ADC pin and use configuration 
+ ****************************************************************************/
+
+// ADC1: ADC1_0 --> PA0, ADC1_1 -->PA1
+//#define USE_ADC1
+//#define ADC1_GPIO_PORT		_GPIOA
+//#define ADC1_GPIO_PINS		PIN_0|PIN_1
+

src/drivers/io.c

@@ -0,0 +1,255 @@
+//target header
+#include "../target/stm32f103xb.h"
+
+//custom header
+#include "../config.h"
+
+//std headers
+#include <stdlib.h>
+
+//driver header
+#include "io.h"
+
+static OnIO io_cb[16]={
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+};
+
+void EXTI0_IRQHandler() {
+	if (io_cb[0]) (io_cb[0])();
+
+	EXTI->PR = 1<<0;
+}
+
+void EXTI1_IRQHandler() {
+	if (io_cb[1]) (io_cb[1])();
+
+	EXTI->PR = 1<<1;
+}
+
+void EXTI2_IRQHandler() {
+	if (io_cb[2]) (io_cb[2])();
+
+	EXTI->PR = 1<<2;
+}
+
+void EXTI3_IRQHandler() {
+	if (io_cb[3]) (io_cb[3])();
+
+	EXTI->PR = 1<<3;
+}
+
+void EXTI4_IRQHandler() {
+	if (io_cb[4]) (io_cb[4])();
+
+	EXTI->PR = 1<<4;
+}
+
+void EXTI9_5_IRQHandler() {
+	if (EXTI->PR & (1<<5)) {
+		if (io_cb[5]) (io_cb[5])();
+		EXTI->PR = 1<<5;
+	} else if (EXTI->PR & (1<<6)) {
+		if (io_cb[6]) (io_cb[6])();
+		EXTI->PR = 1<<6;
+	} else if (EXTI->PR & (1<<7)) {
+		if (io_cb[7]) (io_cb[7])();
+		EXTI->PR = 1<<7;
+	} else if (EXTI->PR & (1<<8)) {
+		if (io_cb[8]) (io_cb[8])();
+		EXTI->PR = 1<<8;
+	} else if (EXTI->PR & (1<<9)) {
+		if (io_cb[9]) (io_cb[9])();
+		EXTI->PR = 1<<9;
+	}
+}
+
+void EXTI15_10_IRQHandler() {
+	if (EXTI->PR & (1<<10)) {
+		if (io_cb[10]) (io_cb[10])();
+		EXTI->PR = 1<<10;
+	} else if (EXTI->PR & (1<<11)) {
+		if (io_cb[11]) (io_cb[11])();
+		EXTI->PR = 1<<11;
+	} else if (EXTI->PR & (1<<12)) {
+		if (io_cb[12]) (io_cb[12])();
+		EXTI->PR = 1<<12;
+	} else if (EXTI->PR & (1<<13)) {
+		if (io_cb[13]) (io_cb[13])();
+		EXTI->PR = 1<<13;
+	} else if (EXTI->PR & (1<<14)) {
+		if (io_cb[14]) (io_cb[14])();
+		EXTI->PR = 1<<14;
+	} else if (EXTI->PR & (1<<15)) {
+		if (io_cb[15]) (io_cb[15])();
+		EXTI->PR = 1<<15;
+	}
+}
+
+/* Definitions for EXTI configuration */
+#define SYSCFG_EXTI_PA_MASK		0
+#define SYSCFG_EXTI_PB_MASK		1
+#define SYSCFG_EXTI_PC_MASK		2
+#define SYSCFG_EXTI_PD_MASK		3
+#define SYSCFG_EXTI_PE_MASK		4
+#define SYSCFG_EXTI_PH_MASK		7
+
+
+int io_configure(GPIO_TypeDef *gpio, uint16_t pin, uint32_t pin_cfg, OnIO cb) {
+
+	// enable GPIOx subsystem clocking
+	if (gpio == GPIOA) RCC->APB2ENR |= 1<<2;
+	else if (gpio == GPIOB) RCC->APB2ENR |= 1<<3;
+	else if (gpio == GPIOC) RCC->APB2ENR |= 1<<4;
+	else if (gpio == GPIOD) RCC->APB2ENR |= 1<<5;
+	else if (gpio == GPIOE) RCC->APB2ENR |= 1<<6;
+
+	// ssetup the config bits
+	uint32_t crx = 0;
+	uint16_t odr = 0;
+	for(int i=0; i<8; i++) {
+		if(pin & (1 << i)) {
+			crx |= (pin_cfg & 0xF) << (4*i);
+			odr |= (pin_cfg & 0xF0) << i;
+		}
+	}
+	gpio->CRL |= crx;
+
+	crx = 0;
+	for(int i=8; i<16; i++) {
+		if(pin & (1 << i)) {
+			crx |= (pin_cfg & 0xF) << (4*(i-8));
+			odr |= (pin_cfg & 0xF0) << i;
+		}
+	}
+	gpio->CRH |= crx;
+	gpio->ODR |= odr;
+
+	/*
+	   if (!cb) return -1; //no callback attached
+
+	//TODO manage alternate functions
+	if (pin_cfg & 0x3) return -1; //callback set, but not in input mode
+
+	// ************* Input GPIO + External IRQ *************
+
+	uint32_t port_mask = 0;
+	uint32_t pin_mask = 0;
+
+	if (gpio == GPIOA) port_mask = SYSCFG_EXTI_PA_MASK;
+	else if (gpio == GPIOB) port_mask = SYSCFG_EXTI_PB_MASK;
+	else if (gpio == GPIOC) port_mask = SYSCFG_EXTI_PC_MASK;
+	else if (gpio == GPIOD) port_mask = SYSCFG_EXTI_PD_MASK;
+	else if (gpio == GPIOE) port_mask = SYSCFG_EXTI_PE_MASK;
+
+	uint32_t bit_mask = 0x1;
+
+	for (int i=0; i<16; i++) {
+	if (pin_mask & bit_mask) {
+	// enable clock for SYSCFG, no need for EXTI (interface not clocked)
+	RCC->APB2ENR = RCC->APB2ENR | (1<<14);
+
+	// configure pin Px_i (4 pin config per EXTICR[] register, 4 bits per pin)
+	//   use port Px and bind Px_i --> EXTIi
+	// i>>2 = i/4 ; i & 0x3 = i%4
+	gpio->EXTICR[i>>2] = (SYSCFG->EXTICR[i>>2] & 
+	~(0x0000000F << ((i & 3)<<2))) | 
+	(port_mask << ((i & 3)<<2));
+
+	// allow pin EXTIi to send an IRQ
+	EXTI->IMR = EXTI->IMR | bit_mask;
+	//   not a wakeup event
+	EXTI->EMR = EXTI->EMR & (~bit_mask);
+
+	// Configure pin event IRQ on rising (RTSR)/falling (FTSR) edge (rising only here)
+	if (pin_cfg & PIN_OPT_IRQ_EDGE_RISE) {
+	EXTI->RTSR = EXTI->RTSR | bit_mask;
+	} else {
+	EXTI->RTSR = EXTI->RTSR & (~bit_mask);
+	}
+
+	if (pin_cfg & PIN_OPT_IRQ_EDGE_FALL) {
+	EXTI->FTSR = EXTI->FTSR | bit_mask;
+	} else {
+	EXTI->FTSR = EXTI->FTSR & (~bit_mask);
+	}
+
+	io_cb[i] = cb;
+
+	// reset any pending IRQ on PC13
+	EXTI->PR = bit_mask;
+
+	// Setup NVIC
+	switch (i) {
+	case 0:
+	NVIC_SetPriority(EXTI0_IRQn, EXTI0_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI0_IRQn);
+	break;
+	case 1:
+	NVIC_SetPriority(EXTI1_IRQn, EXTI1_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI1_IRQn);
+	break;
+	case 2:
+	NVIC_SetPriority(EXTI2_IRQn, EXTI2_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI2_IRQn);
+	break;
+	case 3:
+	NVIC_SetPriority(EXTI3_IRQn, EXTI3_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI3_IRQn);
+	break;
+	case 4:
+	NVIC_SetPriority(EXTI4_IRQn, EXTI4_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI4_IRQn);
+	break;
+	case 5:
+	case 6:
+	case 7:
+	case 8:
+	case 9:
+	NVIC_SetPriority(EXTI9_5_IRQn, EXTI9_5_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI9_5_IRQn);
+	break;
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+	NVIC_SetPriority(EXTI15_10_IRQn, EXTI15_10_IRQ_PRIORITY);
+	NVIC_EnableIRQ(EXTI15_10_IRQn);
+	break;
+	default:
+	return 0;
+}
+}
+bit_mask = bit_mask<<1;
+}
+*/
+return 0;
+}
+
+
+uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask)
+{	
+	return gpio->IDR & mask;	
+}
+
+void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask)
+{
+	gpio->BSRR = (uint32_t)(mask) << (val ? 0 : 16);  
+}
+
+void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask)
+{
+	gpio->BSRR = (uint32_t)(mask) << (val ? 16 : 0);  
+}
+
+void io_set(GPIO_TypeDef *gpio, uint16_t mask)
+{
+	gpio->BSRR = mask;  
+}
+
+void io_clear(GPIO_TypeDef *gpio, uint16_t mask)
+{
+	gpio->BSRR = (uint32_t)(mask) << 16;  
+}

src/drivers/io.h

@@ -0,0 +1,119 @@
+#ifndef _IO_H_
+#define _IO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* --- GPIO pin mask definitions ---------------------------------------- */
+#define PIN_0						(1 << 0)
+#define PIN_1						(1 << 1)
+#define PIN_2						(1 << 2)
+#define PIN_3						(1 << 3)
+#define PIN_4						(1 << 4)
+#define PIN_5						(1 << 5)
+#define PIN_6						(1 << 6)
+#define PIN_7						(1 << 7)
+#define PIN_8						(1 << 8)
+#define PIN_9						(1 << 9)
+#define PIN_10						(1 << 10)
+#define PIN_11						(1 << 11)
+#define PIN_12						(1 << 12)
+#define PIN_13						(1 << 13)
+#define PIN_14						(1 << 14)
+#define PIN_15						(1 << 15)
+#define PIN_ALL						0xFFFF
+
+/* --- GPIO pin mode definitions ---------------------------------------- */
+#define PIN_MODE_INPUT				(0)
+#define PIN_MODE_OUTPUT				(1 << 0)
+#define	PIN_MODE_ALTFUNC			(1 << 3 | 1 << 0)
+#define	PIN_MODE_ANALOG				(0)
+
+/* --- GPIO pin option definitions -------------------------------------- */
+/*   none for analog pin */
+#define PIN_OPT_NONE				(0)
+
+/*   pull up/pull down resistor option */
+#define PIN_OPT_RESISTOR_NONE		(1 << 2)
+#define PIN_OPT_RESISTOR_PULLUP		(1 << 4 | 1 << 3)
+#define PIN_OPT_RESISTOR_PULLDOWN	(1 << 3)
+
+/*   push-pull/open drain output option */
+#define	PIN_OPT_OUTPUT_PUSHPULL		(0)
+#define PIN_OPT_OUTPUT_OPENDRAIN	(1 << 2)
+
+/*   output speed option
+ *   - LOW    ~ 2MHz max
+ *   - MEDIUM ~ 10MHz max
+ *   - FAST   ~ 50MHz max
+ **/
+#define	PIN_OPT_OUTPUT_SPEED_LOW	(10 << 0)
+#define	PIN_OPT_OUTPUT_SPEED_MEDIUM (1 << 0)
+#define	PIN_OPT_OUTPUT_SPEED_FAST	(11 << 0)
+
+/*   alternate function selection option */
+#define PIN_OPT_AF0					0x0
+#define PIN_OPT_AF1					0x1
+#define PIN_OPT_AF2					0x2
+#define PIN_OPT_AF3					0x3
+#define PIN_OPT_AF4					0x4
+#define PIN_OPT_AF5					0x5
+#define PIN_OPT_AF6					0x6
+#define PIN_OPT_AF7					0x7
+#define PIN_OPT_AF8					0x8
+#define PIN_OPT_AF9					0x9
+#define PIN_OPT_AF10				0xA
+#define PIN_OPT_AF11				0xB
+#define PIN_OPT_AF12				0xC
+#define PIN_OPT_AF13				0xD
+#define PIN_OPT_AF14				0xE
+#define PIN_OPT_AF15				0xF
+
+/*   irq pin option */
+#define PIN_OPT_IRQ_EDGE_RISE		(1 << 12)
+#define PIN_OPT_IRQ_EDGE_FALL		(2 << 12)
+#define PIN_OPT_IRQ_EDGE_BOTH		(3 << 12)
+
+typedef void (*OnIO)();
+
+/* io_configure
+ *
+ * configure pins referenced in 'pin_mask' of specified port
+ * 'gpio' according to 'pin_cfg' and associate a callback
+ * function 'cb' if not NULL.
+ * returns 0 if success
+ */
+int io_configure(GPIO_TypeDef *gpio, uint16_t pin_mask, uint32_t pin_cfg, OnIO cb);
+
+/* io_read
+ *
+ * read 32 bit data from port 'gpio', filter the result with mask
+ */
+uint32_t io_read(GPIO_TypeDef *gpio, uint16_t mask);
+
+/* io_write
+ *
+ * write 16 bit data filtered by mask to port 'gpio'
+ * '1' in val are written as HIGH level on port pins
+ */
+void io_write(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask);
+
+/* io_write_n
+ *
+ * write 16 bit data filtered by mask to port 'gpio'
+ * '1' in val are written as LOW level on port pins
+ */
+void io_write_n(GPIO_TypeDef *gpio, uint16_t val, uint16_t mask);
+
+/* io_set/clear
+ *
+ * set or clear outputs according to bit mask
+ */
+void io_set(GPIO_TypeDef *gpio, uint16_t mask);
+void io_clear(GPIO_TypeDef *gpio, uint16_t mask);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

src/drivers/rcc.c

@@ -0,0 +1,252 @@
+/** 
+  ==============================================================================
+##### RCC specific features #####
+==============================================================================
+[..]  
+After reset the device is running from Internal High Speed oscillator 
+(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+and I-Cache are disabled, and all peripherals are off except internal
+SRAM, Flash and JTAG.
+(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+all peripherals mapped on these busses are running at HSI speed.
+(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+(+) All GPIOs are in input floating state, except the JTAG pins which
+are assigned to be used for debug purpose.
+
+[..]          
+Once the device started from reset, the user application has to:        
+(+) Configure the clock source to be used to drive the System clock
+(if the application needs higher frequency/performance)
+(+) Configure the System clock frequency and Flash settings  
+(+) Configure the AHB and APB busses prescalers
+(+) Enable the clock for the peripheral(s) to be used
+(+) Configure the clock source(s) for peripherals which clocks are not
+derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+##### RCC Limitations #####
+==============================================================================
+[..]  
+A delay between an RCC peripheral clock enable and the effective peripheral 
+enabling should be taken into account in order to manage the peripheral read/write 
+from/to registers.
+(+) This delay depends on the peripheral mapping.
+(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle 
+after the clock enable bit is set on the hardware register
+(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle 
+after the clock enable bit is set on the hardware register
+
+[..]  
+Possible Workarounds:
+(#) Enable the peripheral clock sometimes before the peripheral read/write 
+register is required.
+(#) For AHB peripheral, insert two dummy read to the peripheral register.
+(#) For APB peripheral, insert a dummy read to the peripheral register.
+*/
+
+#include "rcc.h"
+
+/* HPRE: AHB high-speed prescaler */
+#define RCC_CFGR_HPRE_DIV_NONE			0x0
+#define RCC_CFGR_HPRE_DIV_2				(0x8 + 0)
+#define RCC_CFGR_HPRE_DIV_4				(0x8 + 1)
+#define RCC_CFGR_HPRE_DIV_8				(0x8 + 2)
+#define RCC_CFGR_HPRE_DIV_16			(0x8 + 3)
+#define RCC_CFGR_HPRE_DIV_64			(0x8 + 4)
+#define RCC_CFGR_HPRE_DIV_128			(0x8 + 5)
+#define RCC_CFGR_HPRE_DIV_256			(0x8 + 6)
+#define RCC_CFGR_HPRE_DIV_512			(0x8 + 7)
+
+/* PPRE1/2: APB high-speed prescalers */
+#define RCC_CFGR_PPRE_DIV_NONE			0x0
+#define RCC_CFGR_PPRE_DIV_2				0x4
+#define RCC_CFGR_PPRE_DIV_4				0x5
+#define RCC_CFGR_PPRE_DIV_8				0x6
+#define RCC_CFGR_PPRE_DIV_16			0x7
+
+/* PPLMUL: PPL multiplier */
+#define RCC_CFGR_PLLMUL(fac)			(fac + 2)
+
+enum rcc_osc {
+	RCC_HSI,
+	RCC_HSE,
+	RCC_PLL,
+	RCC_LSI,
+	RCC_LSE
+};
+
+struct ClockConfig_t {
+	uint8_t		type;
+	uint8_t		pll_src;
+	uint8_t		pllmul;
+	uint8_t		hpre;
+	uint8_t		ppre1;
+	uint8_t		ppre2;
+	uint32_t	flash_cfg;
+	uint32_t	ahb_freq;
+	uint32_t	apb1_freq;
+	uint32_t	apb2_freq;
+};
+
+static struct ClockConfig_t _clock_config[] = {
+	{/* Performance Mode */
+		.type = RCC_PLL,
+		.pll_src = RCC_HSE, //8MHz
+		.pllmul = RCC_CFGR_PLLMUL(9), //freq should noot exceed 72MHz
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_2, //freq should not exceed 36MHz
+		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
+		.flash_cfg = FLASH_ACR_LATENCY_2,
+		.ahb_freq = 72000000,
+		.apb1_freq = 36000000,
+		.apb2_freq = 72000000
+	},
+
+	{/* Powersave Mode */
+		.type = RCC_HSE,
+		.hpre = RCC_CFGR_HPRE_DIV_16,
+		.ppre1 = RCC_CFGR_PPRE_DIV_16,
+		.ppre2 = RCC_CFGR_PPRE_DIV_16,
+		.flash_cfg = FLASH_ACR_LATENCY_0,
+		.ahb_freq = 500000,
+		.apb1_freq = 500000,
+		.apb2_freq = 500000
+	}
+};
+
+static void rcc_osc_on(enum rcc_osc osc)
+{
+	switch (osc) {
+		case RCC_HSI:
+			if (!(RCC->CR & RCC_CR_HSION)) {
+				RCC->CR |= RCC_CR_HSION;
+				while ((RCC->CR & RCC_CR_HSIRDY)==0);
+			}
+			break;
+		case RCC_HSE:
+			if (!(RCC->CR & RCC_CR_HSEON)) {
+				RCC->CR |= RCC_CR_HSEON;
+				while ((RCC->CR & RCC_CR_HSERDY)==0);
+			}
+			break;
+		case RCC_PLL:
+			if (!(RCC->CR & RCC_CR_PLLON)) {
+				RCC->CR |= RCC_CR_PLLON;
+				while ((RCC->CR & RCC_CR_PLLRDY)==0);
+			}
+			break;
+		case RCC_LSI:
+			if (!(RCC->CSR & RCC_CSR_LSION)) {
+				RCC->CSR |= RCC_CSR_LSION;
+				while ((RCC->CSR & RCC_CSR_LSIRDY)==0);
+			}
+			break;
+		case RCC_LSE:
+			if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+				RCC->BDCR |= RCC_BDCR_LSEON;
+				while ((RCC->BDCR & RCC_BDCR_LSERDY)==0);
+			}
+			break;
+	}
+}
+
+static void rcc_osc_off(enum rcc_osc osc)
+{
+	switch (osc) {
+		case RCC_HSI:
+			RCC->CR &= ~RCC_CR_HSION;
+			break;
+		case RCC_HSE:
+			RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+			break;
+		case RCC_PLL:
+			RCC->CR &= ~RCC_CR_PLLON;
+			break;
+		case RCC_LSI:
+			RCC->CSR &= ~RCC_CSR_LSION;
+			break;
+		case RCC_LSE:
+			RCC->BDCR &= ~RCC_BDCR_LSEON;
+			break;
+	}
+}
+
+static void rcc_set_sysclk(enum rcc_osc osc)
+{
+	RCC->CFGR = (RCC->CFGR & ~0x3) | (osc & 3);
+	while (((RCC->CFGR & 0xC)>>2) != osc);
+}
+
+//void SystemInit(void) {
+//	Clock_t tmp_clk;
+//	rcc_config_clock(CLOCK_CONFIG_PERFORMANCE, &tmp_clk);
+//}
+
+void rcc_config_clock(uint32_t config, Clock_t *sysclks)
+{
+	struct ClockConfig_t *clk;
+
+	if (config < CLOCK_CONFIG_END) {
+		clk=&(_clock_config[config]);
+	} else {
+		clk=&(_clock_config[CLOCK_CONFIG_PERFORMANCE]);
+	}
+
+	if (clk->type == RCC_HSE) {			// HSE Clock
+		rcc_osc_on(RCC_HSE);
+		rcc_set_sysclk(RCC_HSE);
+		rcc_osc_off(RCC_PLL);
+		rcc_osc_off(RCC_HSI);
+
+	} else if (clk->type == RCC_PLL) {
+		// enable PWR module clocking
+		RCC->APB1ENR |= 1<<28;
+
+		if (clk->pll_src == RCC_HSE) {	// HSE Clock src
+			rcc_osc_on(RCC_HSE);
+		} else {						// Default: HSI Clock src
+			rcc_osc_on(RCC_HSI);
+		}
+
+		// configure prescalers for 
+		//  AHB: AHBCLK > 25MHz
+		//  APB1: APB1CLK <= 36MHz
+		//  APB2: APB2CLK <= 72MHz
+		RCC->CFGR = ( RCC->CFGR & ~((0x3F<<8) | (0xF<<4)) ) |
+			((clk->hpre & 0xF) << 4) |
+			((clk->ppre1 & 0x7) << 8) |
+			((clk->ppre2 & 0x7) << 11);
+
+		// configure PLL
+		RCC->CFGR &= !(0xF<<18);
+		RCC->CFGR |= clk->pllmul<<18;
+
+		// enable PLL oscillator
+		rcc_osc_on(RCC_PLL);
+
+		// set Flash timings
+		FLASH->ACR &= !0x8;
+		FLASH->ACR |= clk->flash_cfg;
+		//TODO set buffer bits
+
+		// connect to PLL
+		rcc_set_sysclk(RCC_PLL);
+
+		// stop unused clock
+		if ((clk->pll_src == RCC_HSE) && (RCC->CR & RCC_CR_HSION))
+			rcc_osc_off(RCC_HSI);
+		else
+			rcc_osc_off(RCC_HSE);
+
+	} else {							// Default: HSI Clock
+		rcc_osc_on(RCC_HSI);
+		rcc_set_sysclk(RCC_HSI);
+		rcc_osc_off(RCC_PLL);
+		rcc_osc_off(RCC_HSE);
+	}
+	sysclks->ahb_freq = clk->ahb_freq;
+	sysclks->apb1_freq = clk->apb1_freq;
+	//TODO check timer frequencies
+	sysclks->apb1_timer_freq = clk->ppre1==RCC_CFGR_PPRE_DIV_NONE ? clk->apb1_freq : 2*clk->apb1_freq;
+	sysclks->apb2_freq = clk->apb2_freq;
+	sysclks->apb2_timer_freq = clk->ppre2==RCC_CFGR_PPRE_DIV_NONE ? clk->apb2_freq : 2*clk->apb2_freq;
+}

src/drivers/rcc.h

@@ -0,0 +1,33 @@
+#ifndef _RCC_H_
+#define _RCC_H_
+
+#include "../target/stm32f103xb.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+typedef struct _Clock_t {
+	uint32_t	ahb_freq;
+	uint32_t	apb1_freq;
+	uint32_t	apb1_timer_freq;
+	uint32_t	apb2_freq;
+	uint32_t	apb2_timer_freq;
+} Clock_t;
+
+enum Clock_config {
+	CLOCK_CONFIG_PERFORMANCE,
+	CLOCK_CONFIG_POWERSAVE,
+	CLOCK_CONFIG_END
+};
+
+//void SystemInit(void);
+
+void rcc_config_clock(uint32_t config, Clock_t *sysclks);
+
+#
+#ifdef __cplusplus
+}
+#endif
+
+#endif

src/drivers/timer.c

@@ -0,0 +1,128 @@
+#include "timer.h"
+
+extern Clock_t sysclks;
+
+/* 
+ * timerX_isr
+ * timerX ISR (Interrupt Service Routine)
+ */
+static OnTick callback2 = 0;
+static OnTick callback3 = 0;
+static OnTick callback4 = 0;
+
+void TIM2_IRQHandler() {
+	if (callback2) callback2();
+	TIM2->SR &= ~0x1F;
+}
+
+void TIM3_IRQHandler() {
+	if (callback3) callback3();
+	TIM3->SR &= ~0x1F;
+}
+
+void TIM4_IRQHandler() {
+	if (callback4) callback4();
+	TIM4->SR &= ~0x1F;
+}
+
+
+/* 
+ * timer_tick_init
+ * setup timer to call cb function periodically, each tick_ms
+ */
+int timer_tick_init(TIM_TypeDef *tmr, uint32_t tick_ms, OnTick cb) {
+	IRQn_Type irqn;
+	uint32_t irq_priority, clk;
+	//get back the clock frequency
+	clk = sysclks.apb1_timer_freq;
+
+	if (tmr == TIM2) {
+		// register callback function
+		callback2 = cb;
+		irqn = TIM2_IRQn;
+		irq_priority = TIM2_IRQ_PRIORITY;
+
+		// enable timer clocking
+		RCC->APB1ENR |=1<<0;
+
+	} else if (tmr == TIM3) {
+		// register callback function
+		callback3 = cb;
+		irqn = TIM3_IRQn;
+		irq_priority = TIM3_IRQ_PRIORITY;
+
+		// enable timer clocking
+		RCC->APB1ENR |=1<<1;
+
+	} else if (tmr == TIM4) {
+		// register callback function
+		callback4 = cb;
+		irqn = TIM4_IRQn;
+		irq_priority = TIM4_IRQ_PRIORITY;
+
+		// enable timer clocking
+		RCC->APB1ENR |=1<<2;
+	
+	} else {
+		return -1;
+	}
+
+	// clear pending interrupts
+	tmr->SR &= !1;
+
+	// set mode
+	tmr->CR1 = (1<<7);  	//buffering
+	tmr->DIER = (1<<0); 	//Enable interrupts
+
+	// set prescaler 100us
+	tmr->PSC = clk/(10000-1); //100µs = (PSC+1)*Tclk
+
+	// set period
+	if(timer_tick_period(tmr,tick_ms)) return -1; 
+
+	//enable counter
+	tmr->CR1= (1<<0)| tmr->CR1;
+
+	if (cb) {
+		NVIC_SetPriority(irqn,irq_priority);	//enable interuptions
+		NVIC_EnableIRQ(irqn);
+	}
+
+	return 0;
+}
+
+/* 
+ * timer_tick_period
+ * change the tick_ms period
+ */
+int timer_tick_period(TIM_TypeDef *tmr, uint32_t tick_ms) {
+	// set period
+	tmr->ARR = tick_ms*10-1; //tickms = (ARR+1)Tpsc
+
+	// force update to reset counter and prescaler
+	tmr->EGR |= 1;
+	return 0;
+}
+
+/* 
+ * timer_start
+ * reset & enable counting
+ */
+void timer_start(TIM_TypeDef *tmr) {
+	// force update to reset counter and prescaler
+	tmr->EGR |= 1;
+
+	// enable counting
+	tmr->CR1 |= 1;
+}
+
+/* 
+ * timer_stop
+ * stop counting
+ */
+void timer_stop(TIM_TypeDef *tmr) {
+	// disable counting
+	tmr->CR1 &= !1;
+
+}
+

src/drivers/timer.h

@@ -0,0 +1,85 @@
+#ifndef _TIMER_H_
+#define _TIMER_H_
+
+#include "../target/stm32f103xb.h"
+#include "../config.h"
+#include "rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+typedef void (*OnTick)(void);
+
+/***************************************************************************/
+/* timer_wait_ms
+ *   wait for ms millisecoonds function
+ */
+int timer_wait_ms(TIM_TypeDef *tmr, uint32_t ms, OnTick cb);
+
+/* timer_wait_us
+ *   wait for us microsecoonds function
+ */
+int timer_wait_us(TIM_TypeDef *tmr, uint32_t us, OnTick cb);
+
+/***************************************************************************/
+/* timer_tick_init
+ *   setup timer to call cb function periodically, each tick_ms
+ */
+int timer_tick_init(TIM_TypeDef *tmr, uint32_t tick_ms, OnTick cb);
+
+/* timer_tick_period
+ *   change the tick_ms period
+ */
+int timer_tick_period(TIM_TypeDef *tmr, uint32_t tick_ms);
+
+/* timer_start
+ *   start counting to generate ticks
+ */
+void timer_start(TIM_TypeDef *tmr);
+
+/* timer_stop
+ *   stop and reset counting
+ */
+void timer_stop(TIM_TypeDef *tmr);
+
+/***************************************************************************/
+#define PWM_CHANNEL_1		0
+#define PWM_CHANNEL_2		1
+#define PWM_CHANNEL_3		2
+#define PWM_CHANNEL_4		3
+
+/* pwm_init
+ *   setup pwm timer period, each tick_ms
+ */
+int pwm_init(TIM_TypeDef *pwm, uint32_t period_ms, OnTick cb);
+
+/* pwm_channel_enable
+ *   set up pwm channel
+ */
+int pwm_channel_enable(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle, uint32_t oe);
+
+/* pwm_channel_disable
+ *   disable pwm channel
+ */
+int pwm_channel_disable(TIM_TypeDef *pwm, uint32_t channel);
+
+/* pwm_channel_set
+ *   set up dutycycle for pwm channel
+ */
+int pwm_channel_set(TIM_TypeDef *pwm, uint32_t channel, uint32_t dutycycle);
+
+/* pwm_start
+ *   start counting
+ */
+#define pwm_start(pwm)	timer_start(pwm)
+
+/* pwm_stop
+ *   stop and reset counting
+ */
+#define pwm_stop(pwm)	timer_stop(pwm)
+
+#ifdef __cplusplus
+}
+#endif
+#endif

src/main.c

@@ -0,0 +1,29 @@
+#include "drivers/rcc.h"
+#include "drivers/io.h"
+
+Clock_t sysclks;
+
+#include "drivers/timer.h"
+
+int val = 0;
+
+static void timeout_cb(void) {
+	io_write(GPIOC, val, PIN_13);
+	val = !val;
+}
+
+int main(void) {
+
+	rcc_config_clock(CLOCK_CONFIG_PERFORMANCE, &sysclks);
+
+	if(io_configure(GPIOC, PIN_13, PIN_MODE_OUTPUT | PIN_OPT_OUTPUT_PUSHPULL, 0)) return 0;
+	io_write(GPIOC, 1, PIN_13);
+
+	timer_tick_init(TIM2, 1000, timeout_cb);
+	timer_start(TIM2);
+
+	for(;;){
+	}
+
+	return 0;
+}

src/target/STM32F103XB.ld

@@ -0,0 +1,160 @@
+/* Linker script to configure memory regions. */
+/* 0xEC reserved for vectors - 8byte aligned = 0xF0 */
+
+
+STACK_SIZE = 0x400;
+
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
+  RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4)
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(8);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(8);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(8);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(8);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(8);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+    
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - STACK_SIZE;
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+

src/target/startup_stm32f103xb.s

@@ -0,0 +1,371 @@
+/**
+  *************** (C) COPYRIGHT 2016 STMicroelectronics ************************
+  * @file      startup_stm32f103xb.s
+  * @author    MCD Application Team
+  * @version   V4.1.0
+  * @date      29-April-2016
+  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system   
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+
+/* Call the clock system intitialization function.*/
+//  bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  //bl _start
+
+LoopForever:
+  b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_IRQHandler
+  .word RTC_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_2_IRQHandler
+  .word USB_HP_CAN1_TX_IRQHandler
+  .word USB_LP_CAN1_RX0_IRQHandler
+  .word CAN1_RX1_IRQHandler
+  .word CAN1_SCE_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_IRQHandler
+  .word TIM1_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USBWakeUp_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for
+                            STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+  .weak TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

src/target/stm32f1xx.h

@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx.h
+  * @author  MCD Application Team
+  * @version V4.2.0
+  * @date    31-March-2017
+  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *            - Configuration section that allows to select:
+  *              - The STM32F1xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx
+  * @{
+  */
+    
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+  /* #define STM32F100xB */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+  /* #define STM32F100xE */   /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+  /* #define STM32F101x6 */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+  /* #define STM32F101xB */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+  /* #define STM32F101xE */   /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 
+  /* #define STM32F101xG */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+  /* #define STM32F102x6 */   /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+  /* #define STM32F102xB */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+  /* #define STM32F103x6 */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+#define STM32F103xB           /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+  /* #define STM32F103xE */   /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+  /* #define STM32F103xG */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+  /* #define STM32F105xC */   /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+  /* #define STM32F107xC */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+  
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+//#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V4.2.0
+  */
+#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F1_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F100xB)
+  #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+  #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+  #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+  #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+  #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+  #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+  #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+  #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+  #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+  #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+  #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+  #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+  #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+  #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

src/target/system_clock.c

@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO                     | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32f1xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+    RCC->CFGR &= 0xF8FF0000U;
+#else
+    RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+    /* Reset PLL2ON and PLL3ON bits */
+    RCC->CR &= 0xEBFFFFFFU;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x00FF0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#else
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+

src/target/system_stm32f1xx.h

@@ -0,0 +1,118 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.h
+  * @author  MCD Application Team
+  * @version V4.2.0
+  * @date    31-March-2017
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

src/types_c.taghl

@@ -0,0 +1,343 @@
+syn keyword CTagsStructure ClockConfig_t __anon72c4c37e0c08 __anon72c4c37e0708 __anon72c4c37e0608 __anon72c4c37e0408 __anon72c4c37e0308 __anon72c4c37e0a08 __anon72c4c37e1508 _Clock_t __anon72c4c37e0908 __anon72c4c37e1a08 __anon72c4c37e1008 __anon72c4c37e1608 __anon72c4c37e1308 __anon72c4c37e1708 __anon72c4c37e0e08 __anon72c4c37e0208 __anon72c4c37e0f08 __anon72c4c37e1408 __anon72c4c37e0d08 __anon72c4c37e1908 __anon72c4c37e0508 __anon72c4c37e0808 __anon72c4c37e0b08 __anon72c4c37e1c08 __anon72c4c37e1808
+syn keyword CTagsStructure __anon72c4c37e1208 __anon72c4c37e1b08 __anon72c4c37e1108
+syn keyword CTagsMember JDR2 plln FMR JDR4 CRL SMPR1 CRCPR pll_src pllmul WRP0 Data1 PSC apb1_freq RESP2 JDR3 RF0R sTxMailBox DR RESP3 CCER I2SCFGR AHBENR GTPR RDTR MCR CCR MSR IDR DCTRL JDR1 PRLH ISR CFR OBR BSRR PR RESERVED8 RDP EP4R CNTL CRH EVCR CMAR ppre1 BTABLE FA1R JOFR4 RESERVED3 EP1R JOFR3 LTR FIFOCNT SMCR FIFO type CR RESERVEDC DR10 JOFR1 SQR3 JOFR2 RESP1 CPAR CCR1 FFA1R WRP2 FTSR RIR EP0R CNTH CR1 RESP4 RESERVED2 power_save RESERVED0 SQR2 DCR FR2 BRR RDHR RTSR DCOUNT TRISE CR2 DR7 RCR FS1R TIR
+syn keyword CTagsMember SR1 DIVL APB2ENR CCR3 AR CNT ARR EP7R RESERVED7 pllq SQR1 EXTICR apb2_freq HTR CCMR2 DLEN IER CMD DTIMER CCR2 CFGR ISTR RESERVED5 RESPCMD pllr OAR2 CCMR1 KR RF1R pllm EP2R OR SMPR2 STA TXCRCR FNR RTCCR TSR DR5 SR sFilterRegister SR2 IMR FR1 DR8 DR6 TDLR ESR WRPR CR3 ARG WRP3 BDTR DIER OPTKEYR RESERVEDA EP3R IFCR LCKR DMAR RESERVED1 RXCRCR IDCODE CIR EP6R FM1R sFIFOMailBox RESERVED6 DR2 JSQR DADDR apb2_timer_freq ppre2 WRP1 DIVH ODR DR4 USER DR3 POWER ICR OAR1 CCR4 RESERVED4 EMR CNTR
+syn keyword CTagsMember DR1 BTR ALRL RESERVEDB KEYR RLR Data0 RDLR SWIER ahb_freq MAPR flash_cfg APB2RSTR EP5R ACR CSR BDCR CNDTR APB1ENR DR9 EGR hpre RESERVED9 APB1RSTR MASK TDTR CLKCR apb1_timer_freq RESERVED TDHR MAPR2 ALRH pllp PRLL
+syn keyword CTagsGlobalVariable callback4 callback3 io_cb callback2 _clock_config val sysclks
+syn keyword CTagsEnumeratorName __anon571959e70103 __anonbccbea710203 __anonbccbea710303 __anonbccbea710103 rcc_osc __anon72c4c37e0103 Clock_config
+syn keyword CTagsEnumerationValue ADC1_2_IRQn EXTI15_10_IRQn PendSV_IRQn RTC_IRQn SVCall_IRQn CLOCK_CONFIG_PERFORMANCE TAMPER_IRQn I2C1_ER_IRQn USBWakeUp_IRQn USART2_IRQn TIM1_CC_IRQn TIM2_IRQn EXTI9_5_IRQn USB_LP_CAN1_RX0_IRQn TIM1_UP_IRQn DMA1_Channel2_IRQn ENABLE I2C1_EV_IRQn TIM4_IRQn CLOCK_CONFIG_POWERSAVE CLOCK_CONFIG_HSE_96MHz EXTI1_IRQn HardFault_IRQn MemoryManagement_IRQn RCC_IRQn DebugMonitor_IRQn USART1_IRQn USART3_IRQn BusFault_IRQn NonMaskableInt_IRQn I2C2_EV_IRQn RCC_PLL DMA1_Channel6_IRQn
+syn keyword CTagsEnumerationValue TIM1_BRK_IRQn CAN1_RX1_IRQn CLOCK_CONFIG_HSI_16MHz RTC_Alarm_IRQn RCC_LSI CLOCK_CONFIG_HSE_84MHz PVD_IRQn CLOCK_CONFIG_HSI_48MHz RCC_LSE USB_HP_CAN1_TX_IRQn CLOCK_CONFIG_HSE_48MHz RCC_HSI SPI2_IRQn EXTI4_IRQn TIM1_TRG_COM_IRQn UsageFault_IRQn FLASH_IRQn ERROR I2C2_ER_IRQn DISABLE SysTick_IRQn SPI1_IRQn CLOCK_CONFIG_HSE_8MHz RCC_HSE SUCCESS CLOCK_CONFIG_HSI_96MHz RESET CAN1_SCE_IRQn CLOCK_CONFIG_END DMA1_Channel1_IRQn EXTI3_IRQn RCC_PLLI2S CLOCK_CONFIG_HSI_84MHz WWDG_IRQn
+syn keyword CTagsEnumerationValue SET DMA1_Channel4_IRQn DMA1_Channel5_IRQn EXTI0_IRQn EXTI2_IRQn DMA1_Channel3_IRQn TIM3_IRQn DMA1_Channel7_IRQn
+syn keyword CTagsFunction SVC_Handler EXTI15_10_IRQHandler TIM3_IRQHandler io_write EXTI3_IRQHandler DebugMon_Handler EXTI4_IRQHandler TIM2_IRQHandler rcc_set_sysclk timer_start io_set SystemInit EXTI2_IRQHandler io_read timer_stop SysTick_Handler rcc_config_clock MemManage_Handler EXTI0_IRQHandler io_configure timer_tick_period PendSV_Handler timer_tick_init HardFault_Handler main io_clear BusFault_Handler UsageFault_Handler timeout_cb TIM4_IRQHandler EXTI1_IRQHandler EXTI9_5_IRQHandler io_write_n
+syn keyword CTagsFunction rcc_osc_on rcc_osc_off NMI_Handler
+syn keyword CTagsType FunctionalState ADC_TypeDef CAN_TypeDef IWDG_TypeDef EXTI_TypeDef CAN_FIFOMailBox_TypeDef RTC_TypeDef SDIO_TypeDef I2C_TypeDef IRQn_Type DBGMCU_TypeDef CAN_TxMailBox_TypeDef Clock_t ITStatus FlagStatus DMA_TypeDef TIM_TypeDef USART_TypeDef OnTick WWDG_TypeDef USB_TypeDef GPIO_TypeDef CAN_FilterRegister_TypeDef CRC_TypeDef BKP_TypeDef DMA_Channel_TypeDef ErrorStatus RCC_TypeDef SPI_TypeDef AFIO_TypeDef PWR_TypeDef ADC_Common_TypeDef FLASH_TypeDef OB_TypeDef OnIO
+syn keyword CTagsDefinedName CAN_F6R1_FB13 TIM_CCMR2_OC3PE CAN_F0R2_FB5_Pos CAN_TI0R_TXRQ_Pos CAN_F12R1_FB25 CAN_F13R1_FB7 I2C_CR1_START_Pos GPIO_LCKR_LCK6 GPIO_LCKR_LCK1_Pos ADC_SQR3_SQ4_Msk I2C_CR2_FREQ_3 CAN_TDL2R_DATA2_Msk AFIO_EVCR_PIN_PX11 CAN_F5R1_FB3_Pos CAN_F12R2_FB17 EXTI_EMR_EM14 ADC_DR_ADC2DATA RCC_APB2ENR_IOPDEN_Pos CAN_F3R1_FB18_Msk CAN_F10R2_FB10_Pos CAN_RDT1R_TIME_Msk USB_EP4R_EA_Msk EXTI_RTSR_TR10_Pos ADC_SQR2_SQ7_2 BKP_CSR_TIF_Msk TIM_CCMR1_IC1F_Pos USB_EPADDR_FIELD_Msk CAN_F1R2_FB30_Pos
+syn keyword CTagsDefinedName CAN_F8R1_FB0_Msk CAN_F5R2_FB15_Msk CAN_TDH2R_DATA4_Msk ADC_SQR2_SQ8_3 SPI2_BASE CAN_ESR_BOFF_Pos CAN_TDH2R_DATA5_Pos EXTI_RTSR_TR2_Msk SPI_CR1_CRCNEXT_Pos DBGMCU_CR_DBG_STOP_Pos ADC_JSQR_JSQ3_3 RCC_CIR_HSERDYC ADC_JDR3_JDATA_Msk CAN_F3R1_FB15 CAN_F8R1_FB27 DMA_IFCR_CTCIF4_Msk CAN_F3R1_FB11 CAN_F5R1_FB12 AFIO_EVCR_PORT_PD CAN_F11R1_FB10 RTC_CRL_SECF_Pos EXTI_PR_PR0_Msk CAN_F11R2_FB10 CAN_F1R1_FB24_Pos I2C_CR1_PE_Pos CAN_F6R2_FB2 I2C_CR1_SMBTYPE CAN_F8R2_FB20_Msk GPIO_LCKR_LCK10
+syn keyword CTagsDefinedName CAN_F4R1_FB0_Pos CAN_F10R1_FB1 USART_CR1_UE_Pos SPI_SR_OVR_Pos SDIO_STA_TXFIFOF_Pos CAN_F0R1_FB20 ADC_LTR_LT CAN_F7R1_FB3_Msk EXTI_SWIER_SWIER12_Msk CAN_F11R2_FB2_Pos GPIO_CRL_CNF4_0 RCC_CSR_WWDGRSTF_Msk SDIO_MASK_CMDACTIE_Msk RTC_CRL_CNF_Pos CAN_RI0R_IDE SDIO_STA_RXOVERR CAN_F2R1_FB31_Msk CAN_RDT1R_FMI CAN_F9R1_FB19 AFIO_EXTICR4_EXTI13_PE_Msk TIM_SR_UIF CAN_F5R2_FB30 CAN_TDH1R_DATA7_Msk CAN_F12R1_FB12_Msk CAN_F7R2_FB21 SDIO_CMD_WAITRESP CAN_F10R2_FB29_Pos FLASH_BASE
+syn keyword CTagsDefinedName USB_COUNT6_RX_1_NUM_BLOCK_1_1 CAN_F12R2_FB30_Pos CAN_FFA1R_FFA13_Pos CAN_F5R2_FB19 CAN_F4R1_FB7 SPI_SR_UDR_Msk EXTI_RTSR_TR4 AFIO_EXTICR4_EXTI13_PB_Msk AFIO_EXTICR2_EXTI5_PB_Pos CAN_FA1R_FACT8_Msk CAN_F12R1_FB20_Msk CAN_TDT2R_DLC USB_ADDR1_RX_ADDR1_RX EXTI_SWIER_SWIER4 EXTI_FTSR_FT12 EXTI_SWIER_SWIER11 IS_TIM_ETR_INSTANCE RCC_CFGR_PLLMULL7_Msk USB_COUNT3_TX_COUNT3_TX_Msk USB_COUNT4_RX_0_NUM_BLOCK_0_1 CAN_F1R2_FB27_Pos CAN_F5R1_FB25_Msk CAN_RDL1R_DATA2_Pos GPIO_CRH_CNF10_Pos
+syn keyword CTagsDefinedName CAN_F2R1_FB11 USB_COUNT1_RX_BLSIZE CAN_F5R1_FB7_Pos ADC2 USB_FNR_LSOF CAN_F8R1_FB3 SDIO_MASK_TXFIFOHEIE_Msk CAN_F2R2_FB13 TIM_CCER_CC3NP_Pos USB_COUNT4_RX_NUM_BLOCK_Pos RCC_APB2ENR_IOPDEN USB_COUNT3_RX_COUNT3_RX_Pos CAN_F5R1_FB26_Pos RCC_CFGR_MCO_Msk CAN_F5R2_FB30_Msk I2C_SR2_BUSY_Msk RCC_CSR_RMVF_Pos CAN_F5R1_FB2 __NVIC_PRIO_BITS CAN_F5R1_FB31_Pos CAN_F9R1_FB14_Pos USB_COUNT1_RX_1_BLSIZE_1 CAN_F11R2_FB7_Msk USB_FNR_LCK_Msk GPIO_CRL_CNF2 USB_COUNT4_RX_NUM_BLOCK_0 CAN_F10R1_FB22
+syn keyword CTagsDefinedName CAN_F9R2_FB10 CAN_F12R2_FB25 CAN_F0R1_FB1 FLASH_WRP0_WRP0_Msk ADC_HTR_HT_Msk TIM_CR1_DIR_Pos PWR_CR_CSBF_Msk DBGMCU_CR_DBG_TIM1_STOP_Msk ADC_SQR1_SQ13_4 CAN_TDT1R_DLC RCC_APB1ENR_TIM2EN_Msk CAN_F9R1_FB0_Msk TIM_EGR_CC2G_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_0 USB_EP2R_CTR_RX_Msk GPIO_BSRR_BR12_Pos CAN_F12R1_FB5_Msk RCC_APB1ENR_TIM3EN_Msk CAN_F8R2_FB5 DMA1_Channel4 CAN_TDL1R_DATA0_Msk EXTI_RTSR_TR11_Pos CAN_F13R1_FB7_Pos PIN_OPT_AF14 TIM_EGR_CC2G_Msk CAN_F8R2_FB21 CAN_F12R1_FB17
+syn keyword CTagsDefinedName RCC_APB1ENR_I2C1EN_Msk PWR_CR_PLS_LEV0 RCC_APB1RSTR_I2C2RST_Pos CAN_F3R2_FB15 EXTI_SWIER_SWIER0_Msk CAN_F11R1_FB18 CAN_F8R1_FB21 CAN_MCR_RESET_Msk FLASH_RDP_RDP_Pos USB_ISTR_SUSP_Msk CAN_F0R1_FB24_Pos TIM_CCMR1_OC1M_2 AFIO_EVCR_PIN_PX3_Pos DMA_ISR_TEIF3_Pos USB_COUNT4_RX_NUM_BLOCK_1 DMA_ISR_GIF5_Msk CAN_F2R1_FB0_Pos SDIO_MASK_RXOVERRIE CAN_F10R2_FB14 CAN_F10R2_FB0 EXTI_SWIER_SWIER16_Msk I2C_TRISE_TRISE_Pos CAN_F11R1_FB0_Pos EXTI_SWIER_SWIER17_Msk CAN_RI0R_STID TIM_CCER_CC1E_Pos
+syn keyword CTagsDefinedName CAN_F9R2_FB28 GPIO_CRL_CNF3_Msk BKP_CSR_TPIE_Pos CAN_F13R2_FB7_Msk CAN_F9R2_FB1_Msk CAN_F9R1_FB11_Pos CAN_F5R2_FB11_Pos RCC_CFGR_PLLMULL8 CAN_F2R1_FB15 CAN_F13R2_FB28 CAN_ESR_LEC_2 AFIO_EXTICR4_EXTI14_PE_Pos I2C3_IRQ_PRIORITY CAN_F1R1_FB7 CAN_F2R1_FB6 CAN_F4R1_FB15_Msk TIM_SMCR_ETF_3 RCC_CIR_LSERDYIE_Msk SPI_DR_DR_Msk BKP_DR3_D_Pos SDIO_CLKCR_WIDBUS_1 AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk CAN_F3R1_FB12_Msk USB_EP1R_SETUP_Pos SDIO_CMD_WAITINT_Msk GPIO_CRH_CNF_Pos
+syn keyword CTagsDefinedName CAN_F0R1_FB5_Pos CAN_F7R1_FB18_Pos CAN_F13R2_FB27_Pos ADC_JSQR_JSQ1_3 SDIO_CMD_SDIOSUSPEND_Pos GPIO_ODR_ODR1_Pos SDIO_MASK_DTIMEOUTIE_Msk EXTI_RTSR_TR11_Msk AFIO_EXTICR4_EXTI14_PA CAN_FFA1R_FFA9_Pos CAN_F11R2_FB13_Msk CAN_RDH0R_DATA7 CAN_F0R2_FB12_Pos TIM_DIER_COMIE_Msk USB_EP0R_EA_Pos AFIO_EXTICR4_EXTI13 GPIO_IDR_IDR15_Msk AFIO_MAPR_TIM2_REMAP DMA_ISR_TCIF6_Pos SDIO_CMD_CMDINDEX_Pos CAN_F3R2_FB4_Pos TIM_SMCR_ETF_1 ADC_CR2_EXTSEL CAN_F8R2_FB30 USB_EP7R_CTR_RX_Pos
+syn keyword CTagsDefinedName RCC_APB1RSTR_USART3RST_Pos RCC_CIR_LSIRDYF CAN_FS1R_FSC9 DMA_CCR_PSIZE CAN_F1R2_FB25_Msk CAN_F3R2_FB18_Pos RCC_CFGR_PLLMULL11_Msk ADC_CR2_EXTSEL_2 PWR_CR_PDDS SPI_CR1_SSI_Msk I2C_CR1_SWRST_Msk SPI_CR1_BR_Msk GPIO_BSRR_BS10_Msk I2C_CR1_ENPEC_Msk I2C_OAR1_ADDMODE_Pos TIM_CCR4_CCR4 APB1PERIPH_BASE DMA_ISR_GIF1 CAN_F1R1_FB6 DMA_ISR_HTIF6 GPIO_ODR_ODR11_Msk CAN_TDL0R_DATA1_Pos GPIOA_BASE CAN_F12R1_FB27_Msk CAN_FS1R_FSC5 EXTI_PR_PR2 PWR_CSR_WUF_Pos TIM_CCMR1_OC2CE_Msk EXTI_PR_PR8
+syn keyword CTagsDefinedName WWDG_SR_EWIF_Msk USB_COUNT5_RX_NUM_BLOCK_3 CAN1_RX0_IRQHandler CAN_F10R1_FB18_Pos CAN_F11R1_FB6 SDIO_STA_CMDSENT USB_EP_TYPE_MASK_Pos CAN_F12R2_FB7_Msk TIM_SR_CC1IF_Pos DMA_ISR_HTIF6_Pos RCC_CSR_PINRSTF_Msk SDIO_MASK_CCRCFAILIE EXTI_PR_PR11_Pos TIM_CCER_CC4P RCC_APB1ENR_USART3EN_Msk CAN_F5R1_FB5_Pos USB_COUNT4_RX_COUNT4_RX_Pos USB_COUNT6_RX_COUNT6_RX_Msk EXTI_SWIER_SWI10 TIM_BDTR_MOE_Msk TIM11_IRQHandler SDIO_ARG_CMDARG_Pos CAN_F12R1_FB23_Msk GPIO_CRL_CNF7_Pos
+syn keyword CTagsDefinedName AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk FLASH_ACR_LATENCY_0 RCC_APB1RSTR_CAN1RST_Pos IS_GPIO_ALL_INSTANCE CAN_F10R2_FB21_Pos GPIO_CRL_CNF7_Msk CAN_F5R1_FB9_Pos CAN_F7R2_FB19_Msk RCC_APB1ENR_I2C2EN_Msk CRC_CR_RESET EXTI_EMR_MR8_Msk WWDG_BASE ADC_SMPR1_SMP11_1 CAN_F10R2_FB3 CAN_F3R2_FB12 PIN_OPT_IRQ_EDGE_RISE GPIO_BSRR_BR3_Pos RCC_CFGR_SW_Pos CAN_F13R1_FB13_Msk CAN_F7R1_FB12_Msk RCC_CFGR_HPRE_1 ADC_CR1_JEOSIE EXTI_FTSR_TR5_Pos RCC_CIR_HSIRDYC_Pos DBGMCU_CR_DBG_WWDG_STOP_Msk
+syn keyword CTagsDefinedName USB_CNTR_FSUSP_Pos SDIO_ICR_DBCKENDC_Pos CAN_F10R2_FB10_Msk TIM_CCR2_CCR2_Msk USB_COUNT7_RX_NUM_BLOCK_1 USART_GTPR_PSC_6 CAN_F4R2_FB25_Pos CAN_RDH1R_DATA5_Msk USB_FNR_RXDP_Pos USB_EP4R_EP_KIND_Msk ADC_SMPR1_SMP10_Pos CAN_F2R1_FB16_Pos USART_SR_IDLE_Pos TIM_DIER_COMDE_Pos SDIO_MASK_CMDSENTIE_Pos CAN_F0R2_FB8 SDIO_MASK_SDIOITIE_Pos SDIO_CLKCR_CLKDIV_Msk EXTI_FTSR_FT0 AFIO_EXTICR4_EXTI12_PD EXTI_RTSR_TR10_Msk CAN_F1R1_FB26_Pos USART_SR_IDLE_Msk CAN_F5R1_FB16_Msk
+syn keyword CTagsDefinedName RCC_APB1RSTR_PWRRST_Pos RCC_CFGR_PLLMULL8_Pos CAN_F11R2_FB18 USB_EP2R_STAT_RX_Pos CAN_F7R1_FB25 EXTI_PR_PR9 TIM_BDTR_BKE CAN_F10R1_FB13_Pos FLASH_OBR_USER_Pos RCC_APB1RSTR_USBRST_Pos GPIO_BRR_BR12_Msk GPIO_CRH_CNF14_Pos CAN_F8R2_FB10_Msk PIN_OPT_AF7 IS_DMA_ALL_INSTANCE GPIO_CRH_CNF14_0 ADC_SMPR1_SMP17_1 SDIO_STA_TXFIFOF_Msk CAN_F13R2_FB18 CAN_F6R1_FB23_Pos TIM_CCMR2_OC3CE CAN_BTR_TS1_2 DMA_ISR_TCIF1_Pos TIM_CR2_OIS4 EXTI_PR_PR1 I2C_CR1_ACK_Msk RCC_APB2ENR_USART1EN_Msk
+syn keyword CTagsDefinedName TIM_DCR_DBL_1 RCC_CFGR_PPRE_DIV_2 CAN_F13R1_FB11_Pos RCC_CFGR_MCO_Pos CAN_F3R2_FB31_Pos TIM_SR_CC1OF_Msk USB_ADDR2_TX_ADDR2_TX_Pos USART_CR2_STOP ADC_SQR2_SQ7_Msk I2C_CR1_SWRST_Pos CAN_TI2R_RTR AFIO_EXTICR4_EXTI15_Pos CAN_F6R1_FB14_Pos EXTI_PR_PR3 USB_COUNT7_RX_0_COUNT7_RX_0 USART_CR3_DMAT_Msk CAN_FMR_FINIT_Msk CAN_F5R1_FB17_Msk CAN_F13R1_FB22_Pos CAN_F5R1_FB19 USART_CR1_TE_Pos BKP_DR5_D_Msk CAN_F8R1_FB22_Pos RCC_APB2RSTR_IOPCRST_Pos RCC_CFGR_PPRE_DIV_4 CAN_F8R2_FB22_Msk
+syn keyword CTagsDefinedName GPIO_CRH_CNF12_0 CAN_F5R1_FB22_Msk AFIO_EXTICR4_EXTI15_PB_Msk I2C_SR2_PEC_Pos SDIO_STA_CCRCFAIL_Msk ADC_SQR1_SQ16_1 CAN_F13R1_FB10_Msk USB_EP1R_STAT_RX CAN_F4R2_FB18 EXTI_SWIER_SWIER18 RCC_CFGR_PLLMULL3 USB_EP6R_SETUP AFIO_MAPR_SWJ_CFG_0 CAN_F5R2_FB1_Pos AFIO_MAPR_SPI1_REMAP_Pos CAN_F11R2_FB3_Pos CAN_F12R1_FB11_Pos USB_EP_INTERRUPT SDIO_CLKCR_PWRSAV_Pos CAN_F12R2_FB23 CAN_F2R2_FB14_Msk BKP_RTCCR_ASOE CAN_F0R2_FB28_Msk TIM_SR_TIF_Pos CAN_MSR_SAMP_Msk USB_COUNT3_RX_NUM_BLOCK_Msk
+syn keyword CTagsDefinedName CAN_F9R2_FB6 TIM_CCR1_CCR1_Pos IS_UART_HWFLOW_INSTANCE USB_EP5R_SETUP_Pos GPIO_CRH_MODE9_Pos CAN_F12R2_FB18 CAN_F13R1_FB21_Pos EXTI_FTSR_TR0_Pos BKP_RTCCR_ASOS_Msk CAN_F1R2_FB14_Pos AFIO_MAPR_PD01_REMAP RCC_CFGR_MCO_HSI DMA_ISR_HTIF4_Pos CAN_F10R2_FB24_Msk CAN_F9R1_FB30_Msk GPIO_BSRR_BR8_Pos CAN_F3R1_FB30_Pos CAN_IER_ERRIE_Msk CAN_RDL0R_DATA2_Msk DMA_ISR_TEIF5_Pos EXTI_FTSR_TR0 CAN_F9R1_FB31_Pos RCC_CSR_WWDGRSTF CAN_F1R1_FB2 CAN_FS1R_FSC0_Msk USB_EP0R_EP_TYPE_Pos
+syn keyword CTagsDefinedName DMA_IFCR_CTEIF2_Msk CAN_F7R1_FB6_Pos USB_COUNT0_RX_NUM_BLOCK CAN_F10R1_FB13 GPIO_BSRR_BS14_Pos SPI_SR_UDR_Pos CAN_F2R1_FB13_Msk RCC_CFGR_PLLMULL10_Msk USB_EP5R_STAT_RX_1 USB_EP2R_DTOG_RX_Msk CAN_F4R1_FB20_Pos SDIO_CLKCR_BYPASS_Msk ADC_JSQR_JSQ2_Pos AFIO_EXTICR4_EXTI12_PD_Pos CAN_F12R1_FB21_Pos USB_COUNT7_RX_0_NUM_BLOCK_0 CAN_F3R2_FB29_Pos GPIO_LCKR_LCK14 ADC_SQR3_SQ2 GPIO_CRH_MODE10_Pos GPIO_ODR_ODR0_Pos CAN_F4R2_FB4_Pos GPIO_BSRR_BS0_Msk RCC_CR_PLLON_Pos USB_EP6R CAN_FS1R_FSC2
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI15_PC_Msk CAN_F7R2_FB10_Msk TIM_CR1_UDIS_Pos USB_COUNT6_RX_NUM_BLOCK_2 CAN_F6R2_FB24_Pos CAN_TSR_ABRQ0_Msk USB_EP4R USB_EP5R_EP_TYPE CAN_F12R2_FB23_Msk CAN_MSR_SLAKI_Msk CAN_F7R2_FB7 SDIO_MASK_RXFIFOEIE_Msk USART_CR3_IREN_Msk AFIO_EXTICR1_EXTI0_PC_Msk SDIO_DCTRL_DTMODE RCC_APB2ENR_ADC1EN_Pos SPI_CR2_RXNEIE_Pos TIM_CR1_CKD_Msk ADC_JSQR_JSQ3 CAN_FMR_FINIT CAN_F6R2_FB25_Pos EXTI_RTSR_TR4_Pos CAN_F11R1_FB5_Pos RCC_CFGR_HPRE_DIV_NONE EXTI_EMR_MR10
+syn keyword CTagsDefinedName EXTI_SWIER_SWIER9_Msk USB_BTABLE_BTABLE_Pos CAN_F6R2_FB12_Msk CAN_F1R1_FB8_Pos TIM_DCR_DBA_Pos FLASH_SR_WRPRTERR ADC_CR2_JEXTSEL_Msk EXTI_SWIER_SWIER1_Pos CAN_F13R2_FB13 EXTI_EMR_MR14 TIM_SMCR_SMS ADC_JSQR_JSQ3_Msk USB_COUNT2_TX_COUNT2_TX_Msk USB_EP1R_STAT_RX_1 CAN_F10R2_FB28_Pos RTC_CRL_RTOFF_Msk TIM_CCMR1_IC2F_2 RCC_CFGR_PLLMULL8_Msk RCC_APB1ENR_USART3EN RCC_CFGR_SWS_Pos FLASH_KEYR_FKEYR_Pos I2C_OAR1_ADD8 CAN_F10R2_FB16 DMA_IFCR_CGIF1_Msk SDIO_STA_RXFIFOF EXTI_IMR_MR9_Pos
+syn keyword CTagsDefinedName USB_EP0R_SETUP_Msk TIM_CCER_CC2NP TIM_CCER_CC1NP_Pos CAN_FM1R_FBM8_Msk CAN_FA1R_FACT3_Pos CAN_F9R1_FB28_Pos CAN_F7R1_FB22_Pos RCC_CFGR_MCOSEL_PLL_DIV2 CAN_F9R1_FB21_Pos DMA_IFCR_CGIF3_Pos AFIO_EXTICR1_EXTI2_PC_Msk SDIO_BASE CAN_F5R1_FB16 RCC_APB1ENR_BKPEN_Pos CAN_F5R1_FB6 CAN_F8R1_FB26 USB_COUNT7_RX_COUNT7_RX_Pos TIM10_IRQHandler SDIO_MASK_TXDAVLIE BKP_RTCCR_CCO CAN_F6R1_FB28_Pos AFIO_EVCR_PIN_PX3_Msk GPIO_BRR_BR9_Msk CAN_F9R2_FB2_Msk CAN_TSR_LOW0_Msk AFIO_EXTICR3_EXTI10_PC_Pos
+syn keyword CTagsDefinedName I2C_SR2_PEC USART_BRR_DIV_Mantissa_Msk CAN_F11R1_FB8 CAN_F3R1_FB20 USB_DADDR_ADD1_Pos RCC_CR_HSEBYP_Pos AFIO_EXTICR1_EXTI1_PC_Pos EXTI_SWIER_SWI15 CAN_F9R2_FB14 CAN_F2R1_FB7 CAN_FA1R_FACT4_Msk RCC_AHBENR_DMA1EN_Msk AFIO_EXTICR1_EXTI3_PB CAN_F1R1_FB22_Msk CAN_F1R1_FB13_Pos ADC_CR2_JEXTTRIG_Msk USB_EP2R_CTR_RX_Pos CAN_F12R2_FB1 TIM_CCMR2_IC4PSC_0 AFIO_MAPR_SWJ_CFG_DISABLE_Msk AFIO_EXTICR1_EXTI3_PF_Pos CAN_TI1R_STID_Msk RCC_APB2RSTR_IOPERST DMA_ISR_TEIF7_Pos CAN_F7R1_FB20_Pos
+syn keyword CTagsDefinedName USB_EP3R_CTR_RX_Msk CAN_F4R2_FB18_Pos CAN_F1R1_FB17_Msk CAN_FM1R_FBM12 CAN_F5R2_FB28 CAN_F6R1_FB13_Msk SDIO_ICR_CCRCFAILC ADC_SMPR2_SMP2_Pos USB_COUNT1_RX_BLSIZE_Pos CAN_F12R1_FB6_Pos USB_DADDR_ADD0_Msk CAN_FS1R_FSC1_Msk DMA_CCR_HTIE_Msk AFIO_EXTICR4_EXTI13_PF_Pos CAN_F8R2_FB16_Msk CAN_F13R1_FB15_Msk GPIO_CRH_MODE12_1 CAN_F12R1_FB2_Msk CAN_F9R1_FB22 CAN_F4R1_FB17_Msk EXTI_IMR_MR16 CAN_F5R2_FB2_Pos CAN_F6R1_FB0_Msk DBGMCU_CR_DBG_TIM3_STOP_Pos GPIO_IDR_IDR9_Pos CAN_F13R2_FB14_Msk
+syn keyword CTagsDefinedName CAN_F3R1_FB14 RCC_CR_HSITRIM_Msk CAN_FA1R_FACT0_Pos EXTI_PR_PR8_Pos CAN_RF0R_FOVR0 CAN_F5R2_FB21_Msk RCC_CFGR_PLLMULL_Msk CAN_F4R2_FB10 CAN_F5R1_FB13_Msk IS_TIM_CC1_INSTANCE RCC_CSR_LPWRRSTF_Msk CAN_TI2R_EXID USART_CR1_IDLEIE_Pos AFIO_EXTICR4_EXTI14_PC CAN_F9R1_FB6 TIM_CCER_CC3P CAN_F9R1_FB18_Pos AFIO_EXTICR1_EXTI2_PD_Msk SDIO_STA_CMDACT CAN_RF0R_FMP0_Msk CAN_F13R2_FB12 CAN_F6R2_FB29 USB_CNTR_PDWN RCC_APB2RSTR_IOPBRST_Pos SDIO_ICR_DATAENDC_Pos AFIO_EXTICR1_EXTI3_PF_Msk
+syn keyword CTagsDefinedName CAN_F9R2_FB20 RCC_APB1ENR_I2C1EN CAN_F8R1_FB12_Pos EXTI_RTSR_TR14 GPIO_BRR_BR9 CAN_TSR_TXOK0 ADC_JDR4_JDATA_Msk ADC_SMPR2_SMP2_1 ADC_SR_EOS WWDG_CR_T_Pos CAN_F10R1_FB25_Pos EXTI_IMR_MR3_Pos SDIO_STA_RXACT FLASH_KEY1 CAN_F2R1_FB2_Msk DMA1_Channel2 CAN_F2R1_FB13 USB_EP6R_EP_KIND CAN_F3R1_FB29 CAN_TDH0R_DATA4 ADC_SQR1_SQ13_2 CAN_F12R1_FB30_Pos RTC_CNTH_RTC_CNT_Msk USB_COUNT3_RX_NUM_BLOCK_0 USB_ADDR7_RX_ADDR7_RX_Pos RCC_CFGR_PLLMULL3_Msk CAN_F7R1_FB10 DBGMCU_CR_DBG_TIM1_STOP_Pos
+syn keyword CTagsDefinedName ADC_SMPR1_SMP15 ADC_JOFR2_JOFFSET2 CAN_F1R1_FB10_Msk FLASH_SR_PGERR_Msk ADC_CR2_JSWSTART CAN_F0R1_FB8_Pos CAN_F8R1_FB10_Pos IS_TIM_SLAVE_INSTANCE AFIO_EVCR_PIN_PX5_Msk EXTI_IMR_IM3 SDIO_MASK_CMDRENDIE EXTI_SWIER_SWIER6_Msk CAN_F11R2_FB11_Msk DBGMCU_IDCODE_REV_ID_9 CAN_F13R2_FB17_Pos EXTI_RTSR_TR12_Pos CAN_F8R1_FB14 CAN_F7R1_FB21_Msk I2C_SR1_OVR_Pos CAN_FFA1R_FFA0_Msk IS_IWDG_ALL_INSTANCE EXTI_RTSR_TR0 USART_SR_RXNE_Msk ADC_JSQR_JSQ2_3 CAN_F7R1_FB0_Msk CAN_F1R1_FB2_Msk
+syn keyword CTagsDefinedName EXTI_EMR_MR10_Pos RTC_ALRH_RTC_ALR CAN_F1R2_FB1_Msk TIM_SMCR_ETPS_0 USB_EP6R_STAT_RX_1 EXTI_SWIER_SWIER10 USART_CR2_LBDIE_Pos AFIO_MAPR_USART3_REMAP_Msk CAN_F7R1_FB27 DMA_ISR_TEIF2_Msk IWDG_PR_PR_2 DMA_ISR_HTIF5 CAN_RF0R_FULL0_Msk TIM_CR2_OIS1_Pos CAN_F9R1_FB10_Pos GPIO_CRH_CNF15_Msk GPIO_BRR_BR10_Pos CAN_F5R2_FB6_Pos TIM_CCER_CC2P_Pos CAN_F1R2_FB18 CAN_F4R1_FB23 RCC_APB1RSTR_TIM2RST_Msk I2C_SR2_TRA_Pos FLASH_CR_STRT_Msk CAN_F11R1_FB15_Msk CAN_FM1R_FBM11_Pos ADC_JSQR_JSQ4_Pos
+syn keyword CTagsDefinedName GPIO_IDR_IDR10_Msk AFIO_EXTICR1_EXTI3_PG_Pos SDIO_RESP1_CARDSTATUS1_Msk SPI_CR1_CRCNEXT RCC_BDCR_BDRST DMA_ISR_TEIF4_Msk CAN_F12R2_FB29 DMA_ISR_HTIF7_Pos CAN_FS1R_FSC7 PIN_OPT_OUTPUT_SPEED_MEDIUM I2C_SR1_AF_Msk CAN_F10R2_FB11_Msk CAN_F4R1_FB4 CAN_F13R1_FB2_Msk AFIO_EXTICR3_EXTI9_PA GPIO_CRL_MODE5_0 TIM_EGR_CC4G_Pos USB_CNTR_CTRM SDIO_DCOUNT_DATACOUNT SPI_SR_CRCERR_Msk CAN_F2R2_FB1_Pos USB_EP5R_STAT_TX_Msk DMA_IFCR_CTEIF4 EXTI_EMR_EM9 CAN_F5R1_FB6_Msk FLASH_WRP3_WRP3_Pos
+syn keyword CTagsDefinedName CAN_F4R2_FB31 RCC_APB1ENR_BKPEN ADC_SQR1_SQ16_0 CAN_F7R2_FB24_Pos CAN_F12R1_FB25_Msk CAN_F12R1_FB5_Pos CAN_F8R1_FB8_Msk AFIO_EXTICR1_EXTI1_PE_Pos CAN_F0R2_FB9_Pos USB_DADDR_ADD5 CAN_F9R1_FB31 EXTI_IMR_MR7_Msk CAN_F5R1_FB11_Pos TIM_BDTR_DTG_4 CAN_F4R1_FB7_Pos CAN_F7R1_FB16_Msk ADC_JSQR_JSQ4_Msk CAN_F8R1_FB15_Pos CAN_F9R1_FB8_Pos SPI_SR_OVR_Msk RCC_CIR_CSSC TIM_BDTR_DTG_Msk CAN_TDL2R_DATA2 AFIO_EVCR_PORT_PE CAN_F8R1_FB18 GPIO_BRR_BR6_Msk CAN_F12R2_FB15_Msk CAN_F2R2_FB16_Pos
+syn keyword CTagsDefinedName SPI_CR1_LSBFIRST_Msk CAN_F9R1_FB30_Pos EXTI_SWIER_SWI17 SDIO_MASK_CMDACTIE SDIO_FIFO_FIFODATA_Pos CAN_F8R1_FB10_Msk USB_ADDR2_TX_ADDR2_TX_Msk AFIO_EXTICR3_EXTI8_PA USB_EP5R_CTR_RX_Pos USB_COUNT6_RX_COUNT6_RX_Pos TIM_CCMR2_IC3PSC_Pos CAN_F10R2_FB7_Pos CAN_F4R1_FB27 I2C_CR1_NOSTRETCH_Msk CAN_FM1R_FBM9 CAN_TDT2R_TGT_Msk CAN_F8R2_FB15 CAN_F12R1_FB7 CAN_F4R1_FB23_Pos GPIO_CRL_CNF2_Pos USB_ISTR_PMAOVR_Pos FLASH_ACR_PRFTBS DMA_ISR_HTIF1_Pos CAN_F5R2_FB23_Msk CAN_F1R2_FB9_Pos
+syn keyword CTagsDefinedName CAN_F6R1_FB24_Msk USB_ISTR_RESET_Pos CAN_BTR_TS2 RCC_APB1ENR_BKPEN_Msk I2C_SR1_AF_Pos CAN_F5R2_FB3_Msk AFIO_EXTICR4_EXTI12_Msk CAN_F6R1_FB5_Msk USB_EP5R_STAT_TX_0 CAN_F12R1_FB26_Pos CAN_IER_FFIE0 RCC_CFGR_PLLMULL5 RCC_APB2RSTR_IOPERST_Msk EXTI_IMR_IM1 TIM_CR2_OIS3_Pos RCC_CFGR_PLLMULL13 CAN_F9R1_FB0 SDIO_MASK_TXFIFOEIE WWDG_CR_T TIM1_TRG_COM_TIM11_IRQHandler IS_TIM_CLOCK_DIVISION_INSTANCE USB_COUNT7_RX_0_BLSIZE_0 SDIO_FIFOCNT_FIFOCOUNT CAN_F8R1_FB1_Msk GPIO_IDR_IDR2_Msk
+syn keyword CTagsDefinedName SDIO_RESPCMD_RESPCMD_Msk CAN_F12R1_FB28_Msk CAN_RDH1R_DATA4_Msk CAN_F9R1_FB17_Msk IS_TIM_XOR_INSTANCE USB_EP6R_SETUP_Msk CAN_TDL0R_DATA3_Msk CAN_F2R2_FB4_Msk RCC_APB2ENR_IOPEEN_Msk USB_COUNT0_RX_BLSIZE_Msk DMA1_Channel7 RCC_CIR_CSSC_Msk EXTI_IMR_MR11 RTC_CRL_RSF_Msk CAN_F7R2_FB22_Msk RCC_CFGR_PLLMULL_0 TIM_CCMR2_OC4FE __STM32F1_CMSIS_VERSION_SUB1 IS_IRDA_INSTANCE CAN_F7R1_FB2_Pos ADC_SQR2_SQ9_Msk CAN_RDH1R_DATA5 CAN_F3R2_FB24_Pos EXTI_IMR_MR8_Pos CAN_F3R1_FB20_Msk
+syn keyword CTagsDefinedName TIM_CR2_OIS3N_Msk CAN_F6R2_FB22 USB_CNTR_ERRM_Pos AFIO_EXTICR4_EXTI15_PC_Pos AFIO_MAPR_TIM1_REMAP_0 USB_EP_CTR_RX_Msk SET_BIT GPIO_CRH_MODE8_Pos TIM_DIER_UIE PWR_CR_PLS_2V8 USART_BRR_DIV_Fraction_Pos TIM_CCER_CC3NP CAN_F2R2_FB6_Msk CAN_F6R1_FB6_Pos EXTI_EMR_MR17 CAN_F7R2_FB29_Msk USB_DADDR_EF_Pos CAN_F8R2_FB8 RCC_CFGR_PPRE1_DIV2 GPIO_CRL_MODE5_Msk CAN_F3R2_FB0_Pos CAN_F12R2_FB10_Msk CAN_F0R2_FB13_Pos CAN_F12R1_FB7_Msk USART_SR_ORE_Msk TIM_CCMR2_OC3CE_Pos TIM_CCMR2_OC3M
+syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI2_PE_Msk CAN_F3R1_FB20_Pos SYSCFG_EXTI_PH_MASK SPI_CR1_SSM_Pos EXTI_PR_PR14 RTC_CRL_ALRF_Pos CAN_F0R2_FB1_Msk SDIO_ICR_CTIMEOUTC_Msk CAN_F7R2_FB21_Msk CAN_FA1R_FACT9 CAN_F9R2_FB14_Pos SDIO_ICR_CEATAENDC_Msk USB_COUNT0_RX_NUM_BLOCK_3 I2C_SR1_SB_Pos TIM_DIER_CC2DE_Msk RCC_APB2ENR_IOPBEN EXTI_IMR_MR13_Msk CAN_TDL1R_DATA0 SDIO_CLKCR_WIDBUS_Msk ADC_SMPR2_SMP2_Msk CAN_F3R2_FB22_Msk CAN_F4R2_FB12 EXTI_IMR_MR12 FLASH_CR_ERRIE CAN_F7R2_FB28_Msk BKP_DR7_D_Pos
+syn keyword CTagsDefinedName DMA_IFCR_CHTIF2_Pos CAN_F9R1_FB27 CAN_F9R2_FB27_Msk DMA_ISR_TCIF3_Msk CAN_F12R2_FB14 ADC_SQR2_SQ10_Pos CAN_F3R1_FB7 CAN_FM1R_FBM0_Pos RCC_CFGR_SW_HSE CAN_F0R1_FB12 USB_EP_T_FIELD_Msk CAN_F5R2_FB22_Msk CAN_F3R2_FB27 AFIO_EXTICR3_EXTI11_PD_Msk I2C_CR1_ALERT_Pos IS_TIM_MASTER_INSTANCE CAN_F1R1_FB29 USB_EP1R ADC_CR1_AWDCH_2 CAN_F3R1_FB4_Pos CAN_F12R1_FB17_Pos ADC_JDR1_JDATA EXTI_IMR_IM17 GPIO_LCKR_LCK2_Pos AFIO_EXTICR4_EXTI13_PD_Pos DMA_CCR_MEM2MEM_Msk TIM_DMAR_DMAB_Msk
+syn keyword CTagsDefinedName CAN_F9R1_FB28_Msk USART_CR1_RE_Msk SDIO_MASK_RXDAVLIE_Pos CAN_F7R1_FB23 CAN_F10R2_FB23_Msk CAN_F0R2_FB9 ADC_JOFR4_JOFFSET4_Pos EXTI_RTSR_RT8 CAN_F9R1_FB19_Msk FLASH_WRP2_WRP2_Pos USB_EP1R_CTR_RX_Pos I2C_OAR1_ADD6 EXTI_RTSR_RT15 GPIO_CRL_MODE4_Pos TIM_CCER_CC3P_Msk CAN_F9R2_FB8_Msk CAN_F8R2_FB17_Pos CAN_F12R1_FB11_Msk SDIO_CMD_CPSMEN_Pos RCC_BDCR_LSEBYP_Msk CAN_F2R1_FB19_Msk GPIO_CRH_CNF13_Msk BKP_RTCCR_CAL I2C_OAR1_ADD0_Pos TIM_DCR_DBA_0 TIM1_BRK_TIM15_IRQHandler
+syn keyword CTagsDefinedName USB_EP7R_DTOG_RX_Pos RCC_APB1RSTR_USART2RST_Pos CAN_F13R2_FB8_Pos TIM_CCER_CC2P I2C_SR1_TXE_Msk I2C_OAR2_ENDUAL_Msk CAN_F5R2_FB8_Pos CAN_F10R1_FB24_Msk FLASH_CR_OPTPG_Msk USART_DR_DR_Pos CAN_F11R2_FB25_Pos CAN_F6R2_FB29_Pos TIM_CCMR1_CC2S_1 GPIO_CRH_MODE13_1 CAN_MCR_TTCM ADC_SQR2_SQ12_Msk CAN_FFA1R_FFA5_Pos CAN_F4R2_FB15 I2C_CR1_SWRST CAN_ESR_EWGF_Pos PIN_8 USB_EP5R_EA USB_COUNT5_RX_NUM_BLOCK_1 TIM_CCMR1_IC1F_2 CAN_F12R1_FB27_Pos EXTI_IMR_MR6_Msk SPI_SR_RXNE_Pos BKP_CSR_CTE_Msk
+syn keyword CTagsDefinedName ADC_SMPR1_SMP14_2 CAN_F9R2_FB25_Pos CAN_TI0R_STID_Msk ADC_SQR3_SQ1_0 CAN_F5R1_FB8_Msk CAN_F3R2_FB1 TIM_CCR4_CCR4_Msk CAN_F12R1_FB19_Pos USART_GTPR_PSC CAN_RDH1R_DATA6_Pos TIM_CCMR2_OC4M_2 ADC_SQR3_SQ2_0 CAN_F3R1_FB18 DMA_IFCR_CHTIF6_Pos AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos CAN_F3R2_FB15_Pos CAN_TDH2R_DATA4_Pos USART_BRR_DIV_Fraction_Msk CAN_F11R2_FB12_Msk CAN_F0R1_FB9_Pos EXTI_RTSR_TR18_Msk I2C_CR2_FREQ_Pos GPIO_CRL_MODE6 SPI_CR2_ERRIE_Msk ADC_SR_EOC AFIO_EVCR_PORT_0
+syn keyword CTagsDefinedName CAN_F9R2_FB31_Msk CAN_F5R2_FB0 CAN_F11R1_FB4 CAN_F13R2_FB2_Pos CAN_F2R2_FB18 CAN_BTR_SJW_Msk GPIO_BSRR_BS13_Msk CAN_F7R1_FB15_Msk DMA_CCR_DIR_Msk EXTI_SWIER_SWIER10_Msk TIM_CCMR2_CC4S GPIO_CRL_MODE0_Msk CAN_F8R1_FB13_Msk CAN_F4R1_FB19_Pos PIN_OPT_RESISTOR_NONE TIM_CCMR2_OC3PE_Msk CAN_TI0R_EXID_Pos USB_CNTR_WKUPM_Msk CAN_F12R1_FB13 CAN_F12R1_FB26 GPIO_ODR_ODR1_Msk CAN_RI0R_RTR_Msk USB_ADDR3_TX_ADDR3_TX EXTI_SWIER_SWI12 ADC_JSQR_JSQ4_1 CAN_F0R2_FB28_Pos I2C_SR1_ADD10_Pos
+syn keyword CTagsDefinedName EXTI_EMR_MR7 ADC_CR1_JAWDEN_Msk FLASH_DATA1_nDATA1_Pos PERIPH_BB_BASE RTC_PRLL_PRL_Msk USB_DADDR_ADD5_Pos CAN_F4R2_FB2_Msk TIM_PSC_PSC_Pos EXTI_IMR_MR8_Msk CAN_F5R1_FB25 CAN_ESR_LEC_1 CAN_F11R1_FB20_Pos CAN_F6R2_FB14_Pos CAN_F0R1_FB31_Msk USB_ISTR_ESOF CAN_F12R1_FB14_Msk CAN_F2R1_FB9_Msk SDIO_ICR_RXOVERRC_Msk CAN_F8R1_FB17 EXTI_FTSR_TR1 GPIO_CRL_MODE2_Msk SDIO_MASK_STBITERRIE_Pos CAN_F13R2_FB19 USB_COUNT6_RX_NUM_BLOCK_4 CAN_F1R2_FB7_Msk CAN_F4R1_FB3_Pos GPIO_BRR_BR1_Pos
+syn keyword CTagsDefinedName EXTI_PR_PIF5 CAN_F2R1_FB3_Pos GPIO_BRR_BR3_Msk CAN_F1R2_FB28 CAN_F10R1_FB27_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_0 CAN_F6R1_FB26_Msk DMA_ISR_TCIF7_Pos RCC_CFGR_PPRE1_DIV8 CAN_F13R2_FB4_Pos USB_EP6R_EP_TYPE_Pos AFIO_EXTICR1_EXTI3_PG FLASH_CR_PG_Pos I2C_SR1_OVR EXTI_EMR_MR17_Pos CAN_F4R1_FB20 CAN_F0R2_FB26 ADC_SQR3_SQ5_Msk CAN_F2R1_FB15_Msk GPIO_LCKR_LCK1_Msk ADC_CR2_JEXTSEL AFIO_EXTICR2_EXTI5_PF_Pos EXTI_EMR_EM5 IS_GPIO_AF_INSTANCE RCC_CR_PLLRDY_Msk RTC_CRL_SECF_Msk
+syn keyword CTagsDefinedName USB_EP6R_DTOG_RX_Msk GPIO_ODR_ODR3_Msk CAN_F9R2_FB15_Pos CAN_F3R2_FB26_Pos EXTI_PR_PR16 SDIO_ICR_DATAENDC USB_DADDR_EF USB_COUNT5_RX_COUNT5_RX GPIO_CRL_CNF2_0 ADC_JOFR1_JOFFSET1_Msk CAN_FFA1R_FFA6_Msk CAN_IER_FOVIE0_Pos CAN_F2R2_FB2 CAN_F10R2_FB8 TIM_RCR_REP_Pos GPIO_LCKR_LCK0 GPIO_IDR_IDR0_Pos DMA_CCR_CIRC_Pos GPIO_BRR_BR3_Pos GPIO_CRL_CNF6_Msk PIN_OPT_AF4 AFIO_EXTICR4_EXTI13_PB EXTI_EMR_MR3 SDIO_CMD_ENCMDCOMPL_Msk USB_EPTX_DTOG1 ADC_CR1_JAUTO TIM_DCR_DBA_3 USB_DADDR_ADD3
+syn keyword CTagsDefinedName USB_COUNT7_RX_NUM_BLOCK_3 USB_COUNT4_RX_BLSIZE USB_ADDR5_TX_ADDR5_TX USB_EP6R_CTR_TX_Pos CAN_F4R2_FB17 AFIO_EXTICR3_EXTI10_Msk TIM_DIER_CC4IE CAN_F8R2_FB28_Msk SDIO_DCTRL_DBLOCKSIZE_Msk TIM_DIER_TIE_Pos SPI_CRCPR_CRCPOLY_Pos TIM_DIER_CC4DE_Msk CAN_F9R2_FB13_Msk SDIO_STA_RXFIFOF_Pos CAN_F6R2_FB27_Pos PIN_OPT_AF1 SRAM_BASE CAN_F13R1_FB4_Msk CAN_F5R2_FB13 DMA_IFCR_CTCIF1_Msk BKP_DR7_D_Msk CAN_FM1R_FBM5_Pos I2C1_IRQERR_PRIORITY RCC_CR_HSEBYP FLASH_RDP_nRDP_Msk SDIO_STA_RXFIFOE_Msk
+syn keyword CTagsDefinedName CAN_TDT1R_TGT_Pos WWDG_SR_EWIF RCC_APB1RSTR_SPI2RST AFIO_EVCR_PORT CAN_F8R2_FB30_Pos TIM_CCMR1_IC1F_0 CAN_F2R1_FB3_Msk CAN_F6R2_FB28 CAN_F10R1_FB23 I2C_SR1_ADDR_Msk CAN_F8R1_FB0_Pos CAN_F9R1_FB8 DMA_IFCR_CHTIF7 CAN_F8R1_FB31_Msk TIM3_IRQ_PRIORITY CAN_F1R1_FB1_Pos SDIO_MASK_DATAENDIE_Pos RCC_APB1RSTR_PWRRST CAN_FS1R_FSC9_Pos CAN_F9R2_FB11_Pos CAN_F8R2_FB26 GPIO_CRH_MODE13_Pos CAN_RDT0R_TIME_Pos USB_EP2R_EP_KIND CAN_FMR_CAN2SB DMA_IFCR_CTEIF5 CAN_RDT1R_DLC_Msk CAN_F6R1_FB15_Msk
+syn keyword CTagsDefinedName TIM_DIER_CC3IE_Pos CAN_F1R1_FB15_Pos TIM2 DMA_ISR_HTIF2_Pos AFIO_MAPR_CAN_REMAP_Pos CAN_F4R2_FB21_Msk CAN_IER_ERRIE BKP_DR8_D_Pos CAN_F2R2_FB21 USB_HP_IRQn TIM_CCER_CC4P_Pos CAN_MSR_RX TIM_SR_BIF_Pos CAN_F3R2_FB11 I2C_CCR_DUTY EXTI_FTSR_TR4_Pos GPIO_CRH_CNF9_1 TIM_CCMR1_CC1S GPIO_IDR_IDR7_Pos USB_ADDR4_RX_ADDR4_RX CAN_F13R1_FB9 RTC_CRL_CNF_Msk CAN_F4R1_FB10_Msk RCC_CIR_HSERDYIE_Msk USB_CNTR_SOFM_Pos ADC_CR2_SWSTART AFIO_EXTICR2_EXTI6_PF_Pos SPI_CR1_BIDIOE_Pos
+syn keyword CTagsDefinedName USB_EP4R_STAT_TX_Msk FLASH_ACR_HLFCYA_Pos TIM_SR_CC2OF_Pos ADC_SMPR2_SMP3 CAN_F9R1_FB30 CAN_F5R1_FB1_Msk CAN_FFA1R_FFA7 CAN_F1R2_FB7 USART_CR1_PCE_Pos CAN_F3R2_FB20 CAN_F12R2_FB15_Pos CAN_F13R1_FB14 SDIO_CLKCR_NEGEDGE CAN_TDH0R_DATA7_Pos AFIO_MAPR_SWJ_CFG_1 FLASH_OBR_DATA0 CAN_FA1R_FACT_Pos CAN_TDH0R_DATA7_Msk CAN_F13R2_FB20 USART_GTPR_PSC_5 CAN_F4R2_FB2 GPIO_CRH_CNF_Msk CAN_F1R1_FB29_Pos CAN_F9R2_FB31_Pos CAN_F10R2_FB22_Pos CAN_F0R1_FB4_Msk EXTI_FTSR_TR18 CAN_F4R2_FB23_Pos
+syn keyword CTagsDefinedName TIM_CCMR1_OC2M_0 GPIO_BSRR_BS7_Pos RCC_APB2ENR_IOPEEN TIM_CCMR1_OC1FE_Pos CAN_F9R1_FB15 ADC_CR1_AWDEN_Pos AFIO_EXTICR1_EXTI2_PF_Msk TIM_CCMR1_IC1F USART_SR_CTS_Pos CAN_F0R2_FB17_Pos CAN_F10R2_FB16_Msk PWR_CR_PLS_2V6 RCC_APB2ENR_AFIOEN_Msk CAN_TSR_TME_Pos CAN_F0R1_FB22_Msk CAN_F0R2_FB7_Pos ADC_SMPR2_SMP9_0 EXTI_RTSR_RT5 GPIO_BSRR_BS5_Msk USB_EP4R_CTR_RX_Pos CAN_FS1R_FSC13 TIM_CR1_CMS_Msk RCC_APB1RSTR_TIM3RST AFIO_EXTICR3_EXTI10_PA EXTI_PR_PR11 CAN_F7R1_FB22 CAN_MSR_RXM
+syn keyword CTagsDefinedName DMA_IFCR_CTEIF5_Msk AFIO_EXTICR2_EXTI7_PE_Pos AFIO_MAPR_CAN_REMAP_REMAP2 CAN_F4R1_FB5 RCC_APB1RSTR_USART3RST CAN_FS1R_FSC4 CAN_F6R1_FB19_Pos GPIO_BSRR_BS12 IS_FUNCTIONAL_STATE CAN_F7R1_FB2 USB_COUNT7_RX_NUM_BLOCK_4 ADC1_IRQ_PRIORITY AFIO_EXTICR1_EXTI2_PF RCC_CIR_HSIRDYIE_Msk USB_COUNT7_RX_1_NUM_BLOCK_1 CLEAR_REG CAN_F1R1_FB3_Pos EXTI_EMR_EM13 USB_COUNT6_RX_COUNT6_RX SPI_SR_RXNE EXTI_RTSR_TR4_Msk I2C_SR1_SMBALERT_Msk SDIO_MASK_RXACTIE_Msk CAN_F0R2_FB20 CAN_F10R2_FB20
+syn keyword CTagsDefinedName GPIO_BSRR_BS1_Msk I2C_CR1_START_Msk CAN_F13R2_FB13_Msk TIM_ARR_ARR RCC_CFGR_MCOSEL_0 USB_EP2R_STAT_TX_0 CAN_F6R2_FB12 IS_UART_HALFDUPLEX_INSTANCE CAN_F0R2_FB10 AFIO_EXTICR4_EXTI15_PE CAN_F1R1_FB15 ADC_SMPR1_SMP14 TIM_SMCR_ECE_Pos USART_CR1_PEIE_Pos BKP_RTCCR_ASOE_Pos DMA_ISR_TCIF6 CAN_F5R2_FB0_Pos CAN_F4R2_FB21_Pos CAN_F9R2_FB14_Msk RCC_APB2RSTR_ADC2RST_Pos SDIO_CMD_WAITRESP_Msk ADC_SQR1_SQ14_Pos AFIO_EXTICR3_EXTI11_PF_Msk BKP_DR9_D_Pos CAN_F0R2_FB15_Pos CAN_F2R2_FB17_Msk
+syn keyword CTagsDefinedName USB_EP1R_SETUP_Msk CAN_MSR_WKUI_Msk GPIO_CRH_CNF13_0 CAN_F9R2_FB12_Msk FLASH_DATA1_DATA1_Msk SDIO_MASK_DATAENDIE USB_EP4R_CTR_TX_Pos CAN_F13R1_FB29_Pos CAN_FA1R_FACT13_Pos CAN_IER_FMPIE1 CAN_F6R1_FB22 RCC_CSR_SFTRSTF_Msk CAN_F12R1_FB2_Pos I2C_CR1_PEC EXTI_IMR_MR1_Pos CAN_FA1R_FACT0_Msk CAN_F4R2_FB13 CAN_F8R2_FB27_Pos AFIO_EXTICR4_EXTI14_PC_Pos ADC_SQR2_SQ10_0 EXTI_SWIER_SWIER2_Pos CAN_F0R2_FB16_Msk CAN_FM1R_FBM10_Pos CAN_F9R1_FB5_Msk CAN_F11R1_FB29_Msk CAN_F4R2_FB29_Msk
+syn keyword CTagsDefinedName TIM_SR_CC2OF_Msk CAN_F11R2_FB21 DMA_IFCR_CGIF2_Pos CAN_F13R2_FB24 USB_COUNT2_RX_0_COUNT2_RX_0 TIM_DIER_CC1IE_Pos USART_CR2_ADD_Msk CAN_F8R1_FB29 ADC_SMPR1_SMP17_Msk TIM2_BASE CAN_RI1R_STID BKP_DR9_D_Msk CAN_F0R1_FB26_Pos CAN_F11R2_FB17 TIM_BDTR_LOCK_Msk FLASH_CR_EOPIE_Pos GPIO_CRL_CNF1_0 CAN_TDT2R_TIME_Pos CAN_F8R1_FB7_Pos CAN_F2R1_FB26_Pos ADC_CR2_JSWSTART_Msk CAN_F10R2_FB23_Pos CAN_F11R2_FB15_Pos USB_EP_KIND_Pos BKP_CR_TPE_Msk CAN_F1R1_FB25_Msk RTC_CRL_CNF ADC_CR2_ADON_Pos
+syn keyword CTagsDefinedName USB_ADDR2_RX_ADDR2_RX_Pos EXTI_IMR_IM11 RCC_CIR_LSERDYC CAN_F9R1_FB26_Msk RCC_CFGR_MCO_1 AFIO_EXTICR1_EXTI2_Pos USB_ISTR_SUSP_Pos DMA_IFCR_CTEIF6_Msk ADC_SQR1_SQ14_3 AFIO_EVCR_PIN_PX5_Pos I2C_CR1_ALERT_Msk TIM_BDTR_DTG_3 CAN_F11R1_FB28 CAN_F3R2_FB23 PIN_OPT_AF13 GPIO_IDR_IDR10_Pos RCC_CFGR_PLLMULL9_Msk CAN_F4R1_FB0_Msk RTC_CNTH_RTC_CNT_Pos CAN_F7R2_FB20 CAN_BTR_LBKM USB_CNTR_RESUME_Pos CAN_F11R1_FB20 PIN_7 CAN_F11R1_FB7 ADC_SQR3_SQ6_3 USB_EP_CONTROL PWR_CSR_EWUP_Pos
+syn keyword CTagsDefinedName RCC_APB1ENR_CAN1EN_Pos CAN_F11R2_FB14_Pos CAN_F5R1_FB13 IS_TIM_CLOCKSOURCE_TIX_INSTANCE USB_COUNT1_TX_0_COUNT1_TX_0 DMA_IFCR_CGIF3_Msk EXTI_RTSR_TR7_Pos USB_ISTR_ERR CAN_F2R1_FB6_Msk USB_ISTR_ERR_Pos CAN_TDT2R_DLC_Msk CAN_F7R2_FB23_Msk USB_CNTR_FRES CAN_TSR_LOW1 CAN_F10R1_FB7_Msk CAN_TDT0R_TGT_Pos CAN_F13R1_FB16_Msk RCC_CFGR_HPRE_DIV8 CAN_F2R2_FB10 CAN_F6R1_FB31_Msk RCC_CR_HSERDY_Msk ADC_SMPR2_SMP5_Pos ADC_SR_AWD SDIO_ICR_DTIMEOUTC_Msk RCC_CFGR_SWS_PLL USART_SR_IDLE
+syn keyword CTagsDefinedName CAN_FA1R_FACT6_Pos CAN_F11R2_FB21_Msk CAN_F3R1_FB1 WWDG CAN_F4R2_FB31_Pos AFIO_MAPR_CAN_REMAP_REMAP1 CAN_F9R1_FB18_Msk AFIO_EVCR_PIN_PX12_Msk I2C_SR1_BERR_Msk USB_COUNT6_RX_1_NUM_BLOCK_1_4 GPIO_BSRR_BS4_Pos CAN_F9R1_FB12_Msk CAN_F13R2_FB5_Pos USB_COUNT4_RX_COUNT4_RX_Msk CAN_F10R2_FB4_Msk USB_EP1R_DTOG_RX AFIO_EXTICR3_EXTI9_PD_Pos CAN_F13R1_FB9_Msk RCC_APB1ENR_CAN1EN_Msk CAN_FM1R_FBM10_Msk OB CAN_F0R1_FB0_Msk WWDG_CFR_W_1 RDP_KEY_Msk CAN_MSR_SLAKI CAN_MCR_RESET CAN_F5R1_FB12_Pos
+syn keyword CTagsDefinedName CAN_F2R2_FB31_Pos CAN_F10R2_FB1_Pos CAN_TSR_CODE USB_COUNT3_RX_0_NUM_BLOCK_0_3 CAN_F11R2_FB22_Pos CAN_F13R2_FB3_Msk GPIO_ODR_ODR13 ADC_SMPR2_SMP8_Pos CAN_F11R2_FB27 EXTI_IMR_MR7 CAN_F8R2_FB16_Pos RCC_CFGR_MCOSEL_NOCLOCK USB_EP_CTR_RX_Pos GPIO_LCKR_LCK4 DMA_IFCR_CHTIF3 CAN_FFA1R_FFA5_Msk USB_COUNT0_RX_1_NUM_BLOCK_1_0 CAN_F7R2_FB24_Msk CAN_F8R1_FB2 CAN_F1R2_FB20_Msk CAN_F7R2_FB3_Pos CAN_RF1R_FMP1_Pos CAN_F3R1_FB29_Msk AFIO_EVCR_PIN_Pos CAN_BTR_BRP_Msk GPIO_ODR_ODR7_Msk
+syn keyword CTagsDefinedName USART_CR3_DMAR_Msk AFIO_EXTICR4_EXTI13_PF CAN_F2R2_FB16_Msk CAN_FA1R_FACT7_Msk USB_COUNT5_RX_BLSIZE_Msk SPI_SR_OVR GPIO_BSRR_BR7 CAN_F1R1_FB19_Msk CAN_F0R1_FB19_Msk CAN_F13R1_FB10_Pos CAN_FM1R_FBM4 CAN_F1R1_FB9 USB_COUNT5_RX_0_NUM_BLOCK_0_2 DMA_IFCR_CGIF4 I2C_SR1_TXE CAN_TDT2R_TIME OB_BASE USB_ADDR5_TX_ADDR5_TX_Pos TIM_DCR_DBL_4 EXTI_RTSR_RT0 CAN_F8R2_FB20_Pos I2C_DR_DR_Msk SDIO_CLKCR_PWRSAV_Msk CAN_F8R2_FB8_Msk ADC_JOFR1_JOFFSET1_Pos CAN_F7R2_FB15_Pos PWR_CR_PLS CAN_FS1R_FSC12
+syn keyword CTagsDefinedName GPIO_CRH_MODE8 AFIO_EXTICR1_EXTI2_PD USB_CNTR_PMAOVRM USB_EP3R_STAT_RX_Pos CAN_F9R1_FB14 CAN_F11R2_FB6_Pos CAN_FS1R_FSC0 CAN_FS1R_FSC11_Msk BKP_RTCCR_ASOS_Pos USB_EP5R_DTOG_TX_Msk AFIO_EXTICR4_EXTI13_PE EXTI_SWIER_SWIER14_Msk RCC_APB2ENR_IOPCEN __STM32F1_CMSIS_VERSION_MAIN CAN_TDH1R_DATA6 CAN_F5R1_FB21 GPIO_CRH_MODE10 DMA_ISR_TEIF7 USB_COUNT0_TX_0_COUNT0_TX_0 ADC_SMPR2_SMP8_Msk TIM_CR2_CCPC_Pos CAN_F13R1_FB28 CAN_F5R2_FB21_Pos CAN_F10R2_FB29_Msk RTC_CRL_OWF_Pos USART3_BASE
+syn keyword CTagsDefinedName USB_EP6R_STAT_RX_0 USB_COUNT6_RX_1_NUM_BLOCK_1_0 BKP_BASE CAN_F4R2_FB3_Msk CAN_F2R2_FB26_Pos CAN_F7R2_FB2_Pos CAN_F3R2_FB6_Msk CAN_F12R1_FB26_Msk DMA_ISR_GIF2_Msk CAN_F3R1_FB26_Msk CAN_FS1R_FSC8_Msk RTC_ALRL_RTC_ALR USB_CNTR_CTRM_Pos USB_COUNT6_RX_NUM_BLOCK_3 TIM_CCMR1_IC2F_Msk USART_SR_TXE_Msk DBGMCU_CR_DBG_IWDG_STOP_Msk TIM_DIER_CC2IE_Msk CAN_F0R1_FB11 CAN_F3R1_FB13 TIM_CR2_OIS1N_Pos RCC_CSR_SFTRSTF_Pos DMA_ISR_TCIF3_Pos CAN_F5R2_FB17_Pos RCC_APB2RSTR_IOPARST_Msk
+syn keyword CTagsDefinedName USB_EP3R_CTR_TX_Msk CAN_F11R1_FB2 CAN_F2R1_FB8_Pos CAN_F3R1_FB28_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_1 ADC_JSQR_JL SPI_CR2_TXDMAEN_Pos CAN_FFA1R_FFA4_Pos DMA_IFCR_CTEIF3_Msk DMA_CCR_PL_1 GPIO_LCKR_LCK9_Msk ADC_SQR2_SQ11_0 TIM4 TIM_EGR_TG CAN_RDH1R_DATA7_Msk CAN_F11R1_FB2_Msk TIM_CCMR1_OC1FE_Msk RCC_APB2RSTR_SPI1RST AFIO_EXTICR1_EXTI0_Pos CAN_F7R1_FB3_Pos USB_COUNT2_RX_0_NUM_BLOCK_0_0 FLASH_SR_WRPRTERR_Pos CAN_F2R1_FB1_Msk USB_ADDR7_RX_ADDR7_RX CAN_F4R1_FB22_Pos FLASH_CR_PER
+syn keyword CTagsDefinedName USB_COUNT4_TX_COUNT4_TX CAN1_TX_IRQn CAN_F2R1_FB5 CAN_F9R1_FB3 ADC_SMPR1_SMP16 CAN_TDH0R_DATA6_Pos RTC_DIVH_RTC_DIV CAN_F13R2_FB24_Msk AFIO_EVCR_PIN_PX12_Pos USB_EP_TX_STALL CAN_F4R1_FB11_Pos CAN_F8R1_FB19_Pos CAN_F1R1_FB21 CAN_F1R1_FB1_Msk SDIO_DCTRL_RWSTART_Pos CAN_F0R2_FB24_Msk GPIO_BSRR_BR14_Pos CAN_F12R2_FB23_Pos USB_EP7R_DTOG_RX_Msk WWDG_CR_T_4 RCC_CFGR_ADCPRE_0 USART_CR1_PCE_Msk CAN_F3R1_FB4 CAN_F3R1_FB31_Msk AFIO_EXTICR3_EXTI11_PE_Msk USART_CR2_ADD TIM_CCMR1_IC1F_Msk
+syn keyword CTagsDefinedName USART_CR1_PS_Msk SDIO_STA_DBCKEND_Pos RCC_APB1RSTR_WWDGRST ADC_SQR3_SQ6_2 GPIO_BSRR_BR3 CAN_F0R1_FB21_Msk USART_CR3_HDSEL CAN_F7R1_FB4_Msk CAN_F13R2_FB15_Msk WWDG_CR_T3 CAN_F3R1_FB28 SDIO_CLKCR_PWRSAV AFIO_EXTICR2_EXTI4_Pos CAN_F3R2_FB7_Pos USB_COUNT5_RX_NUM_BLOCK_0 AFIO_EXTICR1_EXTI2_PF_Pos CAN_TSR_RQCP1_Msk CAN_F3R1_FB27 CAN_F7R2_FB2 CAN_F10R1_FB10 SDIO_MASK_DTIMEOUTIE GPIO_CRL_MODE2_0 USB_ADDR7_TX_ADDR7_TX CAN_F12R1_FB0 CAN_F10R2_FB26 USB_EP2R_STAT_RX_1 AFIO_EXTICR2_EXTI4_PG
+syn keyword CTagsDefinedName CAN_F10R2_FB31_Pos PIN_1 GPIO_ODR_ODR4 CAN_F5R1_FB21_Pos USART_CR3_NACK_Msk FLASH_KEY1_Pos CAN_F12R1_FB10_Msk GPIO_IDR_IDR11 USB_EP2R_EA CAN_F12R2_FB6 I2C_SR1_STOPF DMA_ISR_HTIF7 USB_COUNT2_RX_COUNT2_RX_Msk USB_COUNT1_RX_BLSIZE_Msk CAN_F12R1_FB22_Pos CAN_F8R1_FB21_Msk AFIO_MAPR_CAN_REMAP_REMAP3_Pos TIM_CCMR1_OC1M_Pos SPI_SR_MODF_Msk FLASH_CR_PG_Msk CAN_TDL2R_DATA0_Msk TIM_BDTR_DTG_7 USB_ISTR_RESET AFIO_EXTICR1_EXTI1_PD_Pos CAN_BTR_SILM_Msk USB_EP5R_CTR_TX_Pos CAN_F9R2_FB15
+syn keyword CTagsDefinedName GPIO_BSRR_BS14 CAN_RI0R_IDE_Msk CAN_F7R1_FB2_Msk GPIO_LCKR_LCK7_Msk SPI_I2SCFGR_I2SMOD_Pos TIM_SR_TIF_Msk RCC_CFGR_PLLSRC_Pos CAN_MSR_ERRI_Msk CAN_F4R1_FB11 DBGMCU_IDCODE_REV_ID_0 CAN_F9R2_FB17 CAN_F5R1_FB19_Pos BKP_DR2_D PWR_CR_PLS_LEV1 I2C_SR2_MSL EXTI_FTSR_FT11 USART_CR1_TXEIE GPIO_LCKR_LCK12_Msk CAN_F9R2_FB19_Msk CAN_RF0R_RFOM0_Msk CAN_F4R1_FB9_Msk CAN_F3R2_FB14_Msk CAN_F3R1_FB12 PIN_OPT_OUTPUT_PUSHPULL RCC_APB2RSTR_AFIORST SDIO_CMD_CEATACMD_Msk CAN_F11R2_FB10_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5 CAN_RDT1R_TIME_Pos TIM_CCMR1_CC1S_1 TIM_CCMR1_OC2PE_Msk IS_UART_INSTANCE AFIO_MAPR_USART3_REMAP_Pos AFIO_EXTICR2_EXTI7_PC_Pos CAN_F12R1_FB14_Pos USART_DR_DR_Msk CAN_F3R2_FB25 AFIO_EXTICR3_EXTI9_PF_Msk CAN_F4R2_FB5_Msk EXTI_RTSR_TR14_Msk TIM_DCR_DBA_2 RCC_APB2ENR_AFIOEN_Pos GPIO_CRH_MODE_Msk ADC_SMPR2_SMP1_2 CAN_MCR_ABOM I2C_SR2_DUALF CAN_F3R1_FB0 TIM_CR1_URS_Pos RTC_CNTL_RTC_CNT_Msk GPIO_BSRR_BS7_Msk CAN_MCR_RESET_Pos CAN_F5R1_FB27_Pos CAN_F7R1_FB8_Msk
+syn keyword CTagsDefinedName CAN_FS1R_FSC1 TIM_CCMR1_IC2F_0 EXTI_FTSR_TR11 SDIO_STA_SDIOIT_Pos GPIO_ODR_ODR3 SDIO_DCTRL_RWSTART DMA_CMAR_MA_Msk AFIO_EVCR_PORT_PD_Msk USB_CNTR_PMAOVRM_Pos GPIO_BRR_BR5_Msk USART6_IRQ_PRIORITY AFIO_EXTICR2_EXTI7_PD_Pos FLASH_ACR_HLFCYA TIM_CCMR2_OC3CE_Msk GPIO_BSRR_BR1_Pos WWDG_CFR_W_4 CAN_F7R2_FB20_Pos CAN_F4R1_FB7_Msk CAN_F9R2_FB4_Pos CAN_F9R1_FB16_Msk ADC_SQR2_SQ12_3 RCC_CFGR_SW_1 ADC_JSQR_JSQ1_1 CAN_F13R2_FB18_Pos CAN_F9R1_FB15_Pos AFIO_EXTICR2_EXTI6_PB_Pos
+syn keyword CTagsDefinedName CAN_F3R1_FB15_Msk RCC_CFGR_MCO_HSE DMA_CCR_TCIE_Pos CAN_F10R1_FB3 ADC_SQR1_SQ14_1 USB_EP4R_EP_KIND USB_EP3R_STAT_RX_0 CAN_FA1R_FACT0 CAN_MCR_NART GPIO_CRL_MODE4_1 EXTI_IMR_IM9 TIM_CR1_URS_Msk GPIO_ODR_ODR9 AFIO_EXTICR3_EXTI8_PE USB_EP1R_STAT_TX_0 USART_CR1_RXNEIE_Pos AFIO_EXTICR2_EXTI4_PD_Pos USB_COUNT3_RX_1_NUM_BLOCK_1_4 AFIO_EXTICR3_EXTI9_PE_Pos TIM_CR2_OIS3 GPIO_ODR_ODR12_Msk USB_EP4R_CTR_TX CAN_F12R2_FB12 CAN_F7R1_FB12_Pos CAN_F13R2_FB9 AFIO_EXTICR1_EXTI2_PG_Pos
+syn keyword CTagsDefinedName ADC_SMPR2_SMP3_0 USB_EP0R_EP_KIND USB_EP4R_SETUP_Pos SDIO_STA_DTIMEOUT_Msk CAN_F11R1_FB11_Msk ADC_JSQR_JL_0 CAN_F3R1_FB7_Pos CAN_F3R1_FB11_Msk RCC_CFGR_PPRE2_DIV8 USB_EP0R_EP_TYPE_Msk ADC_SMPR1_SMP15_Msk USB_COUNT4_RX_1_COUNT4_RX_1 CAN_TDT2R_DLC_Pos TIM_CCER_CC1P TIM_CCMR1_IC1PSC_Pos SPI_CR1_CPOL_Msk EXTI_PR_PR6_Pos CAN_F1R2_FB3_Pos EXTI_RTSR_RT12 I2C2_BASE TIM4_BASE GPIO_BRR_BR11_Msk SPI_CR2_RXNEIE ADC_CR2_DMA_Msk DBGMCU_IDCODE_REV_ID_14 CAN_TSR_ABRQ0_Pos DMA_IFCR_CTCIF2_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR3_EXTI9_PD_Msk EXTI_PR_PIF4 I2C_OAR1_ADD7 CAN_F1R2_FB14_Msk SPI_CR1_CRCEN_Msk AFIO_EXTICR4_EXTI14_PF CAN_F4R2_FB25_Msk CAN_F12R2_FB9_Pos CAN_F11R1_FB6_Msk ADC_SQR3_SQ2_1 CAN_TI0R_IDE_Msk USB_EP7R_STAT_RX_1 CAN_IER_FFIE1_Msk SPI_CR1_MSTR_Msk ADC_SMPR1_SMP13_1 EXTI_SWIER_SWIER13_Pos TIM1_BRK_TIM9_IRQHandler CAN_F9R1_FB25_Pos GPIO_LCKR_LCK9_Pos CAN_F2R2_FB2_Pos I2C_CR1_ACK SPI_DR_DR_Pos CAN_F3R2_FB28 CAN_MCR_INRQ CAN_F7R2_FB17_Pos FLASH_DATA1_nDATA1 CAN_F1R1_FB20_Pos
+syn keyword CTagsDefinedName GPIO_LCKR_LCK4_Msk CAN_F4R1_FB18_Msk CAN_F9R1_FB4_Pos RCC_CFGR_PLLMULL5_Msk CAN_F5R1_FB10 TIM_DIER_CC2DE USB_FNR_RXDM GPIO_IDR_IDR2_Pos AFIO_EXTICR1_EXTI1_PB CAN_F2R2_FB7 AFIO_MAPR_TIM3_REMAP_Pos CAN_F2R1_FB31 PWR_CSR_EWUP DMA_CPAR_PA_Msk CAN_TI2R_RTR_Pos I2C_CR1_SMBUS USB_COUNT6_RX_1_NUM_BLOCK_1_3 CAN_F11R2_FB22 CAN_TSR_RQCP2_Msk EXTI_EMR_MR11_Msk AFIO_EXTICR3_EXTI10_PD_Pos CAN_F1R1_FB13 AFIO_EXTICR1_EXTI3_PE RTC_CNTH_RTC_CNT CAN_F9R2_FB6_Pos TIM_CR1_CMS_Pos USART_CR3_IRLP_Msk
+syn keyword CTagsDefinedName CAN_F11R1_FB25_Pos CAN_TDL2R_DATA1_Msk CAN_F7R2_FB16_Pos CAN_F2R1_FB30_Msk AFIO_EXTICR3_EXTI9_PC_Pos USART_SR_LBD_Pos WWDG_CFR_W_Pos CAN_F7R1_FB11 CAN_F5R1_FB20_Pos CAN_F8R1_FB25_Pos CAN_F6R2_FB15_Pos CAN_F12R1_FB4_Pos CAN_FM1R_FBM12_Pos CAN_F3R1_FB27_Msk USART_CR2_CPHA AFIO_EVCR_PORT_PB_Pos AFIO_MAPR_SWJ_CFG_2 CAN_F13R1_FB24 GPIO_ODR_ODR8 CAN_F7R1_FB17_Pos SDIO_POWER_PWRCTRL_0 CAN_F2R1_FB17_Msk CAN_F1R1_FB3 ADC_CR1_AWDEN_Msk AFIO_EVCR_PIN_PX6 CAN_F4R2_FB14 RCC_CFGR_HPRE_DIV512
+syn keyword CTagsDefinedName USB_EP7R_DTOG_TX_Msk CAN_F8R1_FB1 EXTI_PR_PIF10 CAN_TDH0R_DATA5 CAN_F9R2_FB7_Msk pwm_stop RCC_APB1RSTR_USBRST_Msk CAN_FS1R_FSC2_Pos SDIO_ICR_RXOVERRC_Pos TIM_DIER_TIE SDIO_ICR_CMDRENDC CAN_F7R2_FB29_Pos ADC_SMPR2_SMP1_1 DMA_ISR_GIF6_Msk I2C_OAR1_ADD2_Msk CAN_TI2R_TXRQ_Pos USB_EP0R_STAT_RX_0 ADC_JDR3_JDATA FLASH_CR_OPTER_Msk CAN_F10R2_FB3_Pos CAN_TSR_TME DMA1_Channel3 CAN_F6R1_FB20_Msk USART_SR_ORE_Pos CAN_F4R2_FB24_Pos TIM9_IRQHandler CAN_RI0R_RTR SPI_SR_BSY_Msk BKP_CR_TPAL_Pos
+syn keyword CTagsDefinedName CAN_F5R2_FB29_Pos CAN_F8R2_FB31_Msk CAN_F6R2_FB13 IWDG_RLR_RL CAN_F10R1_FB11_Pos CAN_F5R1_FB2_Msk BKP_CSR_TPIE SPI_SR_UDR USB_EP6R_CTR_TX EXTI_IMR_MR0_Pos AFIO_BASE CAN_TDL2R_DATA3_Pos USB_EP3R_EP_KIND_Pos CAN_TI1R_IDE_Pos CAN_F2R2_FB14 CAN_F10R2_FB26_Pos I2C_CR1_ALERT EXTI_PR_PR15_Pos CAN_F7R2_FB21_Pos GPIO_BSRR_BR6_Msk ADC_CR2_ADON_Msk DMA_IFCR_CHTIF7_Pos CAN_F4R1_FB0 DBGMCU_CR_DBG_TIM4_STOP_Msk CAN_TSR_LOW0 USB_ADDR0_TX_ADDR0_TX_Pos FLASH_OPTKEYR_OPTKEYR_Pos TIM_EGR_BG
+syn keyword CTagsDefinedName CAN_F9R2_FB21_Pos CAN_TDH2R_DATA4 DMA1_Channel5 EXTI_IMR_IM0 SDIO_ICR_CCRCFAILC_Msk EXTI_BASE DMA_CCR_HTIE_Pos SYSCFG_EXTI_PB_MASK CAN_F1R2_FB20_Pos CAN_F13R2_FB1_Pos CAN_F6R1_FB8_Pos CAN_F11R1_FB26_Pos CAN_FS1R_FSC3 GPIO_BSRR_BS11_Msk CAN_FFA1R_FFA7_Msk CAN_F3R1_FB19 ADC_SQR3_SQ4_2 AFIO_MAPR_SWJ_CFG_NOJNTRST TIM_CCMR2_IC3PSC_0 USB_COUNT4_RX_1_NUM_BLOCK_1_3 EXTI_FTSR_TR16 CAN_F0R2_FB7 CAN_F2R1_FB27_Msk CAN_F2R2_FB26_Msk EXTI9_5_IRQ_PRIORITY CAN_F5R2_FB30_Pos CAN_F3R2_FB13_Pos
+syn keyword CTagsDefinedName EXTI_FTSR_FT10 EXTI_FTSR_TR12_Pos TIM_CCMR1_OC1FE CAN_TDL2R_DATA3 CAN_F2R2_FB19_Msk CAN_FM1R_FBM7_Pos CAN_TSR_TME1_Pos CAN_F3R2_FB5_Msk CAN_F6R1_FB25 CAN_F10R1_FB6_Msk USART_CR3_DMAR_Pos CAN_F9R1_FB7_Msk CAN_FFA1R_FFA13_Msk CAN_FFA1R_FFA13 CAN_BTR_TS2_2 CAN_F3R1_FB3_Pos USART_SR_TC_Msk CAN_F0R1_FB23 CAN_F11R1_FB23 CAN_F5R1_FB17 AFIO_EVCR_PIN_PX6_Pos GPIO_CRH_CNF8_1 RCC_APB2RSTR_ADC2RST_Msk PWR_CR_CSBF TIM_CCER_CC2NP_Pos ADC_SQR1_SQ14_Msk CAN_F1R2_FB18_Pos AFIO_EVCR_PIN_PX1
+syn keyword CTagsDefinedName USART_SR_TXE ADC_SQR3_SQ6_4 FLASH_OPTKEYR_OPTKEYR CAN_F8R1_FB9 DBGMCU_CR_DBG_IWDG_STOP RTC_ALRL_RTC_ALR_Msk CAN_F12R2_FB3 TIM_CCMR1_IC1PSC_1 CAN_F11R1_FB9_Msk AFIO_EXTICR3_EXTI8_PD_Pos I2C_OAR2_ADD2 CAN_F3R2_FB14 AFIO_EXTICR2_EXTI6_PD_Msk CAN_F2R1_FB31_Pos CAN_MCR_AWUM USB_EP6R_EP_KIND_Msk TIM_EGR_CC3G_Msk CAN_F8R1_FB25_Msk SDIO_CLKCR_NEGEDGE_Msk CAN_F5R2_FB10_Pos CAN_F4R2_FB28_Msk CAN_F3R2_FB16 BKP_CSR_CTI DBGMCU_CR_DBG_TIM1_STOP CAN_F1R1_FB14_Pos CAN_F11R1_FB19_Pos
+syn keyword CTagsDefinedName CAN_F11R1_FB11_Pos CAN_F12R2_FB16_Msk RCC_CIR_LSIRDYIE_Msk TIM_CCMR2_OC3M_2 EXTI_RTSR_TR1_Msk SDIO_STA_TXUNDERR_Pos CAN_TI0R_TXRQ_Msk CAN_F8R1_FB22 CAN_F13R1_FB30_Pos RCC_APB1RSTR_I2C2RST CAN_F11R1_FB24_Msk RCC_CFGR_HPRE_Msk AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos AFIO_EXTICR3_EXTI11_PF_Pos CAN_F4R2_FB20_Msk RCC_APB2RSTR_ADC1RST_Msk ADC_SQR2_SQ11_Msk USB_ISTR_ESOF_Pos BKP_DR5_D_Pos USB_COUNT4_TX_0_COUNT4_TX_0 TIM_EGR_CC1G_Pos I2C_SR1_STOPF_Pos CAN_F7R2_FB24 EXTI_SWIER_SWIER3_Msk
+syn keyword CTagsDefinedName USB_EP1R_EP_TYPE_Pos USB_EP6R_EA_Msk FLASH_OBR_IWDG_SW GPIO_BSRR_BS6_Msk GPIO_IDR_IDR6_Msk SPI1_BASE DMA_ISR_TEIF4_Pos EXTI_SWIER_SWIER18_Msk CAN_F5R1_FB23 WWDG_CFR_WDGTB_Msk GPIO_ODR_ODR13_Pos CAN_F3R2_FB25_Pos GPIO_BSRR_BS1 GPIO_BSRR_BS10 CAN_F0R2_FB4_Pos GPIO_CRH_CNF15_0 CAN_F8R1_FB6 RCC_APB2RSTR_AFIORST_Msk CAN_F13R2_FB11_Pos I2C_CR1_POS_Pos CAN_F12R2_FB0 EXTI_RTSR_TR12_Msk CAN_F6R1_FB17 CAN_F10R1_FB21_Msk IS_TIM_DMABURST_INSTANCE CAN_F5R1_FB12_Msk CAN_F13R1_FB20_Pos
+syn keyword CTagsDefinedName AFIO_EVCR_PORT_PD_Pos CAN_TSR_RQCP0_Msk CAN_F10R2_FB17_Msk EXTI_RTSR_TR17_Pos SPI_TXCRCR_TXCRC_Pos EXTI_IMR_MR17 AFIO_EXTICR2_EXTI5_PD_Msk UID_BASE TIM_CCMR1_IC2F_1 USB_ISTR_EP_ID_Pos TIM_EGR_BG_Pos DMA_ISR_TEIF6 CRC_DR_DR_Pos SDIO_STA_CMDSENT_Pos AFIO_EXTICR3_EXTI9_PC_Msk CAN_F3R2_FB30 SDIO_DCTRL_DBLOCKSIZE_0 USB_EPKIND_MASK CAN_MSR_TXM CAN_F6R1_FB8_Msk CAN_FA1R_FACT5 CAN_F11R1_FB9_Pos CAN_FA1R_FACT7_Pos ADC_SQR2_SQ8_4 CAN_F0R1_FB7 CAN_F2R1_FB15_Pos GPIO_LCKR_LCK4_Pos
+syn keyword CTagsDefinedName EXTI_SWIER_SWI18 TIM5_IRQ_PRIORITY SDIO_MASK_CTIMEOUTIE_Msk CAN_F2R1_FB8 ADC_SQR3_SQ6 CAN_MSR_WKUI_Pos CAN_F1R1_FB18 AFIO_EXTICR2_EXTI5_PB CAN_F11R2_FB19_Msk CAN_F5R2_FB9_Msk DMA_CCR_DIR_Pos CAN_F9R1_FB24_Msk AFIO_EXTICR4_EXTI13_PD CAN_F7R2_FB31_Msk CAN_F3R1_FB13_Pos EXTI2_IRQ_PRIORITY AFIO_EXTICR1_EXTI3_PG_Msk CAN_F8R2_FB8_Pos USB_EP6R_STAT_RX_Msk CAN_TI1R_TXRQ_Msk USB_EPREG_MASK AFIO_EXTICR3_EXTI8_PG_Msk EXTI_IMR_MR3 SDIO_STA_DTIMEOUT_Pos AFIO_EXTICR4_EXTI12 CAN_F9R1_FB6_Msk
+syn keyword CTagsDefinedName CAN_F7R2_FB16_Msk IS_ADC_DMA_CAPABILITY_INSTANCE CAN_F8R2_FB3_Pos WWDG_SR_EWIF_Pos CAN_RDL1R_DATA1_Msk I2C_DR_DR RCC_CSR_LPWRRSTF_Pos CAN_F13R2_FB22 CAN_F3R2_FB3_Pos TIM_SR_CC1IF USB_ADDR5_TX_ADDR5_TX_Msk CAN_F12R1_FB13_Msk ADC_SMPR1_SMP16_2 SDIO_RESP2_CARDSTATUS2_Msk TIM_BDTR_LOCK CAN_F6R1_FB2_Msk AFIO_EXTICR1_EXTI0_PG SPI_CR1_SPE_Pos ADC_CR2_ALIGN_Msk CAN_IER_EPVIE_Msk TIM_CCMR2_OC4FE_Pos CAN_F0R2_FB12_Msk DMA_IFCR_CGIF6_Pos CAN_F11R1_FB19_Msk DMA_CCR_CIRC_Msk
+syn keyword CTagsDefinedName AFIO_MAPR_SPI1_REMAP_Msk CAN_TSR_RQCP0_Pos CAN_F7R1_FB1 USART_SR_FE CAN_TI1R_STID CAN_F9R2_FB12 CAN_F6R2_FB28_Pos SPI_RXCRCR_RXCRC_Pos USB_EP5R_EP_TYPE_Msk I2C_OAR1_ADD3_Pos CAN_F12R1_FB9_Msk SDIO_CLKCR_HWFC_EN CAN_F2R1_FB5_Msk GPIO_BRR_BR13_Pos EXTI_EMR_MR16 USART_SR_NE_Msk AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk USB_EP2R_STAT_TX_Msk DMA_CCR_MINC CAN_F9R1_FB29_Msk CAN_F10R1_FB4_Pos TIM_SMCR_ETF_2 USART_SR_PE_Pos WWDG_CR_T_6 CAN_RDL1R_DATA1 CAN_F10R1_FB27 CAN_F10R2_FB2
+syn keyword CTagsDefinedName USART_CR3_EIE_Pos CAN_F1R2_FB27 DMA_IFCR_CHTIF3_Msk RCC_APB2ENR_SPI1EN_Pos CAN_F7R2_FB26_Pos RCC_CFGR_ADCPRE_1 GPIO_CRL_MODE_Msk IS_ADC_ALL_INSTANCE RCC_APB1RSTR_PWRRST_Msk CAN_F9R1_FB24 GPIO_LCKR_LCK7 CAN_F3R2_FB19_Msk CAN_F1R1_FB20_Msk USB_CNTR_LP_MODE_Msk TIM_CR1_CKD_Pos USB_DADDR_ADD6 I2C_SR1_PECERR CAN_F2R1_FB28_Pos ADC_SQR3_SQ3_1 CAN_F4R2_FB27 CAN_F9R2_FB25 USB_EP7R_EP_KIND_Pos CAN_F9R2_FB31 CAN_F12R2_FB4_Msk EXTI_PR_PR12_Pos AFIO_EXTICR1_EXTI3_PC_Msk IWDG_PR_PR
+syn keyword CTagsDefinedName DMA_ISR_GIF4_Pos USART_CR1_WAKE_Msk RCC_CFGR_PPRE1_0 I2C_CCR_FS_Pos USB_COUNT7_RX_NUM_BLOCK RCC_CFGR_PPRE2_2 GPIO_BSRR_BR12 AFIO_EXTICR4_EXTI14_PE_Msk RCC_CFGR_PLLMULL6_Pos TIM_CCMR2_OC4M_0 USB_EP3R_EA_Pos PIN_OPT_OUTPUT_SPEED_LOW RTC_BASE GPIO_LCKR_LCK8_Msk CAN_FFA1R_FFA8_Msk DMA_IFCR_CTCIF7 EXTI_SWIER_SWI0 ADC_CR1_JDISCEN IS_TIM_CC3_INSTANCE EXTI_RTSR_TR2_Pos EXTI_SWIER_SWI14 USB_EP0R_STAT_RX_1 USB_EP6R_EA_Pos CAN_TDL1R_DATA3_Msk CAN_F9R2_FB3_Msk CAN_MSR_INAK_Pos
+syn keyword CTagsDefinedName CAN_F10R1_FB12 CAN_F10R1_FB19_Pos CAN_F3R2_FB14_Pos CAN_F8R1_FB25 ADC_SR_EOS_Msk CAN_F1R2_FB18_Msk CAN_RDH1R_DATA4 CAN_F11R1_FB17_Msk USB_CNTR_ESOFM_Msk BKP_DR1_D_Msk USB_COUNT5_RX_1_NUM_BLOCK_1_2 DMA1_Channel7_BASE PWR_CR_PVDE GPIO_CRH_MODE I2C_CR2_FREQ_4 TIM_SMCR_TS_0 CAN_F2R1_FB12_Msk CAN_F11R2_FB4_Msk TIM_CCMR1_CC2S_Msk PWR_CR_PDDS_Pos WWDG_CFR_W5 USB_COUNT1_RX_0_BLSIZE_0 GPIO_LCKR_LCK10_Msk RCC_APB1ENR_SPI2EN_Msk CAN_TDL1R_DATA3 USART_CR1_TXEIE_Pos CAN_F5R2_FB23
+syn keyword CTagsDefinedName ADC_JSQR_JSQ3_1 GPIO_CRH_MODE11_Msk CAN_F1R1_FB30_Pos CAN_F0R2_FB24 CAN_F11R1_FB17 CAN_F13R2_FB11 CAN_IER_FMPIE0_Msk USB_EPTX_STAT_Pos RCC_BDCR_RTCSEL_NOCLOCK AFIO_EXTICR4_EXTI13_Msk AFIO_EVCR_PIN_PX14 AFIO_EXTICR2_EXTI4_PB CAN_F3R2_FB11_Pos SYSCFG_EXTI_PE_MASK USB_COUNT4_RX_1_NUM_BLOCK_1 CAN_FFA1R_FFA4 CAN_F12R1_FB20_Pos GPIO_BRR_BR1_Msk CAN_F12R1_FB0_Msk DMA_CCR_PINC USB_COUNT5_TX_COUNT5_TX AFIO_EVCR_PIN_PX8 I2C_CR1_SMBUS_Msk CAN_FS1R_FSC10 ADC_SMPR2_SMP2 ADC_CR2_CONT_Msk
+syn keyword CTagsDefinedName EXTI_RTSR_RT4 SDIO_CLKCR_WIDBUS_0 FLASH_ACR_PRFTBE SDIO_MASK_DCRCFAILIE_Msk EXTI_SWIER_SWI11 PWR_CR_PLS_1 CAN_F10R2_FB23 EXTI0_IRQ_PRIORITY USART_GTPR_PSC_2 ADC_SMPR1_SMP11 CAN_F13R2_FB28_Msk CAN_F6R1_FB28 TIM_DIER_CC1IE_Msk RCC_CFGR_PPRE2_DIV4 GPIO_LCKR_LCK9 CAN_F9R1_FB26_Pos GPIO_ODR_ODR2_Pos CAN_F11R2_FB19 AFIO_EXTICR1_EXTI2_PG_Msk GPIO_CRH_MODE_Pos PWR_CR_DBP_Pos SDIO_CMD_SDIOSUSPEND TIM_CCMR1_CC2S_Pos USB_EP0R_EP_TYPE SDIO_RESP4_CARDSTATUS4_Pos CAN_F6R1_FB8
+syn keyword CTagsDefinedName ADC_SMPR1_SMP17_Pos AFIO_EVCR_PIN_PX7_Pos CAN_F4R1_FB28_Pos CAN_F8R1_FB23_Pos SPI1_IRQ_PRIORITY CAN_F0R2_FB15_Msk ADC_SQR3_SQ3_3 CAN_F12R2_FB26_Pos CAN_F10R1_FB20_Msk CAN_FS1R_FSC12_Msk CAN_F0R2_FB18 CAN_F9R2_FB30_Msk USB_COUNT6_TX_0_COUNT6_TX_0 EXTI_EMR_MR5_Pos CAN_F2R2_FB18_Msk CAN_F4R1_FB21 CAN_TSR_LOW1_Msk USB_COUNT5_RX_1_COUNT5_RX_1 EXTI_PR_PR5_Msk CAN_F12R1_FB6 AFIO_EXTICR2_EXTI6_PG GPIO_CRH_CNF10 CAN_F6R1_FB19 CAN_TSR_RQCP2 IS_RTC_ALL_INSTANCE CAN_F12R2_FB24_Pos
+syn keyword CTagsDefinedName USART_CR3_DMAT_Pos AFIO_EXTICR1_EXTI0_PC SDIO_STA_TXDAVL_Msk CAN_F3R2_FB10_Msk CAN_F7R2_FB6 CAN_F5R2_FB0_Msk USB_HP_IRQHandler ADC_CR1_EOSIE_Msk CAN_F11R1_FB10_Msk CAN_F11R2_FB27_Pos CAN_RDT1R_DLC_Pos CAN_F11R1_FB31_Pos RCC_CFGR_PPRE2_DIV16 CAN_F3R2_FB13 CAN_F8R1_FB10 FLASH_DATA0_nDATA0_Pos CAN_F8R2_FB5_Msk CAN_F4R1_FB27_Pos CAN_F12R1_FB19_Msk ADC_CR1_AWDIE USB_COUNT7_RX_BLSIZE_Msk I2C1_BASE CAN_F4R2_FB31_Msk CAN_FA1R_FACT1 CAN_F2R1_FB12_Pos CAN_F8R1_FB24_Msk CAN_F12R2_FB29_Pos
+syn keyword CTagsDefinedName I2C_OAR1_ADD4 CAN_F0R2_FB15 IWDG_RLR_RL_Pos USART_CR3_NACK USB_COUNT5_TX_0_COUNT5_TX_0 CAN_F6R1_FB4 RCC_CR_HSEON_Pos RCC_CFGR_HPRE_Pos CAN_TDL1R_DATA1_Msk USB_EP_RX_DIS EXTI_EMR_MR17_Msk CAN_F1R2_FB13_Msk USB_EP2R_CTR_TX_Msk ADC_SMPR1_SMP10 EXTI_IMR_IM12 USB_ADDR5_RX_ADDR5_RX USB_DADDR_ADD0 CAN_F12R1_FB10 CAN_F8R2_FB9 AFIO_EXTICR3_EXTI8_PE_Msk USB_EP2R_EP_TYPE_0 CAN_F4R1_FB17 CAN_F4R1_FB30_Msk CAN_F9R2_FB15_Msk CAN_F8R1_FB2_Pos CAN_F13R1_FB3_Pos READ_BIT BKP_DR3_D
+syn keyword CTagsDefinedName WWDG_CFR_WDGTB_1 CAN_F12R1_FB16 SDIO_DCTRL_RWSTOP_Pos CAN_F8R2_FB11 CAN_F13R1_FB7_Msk FLASH_OBR_nRST_STDBY_Pos USB_EPTX_STAT_Msk SDIO_DCTRL_RWMOD RCC_CFGR_SWS_Msk USB_EP0R_STAT_RX CAN_TDH2R_DATA7_Pos RCC_CR_HSION_Pos RCC_APB1RSTR_WWDGRST_Pos CAN_F0R2_FB11_Pos RCC_APB2ENR_IOPCEN_Pos CAN_F9R2_FB22_Msk I2C_CR1_ENGC_Msk CAN_F4R1_FB18_Pos EXTI_RTSR_TR3_Msk GPIO_CRH_CNF14_1 GPIO_BRR_BR4_Pos CAN_TDT1R_TIME_Msk CAN_F2R2_FB28 CAN_F10R2_FB6 CAN_F0R1_FB6_Msk CAN_F11R2_FB8_Pos
+syn keyword CTagsDefinedName USB_DADDR_ADD6_Pos ADC_SQR1_SQ14 USB_EP5R_STAT_RX_Pos CAN_TDH0R_DATA4_Pos CAN_F8R2_FB25_Msk AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos CAN_F12R2_FB10_Pos RCC_APB1RSTR_TIM4RST_Msk CAN_FFA1R_FFA_Msk CAN_F11R1_FB4_Pos CAN_F8R1_FB11_Msk RCC_MAX_FREQUENCY EXTI_RTSR_TR5 CAN_F10R2_FB18_Pos USB_EP_DTOG_RX FLASH_RDP_nRDP CAN_F9R1_FB23_Pos SDIO_MASK_CMDACTIE_Pos EXTI_FTSR_FT6 RCC_CIR_PLLRDYF DBGMCU_CR_DBG_TIM4_STOP FLASH_OBR_OPTERR DMA_IFCR_CTCIF2_Pos ADC_CR2_JSWSTART_Pos CAN_FMR_CAN2SB_Msk
+syn keyword CTagsDefinedName DMA_IFCR_CTCIF3 RCC_CFGR_PLLXTPRE_HSE USB_EP2R_CTR_TX_Pos ADC_SQR3_SQ4_0 EXTI_PR_PR18 USART_SR_PE AFIO_EXTICR3_EXTI9_Msk SDIO_CMD_CMDINDEX_Msk ADC_SMPR1_SMP16_Pos FLASH_RDP_RDP_Msk CAN_F1R1_FB16 RCC_CR_CSSON_Msk USB_COUNT7_RX_1_COUNT7_RX_1 TIM_CCMR1_CC2S OTG_FS_WKUP_IRQn CAN_TDL0R_DATA0 USB_EP7R_DTOG_TX CAN_F5R2_FB20_Pos CAN_TI2R_EXID_Pos ADC_JDR4_JDATA CAN_F10R2_FB16_Pos CAN_F7R1_FB12 DBGMCU ADC_DR_ADC2DATA_Pos CAN_F12R2_FB12_Msk USB_EP0R_STAT_RX_Pos CAN_F13R2_FB5
+syn keyword CTagsDefinedName I2C_CCR_DUTY_Msk TIM_BDTR_AOE CAN_F12R2_FB5_Msk CAN_FM1R_FBM9_Pos CAN_F2R2_FB11_Msk USB_ADDR4_TX_ADDR4_TX_Msk PIN_OPT_AF6 USART_SR_RXNE CAN_F7R2_FB10 GPIO_CRL_MODE3_Msk GPIO_CRL_CNF0_0 CAN_F7R2_FB2_Msk AFIO_EVCR_PIN_PX8_Pos CAN_F3R1_FB11_Pos CAN_F8R2_FB1 EXTI_SWIER_SWIER4_Pos CAN_F9R1_FB22_Msk AFIO_EXTICR3_EXTI11_PC CAN_F8R2_FB24_Pos CAN_F4R2_FB0_Pos RCC_CSR_PINRSTF_Pos USB_EP3R_EP_TYPE DMA_CCR_DIR EXTI_SWIER_SWIER5_Msk DMA_ISR_GIF5_Pos CAN_F3R1_FB23 CAN_F7R2_FB11
+syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI1_PE SDIO_DCTRL_SDIOEN DBGMCU_CR_DBG_STANDBY_Pos USB_ADDR0_RX_ADDR0_RX_Pos RCC_APB2RSTR_ADC1RST_Pos USB_COUNT3_TX_0_COUNT3_TX_0 CAN_F13R1_FB24_Pos CAN_F2R2_FB11_Pos CAN_F11R1_FB4_Msk RTC_CRL_RTOFF_Pos USART_GTPR_GT TIM_SMCR_ETP USB_EP4R_DTOG_TX_Msk RCC_APB1ENR_USART3EN_Pos GPIO_LCKR_LCK7_Pos USB_EPRX_STAT_Pos CAN_RDT0R_FMI_Msk USB_EP3R_EP_TYPE_1 CAN_F3R2_FB3 CAN_F2R2_FB20_Msk TIM_EGR_CC1G CAN_MSR_SLAK_Msk CAN_F0R2_FB16_Pos DBGMCU_CR_TRACE_MODE_1
+syn keyword CTagsDefinedName CAN_F2R2_FB1_Msk AFIO_EXTICR2_EXTI5_PB_Msk SDIO_DTIMER_DATATIME_Msk TIM_SR_CC3OF_Pos BKP_CSR_CTE EXTI_SWIER_SWIER9 ADC_JSQR_JSQ4 USB_ISTR_RESET_Msk I2C_SR2_DUALF_Msk RCC_CIR_HSERDYC_Pos USB_COUNT5_RX_NUM_BLOCK CAN_F1R1_FB15_Msk ADC_SMPR2_SMP8_1 GPIO_IDR_IDR12_Pos CAN_F13R1_FB8_Pos DMA_ISR_TEIF3 RCC_CIR_LSERDYF_Pos AFIO_EXTICR1_EXTI0_PD_Msk AFIO_EXTICR3_EXTI8_PG CAN_F13R2_FB2_Msk CAN_F3R1_FB1_Msk CAN_F2R1_FB20_Msk TIM_CCMR1_OC1M_0 CAN_F3R2_FB27_Msk AFIO_EXTICR3_EXTI8_PF
+syn keyword CTagsDefinedName USART_CR1_TXEIE_Msk USB_EP3R_CTR_TX CAN_F4R1_FB2_Msk CAN_F7R1_FB27_Pos USB_EP3R_EP_TYPE_Msk AFIO_EXTICR2_EXTI5_PF TIM_CCMR2_IC3F_1 USB_EP2R_STAT_RX AFIO_EXTICR3_EXTI8_PB TIM_CR1_CMS USB_EP0R_STAT_TX CAN_F5R2_FB14_Pos GPIO_LCKR_LCK2_Msk USB_EP1R_CTR_RX RCC_APB1ENR_WWDGEN_Pos USB_EP1R_EP_KIND_Msk GPIO_IDR_IDR4_Pos USART_CR2_LBCL_Msk CAN_F11R2_FB20 TIM_DIER_CC3DE SDIO_CMD_CPSMEN_Msk EXTI_EMR_MR6_Msk SDIO_STA_RXFIFOHF_Msk DBGMCU_IDCODE_REV_ID_10 GPIO_IDR_IDR1_Msk
+syn keyword CTagsDefinedName RCC_CIR_HSIRDYF_Pos USB_EP0R_CTR_TX_Pos CAN_F3R2_FB1_Msk AFIO_EXTICR4_EXTI15_PD I2C_OAR2_ADD2_Msk CAN_RI1R_EXID GPIO_CRH_MODE15 RCC_CSR_IWDGRSTF_Pos CAN_RDL0R_DATA0_Pos CAN_F4R2_FB30 CAN_F0R1_FB19_Pos CAN_F7R2_FB1_Pos CAN_F6R1_FB6_Msk AFIO_EXTICR1_EXTI0_PD USB_COUNT7_TX_COUNT7_TX_Pos EXTI_PR_PR17 ADC_SMPR1_SMP12 CAN_F2R2_FB30 CAN_TSR_TXOK1 CAN_F6R1_FB12_Msk IS_TIM_OCXREF_CLEAR_INSTANCE DBGMCU_CR_TRACE_IOEN_Pos CAN_F4R1_FB11_Msk CAN_F3R2_FB27_Pos CAN_F5R1_FB30_Pos
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PE_Pos GPIO_CRH_CNF12_Pos SDIO_STA_RXFIFOE_Pos ADC_SQR2_SQ8 USB_EP4R_DTOG_RX USB_EP7R_DTOG_TX_Pos AFIO_EXTICR3_EXTI9_PE_Msk CAN_FA1R_FACT12_Pos GPIO_ODR_ODR10 EXTI_IMR_MR15_Msk SDIO_DCTRL_DBLOCKSIZE TIM_SMCR_TS_1 CAN_F0R1_FB2_Pos DMA_CCR_PSIZE_Pos RCC_BDCR_BDRST_Msk AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PG_Pos AFIO_EXTICR3_EXTI11_PD_Pos TIM_SMCR_ETF CAN_F0R2_FB23_Msk CAN_RDL0R_DATA1_Msk EXTI_FTSR_FT13 DMA_CMAR_MA CAN_F13R1_FB4_Pos TIM_CCMR2_CC4S_Msk
+syn keyword CTagsDefinedName SDIO_MASK_TXUNDERRIE_Pos EXTI_IMR_MR14_Pos USB_EP0R_EP_TYPE_1 TIM_CR1_ARPE_Pos TIM_SMCR_ECE_Msk I2C_SR1_SMBALERT USART_GTPR_PSC_Msk ADC_SQR1_SQ14_0 USB_ADDR7_TX_ADDR7_TX_Pos GPIO_LCKR_LCKK_Pos PIN_5 CAN_F13R2_FB22_Msk PIN_4 CAN_FFA1R_FFA10_Msk USB_ADDR6_TX_ADDR6_TX_Msk CAN_F11R1_FB18_Msk CAN_F6R2_FB19_Pos AFIO_EXTICR2_EXTI5_PE USB_CNTR_FRES_Pos USB_CNTR_CTRM_Msk USART2_IRQ_PRIORITY CAN_F7R1_FB31_Pos TIM_EGR_CC4G I2C_CR2_FREQ_Msk CAN_F8R1_FB27_Pos USB_EP5R_EP_KIND_Pos
+syn keyword CTagsDefinedName ADC_SMPR1_SMP15_1 SDIO_ICR_CMDRENDC_Pos SDIO_STA_DBCKEND_Msk USB_FNR_RXDP SPI_CR1_BIDIMODE CAN_F2R2_FB2_Msk IS_ADC_MULTIMODE_MASTER_INSTANCE AFIO_EXTICR3_EXTI9_PF CAN_F11R1_FB8_Pos ADC_SMPR2_SMP3_Pos ADC_CR2_EXTSEL_Pos USB_COUNT3_RX_1_NUM_BLOCK_1_2 CAN_F2R2_FB5_Msk CAN_F1R1_FB13_Msk CAN_F4R1_FB29 CAN_F0R1_FB13_Pos CAN_F13R1_FB5_Msk GPIO_LCKR_LCK5_Msk CAN_F2R1_FB25_Msk USB_COUNT2_RX_NUM_BLOCK_0 CAN_F5R2_FB2 AFIO_EXTICR1_EXTI3_PE_Msk AFIO_EXTICR2_EXTI4_PD_Msk CAN_F5R1_FB0_Pos
+syn keyword CTagsDefinedName CAN_F6R1_FB0_Pos CAN_FFA1R_FFA2_Msk CAN_F13R1_FB27 GPIO_IDR_IDR2 CAN_F1R1_FB29_Msk CAN_F0R2_FB6_Pos USB_FNR_LSOF_Msk CAN_F1R1_FB27_Pos CAN_TDL1R_DATA1_Pos CAN_FM1R_FBM13 CAN_F6R1_FB18_Msk CAN_FM1R_FBM10 GPIO_IDR_IDR11_Pos DMA_IFCR_CHTIF4_Pos SDIO_CMD_WAITPEND SDIO_DCTRL_SDIOEN_Msk SPI_CR2_TXEIE_Pos TIM_SMCR_TS_2 TIM_CR2_OIS2N_Pos CAN_F9R1_FB17 CRC_IDR_IDR_Pos CAN_RDL1R_DATA2_Msk IWDG_PR_PR_Pos USB_DADDR_ADD2_Msk EXTI_SWIER_SWIER12_Pos CAN_F1R1_FB24_Msk CAN_F4R2_FB15_Pos
+syn keyword CTagsDefinedName CAN_F10R2_FB13_Msk FLASH_DATA0_DATA0_Pos WWDG_CFR_W_3 CAN_F8R1_FB16_Pos CAN_F2R2_FB10_Pos RCC_APB2ENR_IOPBEN_Msk ADC_SQR3_SQ5_Pos USB_EP5R_DTOG_TX CAN_F7R1_FB1_Pos FLASH_WRP1_WRP1_Msk EXTI_EMR_EM16 RCC_CFGR_HPRE_DIV_128 EXTI_FTSR_FT14 GPIO_ODR_ODR1 USB_EP7R_EP_TYPE_1 TIM_CR1_CEN_Pos CAN_F6R2_FB24_Msk CAN_RF0R_FULL0_Pos USB_COUNT7_RX_COUNT7_RX_Msk CAN_F0R1_FB2_Msk TIM_CCMR1_OC2M_2 PIN_OPT_RESISTOR_PULLDOWN CAN_F11R1_FB0 SPI_CR1_BIDIOE_Msk EXTI_RTSR_RT10 CAN_MSR_INAK SPI_CR1_DFF
+syn keyword CTagsDefinedName I2C_SR1_PECERR_Msk CAN_F5R1_FB13_Pos TIM_CCMR1_CC1S_Pos FLASH_ACR_LATENCY USB_COUNT1_RX_0_NUM_BLOCK_0_4 AFIO_EXTICR1_EXTI3_PD_Msk RCC_APB1ENR_TIM2EN ADC_SR_STRT_Msk CAN_TSR_TXOK2 CAN_TSR_TXOK0_Msk GPIO_CRL_CNF3 USB_EPRX_DTOG1 CAN_F6R1_FB18_Pos CAN_F1R1_FB6_Pos CAN_F3R1_FB19_Pos SDIO_STA_STBITERR CAN_F1R2_FB26_Pos TIM10_IRQn CAN_F2R1_FB14_Pos PWR_CR_CSBF_Pos CAN_F5R2_FB26_Pos GPIO_IDR_IDR11_Msk TIM_DCR_DBL CAN_F7R1_FB31_Msk CAN_FA1R_FACT10_Pos FLASH_OBR_DATA1 CAN_F6R2_FB14_Msk
+syn keyword CTagsDefinedName AFIO_EVCR_PORT_PC CAN_F0R2_FB26_Msk AFIO_EXTICR1_EXTI1_PC_Msk GPIO_LCKR_LCK15_Msk EXTI_EMR_MR4_Pos TIM_CCER_CC1E AFIO_EXTICR4_EXTI14_PC_Msk AFIO_EVCR_PIN_PX14_Msk CAN_F3R2_FB16_Pos TIM_CCMR2_IC3PSC_Msk RCC_APB1ENR_USBEN_Pos CAN_F10R1_FB12_Pos CAN_FA1R_FACT_Msk GPIO_BSRR_BR4_Msk CAN_F6R2_FB16_Pos CAN_F2R1_FB0_Msk CAN_F12R2_FB13_Pos CAN_TI2R_STID GPIO_IDR_IDR5 GPIO_BRR_BR13_Msk RCC_CFGR_MCO_2 CAN_F4R1_FB3_Msk CAN_F13R2_FB25_Pos CAN_F11R2_FB21_Pos I2C_CR1_NOSTRETCH
+syn keyword CTagsDefinedName GPIO_ODR_ODR9_Pos CAN_F4R1_FB1 CAN_F11R1_FB14_Pos RCC_APB1RSTR_TIM3RST_Pos BKP_CR_TPE CAN_ESR_TEC_Msk CAN_TSR_TME0 GPIO_BRR_BR8 CAN_F13R1_FB13_Pos GPIO_BSRR_BR3_Msk IWDG_RLR_RL_Msk CAN_TI1R_EXID_Pos CAN_TSR_CODE_Msk CAN_F5R1_FB4_Pos I2C_CR2_ITERREN RCC_APB2RSTR_IOPBRST_Msk SDIO_STA_STBITERR_Msk CAN_ESR_BOFF TIM_CCER_CC2NE USB_COUNT1_RX_NUM_BLOCK_0 I2C_SR2_DUALF_Pos SPI_CR1_SSI GPIO_ODR_ODR12_Pos CAN_RI1R_RTR_Msk GPIO_BSRR_BR11_Pos CAN_F3R1_FB21_Msk CAN_F9R2_FB22
+syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP CAN_F0R2_FB19 EXTI_RTSR_TR16_Pos CAN_FFA1R_FFA3_Pos CAN_F13R2_FB15 GPIO_BRR_BR14 USB_DADDR_ADD4 CAN_F7R1_FB30_Pos AFIO_MAPR_CAN_REMAP_REMAP3 USB_EP0R_STAT_RX_Msk CAN_F8R2_FB15_Pos USB_EP6R_SETUP_Pos CAN_F11R2_FB9 USART_CR1_TCIE_Pos CAN_F12R1_FB2 CAN_TI0R_RTR_Pos SPI_I2SCFGR_I2SMOD AFIO_EXTICR1_EXTI0_PF_Pos DMA_CCR_MSIZE USB_DADDR_ADD2_Pos I2C_CR2_FREQ_1 SDIO_DCTRL_SDIOEN_Pos GPIO_CRH_CNF10_0 CAN_F11R2_FB26_Pos CAN_F3R2_FB21_Msk USB_EP3R_DTOG_TX_Msk
+syn keyword CTagsDefinedName CAN_F9R1_FB29 TIM_CNT_CNT_Pos ADC_SQR2_SQ12_4 DMA_ISR_GIF6_Pos CAN_F2R2_FB25_Pos AFIO_MAPR_SPI1_REMAP ADC_CR1_AWDSGL CAN_F10R2_FB12_Msk CAN_F12R1_FB23_Pos SDIO_CMD_CEATACMD_Pos CAN_F1R2_FB28_Msk CAN_F4R2_FB4_Msk GPIO_BRR_BR12_Pos CAN_MCR_NART_Msk CAN_RDT1R_DLC CAN_F12R2_FB19_Msk BKP_CSR_TEF SDIO_MASK_CEATAENDIE_Msk CAN_F3R1_FB8 AFIO_EXTICR1_EXTI2_PB_Pos CAN_F5R1_FB19_Msk SDIO_ARG_CMDARG GPIO_IDR_IDR8_Msk CEC_IRQHandler TIM_CCMR2_CC4S_Pos USB_EP3R_DTOG_TX USB_EP7R_CTR_RX_Msk
+syn keyword CTagsDefinedName FLASH_BANK1_END CAN_FS1R_FSC9_Msk DMA_CCR_PINC_Pos CAN_F7R1_FB4 RCC_CR_PLLON_Msk TIM_CCMR1_IC2PSC_1 FLASH_WRP1_WRP1_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_4 CAN_F1R2_FB1 GPIO_CRH_MODE8_1 USB_EP0R_DTOG_RX ADC_CR1_DISCEN BKP_DR9_D ADC_CR2_EXTSEL_Msk USB_CNTR_WKUPM CAN_F2R2_FB24_Msk SDIO_ICR_DCRCFAILC CAN_F1R1_FB11_Pos CAN_F0R1_FB18_Msk EXTI_PR_PR16_Msk CAN_F7R2_FB25 CAN_IER_EWGIE_Pos SPI_CR1_BIDIMODE_Msk TIM_CCMR2_OC4FE_Msk RCC_CFGR_USBPRE USB_COUNT2_RX_NUM_BLOCK_3 GPIO_CRH_CNF8_Msk
+syn keyword CTagsDefinedName USB_CNTR_ERRM_Msk ADC_SQR2_SQ12_Pos DMA_IFCR_CHTIF5_Msk CAN_F0R1_FB15 AFIO_EXTICR1_EXTI0_PE_Pos USB_EPRX_STAT RCC_CSR_PINRSTF USB_EP7R_CTR_RX CAN_F6R1_FB0 TIM_CCER_CC1E_Msk USB_ADDR3_RX_ADDR3_RX_Pos CAN_TDT1R_TGT USB_EP2R_DTOG_RX_Pos CAN_F1R2_FB2_Msk AFIO_EVCR_PIN_0 GPIO_IDR_IDR7 TIM_CR2_OIS1N_Msk GPIO_CRL_MODE TIM_CCMR2_OC4PE CAN_F7R1_FB30 GPIO_CRH_MODE8_Msk CAN_F6R1_FB4_Msk CAN_F2R2_FB21_Pos CAN_F5R2_FB24 GPIO_CRL_CNF0_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_2 CAN_F9R1_FB10
+syn keyword CTagsDefinedName USB_CNTR_RESUME IWDG_PR_PR_1 CAN_RDT1R_FMI_Msk CAN_F4R2_FB27_Msk CAN_F10R2_FB3_Msk EXTI_SWIER_SWI16 CAN_F0R2_FB18_Pos EXTI_FTSR_TR10 CAN_F9R1_FB5 CAN_F11R2_FB24 CAN_F10R1_FB20 RCC_BDCR_RTCSEL_Msk CAN_F8R2_FB15_Msk CEC_IRQn CAN_F13R1_FB31_Msk FLASHSIZE_BASE CAN_F8R1_FB24_Pos SDIO_DLEN_DATALENGTH_Pos EXTI_RTSR_TR6_Pos BKP_DR10_D_Pos CAN_F12R1_FB30_Msk RCC_CSR_LSION TIM2_IRQ_PRIORITY USB_COUNT6_RX_1_COUNT6_RX_1 CAN_F1R1_FB8_Msk EXTI_EMR_MR9_Pos TIM_SR_CC3IF_Msk IS_SPI_ALL_INSTANCE
+syn keyword CTagsDefinedName CAN_TDL0R_DATA0_Msk GPIO_CRL_CNF2_1 CAN_F10R2_FB8_Msk RCC_CIR_CSSF_Pos CAN_F5R1_FB6_Pos USART_CR1_M CAN_TDH1R_DATA6_Msk RCC_CIR_LSIRDYIE CAN_FFA1R_FFA9_Msk CAN_F11R2_FB5 TIM_DMAR_DMAB_Pos CAN_F12R2_FB1_Pos CAN_F0R2_FB19_Msk AFIO_EVCR_PIN_PX4_Pos CAN_F1R1_FB21_Msk CAN_F6R1_FB5_Pos AFIO_EXTICR2_EXTI7_PC_Msk FLASH_DATA0_nDATA0_Msk TIM_ARR_ARR_Pos SPI_CR2_SSOE_Msk CAN_F10R1_FB8_Msk CAN_F8R1_FB27_Msk CAN_F9R1_FB1_Msk ADC_CR1_DISCEN_Pos ADC_CR2_ADON ADC_CR2_EXTSEL_1 CAN_F1R2_FB0_Msk
+syn keyword CTagsDefinedName CAN_F2R2_FB9_Pos CAN_F8R1_FB22_Msk GPIO_BSRR_BR8_Msk TIM_CCMR1_OC2CE AFIO_EXTICR2_EXTI6_PF USART_CR3_HDSEL_Msk SDIO_MASK_CMDRENDIE_Msk CAN_MSR_SLAK CAN_F8R2_FB6_Msk DMA_CCR_TCIE GPIO_LCKR_LCK12_Pos EXTI_RTSR_TR10 CAN_IER_FOVIE0_Msk I2C_SR1_BTF_Pos SDIO_STA_RXOVERR_Msk SPI_RXCRCR_RXCRC USB_EP6R_EP_TYPE USB_EP_T_MASK FLASH_WRP1_nWRP1_Msk TIM_CCMR1_CC2S_0 CAN_F0R1_FB4 DMA_ISR_HTIF5_Pos EXTI_IMR_MR16_Pos I2C_CR1_POS_Msk USB_COUNT5_RX_1_NUM_BLOCK_1_3 USB_EP2R_STAT_RX_Msk
+syn keyword CTagsDefinedName I2C_CR1_SMBTYPE_Msk CAN_MCR_SLEEP_Msk CAN_F12R2_FB11 CAN_F8R1_FB3_Msk EXTI_RTSR_TR9_Pos SDIO_MASK_DBCKENDIE_Msk SPI_SR_RXNE_Msk CAN_F1R1_FB8 USB_EP7R_STAT_RX DMA_ISR_HTIF6_Msk GPIO_BSRR_BS13 CAN_F13R1_FB19_Msk GPIO_CRL_CNF3_Pos CAN_BTR_BRP CAN_F3R1_FB23_Msk GPIO_LCKR_LCK11_Msk CAN_F3R2_FB4 TIM1 I2C_OAR1_ADD1_7 RCC_CIR_PLLRDYC_Pos USART_GTPR_PSC_0 SPI_SR_BSY_Pos EXTI_IMR_MR13 FLASH_SR_PGERR FLASH_OBR_DATA1_Msk CAN_F1R2_FB10 CAN_F2R2_FB24 CAN_F8R2_FB6_Pos CAN_F11R1_FB15
+syn keyword CTagsDefinedName CAN_F3R2_FB29 CAN_F9R1_FB23_Msk CAN_F13R1_FB30 CAN_F1R1_FB5_Msk CAN_F11R2_FB13_Pos AFIO_EVCR_PIN_PX9 DMA_CCR_MEM2MEM_Pos RCC_CFGR_PLLMULL4_Msk ADC_SQR2_SQ7_1 CAN_F9R1_FB12 CAN_F2R2_FB22 CAN_F8R2_FB21_Msk CAN_RDL0R_DATA0_Msk GPIO_ODR_ODR11_Pos USB_EP6R_DTOG_TX_Msk CAN_TDL1R_DATA2_Msk GPIO_CRH_CNF9_Msk RCC_CFGR_USBPRE_Msk CAN_TSR_ALST2_Msk CAN_F2R1_FB25 CAN_F11R2_FB11_Pos EXTI_FTSR_TR7_Msk RTC_PRLH_PRL_Pos CAN_F4R1_FB30 EXTI_SWIER_SWIER2_Msk CAN_RDT0R_DLC_Msk CAN_BTR_TS1_3
+syn keyword CTagsDefinedName CAN_F13R1_FB14_Pos SDIO_POWER_PWRCTRL_Msk USB_COUNT3_RX_0_NUM_BLOCK_0_0 EXTI_SWIER_SWIER3_Pos ADC_SR_AWD_Pos USB_COUNT5_RX_NUM_BLOCK_4 CAN_F4R1_FB19_Msk CAN_F0R1_FB25_Msk TIM_CCMR1_IC1F_1 ADC_JSQR_JSQ4_2 AFIO_EXTICR4_EXTI14_PD PIN_MODE_OUTPUT CAN_F8R2_FB13 CAN_F11R2_FB31_Msk CAN_TSR_TME2 DBGMCU_IDCODE_REV_ID_8 USB_COUNT0_RX_COUNT0_RX_Msk SDIO_MASK_TXDAVLIE_Pos USART_SR_LBD DMA_ISR_TEIF1_Pos FLASH_WRP3_nWRP3_Msk USB_COUNT4_RX_NUM_BLOCK RCC_CFGR_HPRE_3 TIM_SMCR_SMS_1
+syn keyword CTagsDefinedName CAN_F1R2_FB8_Msk CAN_F8R2_FB6 TIM_BDTR_DTG_2 ADC_DR_DATA EXTI_RTSR_TR6 WWDG_CFR_EWI_Msk CAN_F10R2_FB6_Pos CAN_F9R2_FB30_Pos DMA_IFCR_CTEIF4_Msk I2C_CR1_ENPEC_Pos AFIO_EXTICR2_EXTI5_PG_Pos RCC_CIR_LSIRDYC_Msk CAN_F2R2_FB3_Msk CAN_F12R1_FB25_Pos CAN_TI0R_RTR_Msk DMA1_Channel1_BASE AFIO_EXTICR4_EXTI14_PF_Pos CAN_F1R2_FB16 CAN_F1R2_FB25_Pos GPIO_IDR_IDR13_Pos AFIO_MAPR_CAN_REMAP_Msk CAN_F9R1_FB27_Pos USB_EP5R_EP_TYPE_0 CAN_F11R2_FB20_Msk AFIO_EXTICR3_EXTI8_Msk RCC_APB1RSTR_TIM2RST
+syn keyword CTagsDefinedName USB_EP2R_DTOG_RX USB_ADDR5_RX_ADDR5_RX_Msk PWR_CSR_WUF EXTI_FTSR_FT5 AFIO_EXTICR2_EXTI4_Msk CAN_F2R1_FB28_Msk RCC_APB1ENR_TIM2EN_Pos TIM_CR2_OIS2N AFIO_EXTICR1_EXTI1_PG_Msk ADC_CR1_AWDSGL_Msk CAN_TSR_TXOK2_Pos CAN_F12R2_FB7 DMA_ISR_HTIF2 GPIO_ODR_ODR5_Pos AFIO_EXTICR1_EXTI0_PB_Msk SDIO_DLEN_DATALENGTH TIM_SMCR_SMS_0 USART_CR3_EIE DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk EXTI_IMR_IM15 EXTI_SWIER_SWI3 CAN_F2R1_FB12 CAN_F13R1_FB31_Pos CAN_F0R2_FB25_Msk CAN_F7R1_FB19_Pos
+syn keyword CTagsDefinedName CAN_TDL0R_DATA1 ADC_SMPR1_SMP14_Msk RCC_CFGR_SW IWDG_SR_RVU_Pos GPIO_BRR_BR7_Pos CAN_F2R1_FB20_Pos ADC_CR2_RSTCAL_Pos CAN_TSR_CODE_Pos EXTI_EMR_EM17 TIM_BDTR_MOE USB_COUNT3_RX_BLSIZE_Pos CAN_F10R2_FB30_Pos CAN_F11R1_FB3 CAN_F3R2_FB18 CAN_F13R1_FB1_Msk I2C_CCR_DUTY_Pos USB_EP3R_STAT_RX_1 RCC_BDCR_LSEON_Msk WWDG_CFR_W4 CAN_F9R2_FB18_Msk FLASH_ACR_PRFTBS_Msk CAN_F6R1_FB29 CAN_F3R1_FB25_Pos TIM_BDTR_BKE_Msk CAN_F11R1_FB31_Msk ADC_CR2_JEXTTRIG_Pos CAN_F8R1_FB23 ADC_JSQR_JSQ3_4
+syn keyword CTagsDefinedName CAN_F5R2_FB13_Pos TIM_CR2_OIS3N RCC_CFGR_MCOSEL_HSI RCC_CIR_HSIRDYIE_Pos GPIO_CRL_MODE0 ADC_CR2_RSTCAL TIM_CCMR2_IC3F_0 WWDG_CR_T_3 RTC_CRL_SECF CAN_F9R2_FB19 AFIO_EVCR_PIN_PX1_Msk RCC_CFGR_USBPRE_Pos CAN_F1R2_FB29_Pos I2C_CR2_LAST_Pos ADC_SQR2_SQ8_Pos DMA_ISR_TEIF7_Msk GPIO_CRH_MODE14_Pos TIM_CCMR2_IC4PSC_Pos USB_EP1R_DTOG_RX_Pos DMA_ISR_HTIF3_Pos CAN_F6R2_FB21_Msk CAN_F13R2_FB9_Msk RCC_APB2ENR_IOPBEN_Pos CAN_MCR_AWUM_Pos BKP_CSR_CTI_Msk CAN_F6R2_FB20 AFIO_EXTICR1_EXTI3_PF
+syn keyword CTagsDefinedName USB_ISTR_SOF_Msk GPIO_CRL_MODE2 AFIO_EXTICR3_EXTI8 DBGMCU_CR_DBG_WWDG_STOP_Pos TIM1_UP_TIM10_IRQn DMA_CCR_TCIE_Msk ADC_SMPR2_SMP0_Msk AFIO_MAPR_USART3_REMAP_1 GPIO_IDR_IDR3_Msk I2C_CR2_ITEVTEN SDIO_ICR_DTIMEOUTC_Pos USB_EP_SETUP_Pos USB_ADDR1_TX_ADDR1_TX_Msk CAN_F3R1_FB22 CAN_TSR_TME0_Pos USB_COUNT1_RX_1_NUM_BLOCK_1_2 CAN_F9R1_FB9_Msk GPIO_BSRR_BS11 CAN_MSR_ERRI SPI_SR_TXE RCC_CFGR_MCO_NOCLOCK SYSCFG_EXTI_PC_MASK CAN_F11R1_FB30_Pos FLASH_CR_LOCK_Msk SDIO_RESP1_CARDSTATUS1_Pos
+syn keyword CTagsDefinedName CAN_F13R2_FB30_Pos CAN_F12R2_FB31_Pos ADC_SQR3_SQ6_1 CAN_F2R1_FB30 CAN_TSR_TXOK0_Pos USB_FNR_FN CAN_F6R1_FB12_Pos CAN_F11R2_FB0_Pos CAN_F6R2_FB21_Pos CAN_F11R1_FB0_Msk USB_EP6R_STAT_TX_Pos ADC_SMPR1_SMP12_Pos CAN_MCR_RFLM_Msk USART_SR_FE_Pos CLEAR_BIT CAN_FFA1R_FFA0 EXTI_EMR_MR12_Msk CAN_F13R1_FB0 CAN_F1R1_FB18_Msk USB_EPADDR_FIELD CAN_F0R2_FB3 SDIO_STA_CMDREND_Msk CAN_F12R2_FB12_Pos ADC_CR1_AWDIE_Pos SDIO_MASK_DBCKENDIE_Pos CAN_F13R1_FB29 CAN_F9R1_FB24_Pos EXTI_FTSR_FT3
+syn keyword CTagsDefinedName GPIO_IDR_IDR9_Msk AFIO_EXTICR1_EXTI1_Pos CAN_F1R2_FB24_Pos CAN_F6R1_FB9 GPIO_ODR_ODR4_Msk CAN_F7R2_FB5 USB_EP6R_DTOG_RX_Pos GPIO_IDR_IDR4 CAN_F10R1_FB10_Pos EXTI_RTSR_TR15_Msk CAN_ESR_EPVF_Pos AFIO_EXTICR3_EXTI9_PG_Pos USB_COUNT2_RX_BLSIZE ADC_CR1_DISCNUM_0 CAN_FFA1R_FFA4_Msk CAN_F1R2_FB9 CAN_F9R2_FB18 CAN_F1R1_FB6_Msk CAN_TSR_ALST0_Pos PERIPH_BASE CAN_F12R2_FB0_Msk DMA_ISR_TCIF4_Msk FLASH_KEY2_Msk DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT RCC_CFGR_HPRE_DIV1 AFIO_EVCR_PIN_PX2_Msk
+syn keyword CTagsDefinedName USB_COUNT5_RX_BLSIZE_Pos TIM_CR2_CCUS_Pos ADC_SMPR1_SMP17 CAN_F8R1_FB21_Pos GPIO_CRL_MODE2_Pos GPIO_CRL_MODE6_Pos CAN_RF1R_FOVR1_Pos GPIO_CRL_CNF6_Pos SDIO_ARG_CMDARG_Msk CAN_F2R2_FB10_Msk AFIO_EXTICR1_EXTI0_PE BKP_CSR_TEF_Msk CAN_F2R2_FB29_Msk CAN_F8R2_FB31_Pos CAN_TSR_ABRQ2_Msk CAN_F5R1_FB11 CAN_FFA1R_FFA_Pos DBGMCU_IDCODE_REV_ID_Pos CAN_F6R1_FB31 RCC_CFGR_PLLMULL14 RCC_APB2ENR_AFIOEN USB_COUNT0_RX_0_NUM_BLOCK_0_4 AFIO_EXTICR4_EXTI12_PE_Pos CAN_ESR_TEC_Pos PIN_0
+syn keyword CTagsDefinedName USB_EP1R_EP_TYPE TIM_BDTR_OSSI_Pos CAN_F13R2_FB8_Msk CAN_F1R2_FB9_Msk CAN_RDL1R_DATA0_Msk CAN_F9R1_FB1_Pos I2C_OAR1_ADD1_Pos SDIO_STA_RXACT_Msk USB_ADDR7_RX_ADDR7_RX_Msk EXTI_IMR_IM16 CAN_F0R2_FB25_Pos PWR_CR_PLS_LEV6 EXTI_FTSR_TR5_Msk CAN_F8R2_FB31 CAN_F6R2_FB18_Pos TIM_BDTR_OSSI USART_CR2_CLKEN CAN_ESR_REC_Pos USB_EP3R_STAT_TX_0 CAN_F1R2_FB0 CAN_F9R2_FB9 I2C_CR1_PEC_Pos TIM_CR2_OIS2 EXTI_FTSR_TR6_Pos TIM_DIER_CC1DE ADC_CR2_EXTTRIG_Pos CAN_F1R1_FB17_Pos EXTI_FTSR_TR14
+syn keyword CTagsDefinedName USB_COUNT2_RX_BLSIZE_Pos CAN_FA1R_FACT1_Pos CAN_F11R2_FB17_Msk CAN_F12R1_FB3 CAN_TI1R_IDE CAN_F9R1_FB9_Pos CAN_F0R1_FB13 AFIO_EXTICR2_EXTI6_Msk USB_COUNT3_RX_0_NUM_BLOCK_0_4 CAN_F11R1_FB23_Msk DMA1_Channel5_BASE TIM_SR_CC3IF USB_COUNT7_RX_1_BLSIZE_1 USB_ISTR_PMAOVR_Msk CAN_F8R2_FB25 GPIO_ODR_ODR14_Pos USB_EP6R_EA TIM_CCMR2_IC4PSC I2C_CR2_ITBUFEN_Msk USB_EP5R_DTOG_RX USB_EP3R_STAT_TX_Pos CAN_F10R2_FB22_Msk RCC_BDCR_RTCEN_Msk CAN_F0R2_FB27 USB_EP_DTOG_TX RCC_CIR_LSERDYC_Pos
+syn keyword CTagsDefinedName CAN_F7R2_FB12 FLASH_KEYR_FKEYR_Msk ADC_CR2_TSVREFE_Pos EXTI_IMR_MR14_Msk DMA_IFCR_CGIF1 CAN_F4R2_FB12_Msk BKP_CSR_CTI_Pos GPIO_BSRR_BR11_Msk TIM_CCR3_CCR3_Pos USB_EP3R_SETUP_Pos CAN_F9R1_FB4 EXTI_IMR_MR5_Pos USB_CNTR_FRES_Msk RCC_APB1ENR_USART2EN I2C_CR1_ENGC_Pos TIM_SMCR_ETP_Msk CAN_F0R2_FB21_Pos BKP_RTCCR_ASOS FLASH_WRP3_nWRP3_Pos USB_EP2R_SETUP_Pos CAN_F6R2_FB0_Msk CAN_F5R2_FB22_Pos CAN_FFA1R_FFA6 USB_EP0R_STAT_TX_Msk GPIO_LCKR_LCK15_Pos CAN_F9R1_FB3_Msk
+syn keyword CTagsDefinedName SDIO_RESP3_CARDSTATUS3_Pos CAN_TI2R_IDE_Pos CAN_FA1R_FACT8_Pos CAN_FS1R_FSC10_Msk RCC_APB1RSTR_USART2RST IWDG CAN_F0R2_FB2_Pos SDIO_MASK_CEATAENDIE AFIO_EVCR_PIN_PX4 BKP_DR2_D_Msk GPIO_BSRR_BR5 TIM_CNT_CNT_Msk CAN_F13R1_FB5_Pos GPIO_CRH_MODE11 GPIO_BRR_BR8_Msk GPIO_CRH_MODE15_1 USB_CNTR_RESETM EXTI_PR_PIF17 USB_EP6R_STAT_TX_1 CAN_F5R1_FB31_Msk TIM_CCR4_CCR4_Pos EXTI_PR_PR7 CAN_F11R1_FB19 CAN_F10R2_FB29 USART1 USART_SR_TXE_Pos USB_EPTX_DTOGMASK TIM_CCMR1_IC2PSC
+syn keyword CTagsDefinedName CAN_F11R1_FB13_Pos AFIO_EXTICR4_EXTI13_PB_Pos ADC_SQR1_L_1 CAN_F11R2_FB8 CAN_F11R2_FB16_Msk CAN_F11R2_FB6_Msk ADC_CR1_AWDCH_Pos GPIO_BSRR_BR2_Pos CAN_MSR_RXM_Pos USB_COUNT7_RX_0_NUM_BLOCK_0_1 RCC_CFGR_PPRE1_Pos ADC_SR_AWD_Msk CAN_F10R1_FB17 CAN_F12R2_FB24_Msk AFIO_EVCR_PIN_PX4_Msk USB_COUNT6_RX_NUM_BLOCK_Pos CAN_F2R2_FB0_Pos CAN_F3R2_FB8_Pos SDIO_RESP0_CARDSTATUS0_Msk CAN_F1R2_FB19 PIN_14 ADC_SMPR2_SMP6_Msk SDIO_RESP2_CARDSTATUS2_Pos I2C_CR2_ITEVTEN_Msk ADC_CR2_JEXTSEL_Pos
+syn keyword CTagsDefinedName AFIO_EXTICR3_EXTI10_PF_Pos CAN_F0R2_FB6_Msk CAN_TDH2R_DATA7 CAN_F1R2_FB25 CAN_F9R1_FB20 TIM_DIER_CC2DE_Pos AFIO_EXTICR4_EXTI12_PB_Pos CAN_F5R2_FB3 CAN_F4R2_FB23 CAN_TSR_TME0_Msk CAN_F8R1_FB4_Msk CAN_F13R2_FB1 CAN_F11R2_FB13 RCC_CFGR_SWS_HSE GPIO_LCKR_LCK14_Pos I2C_OAR1_ADD0 CAN_F12R1_FB1_Msk AFIO_EVCR_PORT_1 AFIO_EVCR_PIN_3 USB_EP_RX_STALL CAN_F5R1_FB2_Pos AFIO_EXTICR2_EXTI6_PG_Msk CAN_F12R2_FB8 SDIO_DCTRL_RWMOD_Pos CAN_FA1R_FACT11 CAN_F6R2_FB23_Pos TIM_CCER_CC4P_Msk
+syn keyword CTagsDefinedName DMA_ISR_TCIF2 GPIO_CRL_MODE1 EXTI_SWIER_SWIER14_Pos USB_ADDR1_TX_ADDR1_TX AFIO_EXTICR2_EXTI6_PC TIM_EGR_CC2G CAN_F6R2_FB10_Msk RCC_BDCR_RTCSEL_Pos DMA1_Channel6 RCC_CR_HSERDY WWDG_CFR_W3 SDIO_STA_RXFIFOHF TIM_CR2_TI1S USB_EP_CTR_TX ADC_SQR3_SQ2_2 CAN_BTR_LBKM_Pos CAN_F1R2_FB15 GPIO_BSRR_BS12_Msk RCC_CFGR_PLLMULL6_Msk CAN_F11R2_FB27_Msk CAN_F12R2_FB18_Msk I2C_CR1_ACK_Pos RCC_CSR_LPWRRSTF CAN_MCR_TXFP_Pos SDIO_RESPCMD_RESPCMD_Pos CAN_FM1R_FBM3 CAN_F7R1_FB7
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PF_Msk CAN_F5R1_FB21_Msk CAN_F7R1_FB21 CAN_F6R1_FB30_Pos FLASH_OBR_nRST_STOP_Pos PIN_2 CAN_F10R1_FB27_Pos CAN_F3R2_FB24 TIM_CCMR1_OC1CE_Msk AFIO_EXTICR3_EXTI10_PE_Pos CAN_F10R1_FB22_Pos I2C_SR1_ADD10_Msk USB_COUNT3_RX_1_NUM_BLOCK_1_1 ADC_CR1_DUALMOD_Pos CAN_F7R1_FB14 CAN_F4R2_FB20 CAN_F7R2_FB4 CAN_F9R1_FB22_Pos IS_TIM_COMMUTATION_EVENT_INSTANCE CAN_RDL0R_DATA1_Pos CAN_F6R2_FB6_Pos GPIO_CRL_CNF4 AFIO_EXTICR2_EXTI6_PE_Msk AFIO_EXTICR3_EXTI9_PC
+syn keyword CTagsDefinedName RCC_APB2RSTR_SPI1RST_Msk EXTI_PR_PR3_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk EXTI_IMR_IM6 CAN_F3R1_FB26 TIM_SMCR_SMS_2 CAN_RDH0R_DATA6 IS_SMARTCARD_INSTANCE CAN_F13R2_FB1_Msk GPIO_CRH_MODE13 CAN_F12R1_FB20 USB_EP1R_EP_TYPE_0 CAN_F11R2_FB25_Msk EXTI_PR_PR13_Pos AFIO_EXTICR4_EXTI14 SDIO_CLKCR_WIDBUS GPIO_IDR_IDR1 FLASH_DATA1_DATA1 CAN_F1R1_FB4_Msk GPIO_CRH_CNF9 CAN_F7R2_FB30_Pos TIM_CCMR2_IC3F_Msk CAN_F12R2_FB2_Pos CAN_F1R2_FB16_Pos USART_CR2_LBDL CAN_MCR_INRQ_Pos
+syn keyword CTagsDefinedName TIM_SR_UIF_Pos CAN_F0R1_FB30_Msk CAN_IER_FMPIE1_Pos CAN_FMR_FINIT_Pos CAN_F1R1_FB28 CAN_F10R1_FB28_Pos RCC_APB1ENR_I2C2EN BKP_DR6_D CAN_F12R2_FB28 CAN_F6R1_FB6 SDIO_DCTRL_DBLOCKSIZE_Pos SDIO_MASK_TXFIFOFIE_Pos USB_EP_CTR_TX_Msk CAN_FS1R_FSC4_Msk USB_EP1R_EA_Pos TIM_CCER_CC2E SDIO_STA_DCRCFAIL_Msk USB_COUNT7_TX_1_COUNT7_TX_1 CAN_F0R2_FB17 CAN_F10R2_FB1 __STM32F1_CMSIS_VERSION CAN_F8R2_FB3 TIM_SR_CC1IF_Msk AFIO_EXTICR3_EXTI8_PC AFIO_MAPR_SWJ_CFG_DISABLE_Pos
+syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI0_PF_Msk FLASH_WRPR_WRP_Pos RCC_CIR_LSIRDYC_Pos CRC_CR_RESET_Pos CAN_RDL0R_DATA2 ADC_SQR3_SQ2_Msk CAN_BTR_SJW_Pos CAN_TSR_ALST2 EXTI_RTSR_TR11 RTC_CRL_RSF CAN_F3R1_FB0_Pos CAN_F7R1_FB9_Msk CAN_F9R1_FB16 EXTI_FTSR_FT16 DMA_IFCR_CGIF2 GPIO_ODR_ODR14_Msk SDIO_ICR_DATAENDC_Msk CAN_F5R1_FB22_Pos DMA_CCR_MINC_Msk SDIO_CMD_NIEN_Pos CAN_F7R1_FB7_Msk ADC_SMPR1_SMP12_Msk TIM_BDTR_AOE_Msk CAN_F11R1_FB25_Msk CAN_F11R2_FB9_Pos CAN_TDT2R_TIME_Msk CAN_F10R1_FB5_Msk
+syn keyword CTagsDefinedName CAN_TDT2R_TGT_Pos CAN_F0R1_FB23_Msk PWR_CR_CWUF_Pos SPI_CR2_SSOE BKP_RTCCR_CAL_Pos CAN_ESR_REC_Msk CAN_F12R2_FB9_Msk SDIO_FIFOCNT_FIFOCOUNT_Pos AFIO_EVCR_PIN_PX1_Pos RCC_CIR_PLLRDYF_Msk CAN_F0R2_FB31_Pos CAN_F11R1_FB25 SDIO_STA_CTIMEOUT_Pos CAN_TDL0R_DATA1_Msk AFIO_MAPR_TIM2_REMAP_NOREMAP CAN_F1R1_FB26 CAN_F12R1_FB24 FLASH_CR_OPTER DMA_CNDTR_NDT DBGMCU_IDCODE_DEV_ID_Msk SPI_SR_CRCERR CAN_BTR_TS1_0 CAN_F7R2_FB9_Pos CAN_F2R1_FB9_Pos GPIO_CRL_CNF2_Msk TIM_CR2_OIS1_Msk WWDG_CFR_W
+syn keyword CTagsDefinedName CAN_TSR_RQCP1 TIM_CCMR2_IC3F DMA_IFCR_CGIF1_Pos IS_CAN_ALL_INSTANCE TIM_CR1_CMS_0 CAN_F9R2_FB8 PWR_CSR_EWUP_Msk IS_TIM_CCX_INSTANCE CAN_F1R1_FB0 CAN_F3R1_FB10 CAN_F9R1_FB20_Pos CAN_F8R1_FB19 IS_UART_MULTIPROCESSOR_INSTANCE ADC_JOFR1_JOFFSET1 CAN_F6R2_FB0_Pos USB_COUNT4_RX_0_NUM_BLOCK_0_4 AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos SDIO_DCTRL_DBLOCKSIZE_1 USART_CR1_PS_Pos ADC_SMPR2_SMP4_Pos DMA_IFCR_CGIF5_Pos CAN_TI2R_RTR_Msk USB_EP6R_DTOG_RX CAN_F1R2_FB24 WWDG_CFR_W0 AFIO
+syn keyword CTagsDefinedName USB_ISTR_WKUP_Pos RCC_CR_HSION USB_COUNT4_RX_NUM_BLOCK_Msk USB_EP0R_DTOG_RX_Msk CAN_TSR_ALST1_Pos PWR_CR_PLS_LEV5 CAN_F7R1_FB20_Msk GPIO_BSRR_BS9 BKP_RTCCR_CCO_Pos EXTI_FTSR_FT2 CAN_F8R2_FB2 CAN_F6R1_FB11_Msk AFIO_MAPR_TIM3_REMAP_1 DMA_IFCR_CHTIF6 CAN_F3R1_FB29_Pos SPI_TXCRCR_TXCRC_Msk ADC_CR2_SWSTART_Pos FLASH_ACR_HLFCYA_Msk GPIO_BSRR_BR4_Pos RCC_CFGR_PPRE1 AFIO_EXTICR3_EXTI10_PG_Msk CAN_FM1R_FBM6_Msk CAN_F4R2_FB7_Pos GPIO_LCKR_LCKK AFIO_EXTICR2_EXTI6_PC_Pos
+syn keyword CTagsDefinedName FLASH_ACR_PRFTBE_Pos CAN_F11R2_FB28 USB_EP0R_STAT_TX_Pos EXTI_PR_PR0_Pos GPIO_ODR_ODR9_Msk USB_EP6R_CTR_RX_Msk CAN_F2R2_FB24_Pos CAN_F12R1_FB12 CAN_F2R1_FB4 SPI_CR1_CRCNEXT_Msk RCC_CFGR_PPRE2_DIV2 RCC_CFGR_SWS CAN_F7R2_FB22 CAN_F10R2_FB24_Pos EXTI_PR_PR12 FLASH_OBR_DATA0_Pos CAN_F7R2_FB12_Msk USART_CR2_CPOL_Pos CAN_F13R2_FB16_Msk CAN_F9R2_FB21 RCC_CFGR_PLLMULL_2 RCC_APB1RSTR_USBRST CAN_IER_FMPIE0_Pos CAN_F10R1_FB23_Msk USB_COUNT6_RX_NUM_BLOCK CAN_IER_FFIE1_Pos EXTI_IMR_MR1_Msk
+syn keyword CTagsDefinedName TIM_PSC_PSC_Msk RCC_BDCR_RTCSEL_LSE USB_EP6R_STAT_TX_0 GPIOE_BASE CAN_F7R2_FB27_Pos EXTI_EMR_MR1_Pos USB_CNTR_PMAOVRM_Msk USB_COUNT7_RX_1_NUM_BLOCK_1_0 ADC_SQR1_SQ13_3 USB_EP3R_EP_KIND CAN_F0R1_FB30_Pos GPIO_BRR_BR3 USART_CR2_LINEN CAN_F10R1_FB16 AFIO_MAPR_CAN_REMAP_REMAP3_Msk CAN_F9R1_FB4_Msk CAN_F7R1_FB11_Msk DMA_IFCR_CGIF4_Msk CAN_F11R1_FB8_Msk TIM_CCMR1_OC2FE TIM_CR1_CKD USB_ADDR6_TX_ADDR6_TX SDIO_ICR_DBCKENDC AFIO_MAPR_PD01_REMAP_Pos USB_COUNT1_RX_COUNT1_RX_Msk
+syn keyword CTagsDefinedName USB_EPRX_DTOGMASK GPIO_BSRR_BS15_Msk TIM_BDTR_OSSI_Msk GPIO_CRH_CNF11_Pos AFIO_MAPR_TIM4_REMAP CAN_F1R1_FB17 ADC_SMPR2_SMP7_Pos CAN_F11R1_FB18_Pos CAN_F11R2_FB20_Pos CAN_F6R1_FB17_Pos CAN_FS1R_FSC2_Msk ADC_SR_JEOS_Msk CAN_F11R2_FB15 AFIO_EXTICR2_EXTI4_PG_Pos DMA_IFCR_CTCIF3_Pos CAN_F5R1_FB4 CAN_F3R1_FB2 CAN_F8R2_FB10 CAN_F11R2_FB18_Pos CAN_FM1R_FBM_Pos USART_CR3_SCEN_Msk USB_CNTR_SOFM_Msk CAN_F5R1_FB14_Msk SDIO_CMD_WAITINT ADC_CR1_DISCNUM_Pos USB_COUNT3_TX_COUNT3_TX
+syn keyword CTagsDefinedName CAN_RDH0R_DATA4_Msk CAN_F11R2_FB10_Pos SPI3_IRQ_PRIORITY EXTI_EMR_MR10_Msk CAN_F2R2_FB25 CAN_F8R1_FB15 USART_CR3_CTSIE_Pos DMA_ISR_TEIF6_Msk CAN_F5R2_FB4_Pos SPI_CR2_TXEIE CAN_F3R1_FB19_Msk CAN_F1R1_FB11 CAN_F6R1_FB27_Pos CAN_F2R1_FB10_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_3 CAN_F9R2_FB17_Msk DBGMCU_CR_DBG_WWDG_STOP SDIO_DCTRL_DTDIR CAN_F10R1_FB21 TIM_CCMR1_OC1PE AFIO_EXTICR4_EXTI12_PC_Pos EXTI_RTSR_TR5_Pos CAN_F11R2_FB16_Pos TIM_DIER_BIE_Pos USB_EP5R_DTOG_RX_Pos RCC_APB1ENR_PWREN
+syn keyword CTagsDefinedName DMA_ISR_TCIF1_Msk RCC_CIR_CSSF I2C_SR1_TIMEOUT TIM1_BRK_TIM15_IRQn USB_COUNT5_RX_COUNT5_RX_Pos FLASH_ACR_LATENCY_Msk ADC_SQR3_SQ5_1 ADC_CR1_AWDSGL_Pos CAN_F13R2_FB0_Pos CAN_F2R2_FB18_Pos CAN_F12R2_FB25_Pos SDIO_MASK_RXFIFOHFIE_Msk CAN_IER_SLKIE_Msk EXTI_FTSR_FT17 RCC_CFGR_HPRE_DIV2 TIM_CCR2_CCR2_Pos USART_CR3_SCEN ADC_CR1_EOSIE ADC_SQR3_SQ2_3 USART_CR3_DMAT CAN_F2R1_FB28 DBGMCU_IDCODE_REV_ID_3 USB_COUNT2_RX_0_BLSIZE_0 AFIO_EXTICR3_EXTI10_PG CAN_F3R2_FB10 CAN_F6R1_FB28_Msk
+syn keyword CTagsDefinedName EXTI_FTSR_TR3_Msk I2C_SR1_BTF CAN_F12R1_FB27 USB_EP1R_DTOG_TX_Msk ADC_SQR3_SQ4_4 DMA_IFCR_CTEIF1_Msk AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_EXTICR2_EXTI7_Msk CAN_FA1R_FACT DMA_CNDTR_NDT_Pos CAN_F6R2_FB27_Msk CAN_F1R2_FB6_Pos CAN_F6R2_FB6 EXTI_SWIER_SWIER10_Pos CAN_F1R2_FB22 CAN_F5R2_FB12_Msk GPIO_CRL_CNF0_1 CAN_FFA1R_FFA11_Pos FLASH_RDP_RDP CAN_F10R1_FB15_Pos CAN_F11R1_FB7_Msk USB_FNR_LCK_Pos EXTI_IMR_MR12_Pos CAN_FFA1R_FFA5 CAN_F11R2_FB23_Pos CAN_F8R1_FB20_Pos WWDG_CFR_EWI_Pos
+syn keyword CTagsDefinedName CAN_F0R1_FB10_Pos CAN_RDH1R_DATA6 SDIO_DCOUNT_DATACOUNT_Msk CAN_F4R1_FB22 USB_EP7R_STAT_TX_1 CAN_TDL0R_DATA2_Pos AFIO_EXTICR2_EXTI4_PE CAN_F4R1_FB4_Pos AFIO_EXTICR1_EXTI1_PD_Msk EXTI_SWIER_SWIER9_Pos __SYS_HANDLERS_H_ CAN_F7R2_FB0_Msk CAN_F12R2_FB26_Msk AFIO_MAPR_USART2_REMAP RCC_APB2ENR_IOPAEN_Msk CAN_TSR_RQCP2_Pos RCC_BDCR_LSERDY CAN_F2R1_FB22 EXTI_EMR_EM15 CAN_F7R2_FB27_Msk EXTI_RTSR_TR15 CAN_FM1R_FBM0 CAN_F0R1_FB2 ADC_JSQR_JSQ2_4 EXTI_FTSR_TR14_Msk
+syn keyword CTagsDefinedName USB_COUNT2_RX_1_NUM_BLOCK_1_2 CAN_RI0R_EXID_Pos CAN_F4R1_FB16_Pos AFIO_EVCR_PIN_PX13_Msk CAN_F0R1_FB28 CAN_F7R1_FB26 PIN_OPT_OUTPUT_SPEED_FAST USB_ADDR1_RX_ADDR1_RX_Pos TIM_CR1_UDIS SPI_CR2_TXEIE_Msk USB_EPTX_STAT CAN_F2R2_FB8 EXTI_SWIER_SWI2 CAN_RDH0R_DATA5 CAN_F2R2_FB7_Msk CAN_F5R1_FB7_Msk EXTI_FTSR_TR7 CAN_F8R2_FB7 TIM_CCER_CC1NP TIM_BDTR_DTG IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE CAN_TI1R_TXRQ USB_DADDR_ADD6_Msk I2C_OAR2_ENDUAL USB_EP6R_DTOG_TX CAN_IER_LECIE_Msk
+syn keyword CTagsDefinedName ADC_SMPR2_SMP5_Msk ADC_SQR1_SQ15_Pos USB_EP_KIND CAN_F7R1_FB23_Msk RCC_APB2ENR_IOPDEN_Msk USB_COUNT1_RX_NUM_BLOCK_Pos RTC_CRH_SECIE CAN_IER_TMEIE CAN_F1R1_FB28_Pos EXTI_EMR_EM0 CAN_FFA1R_FFA3 RCC_CFGR_PLLMULL15 CAN_RDH0R_DATA5_Msk CAN_F10R1_FB8 CAN_F1R1_FB27 CAN_F3R2_FB19_Pos CAN_F4R2_FB29 FLASH_WRP0_WRP0_Pos ADC_JSQR_JL_1 RCC_CFGR_PLLMULL16_Msk CAN_F9R1_FB17_Pos CAN_TDL0R_DATA0_Pos CAN_RF0R_FOVR0_Pos EXTI_IMR_IM4 ADC_SMPR2_SMP8_2 ADC_SQR2_SQ12_1 SDIO_STA_CMDREND_Pos
+syn keyword CTagsDefinedName CAN_F8R1_FB5_Msk RCC_BDCR_RTCEN_Pos CAN_F4R1_FB1_Pos RCC_BASE GPIO_BSRR_BS2_Msk I2C_SR1_ARLO_Pos USB_COUNT1_RX_COUNT1_RX FLASH_RDP_nRDP_Pos CAN_MSR_INAK_Msk USART_BRR_DIV_Mantissa CAN_F11R1_FB21 AFIO_EXTICR4_EXTI14_PD_Pos RCC_APB1RSTR_TIM4RST CAN_F8R2_FB2_Msk IS_TIM_DMA_CC_INSTANCE ADC_CR1_JAWDEN_Pos CAN_RF1R_FOVR1 CAN_TDH1R_DATA4_Msk CAN_FA1R_FACT5_Msk GPIOB_BASE BKP_DR5_D RCC_CIR_HSIRDYIE CAN_F0R1_FB0 AFIO_EXTICR1_EXTI1_PG_Pos USB_COUNT2_TX_COUNT2_TX_Pos CAN_F13R2_FB21_Msk
+syn keyword CTagsDefinedName IS_TIM_CLOCKSOURCE_ITRX_INSTANCE AFIO_EXTICR3_EXTI9_PB CAN_F1R1_FB1 SDIO_CMD_WAITRESP_1 TIM_CCMR2_OC4CE_Pos ADC_SMPR1_SMP15_2 CAN_F5R2_FB25_Pos EXTI_EMR_MR2_Msk I2C_SR1_STOPF_Msk CAN_F13R1_FB11_Msk CAN_F3R1_FB4_Msk CAN_F12R2_FB4 CAN_F4R2_FB30_Msk CAN_F11R1_FB29_Pos AFIO_EXTICR3_EXTI9 CAN_RDH0R_DATA7_Pos CAN_F4R1_FB15 SDIO_MASK_RXDAVLIE USB_EP0R_STAT_TX_0 CAN_F5R2_FB10 EXTI_SWIER_SWIER5 AFIO_EXTICR2_EXTI4_PB_Pos CAN_F0R2_FB18_Msk TIM_SMCR_TS RCC_BDCR_LSEON DMA_CCR_EN_Msk
+syn keyword CTagsDefinedName USB_COUNT6_RX_0_NUM_BLOCK_0_0 TIM_SR_COMIF GPIOB RCC_CFGR_MCO_PLLCLK_DIV2 TIM_CCER_CC2P_Msk ADC_SQR2_SQ9 CAN_TDH0R_DATA5_Pos EXTI_EMR_MR18_Pos CAN_F9R1_FB9 SDIO_CLKCR_HWFC_EN_Msk USART_SR_NE AFIO_EXTICR2_EXTI7_PG_Pos CAN_F8R2_FB3_Msk RCC_CFGR_HPRE_DIV_2 CAN_F12R2_FB22 CAN_F8R1_FB5 CAN_FM1R_FBM13_Msk RCC_CFGR_PPRE_DIV_8 DMA_ISR_HTIF1 CAN_F4R1_FB25 RCC_APB2ENR_ADC1EN_Msk SDIO_DCTRL_DTEN_Pos TIM_CCMR1_OC1M_1 TIM_CR1_UDIS_Msk FLASH_OBR_DATA0_Msk TIM_CR2_TI1S_Pos CAN_F0R1_FB14
+syn keyword CTagsDefinedName PWR_BASE TIM_CCMR2_OC3FE_Msk CAN_F2R1_FB13_Pos SDIO_STA_DATAEND_Pos CAN_F8R1_FB12 EXTI_IMR_MR4 GPIO_BRR_BR7_Msk SDIO_ICR_SDIOITC PWR_CR_PLS_LEV7 TIM_CCMR1_OC1M RCC_CIR_HSIRDYC_Msk USB_EP3R_DTOG_RX_Msk CAN_F4R2_FB16 CAN_F5R2_FB5_Msk EXTI_SWIER_SWIER6_Pos TIM_CR1_CEN_Msk CAN_RF1R_RFOM1_Msk CAN_F2R2_FB15_Msk SDIO_MASK_TXACTIE_Pos USB_ISTR_CTR_Msk DMA_CCR_PINC_Msk CAN_F0R1_FB4_Pos USART_CR3_CTSIE_Msk CAN_F6R2_FB19_Msk DMA_IFCR_CTCIF5_Msk TIM_PSC_PSC CAN_F10R2_FB2_Msk CAN_F4R1_FB14
+syn keyword CTagsDefinedName CAN_F10R1_FB18_Msk CAN_F6R1_FB29_Pos CAN_FA1R_FACT9_Msk CAN_F3R1_FB8_Msk CAN_F1R2_FB10_Msk USB_COUNT2_RX_COUNT2_RX_Pos CAN_F2R2_FB23_Pos USB_COUNT7_RX_NUM_BLOCK_2 TIM_DIER_COMDE CAN_F7R2_FB30_Msk ADC_SMPR2_SMP4_0 PWR_CR_PLS_LEV4 SDIO_ICR_STBITERRC EXTI_EMR_MR4 DBGMCU_CR_DBG_STANDBY_Msk USART_CR3_RTSE_Msk PIN_3 USB_EP3R_EA_Msk AFIO_EXTICR1_EXTI3_PC CAN_F13R1_FB1_Pos CAN_F3R1_FB25 RTC_CRH_ALRIE GPIO_BSRR_BR13 CAN_F2R1_FB2_Pos EXTI_FTSR_TR0_Msk CAN_MCR_SLEEP TIM_CR1_DIR
+syn keyword CTagsDefinedName USB_EP0R_SETUP GPIO_BSRR_BS3 CAN_F2R1_FB14_Msk CAN_F7R1_FB16_Pos GPIO_BSRR_BR10_Msk CAN_F3R1_FB5_Msk AFIO_EXTICR4_EXTI12_PG_Pos TIM_SR_CC1OF CAN_F10R1_FB31 PWR_CR_PLS_2V7 TIM11_IRQn FLASH_WRP2_nWRP2 USB_COUNT2_RX_0_NUM_BLOCK_0_4 CAN_F3R2_FB9 EXTI_EMR_MR0 USB_COUNT6_RX_NUM_BLOCK_1 BKP_DR6_D_Msk CAN_F6R1_FB22_Msk USB_COUNT5_RX_1_BLSIZE_1 ADC_SQR1_SQ14_2 TIM_DCR_DBA_Msk DMA_ISR_HTIF4 AFIO_EXTICR2_EXTI7_Pos CAN_F0R1_FB9 SDIO_MASK_RXFIFOFIE TIM_CR2_OIS1 EXTI_PR_PR4 RCC_CIR_PLLRDYC
+syn keyword CTagsDefinedName CAN_F12R1_FB17_Msk CAN_F2R2_FB3 CAN_F2R1_FB21_Msk CAN_F2R1_FB4_Msk USB_EP7R_CTR_TX FLASH_OPTKEY2 ADC_SMPR2_SMP8 EXTI_SWIER_SWIER13_Msk CAN_F6R2_FB7 CAN_F3R1_FB31_Pos SDIO_ICR_CTIMEOUTC EXTI_EMR_EM7 CAN_F5R2_FB11_Msk GPIO_BRR_BR2_Msk CAN_F0R1_FB3_Pos CAN_F0R1_FB28_Msk CAN_F4R1_FB28_Msk CAN_RDL0R_DATA0 CAN_F3R1_FB17 ADC_SQR2_SQ8_1 USB_COUNT4_RX_1_NUM_BLOCK_1_1 I2C_SR2_GENCALL_Msk SDIO_CMD_CEATACMD CAN_F5R1_FB9_Msk USB_EP4R_STAT_RX AFIO_EXTICR1_EXTI0_PB_Pos PIN_13
+syn keyword CTagsDefinedName CAN_F4R1_FB13_Pos CAN_F9R2_FB24 TIM_CCER_CC4E_Pos CAN_F2R1_FB7_Pos CAN_FM1R_FBM8 CAN_F7R2_FB19_Pos GPIO_IDR_IDR6 CAN_F3R1_FB6 CAN_F9R2_FB9_Msk ADC_CR2_EXTSEL_0 RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL12 CAN_FFA1R_FFA1_Msk CAN_F11R2_FB4 USART_CR3_DMAR CAN_TI2R_STID_Msk USART_CR1_RXNEIE_Msk USB_EP4R_EA_Pos AFIO_MAPR_CAN_REMAP_1 TIM_SR_BIF TIM_SR_CC2IF_Pos USB_ADDR2_RX_ADDR2_RX_Msk USB_EP0R_SETUP_Pos TIM_CR2_TI1S_Msk RCC_APB2RSTR_IOPERST_Pos CAN_F4R1_FB21_Msk EXTI_EMR_MR11
+syn keyword CTagsDefinedName CAN_FFA1R_FFA8 CAN_F5R1_FB8_Pos CAN_F3R2_FB18_Msk ADC_CR2_CAL_Pos USB_COUNT4_RX_0_COUNT4_RX_0 I2C_CR1_NOSTRETCH_Pos I2C_SR1_BERR_Pos CAN_F12R2_FB21_Pos CAN_F9R1_FB27_Msk I2C_CR1_SMBTYPE_Pos CAN_RI1R_RTR ADC_CR1_DUALMOD AFIO_EXTICR1_EXTI1 AFIO_EXTICR4_EXTI13_PF_Msk TIM_CCMR1_IC2PSC_Pos CAN_F4R1_FB14_Msk IS_TIM_CCXN_INSTANCE CAN_F0R1_FB24 CAN_F12R1_FB24_Pos CAN_F3R1_FB1_Pos SDIO_MASK_RXFIFOEIE GPIO_CRL_MODE7_Msk RCC_CFGR_HPRE_DIV16 TIM_EGR_TG_Msk CAN_F6R2_FB14 RCC_CSR_PORRSTF_Msk
+syn keyword CTagsDefinedName CAN_FFA1R_FFA10 ADC_SMPR2_SMP7 RCC_CFGR_PPRE2_0 ADC_HTR_HT ADC_SQR2_SQ8_Msk GPIO_ODR_ODR10_Msk CAN_F2R2_FB17 CAN_F3R2_FB6 CAN_F9R2_FB1 TIM_CCR3_CCR3 BKP_DR6_D_Pos CAN_FS1R_FSC12_Pos ADC_SQR3_SQ4_Pos CAN_F2R2_FB15 RCC_CFGR_HPRE_0 TIM_CR2_OIS2_Msk CAN_RDL0R_DATA3 RCC AFIO_EXTICR1_EXTI1_PB_Pos CAN_F12R2_FB5_Pos GPIO_BSRR_BR10 CAN_F8R1_FB9_Pos CAN_FS1R_FSC6_Msk USART_CR1_PEIE AFIO_EXTICR3_EXTI11_PG I2C_CR1_STOP _IO_H_ AFIO_EVCR_PIN_PX9_Msk TIM_BDTR_LOCK_1 CAN_F3R2_FB15_Msk
+syn keyword CTagsDefinedName ADC_SQR3_SQ6_Msk CAN_F7R1_FB5_Msk GPIO_BSRR_BS5 SDIO_STA_TXACT_Msk AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk CAN_F1R1_FB26_Msk AFIO_EXTICR3_EXTI11_PE_Pos CAN_TDH0R_DATA5_Msk READ_REG AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR1_EXTI3_PE_Pos TIM_BDTR_OSSR_Pos WWDG_CFR_W6 GPIO_BSRR_BS2 GPIO_CRL_MODE6_1 USART_CR1_WAKE GPIO_BSRR_BR5_Msk I2C1 TIM_CCMR2_OC3M_0 RTC_CRL_ALRF CAN_F10R1_FB0 CAN_F0R2_FB23_Pos CAN_RDT1R_TIME CAN_F12R2_FB30 CAN_F3R1_FB21_Pos USB_ISTR_DIR_Pos AFIO_EXTICR1_EXTI3_PB_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI7_PB_Msk USB_DADDR_ADD0_Pos CAN_F7R2_FB26_Msk DBGMCU_CR_DBG_SLEEP_Msk CAN_F5R1_FB29_Pos CAN_F6R2_FB0 USB_COUNT6_RX_BLSIZE_Pos SDIO_ICR_TXUNDERRC_Msk CAN_F9R1_FB10_Msk CAN_F4R2_FB12_Pos EXTI_PR_PIF6 USART_SR_ORE RCC_CFGR_PLLMULL_Pos CAN_F12R2_FB29_Msk I2C1_IRQ_PRIORITY CAN_BTR_SILM CAN_F5R2_FB5_Pos CAN_F11R2_FB15_Msk USB_COUNT2_RX_NUM_BLOCK_4 AFIO_EXTICR3_EXTI10_PG_Pos TIM_DIER_CC1DE_Pos PWR_CR_PLS_2V4 AFIO_EVCR_PIN_PX7 RCC_APB1ENR_WWDGEN_Msk
+syn keyword CTagsDefinedName SDIO_CLKCR_NEGEDGE_Pos AFIO_EXTICR2_EXTI7_PE_Msk CAN_F9R2_FB25_Msk CAN_F2R1_FB24_Pos SPI_CR2_TXDMAEN_Msk TIM_BDTR_OSSR_Msk CAN_F13R1_FB3_Msk CAN_F6R2_FB31 USB_CNTR_WKUPM_Pos CAN_MSR_SLAKI_Pos AFIO_EXTICR4_EXTI12_PG CAN_F8R1_FB18_Msk CAN_TI2R_EXID_Msk CAN_MSR_ERRI_Pos CAN_F2R1_FB6_Pos CAN_F4R1_FB1_Msk CAN_F9R1_FB0_Pos AFIO_EXTICR2_EXTI7_PF_Msk USB_EP5R_EP_TYPE_Pos CAN_F6R2_FB4_Msk TIM1_BASE CAN_FFA1R_FFA1 AFIO_MAPR_TIM4_REMAP_Msk IS_ADC_COMMON_INSTANCE CAN_F11R1_FB20_Msk
+syn keyword CTagsDefinedName CAN_F0R1_FB11_Msk PWR_CSR_SBF_Msk USB_COUNT1_RX_0_NUM_BLOCK_0_0 FLASH_WRP0_WRP0 TIM_CCER_CC3NP_Msk USB_EP2R_EA_Msk CAN_F8R2_FB27 FLASH_SR_BSY CAN_F3R1_FB5_Pos ADC_SMPR2_SMP6_2 RCC_APB2RSTR_AFIORST_Pos TIM_DIER_CC2IE AFIO_EXTICR2_EXTI4_PF_Msk CAN_F1R2_FB27_Msk WWDG_CR_T1 CAN_F3R2_FB23_Pos ADC_CR1_DUALMOD_1 USB_DADDR_ADD1_Msk CAN_FFA1R_FFA0_Pos CAN_F4R1_FB12_Msk ADC_SQR3_SQ3_Msk CAN_F7R1_FB18_Msk CAN_F3R2_FB8_Msk SDIO_ICR_SDIOITC_Msk CAN_F1R2_FB5 RTC_PRLH_PRL CAN_F10R1_FB12_Msk
+syn keyword CTagsDefinedName ADC_SQR2_SQ8_0 CAN_F4R1_FB9 USB_COUNT3_TX_COUNT3_TX_Pos CAN_F7R2_FB8_Msk DMA_ISR_HTIF2_Msk AFIO_MAPR_TIM2_REMAP_Msk ADC_LTR_LT_Msk CAN_F2R2_FB5_Pos RCC_APB2RSTR_IOPDRST_Msk AFIO_MAPR_USART3_REMAP CAN_F7R1_FB15 SDIO_STA_DATAEND_Msk SPI_CR1_MSTR_Pos USB_EP5R_EA_Pos GPIO_CRH_CNF TIM_CCMR2_CC4S_0 CAN_F2R2_FB27_Msk USB_EP0R_DTOG_TX TIM_EGR_CC3G_Pos CAN_F13R1_FB15 TIM_CCER_CC1NP_Msk USB_COUNT2_RX_NUM_BLOCK_2 EXTI_EMR_MR18 CAN_F3R2_FB5 CAN_F3R2_FB20_Msk EXTI_IMR_MR15
+syn keyword CTagsDefinedName RCC_APB1ENR_TIM4EN_Msk AFIO_EXTICR3_EXTI11_PB_Pos PWR_CSR_PVDO CAN_F0R1_FB28_Pos CAN_F12R1_FB14 CAN_FFA1R_FFA12 USB_EPRX_STAT_Msk TIM_DCR_DBL_0 USB_FNR_LCK AFIO_EVCR_PIN_PX2_Pos CAN_F0R2_FB30 RCC_APB1ENR_TIM4EN CAN_F10R1_FB19 CAN_F2R1_FB23_Msk RCC_APB2RSTR_ADC1RST CAN_F5R1_FB24_Msk USB_COUNT6_RX_BLSIZE_Msk CAN_F1R2_FB4_Msk EXTI_SWIER_SWIER7_Msk CAN_F5R2_FB8_Msk TIM_CCMR2_OC3FE_Pos AFIO_EXTICR3_EXTI11_PC_Pos CAN_F7R2_FB0 ADC_CR2_CONT FLASH_CR_LOCK_Pos TIM_DCR_DBA_1
+syn keyword CTagsDefinedName DMA_ISR_GIF1_Msk CAN_F11R1_FB1_Pos CAN_F12R2_FB17_Pos I2C_OAR1_ADD1_Msk AFIO_EVCR_PIN_PX0 CAN_FA1R_FACT8 PIN_OPT_AF10 CAN_F13R2_FB10_Msk FLASH_SR_BSY_Msk CAN_F5R2_FB6 ADC_JSQR_JSQ3_2 CAN_F5R2_FB4_Msk ADC_SMPR2_SMP2_2 EXTI_FTSR_TR2 USB_COUNT1_TX_1_COUNT1_TX_1 TIM_DIER_UIE_Pos CAN_F8R1_FB20 CAN_MCR_TXFP_Msk DMA_ISR_HTIF5_Msk CAN_F1R1_FB25_Pos CAN_TDH0R_DATA6 RCC_APB1RSTR_TIM4RST_Pos CAN_F6R2_FB9 ADC_CR2_ALIGN_Pos CAN_TDL0R_DATA2 FLASH_ACR_PRFTBS_Pos RCC_CFGR_ADCPRE_Msk
+syn keyword CTagsDefinedName __STM32F1_CMSIS_VERSION_SUB2 EXTI_FTSR_TR9_Msk EXTI_FTSR_TR9 CAN_TSR_ALST0 TIM_DCR_DBA_4 CAN_F1R1_FB10_Pos AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos AFIO_EXTICR2_EXTI4_PE_Pos CAN_F4R2_FB19_Msk I2C_SR2_SMBHOST_Msk RCC_APB2ENR_SPI1EN_Msk CAN_F0R1_FB6_Pos USB_EP3R_STAT_TX AFIO_EXTICR1_EXTI2 USB_EP4R_STAT_RX_Pos EXTI_RTSR_RT7 TIM_BDTR_BKP_Msk I2C_CR2_ITBUFEN CAN_F5R2_FB17_Msk CAN_F6R1_FB11 EXTI_IMR_IM18 GPIO_CRH_MODE9_1 CAN_F10R1_FB24_Pos RCC_APB2RSTR_USART1RST_Msk DMA_CCR_MINC_Pos
+syn keyword CTagsDefinedName CAN_F9R1_FB21_Msk CAN_F1R2_FB26 SPI_CR1_CPOL_Pos WWDG_CFR_W1 ADC_SMPR1_SMP12_0 CAN_F13R1_FB23 RCC_CR_HSICAL_Msk AFIO_EXTICR1_EXTI2_PC RCC_CFGR_HPRE_DIV64 CAN_F12R1_FB6_Msk CAN_F12R2_FB3_Msk I2C_OAR1_ADD8_Msk I2C_CCR_FS_Msk ADC_SMPR2_SMP3_Msk CAN_F6R1_FB26_Pos CAN_TDT0R_TGT FLASH_DATA0_DATA0 SDIO_FIFO_FIFODATA_Msk SPI4_IRQ_PRIORITY USB_EP6R_DTOG_TX_Pos CAN_F2R2_FB15_Pos ADC_SQR2_SQ12_2 AFIO_EXTICR2_EXTI6_PA EXTI_EMR_MR1 TIM_DIER_CC3DE_Pos GPIO_CRL_MODE1_1 CAN_F4R2_FB8
+syn keyword CTagsDefinedName SDIO_STA_CEATAEND ADC_SQR1_L_0 GPIO_CRL_MODE1_Msk EXTI_IMR_MR6_Pos CAN_MCR_DBF CAN_F3R1_FB25_Msk EXTI_RTSR_TR16 USB_COUNT5_RX_NUM_BLOCK_Msk DMA_IFCR_CTEIF1_Pos SPI_CR1_CPOL CAN_F9R2_FB9_Pos EXTI15_10_IRQ_PRIORITY CAN_F12R2_FB25_Msk BKP_DR7_D CAN_F11R2_FB5_Pos AFIO_EXTICR3_EXTI10_PB_Pos PWR_CR_PLS_0 CAN_F7R1_FB23_Pos CAN_FA1R_FACT10_Msk CAN_F8R2_FB1_Msk EXTI_FTSR_TR13_Pos CAN_F6R2_FB2_Msk TIM_CCMR2_IC4F_1 CAN_F8R1_FB31_Pos TIM_CR1_ARPE USB_EP0R_EA_Msk USB_COUNT3_RX_NUM_BLOCK_4
+syn keyword CTagsDefinedName RCC_AHBENR_SRAMEN_Msk USB_COUNT2_RX_COUNT2_RX EXTI_FTSR_TR11_Pos GPIO_LCKR_LCK14_Msk CAN_F8R2_FB14_Msk AFIO_EXTICR2_EXTI7_PD_Msk FLASH_SR_WRPRTERR_Msk GPIO_BSRR_BR9_Msk CAN_F8R1_FB20_Msk TIM1_TRG_COM_TIM17_IRQHandler CAN_F5R2_FB16_Msk CAN_F12R2_FB15 CAN_F8R1_FB28 CAN_TDH2R_DATA6 EXTI_FTSR_TR10_Pos SDIO_MASK_RXACTIE_Pos DMA_CNDTR_NDT_Msk EXTI_RTSR_TR1 USB_FNR_LSOF_Pos CAN_F13R1_FB6_Pos EXTI_PR_PR2_Msk RCC_CFGR_PPRE2_Pos AFIO_EVCR_PIN_PX15_Pos CAN_FM1R_FBM3_Msk CAN_F2R2_FB23_Msk
+syn keyword CTagsDefinedName FLASH_OBR_OPTERR_Pos GPIO_CRL_CNF4_Msk I2C_OAR2_ENDUAL_Pos USB_EP7R_EP_KIND GPIO_CRH_CNF8_0 GPIO_BSRR_BR9_Pos AFIO_EXTICR3_EXTI11_PF GPIO_BSRR_BR0 CAN_F3R2_FB28_Msk EXTI_FTSR_TR1_Msk GPIO_CRL_MODE2_1 SPI_CRCPR_CRCPOLY_Msk EXTI_IMR_MR11_Msk CAN_F11R2_FB25 TIM_CCMR2_IC4F_3 CAN_ESR_LEC_Pos CAN_F2R1_FB18 USB_COUNT5_RX_1_NUM_BLOCK_1_4 I2C_OAR1_ADD9_Msk CAN_F2R1_FB1 CAN_F3R1_FB9_Msk ADC_CR2_JEXTSEL_0 GPIO_CRH_CNF11_1 TIM_SR_CC3IF_Pos GPIO_BSRR_BR15 USB_EP_T_FIELD_Pos USB_EP6R_STAT_RX
+syn keyword CTagsDefinedName USB_COUNT5_RX_0_NUM_BLOCK_0_1 USART_SR_TC_Pos CAN_F7R1_FB5 RCC_CR_HSERDY_Pos USB_COUNT3_RX_COUNT3_RX_Msk CAN_F10R1_FB0_Pos USB_COUNT0_RX_NUM_BLOCK_2 DMA_IFCR_CTEIF2 CAN_F3R2_FB13_Msk USB_EP5R_EP_TYPE_1 TIM_DIER_UDE_Pos CAN_RF1R_FOVR1_Msk CAN_F1R2_FB22_Msk USB_EP3R USART_CR2_STOP_Msk CAN_F12R1_FB28_Pos CAN_FS1R_FSC3_Pos SDIO_MASK_DTIMEOUTIE_Pos CAN_F10R1_FB22_Msk CAN_F12R2_FB18_Pos DBGMCU_IDCODE_REV_ID_13 CAN1_TX_IRQHandler EXTI_EMR_MR5 CAN_TDT1R_TIME CAN_F11R1_FB17_Pos
+syn keyword CTagsDefinedName EXTI_PR_PR5 EXTI_SWIER_SWIER0 SPI_CR1_CPHA_Msk ADC_CR1_AWDCH_1 CAN_F10R2_FB9 CAN_F9R2_FB1_Pos CAN_F8R1_FB2_Msk CAN_F13R1_FB1 CAN_F5R1_FB3 CAN_MSR_RX_Msk DMA_IFCR_CGIF6_Msk AFIO_EXTICR1_EXTI1_PF_Pos I2C_CR1_ENARP CAN_F1R1_FB20 EXTI_FTSR_TR3_Pos CAN_F0R1_FB22 USB_COUNT1_RX_NUM_BLOCK_4 CAN_F10R2_FB8_Pos CAN_F8R1_FB26_Pos CAN_F11R2_FB4_Pos DMA_CCR_PL_Pos AFIO_EXTICR2_EXTI6_PE CAN_F3R1_FB17_Msk SPI_CR1_LSBFIRST_Pos AFIO_EXTICR2_EXTI5_PE_Msk DMA_IFCR_CTCIF3_Msk CAN_F8R2_FB29_Pos
+syn keyword CTagsDefinedName CAN_F7R2_FB8 CAN_F2R1_FB22_Msk CAN_F11R1_FB12_Pos AFIO_MAPR_TIM3_REMAP_NOREMAP EXTI_RTSR_TR2 USB_EP1R_STAT_TX ADC_SQR2_SQ12 CAN_F1R2_FB2 TIM_CCMR1_OC2M_1 SDIO_DCTRL_DTDIR_Msk BKP_DR4_D_Pos AFIO_MAPR_TIM4_REMAP_Pos ADC1_BASE CAN_F5R2_FB25 RCC_CIR_LSERDYC_Msk RCC_CFGR_HPRE_DIV_64 CAN_FM1R_FBM5 CAN_IER_LECIE CAN_TI0R_IDE_Pos SPI_CR1_RXONLY_Msk CAN_IER_EPVIE_Pos AFIO_EXTICR4_EXTI12_PE_Msk IWDG_KR_KEY_Msk AFIO_EXTICR4_EXTI14_Msk IWDG_SR_RVU_Msk EXTI_EMR_MR8_Pos ADC_SQR3_SQ1_1
+syn keyword CTagsDefinedName ADC_SMPR2_SMP5_2 CAN_MCR_TTCM_Pos CAN_F12R2_FB5 TIM_DIER_CC3IE CAN_FFA1R_FFA CAN_F13R1_FB28_Msk DMA_CCR_EN DMA_IFCR_CTEIF5_Pos EXTI_EMR_EM8 IS_TIM_ADVANCED_INSTANCE RTC_PRLH_PRL_Msk USB_COUNT0_RX_0_COUNT0_RX_0 CAN_F9R1_FB28 ADC_SMPR2_SMP6_0 CAN_F4R1_FB18 CAN_F7R2_FB3_Msk CAN_FS1R_FSC5_Pos EXTI_FTSR_TR12 CAN_F8R2_FB20 DMA_CCR_MSIZE_Pos GPIO_CRL_MODE0_0 USB_COUNT5_RX_0_COUNT5_RX_0 CAN_TSR_TERR1_Pos CAN_F6R1_FB24_Pos PIN_OPT_AF2 CAN_F13R2_FB6 USB_EP5R_STAT_TX_Pos CAN_F5R1_FB14
+syn keyword CTagsDefinedName CAN_F11R1_FB30 USB_COUNT1_RX_0_NUM_BLOCK_0_1 USB_EP5R_DTOG_RX_Msk USB_EP1R_CTR_TX_Pos DMA_IFCR_CGIF7 GPIO_BRR_BR15_Pos USART_CR1_SBK CAN_F9R1_FB13 ADC_SMPR2_SMP1_0 CAN_F0R2_FB5_Msk RCC_APB2ENR_IOPAEN AFIO_EXTICR4_EXTI15_PB EXTI_FTSR_TR9_Pos CAN_F6R2_FB18_Msk CAN_F12R2_FB24 EXTI_IMR_MR17_Pos CAN_F4R2_FB17_Pos PWR_CSR_SBF USB_COUNT1_RX_NUM_BLOCK_Msk CAN_F6R1_FB7_Pos CAN_F12R1_FB4 USB_EP4R_EP_TYPE_Pos ADC_SQR1_SQ15 EXTI_PR_PR10_Pos ADC_LTR_LT_Pos CAN_F7R1_FB19_Msk
+syn keyword CTagsDefinedName RCC_APB1ENR_USBEN ADC_CR2_CAL I2C_SR1_PECERR_Pos GPIO_CRH_MODE10_0 CAN_MCR_DBF_Pos CAN_F5R2_FB26_Msk CAN_F8R2_FB28_Pos RCC_CR_PLLRDY TIM_CCMR2_OC3M_Msk CAN_F12R2_FB14_Msk EXTI_PR_PR14_Pos RCC_APB1ENR_CAN1EN ADC_SQR2_SQ10_3 CAN_F12R2_FB21_Msk GPIO_BSRR_BS6 CAN_F2R1_FB19_Pos SDIO_STA_CEATAEND_Msk USB_EP7R_EP_TYPE_Pos CAN_F9R2_FB20_Msk STM32F103xB WWDG_CFR_WDGTB0 TIM_DIER_BIE AFIO_EXTICR2_EXTI5_PC_Msk CAN_F6R2_FB15 ADC_SQR2_SQ10_1 CAN_TSR_TERR1_Msk RCC_APB1ENR_PWREN_Msk
+syn keyword CTagsDefinedName PWM_CHANNEL_4 CAN_F8R2_FB11_Msk CAN_F8R2_FB23_Msk CAN_RI0R_RTR_Pos I2C_SR2_SMBDEFAULT_Msk GPIO_CRL_MODE0_1 AFIO_EXTICR4_EXTI14_PG_Pos CAN_F11R1_FB26_Msk SDIO_RESPCMD_RESPCMD USB_EP0R_EP_KIND_Pos CAN_F3R1_FB23_Pos PWR_CR_LPDS_Pos CAN_F13R2_FB25 USB_EP1R_EP_KIND_Pos CAN_F11R1_FB14 CAN_F0R2_FB8_Pos USB_EP0R_CTR_RX CAN_F13R2_FB26 CAN_F6R2_FB5_Msk USB_EP7R_STAT_RX_0 TIM_CCER_CC2E_Msk GPIO_CRL_CNF0 GPIO_BRR_BR13 ADC_SQR3_SQ6_Pos CAN_F0R2_FB4 CAN_F0R1_FB13_Msk
+syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP_Msk I2C_CR1_PE AFIO_EXTICR2_EXTI4_PC_Msk CAN_F0R2_FB2_Msk USB_ADDR1_TX_ADDR1_TX_Pos SPI2_IRQ_PRIORITY CAN_F5R2_FB9 TIM9_IRQn USB_CNTR_SOFM DBGMCU_IDCODE_REV_ID_15 CAN_F3R1_FB9_Pos USB_COUNT0_RX_1_BLSIZE_1 SPI2 CAN_F2R1_FB17 TIM_CCMR1_IC2F_Pos GPIO_CRH_MODE11_1 CAN_F1R2_FB17_Msk ADC1_IRQn ADC_SQR1_SQ13_Msk GPIO_IDR_IDR15 RCC_APB2ENR_ADC2EN_Pos CAN_F0R1_FB15_Msk AFIO_EXTICR2_EXTI5_Msk CAN_F1R1_FB30 RCC_APB2ENR_IOPEEN_Pos SPI_TXCRCR_TXCRC CAN_F1R2_FB0_Pos
+syn keyword CTagsDefinedName BKP_CSR_TEF_Pos FLASH_CR_LOCK RCC_APB2RSTR_TIM1RST AFIO_EVCR_PIN_PX3 GPIO_LCKR_LCK3_Pos USART_CR3_CTSE_Pos CAN_F1R2_FB31 CAN_RF1R_FMP1_Msk USART_CR2_LBDIE_Msk GPIO_IDR_IDR5_Msk CAN_F10R2_FB20_Msk ADC_CR1_AWDCH_3 GPIO_CRL_CNF6_1 CAN_F11R1_FB13_Msk FLASH_CR_MER CAN_F3R2_FB21 CAN_IER_EWGIE_Msk CAN_FFA1R_FFA8_Pos CAN_F7R1_FB10_Msk TIM_CCMR2_IC3F_2 EXTI_IMR_MR2_Pos CAN_F9R1_FB7 CAN_F12R1_FB29_Msk GPIO_CRH_MODE12_0 AFIO_EXTICR2_EXTI5_PD I2C_SR1_BTF_Msk USB_ADDR2_RX_ADDR2_RX
+syn keyword CTagsDefinedName RCC_APB1RSTR_I2C1RST CAN_F8R1_FB9_Msk USB_CNTR_ERRM EXTI_EMR_MR6_Pos CAN_F9R1_FB29_Pos CAN_F3R2_FB7 RCC_CIR_CSSF_Msk CAN_F13R1_FB25_Msk USB_COUNT4_RX_0_NUM_BLOCK_0_0 PWR_CR_CWUF_Msk TIM_CCMR1_OC1PE_Msk CAN_F9R2_FB20_Pos ADC_SMPR1_SMP13_2 CAN_F13R1_FB4 USB_EP0R_DTOG_TX_Msk CAN_F0R2_FB0_Msk CAN_F4R2_FB22_Msk CAN_F3R1_FB26_Pos EXTI_EMR_MR0_Msk I2C_SR2_MSL_Pos CAN_F7R1_FB13_Msk CAN_F5R1_FB23_Pos CAN_FS1R_FSC0_Pos CAN_F9R2_FB17_Pos RCC_CFGR_PLLXTPRE_Pos CAN_F13R2_FB10_Pos
+syn keyword CTagsDefinedName CAN_F1R1_FB21_Pos DMA_IFCR_CTCIF4_Pos USB_EP7R_SETUP AFIO_EXTICR2_EXTI4_PC_Pos SDIO_CLKCR_BYPASS_Pos USB_COUNT5_RX_NUM_BLOCK_2 DMA_IFCR_CTCIF5_Pos SDIO_ICR_TXUNDERRC_Pos EXTI_PR_PIF11 CAN_FA1R_FACT9_Pos TIM_CCMR2_OC4CE GPIO_IDR_IDR8_Pos ADC_SQR2_SQ11 DMA_IFCR_CTEIF7 USB_EP1R_EP_TYPE_Msk GPIO_BSRR_BR7_Msk CAN_F9R1_FB25 SDIO_RESP2_CARDSTATUS2 EXTI_PR_PR9_Pos PWR_CR_PLS_2V5 ADC_SQR2_SQ7_3 TIM_CR2_CCUS_Msk TIM_CCMR2_OC3FE CAN_F12R1_FB15 CAN_F0R1_FB21 CAN_F6R1_FB23_Msk
+syn keyword CTagsDefinedName I2C_SR2_SMBHOST CAN_F8R2_FB2_Pos CAN_F13R1_FB25_Pos AFIO_EXTICR2_EXTI6 FLASH_R_BASE CAN_F10R2_FB9_Pos CAN_F9R2_FB16_Pos RCC_CIR_LSERDYF_Msk AFIO_MAPR_TIM2_REMAP_FULLREMAP CAN_F12R1_FB3_Pos TIM_EGR_UG_Msk USB_COUNT0_RX_NUM_BLOCK_Pos USB_ADDR4_TX_ADDR4_TX USB_COUNT7_TX_COUNT7_TX_Msk CAN_F0R2_FB26_Pos SDIO_MASK_CTIMEOUTIE_Pos CAN_F13R2_FB20_Msk USART_CR3_IRLP CAN_F5R2_FB13_Msk DMA_ISR_TCIF5_Pos I2C_OAR2_ADD2_Pos USB_EP2R_CTR_RX USB_COUNT7_RX_1_NUM_BLOCK_1_4 CAN_F10R2_FB25_Pos
+syn keyword CTagsDefinedName CAN_F5R2_FB18_Pos RCC_CIR_CSSC_Pos CAN_F13R1_FB25 CAN_IER_EPVIE SDIO_DCOUNT_DATACOUNT_Pos AFIO_EXTICR1_EXTI3_PD_Pos USB_ISTR_CTR_Pos USART_CR1_IDLEIE TIM_EGR_COMG_Pos CAN_TI0R_RTR CAN_F6R1_FB14 CAN_FFA1R_FFA1_Pos CAN_F13R2_FB17 RCC_APB1ENR_SPI2EN GPIO_IDR_IDR5_Pos RTC_CRL_OWF CAN_F2R2_FB30_Msk SDIO_MASK_RXACTIE FLASH_CR_OPTPG CAN_F12R2_FB13 GPIO_BSRR_BS5_Pos CAN_F12R2_FB6_Msk SDIO_STA_SDIOIT ADC_SQR3_SQ1_2 GPIO_CRH_CNF13_1 AFIO_EXTICR4_EXTI15_Msk CAN_F13R2_FB14
+syn keyword CTagsDefinedName CAN_FS1R_FSC13_Pos AFIO_EXTICR2_EXTI5_PD_Pos EXTI_IMR_MR10_Msk TIM_SMCR_ETP_Pos USB_COUNT1_TX_COUNT1_TX_Pos CAN_F11R1_FB16 WWDG_CR_T0 CAN_F5R1_FB18_Msk SPI_CR1_MSTR GPIO_CRH_CNF13 USB_COUNT3_RX_NUM_BLOCK_Pos EXTI_IMR_MR4_Msk EXTI_PR_PIF8 TIM_DIER_CC4IE_Pos RCC_AHBENR_FLITFEN DMA_ISR_TEIF5_Msk GPIO_BSRR_BR14 USART_CR1_RWU AFIO_MAPR_CAN_REMAP_REMAP2_Msk SDIO_STA_DBCKEND CAN_TI0R_IDE AFIO_EXTICR4_EXTI15_PF_Msk SDIO_DCTRL_DTMODE_Msk PWR_CR_PLS_LEV3 CAN_F10R2_FB31_Msk
+syn keyword CTagsDefinedName USB_COUNT7_RX_0_NUM_BLOCK_0_4 CAN_F1R2_FB19_Msk GPIO_CRH_CNF13_Pos USB_COUNT0_RX_NUM_BLOCK_4 GPIO_BSRR_BS0 SDIO_STA_CMDACT_Msk EXTI_FTSR_TR8_Pos ADC_SMPR1_SMP10_Msk DMA_IFCR_CGIF5_Msk CAN_FFA1R_FFA9 AFIO_EXTICR1_EXTI3_PC_Pos EXTI_FTSR_TR17_Pos SDIO_MASK_CMDSENTIE USB_COUNT3_RX_1_NUM_BLOCK_1 CAN_F2R2_FB14_Pos CAN_F10R2_FB24 USART_GTPR_PSC_7 CAN_F11R1_FB22_Msk CAN_F7R1_FB21_Pos GPIO_IDR_IDR14_Pos CAN_FM1R_FBM12_Msk EXTI_PR_PIF2 CAN_F2R2_FB0 SDIO_CMD_SDIOSUSPEND_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PC_Msk CAN_FM1R_FBM1_Pos USB_ADDR6_TX_ADDR6_TX_Pos CAN_F11R1_FB22_Pos SDIO_ICR_TXUNDERRC USB_COUNT2_TX_COUNT2_TX CAN_F8R2_FB28 CAN_F8R1_FB16 AFIO_EXTICR4_EXTI13_Pos GPIO_CRL_CNF7_0 CAN_F10R1_FB9_Pos CAN_F6R2_FB25_Msk CAN_F11R2_FB16 CAN_TDT0R_DLC_Pos USB_EP0R AFIO_EXTICR3_EXTI8_PB_Msk CAN_F2R2_FB25_Msk AFIO_EXTICR1_EXTI1_PA CAN_F7R1_FB14_Msk CAN_FS1R_FSC10_Pos GPIO_CRL_CNF0_Pos I2C_TRISE_TRISE_Msk GPIO_CRH_MODE13_Msk CAN_F8R2_FB12_Msk WWDG_CR_T5
+syn keyword CTagsDefinedName GPIO_CRL_CNF3_0 AFIO_EXTICR4_EXTI15_PD_Pos CAN_F3R1_FB16_Pos CAN_FS1R_FSC11_Pos TIM_BDTR_LOCK_Pos RCC_CFGR_PPRE2_Msk CAN_FS1R_FSC4_Pos CAN_F2R2_FB4 SDIO_DCTRL_DTEN TIM_SMCR_MSM_Pos CAN_FA1R_FACT5_Pos RCC_CSR_LSIRDY_Msk CAN_F0R1_FB21_Pos CAN_F1R2_FB17 RTC_CNTL_RTC_CNT AFIO_EXTICR4_EXTI13_PC_Msk CAN_F1R2_FB13_Pos CAN_F4R1_FB12 CAN_F4R2_FB1_Pos AFIO_EVCR_PIN_1 CAN_F13R2_FB21 ADC_SMPR1_SMP17_0 TIM_BDTR_BKP CAN_RDH0R_DATA5_Pos CAN_F4R2_FB3 CAN_RF0R_RFOM0_Pos TIM_SR_CC2IF_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI1_PF CAN_F7R1_FB27_Msk CAN_F10R2_FB4 EXTI_EMR_MR15_Msk USB_COUNT0_RX_COUNT0_RX CAN_F12R1_FB15_Pos CAN_F4R2_FB28_Pos AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos FLASH_USER_USER_Msk CAN_F12R1_FB8_Pos CAN_F13R1_FB12 CAN_F8R1_FB7_Msk GPIO_CRH_MODE9 CAN_F13R1_FB23_Pos CAN_F0R2_FB10_Pos CAN_F8R1_FB6_Msk CAN_F4R1_FB8_Msk CAN_RDH1R_DATA7 CAN_F6R2_FB11_Msk ADC_SQR1_SQ13_0 GPIO_BRR_BR14_Pos AFIO_EXTICR2_EXTI5_PC_Pos I2C_SR1_SB_Msk AFIO_EXTICR4_EXTI13_PG SDIO_MASK_TXFIFOHEIE
+syn keyword CTagsDefinedName EXTI_FTSR_TR1_Pos AFIO_EXTICR4_EXTI12_PA AFIO_EXTICR1_EXTI1_PD SDIO_STA_RXFIFOHF_Pos CAN_RI0R_IDE_Pos USB_CNTR_LP_MODE CAN_F8R2_FB29_Msk CAN_RF0R_FMP0 GPIOC CAN_F10R2_FB0_Msk USART_CR1_TE_Msk CAN_F8R2_FB4_Pos AFIO_MAPR_TIM1_REMAP_1 CAN_F1R2_FB5_Pos AFIO_EXTICR2_EXTI6_PB_Msk SDIO_STA_TXUNDERR_Msk USB_EP2R_EP_KIND_Msk RCC_AHBENR_CRCEN_Msk CAN_F12R2_FB26 CAN_F13R1_FB22_Msk ADC_SMPR1_SMP13_Msk AFIO_EXTICR1_EXTI1_PE_Msk CAN_F13R2_FB8 RCC_APB1RSTR_USART2RST_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI6_PG_Pos CAN_F0R1_FB25_Pos EXTI_RTSR_TR18_Pos USB_COUNT1_RX_0_NUM_BLOCK_0_2 CRC_CR_RESET_Msk CAN_F4R1_FB6_Msk SDIO_POWER_PWRCTRL_1 ADC_CR1_SCAN_Msk CAN_F6R2_FB2_Pos CAN_F6R1_FB16 CAN_F0R1_FB1_Msk CAN_F10R2_FB2_Pos DMA_CCR_MSIZE_0 USB_EP1R_STAT_RX_Pos SDIO_STA_CCRCFAIL CAN_F3R2_FB30_Pos GPIO_LCKR_LCK15 CAN_F5R2_FB7_Msk DMA_CCR_TEIE_Pos USART_CR3_SCEN_Pos CAN_F1R1_FB10 RCC_CFGR_PPRE_DIV_16 GPIO_BRR_BR6_Pos CAN_F3R2_FB4_Msk RCC_BDCR_RTCSEL_LSI
+syn keyword CTagsDefinedName RCC_AHBENR_DMA1EN_Pos CAN_F12R1_FB10_Pos SDIO_DLEN_DATALENGTH_Msk USB_COUNT7_TX_COUNT7_TX CAN_F8R2_FB18_Msk CAN_F6R2_FB23 CAN_MSR_SAMP_Pos CAN_MCR_TTCM_Msk TIM_DIER_CC4DE_Pos USART_CR2_STOP_Pos IS_WWDG_ALL_INSTANCE EXTI_IMR_MR10 CAN_F10R2_FB0_Pos I2C2_IRQERR_PRIORITY EXTI_FTSR_TR17 TIM_CR2_CCDS_Pos RCC_CR_HSITRIM_Pos CAN_F5R1_FB26 DMA_ISR_TCIF3 TIM_CCR2_CCR2 IS_GPIO_LOCK_INSTANCE EXTI_FTSR_TR2_Pos EXTI_FTSR_FT18 USB_EP0R_EP_KIND_Msk CAN_F11R1_FB5_Msk DMA_IFCR_CHTIF1_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI12_PD_Msk GPIO_ODR_ODR10_Pos GPIO_CRH_MODE15_Pos USART_CR3_RTSE RCC_APB1ENR_WWDGEN CAN_F11R2_FB0 SDIO_FIFO_FIFODATA USB_EP4R_STAT_RX_1 USB_EP7R CAN_F10R2_FB19_Msk USB_EP7R_EP_TYPE FLASH_SR_EOP_Pos CAN_F6R2_FB17_Msk AFIO_EXTICR4_EXTI12_PC EXTI_PR_PIF16 CAN_F2R2_FB8_Msk EXTI_SWIER_SWIER18_Pos GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk RCC_APB1ENR_TIM3EN EXTI_IMR_MR1 CAN_F6R1_FB12 SDIO_ICR_STBITERRC_Msk CAN_F1R2_FB10_Pos CAN_F4R1_FB4_Msk AFIO_EVCR_PIN_PX8_Msk CAN_F5R2_FB16
+syn keyword CTagsDefinedName DMA_CCR_MSIZE_Msk USB_DADDR_ADD CAN_FA1R_FACT13 CAN_F13R1_FB8 USB_ADDR1_RX_ADDR1_RX_Msk USB_COUNT2_RX_0_NUM_BLOCK_0_1 CAN_F0R1_FB27_Pos TIM_DIER_TIE_Msk ADC_SQR2_SQ8_2 AFIO_EXTICR4_EXTI14_Pos CAN_F3R2_FB30_Msk ADC_CR1_SCAN_Pos ADC_JOFR2_JOFFSET2_Pos CAN_TSR_ALST1_Msk RCC_CFGR_PLLMULL14_Pos GPIO_CRH_CNF11_Msk CAN_F2R2_FB31_Msk GPIO_BRR_BR2_Pos CAN_F5R2_FB11 ADC_SMPR2_SMP7_0 CAN_TI2R_STID_Pos CAN_RDL1R_DATA0_Pos TIM_CCMR1_CC1S_Msk SDIO_STA_TXUNDERR CAN_F9R2_FB26 USB_ISTR_SOF
+syn keyword CTagsDefinedName CAN_FM1R_FBM2_Pos CAN_F4R1_FB19 USB_EP7R_EA AFIO_EXTICR2_EXTI7_PB_Pos EXTI_SWIER_SWIER5_Pos IS_USART_INSTANCE TIM1_UP_TIM16_IRQHandler CAN_F6R1_FB16_Pos RCC_CFGR_PLLSRC_Msk USB_COUNT0_RX_0_BLSIZE_0 AFIO_EXTICR3_EXTI11_Pos BKP_CSR_TIF CAN_TDH2R_DATA5_Msk USB_CNTR_SUSPM USB_EP7R_EP_TYPE_0 BKP_DR1_D_Pos USART_CR1_SBK_Msk CAN_F3R1_FB14_Pos EXTI_IMR_MR9_Msk DMA_ISR_GIF5 EXTI RCC_CIR_LSERDYIE_Pos RCC_APB1RSTR_I2C2RST_Msk CAN_F7R2_FB12_Pos FLASH_WRP3_WRP3_Msk CAN_F13R1_FB14_Msk
+syn keyword CTagsDefinedName EXTI_PR_PR6 CAN_F6R1_FB10_Msk FLASH_KEY2_Pos AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk USB_EP0R_CTR_RX_Pos CAN_F8R2_FB0_Pos USB_ISTR_WKUP_Msk SPI_CR1_CPHA CAN_F2R2_FB28_Pos USB_EP3R_EP_TYPE_0 EXTI_PR_PR14_Msk PIN_10 RCC_CFGR_HPRE_DIV_8 CAN_TSR_TERR2_Msk EXTI_RTSR_TR1_Pos CAN_F4R1_FB2 ADC_SMPR2_SMP1_Pos AFIO_EXTICR2_EXTI6_Pos CAN_F3R2_FB2 USB_COUNT5_RX_0_NUM_BLOCK_0 EXTI_SWIER_SWIER0_Pos SDIO_MASK_CTIMEOUTIE CAN_F13R2_FB19_Pos DMA1_Channel1 RCC_CFGR_PLLMULL11_Pos CAN_F6R1_FB11_Pos
+syn keyword CTagsDefinedName CAN_F1R1_FB9_Pos I2C_SR1_ARLO_Msk TIM_CR2_CCUS CAN_TSR_ALST0_Msk AFIO_EXTICR3_EXTI9_PG GPIO_CRL_MODE7 USART_CR2_LBDL_Pos USB_ISTR_PMAOVR CAN_F13R2_FB31_Msk CAN_F13R2_FB4_Msk CAN_F0R1_FB27 USB_COUNT0_RX_1_NUM_BLOCK_1_4 CAN_F13R2_FB27 GPIO_IDR_IDR0 CAN1 SDIO_ICR_CMDSENTC EXTI_SWIER_SWI7 SDIO_CMD_NIEN_Msk CAN_RDH1R_DATA7_Pos GPIO_BSRR_BS3_Pos MODIFY_REG RCC_APB2ENR_IOPCEN_Msk CAN_F9R2_FB7 USART_CR1_SBK_Pos CAN_TSR_ALST2_Pos GPIO_CRL_MODE4_0 CAN_F0R1_FB24_Msk USB_EP5R_SETUP
+syn keyword CTagsDefinedName CAN_F2R2_FB6_Pos CAN_F4R2_FB7 RCC_BDCR_RTCSEL_1 IS_CRC_ALL_INSTANCE CAN_F4R2_FB5 CAN_F2R2_FB16 USB_COUNT0_RX_COUNT0_RX_Pos CAN_F6R2_FB25 I2C_SR1_TIMEOUT_Msk DMA_IFCR_CHTIF1_Pos DMA_IFCR_CHTIF4 EXTI_RTSR_TR12 CAN_F4R2_FB13_Msk CAN_F7R2_FB29 PIN_OPT_AF8 RTC_CRL_ALRF_Msk GPIO_LCKR_LCK6_Pos TIM_CR2_MMS_Msk USB_COUNT2_RX_1_NUM_BLOCK_1_3 GPIO_LCKR_LCK2 CAN_F4R1_FB23_Msk DBGMCU_CR_TRACE_IOEN_Msk RCC_CIR_PLLRDYF_Pos USB_COUNT6_RX_0_BLSIZE_0 EXTI_EMR_MR13_Msk AFIO_EVCR_PIN_PX13
+syn keyword CTagsDefinedName CAN_F12R2_FB22_Msk USB_COUNT3_RX_1_COUNT3_RX_1 CAN_RDL0R_DATA3_Pos TIM_CCMR2_IC3F_Pos SDIO_MASK_DBCKENDIE USB_COUNT3_TX_1_COUNT3_TX_1 DBGMCU_CR_DBG_STANDBY USB_DADDR_ADD3_Msk AFIO_EXTICR3_EXTI11 ADC_CR1_DISCEN_Msk ADC_CR1_JDISCEN_Msk CAN_F0R2_FB20_Msk EXTI_RTSR_TR14_Pos GPIO_ODR_ODR15 CAN_TDL2R_DATA1_Pos CAN_F11R1_FB15_Pos TIM_CCMR1_IC2F_3 CAN_TDL1R_DATA2 CAN_F7R2_FB18 GPIO_BSRR_BR15_Pos SDIO_MASK_DCRCFAILIE CAN_TSR_ABRQ2_Pos CAN_F3R2_FB31 CAN_F10R1_FB26_Msk CAN_TDL2R_DATA0
+syn keyword CTagsDefinedName CAN_F9R1_FB11 USART_CR1_RE_Pos BKP_CR_TPE_Pos GPIO_LCKR_LCKK_Msk CAN_F1R2_FB12_Msk RCC_APB1RSTR_BKPRST_Msk AFIO_EXTICR1_EXTI1_PF_Msk GPIO_BSRR_BS12_Pos SDIO_STA_TXACT_Pos EXTI_IMR_MR5 USB_EP3R_SETUP_Msk USB_EP6R_EP_TYPE_0 CAN_IER_FFIE0_Msk TIM_DIER_TDE CAN_F10R1_FB10_Msk CAN_F7R1_FB5_Pos EXTI_FTSR_TR7_Pos CAN_TSR_RQCP1_Pos ADC_SQR1_SQ13_Pos __STM32F1_CMSIS_VERSION_RC EXTI_IMR_MR10_Pos EXTI_RTSR_TR13_Pos WWDG_CR_T_5 CAN_F1R1_FB25 GPIO_LCKR_LCK5 EXTI_RTSR_RT3 CAN_F0R2_FB23
+syn keyword CTagsDefinedName CAN_TSR_LOW2_Msk ADC_SMPR2_SMP3_1 CAN_F10R2_FB10 CAN_F3R1_FB10_Pos I2C_OAR1_ADD7_Msk CAN_F6R1_FB16_Msk TIM_SR_CC2IF CAN_F8R1_FB0 RCC_CIR_PLLRDYIE AFIO_EXTICR1_EXTI3 USB_COUNT6_RX_1_BLSIZE_1 RCC_CFGR_PPRE1_1 RCC_AHBENR_DMA1EN CAN_F2R2_FB28_Msk CAN_F10R1_FB24 CAN_F0R2_FB14 RCC_BDCR_LSERDY_Msk CAN_TI0R_EXID_Msk CAN_F4R2_FB17_Msk CAN_F7R1_FB31 EXTI_FTSR_TR15_Msk EXTI_SWIER_SWIER16 ADC_SQR1_L_3 GPIO_CRL_MODE6_Msk CAN_TDL1R_DATA3_Pos CAN_F0R1_FB23_Pos AFIO_EVCR_EVOE CAN_F7R1_FB22_Msk
+syn keyword CTagsDefinedName CAN_F3R1_FB16 DMA_IFCR_CHTIF1 EXTI_PR_PR9_Msk CAN_FA1R_FACT4_Pos I2C_SR1_RXNE PIN_MODE_ALTFUNC ADC_SQR1_L_Msk CAN_TDH2R_DATA7_Msk RCC_AHBENR_CRCEN_Pos AFIO_EXTICR1_EXTI2_PC_Pos CAN_F2R1_FB18_Pos SPI_SR_TXE_Msk SPI_DR_DR CAN_F8R2_FB0_Msk AFIO_EXTICR1_EXTI2_PG FLASH_OBR_nRST_STDBY USART_CR2_CLKEN_Pos CAN_F13R2_FB0_Msk CAN_F10R1_FB11_Msk EXTI_SWIER_SWIER4_Msk CAN_F0R1_FB12_Pos NVIC_NUM_VECTORS TIM_CR2_CCDS AFIO_EVCR_PIN_Msk SDIO_DCTRL_RWSTART_Msk AFIO_EVCR_PIN
+syn keyword CTagsDefinedName USB_COUNT0_RX_1_NUM_BLOCK_1_2 GPIO_BRR_BR0 RCC_CIR_HSERDYIE ADC_JSQR_JSQ1_0 CAN_F6R1_FB14_Msk CAN_F4R2_FB11 USB_COUNT1_RX_NUM_BLOCK_3 EXTI_PR_PR17_Pos AFIO_MAPR_TIM3_REMAP_Msk CAN_TSR_ABRQ2 CAN_F3R1_FB27_Pos CAN_MSR_SLAK_Pos GPIO_BSRR_BR11 CAN_F1R1_FB12_Msk RCC_CFGR_PPRE_DIV_NONE CAN_F4R1_FB31 CAN_F6R1_FB25_Msk USB_ADDR3_RX_ADDR3_RX_Msk GPIO_CRH_MODE13_0 CAN_TI1R_EXID_Msk PWR_CSR_SBF_Pos CAN_F6R2_FB22_Msk RCC_APB1RSTR_CAN1RST_Msk FLASH_OBR_DATA1_Pos TIM_CCMR2_OC3M_Pos
+syn keyword CTagsDefinedName CAN_F13R1_FB18_Msk EXTI_EMR_MR5_Msk CAN_F1R2_FB24_Msk CAN_F2R2_FB29_Pos EXTI_EMR_MR12 TIM_CCMR2_IC4F_2 AFIO_MAPR_I2C1_REMAP_Pos CAN_F5R2_FB29_Msk EXTI_IMR_IM2 ADC_SQR3_SQ2_Pos USB_ADDR0_TX_ADDR0_TX_Msk EXTI_RTSR_TR0_Pos CAN_F5R1_FB29 CAN_F10R1_FB2_Pos USB_EP5R_EP_KIND_Msk DMA_ISR_GIF7_Pos I2C3_IRQERR_PRIORITY I2C_OAR1_ADD8_Pos CAN_F12R1_FB29_Pos CAN_F8R2_FB11_Pos SDIO_STA_RXDAVL_Msk RCC_CIR_HSIRDYF USART_CR1_RWU_Pos RCC_APB2ENR_IOPAEN_Pos CAN_F7R1_FB8 CAN_F7R1_FB15_Pos
+syn keyword CTagsDefinedName CAN_F7R1_FB25_Pos CAN_F10R1_FB15_Msk CAN_TI2R_TXRQ CAN_F2R2_FB3_Pos USB_COUNT6_RX_NUM_BLOCK_0 ADC_CR1_AWDCH CAN_FA1R_FACT6_Msk DMA_IFCR_CGIF6 CAN_F2R1_FB14 CAN_FM1R_FBM7 CAN_F13R2_FB3 USB_EP_TYPE_MASK CAN_F6R2_FB30 CAN_F8R1_FB18_Pos CAN_F3R2_FB29_Msk USB_EP1R_STAT_RX_Msk EXTI_IMR_IM8 I2C_CR2_FREQ_2 GPIO_CRL_MODE3 CAN_TSR_LOW_Msk USB_CNTR_ESOFM CAN_F4R2_FB20_Pos ADC_JOFR3_JOFFSET3_Pos CAN_F2R1_FB18_Msk CAN_F0R2_FB21 CAN_F4R2_FB24_Msk USB_COUNT4_RX_1_BLSIZE_1 GPIO_CRL_MODE6_0
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI13_PG_Pos CAN_F6R1_FB21 CAN_TI1R_IDE_Msk USB_EP4R_DTOG_TX_Pos USB_COUNT7_RX_1_NUM_BLOCK_1_2 TIM_CCMR2_OC3PE_Pos USB_EP1R_CTR_RX_Msk USB_ADDR2_TX_ADDR2_TX CAN_F3R2_FB7_Msk CAN_F7R2_FB9 TIM_CCMR2_CC3S_0 RCC_APB1ENR_TIM4EN_Pos CAN_FA1R_FACT1_Msk GPIO_BSRR_BS8_Msk USB_COUNT2_RX_BLSIZE_Msk CAN_F6R2_FB31_Msk CAN_F12R1_FB19 CAN_F10R1_FB29 AFIO_MAPR_PD01_REMAP_Msk CAN_F10R1_FB30 SDIO_MASK_TXFIFOFIE USART_BRR_DIV_Mantissa_Pos AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos
+syn keyword CTagsDefinedName USB_ADDR0_RX_ADDR0_RX CAN_F9R1_FB19_Pos CAN_F11R1_FB21_Pos CAN_F7R1_FB30_Msk CAN_F13R2_FB29_Msk AFIO_EXTICR3_EXTI10_PB CAN_F11R1_FB10_Pos CAN_F11R2_FB7 USB_ADDR0_RX_ADDR0_RX_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_3 SDIO_STA_TXFIFOHE_Msk CAN_F3R2_FB19 EXTI_IMR_MR14 TIM_CCMR2_CC3S_1 CAN_F7R1_FB24 EXTI_FTSR_TR18_Pos AFIO_EXTICR4_EXTI13_PE_Pos CAN_F0R2_FB29_Pos CAN_RDL0R_DATA3_Msk RCC_CFGR_PLLMULL13_Msk CAN_TDH0R_DATA4_Msk CAN_F10R1_FB31_Pos CAN_F10R2_FB25 RCC_BDCR_RTCSEL_HSE USART_CR1_RE
+syn keyword CTagsDefinedName CAN_F4R2_FB29_Pos CAN_F1R1_FB23_Pos USB_COUNT5_RX_1_NUM_BLOCK_1 DMA1 SPI_SR_BSY CAN_F5R1_FB9 GPIO_CRH_CNF10_Msk CAN_TDH2R_DATA6_Msk AFIO_EXTICR1_EXTI0_PB CAN_F7R1_FB9 CAN_F5R2_FB23_Pos DMA_CCR_CIRC SDIO_MASK_TXUNDERRIE TIM_SR_COMIF_Pos CAN_F8R2_FB19_Msk CAN_F5R2_FB29 CAN_F12R1_FB29 EXTI_PR_PR0 WRITE_REG CAN_F0R2_FB22_Msk DMA_IFCR_CTCIF6_Msk CAN_F7R1_FB26_Msk CAN_TSR_ABRQ1 CAN_F4R1_FB10 I2C_SR2_BUSY_Pos TIM_CCMR2_OC4M RCC_APB1RSTR_TIM3RST_Msk CAN_F0R2_FB22_Pos
+syn keyword CTagsDefinedName EXTI_SWIER_SWIER8_Msk CAN_F6R2_FB31_Pos CAN_F12R1_FB5 SPI_CR1_SSI_Pos USB_EP7R_EP_KIND_Msk CAN_F10R2_FB13 CAN_F0R1_FB3 EXTI_SWIER_SWI5 ADC_SMPR2_SMP6_1 CAN_F0R1_FB12_Msk CAN_F2R2_FB0_Msk TIM_SMCR_ETPS_Pos DMA_ISR_TCIF2_Pos SDIO_CMD_WAITPEND_Pos DMA_IFCR_CTCIF6_Pos CAN_IER_FMPIE0 CAN_F8R2_FB17_Msk DMA_IFCR_CTEIF7_Pos EXTI_IMR_MR15_Pos TIM_CCMR1_OC1CE_Pos CAN_F12R2_FB4_Pos CAN_F6R2_FB24 USB_ADDR6_RX_ADDR6_RX_Msk I2C_CR2_LAST_Msk ADC_SQR1_SQ15_1 IWDG_SR_PVU_Msk AFIO_MAPR_SWJ_CFG
+syn keyword CTagsDefinedName RCC_CIR_HSIRDYF_Msk USART_CR2_ADD_Pos AFIO_EXTICR4_EXTI13_PC_Pos AFIO_EXTICR3_EXTI8_PE_Pos AFIO_EXTICR4_EXTI12_PF_Pos USB_EPTX_DTOG2 EXTI_FTSR_TR13 CAN_F7R2_FB8_Pos RCC_AHBENR_CRCEN RTC_CRH_OWIE I2C_CR1_STOP_Pos ADC_CR1_EOCIE DMA_IFCR_CTEIF6_Pos I2C_CR1_START CAN_TDL2R_DATA2_Pos CAN_F6R1_FB21_Pos CAN_F13R2_FB15_Pos CAN_F3R2_FB26_Msk RCC_CIR_LSERDYIE CAN_F1R2_FB21_Pos RCC_CFGR_MCOSEL_SYSCLK DMA_IFCR_CTEIF3_Pos EXTI_RTSR_TR7 GPIO_BSRR_BS15 RCC_CFGR_PLLMULL2 GPIO_BRR_BR10_Msk
+syn keyword CTagsDefinedName CAN_TSR_RQCP0 SRAM_BB_BASE USB_ADDR4_TX_ADDR4_TX_Pos ADC_CR2_CAL_Msk CAN_F6R2_FB10 I2C_SR2_TRA USB_COUNT4_RX_NUM_BLOCK_3 USB_EP5R_STAT_RX CAN1_RX0_IRQn CAN_F0R1_FB29_Pos CAN_F8R2_FB14 CAN_F0R1_FB29 EXTI_PR_PR6_Msk SPI_CR2_RXDMAEN_Msk USB_EP4R_STAT_RX_Msk AFIO_EVCR_EVOE_Msk CAN_F2R2_FB19 CAN_F0R1_FB18_Pos USART_CR1_PS AFIO_EXTICR1_EXTI1_PC TIM_CCER_CC2E_Pos ADC_SMPR1_SMP13_0 USB_COUNT0_RX_1_COUNT0_RX_1 RCC_APB1RSTR_I2C1RST_Pos ADC_SMPR2_SMP1_Msk TIM_CCMR1_OC2CE_Pos
+syn keyword CTagsDefinedName CAN_F13R1_FB19_Pos CAN_F4R1_FB10_Pos USB_COUNT5_RX_0_NUM_BLOCK_0_3 CAN_F7R1_FB13 EXTI_RTSR_RT13 CAN_F4R1_FB25_Msk USB_EP2R CAN_F2R1_FB22_Pos SPI_SR_CHSIDE PIN_MODE_ANALOG TIM_SR_CC4OF SYSCFG_EXTI_PA_MASK CAN_F1R1_FB3_Msk USB_COUNT1_RX_0_NUM_BLOCK_0 CAN_TDT1R_DLC_Pos CAN_F0R2_FB20_Pos APB2PERIPH_BASE CAN_F10R2_FB7_Msk RCC_CFGR_PPRE1_DIV1 CAN_F10R1_FB1_Pos CAN_F2R1_FB19 USB_COUNT3_RX_NUM_BLOCK_3 TIM_EGR_CC1G_Msk CAN_F2R1_FB4_Pos DBGMCU_CR_DBG_SLEEP_Pos CAN_F11R2_FB28_Msk
+syn keyword CTagsDefinedName PIN_MODE_INPUT CAN_RDT0R_FMI_Pos ADC_SMPR2_SMP5 USB_EP4R_DTOG_RX_Msk TIM_SR_CC4IF_Msk USB_EP3R_EP_KIND_Msk RCC_APB1RSTR_TIM2RST_Pos GPIO_CRL_CNF5_Msk USB_COUNT3_RX_BLSIZE CAN_F1R1_FB11_Msk CAN_RF1R_RFOM1_Pos SDIO_MASK_TXFIFOEIE_Msk EXTI_PR_PR8_Msk CAN_F6R2_FB7_Msk AFIO_EXTICR1_EXTI0_PC_Pos CAN_FM1R_FBM7_Msk ADC_CR2_ALIGN DMA_IFCR_CHTIF7_Msk GPIO_BSRR_BS10_Pos I2C_CCR_CCR_Msk CAN_F7R1_FB8_Pos CAN_TDH1R_DATA7 CAN_F6R2_FB6_Msk PWR_CR_PLS_2 CAN_ESR_EPVF USB_COUNT0_RX_BLSIZE_Pos
+syn keyword CTagsDefinedName TIM_CCMR2_IC4F_Msk USB_EP4R_SETUP_Msk EXTI_FTSR_TR8 PWR_CR_CWUF ADC_SQR3_SQ3_2 CAN_F0R1_FB18 CAN_F13R1_FB21 BKP_CSR_TPIE_Msk RCC_CFGR_SWS_1 EXTI_RTSR_RT1 DMA1_Channel4_BASE ADC_SMPR1_SMP15_0 CAN_F6R1_FB27 GPIOE RCC_CFGR_ADCPRE_Pos TIM_CR2_OIS4_Pos CAN_F4R1_FB12_Pos CAN_F7R1_FB19 USART_CR1_M_Pos USB_ADDR3_RX_ADDR3_RX ADC_SQR3_SQ1_3 CAN_F4R2_FB6_Msk CAN_F9R1_FB3_Pos EXTI_PR_PR15_Msk USB_EP0R_DTOG_RX_Pos CAN_F13R1_FB18_Pos EXTI_IMR_MR9 TIM_SMCR_SMS_Msk EXTI_SWIER_SWIER12
+syn keyword CTagsDefinedName USB_EP4R_EA USB_EP3R_CTR_RX USB_COUNT6_RX_NUM_BLOCK_Msk CAN_RDH1R_DATA5_Pos TIM_SR_CC4OF_Msk CAN_F12R2_FB20_Pos CAN_FM1R_FBM SPI_CR1_BIDIMODE_Pos WWDG_CR_WDGA DBGMCU_CR_DBG_IWDG_STOP_Pos USB_COUNT1_RX_1_COUNT1_RX_1 CAN_F12R1_FB1_Pos ADC_SQR3_SQ1 CAN_F6R2_FB29_Msk EXTI_FTSR_TR4 PIN_11 CAN_F2R2_FB30_Pos CAN_F1R2_FB4_Pos CAN_F12R1_FB22 CAN_F2R1_FB27_Pos CAN_F1R2_FB22_Pos CAN_RI1R_IDE_Msk RCC_APB2RSTR_IOPBRST DMA_IFCR_CTCIF2 FLASH_WRP2_WRP2_Msk CAN_FA1R_FACT10 GPIO_ODR_ODR2_Msk
+syn keyword CTagsDefinedName TIM_CCMR1_IC1PSC_Msk USART_CR1_TCIE RCC_APB2RSTR_ADC2RST CAN_F10R2_FB17 CAN_F6R2_FB1 EXTI_EMR_MR16_Pos ADC_CR1_JAWDEN ADC_JDR1_JDATA_Pos USB_DADDR_ADD1 CAN_F5R2_FB5 FLASH_DATA0_DATA0_Msk SDIO_DTIMER_DATATIME_Pos CAN_IER_FOVIE0 RTC_DIVH_RTC_DIV_Pos CAN_F10R2_FB15 SDIO_CMD_WAITRESP_0 RCC_CFGR_PLLSRC WWDG_CFR_EWI CAN_F13R2_FB18_Msk USB_EP4R_STAT_TX_1 CAN_F5R1_FB28_Msk TIM_CCMR2_IC3PSC_1 CAN_F6R1_FB21_Msk ADC_CR1_DUALMOD_0 USB_CNTR_RESUME_Msk CAN_F13R1_FB10 CAN_TDH1R_DATA7_Pos
+syn keyword CTagsDefinedName TIM_SR_BIF_Msk CAN_F1R1_FB31_Msk AFIO_EXTICR3_EXTI10_PC RCC_CFGR_PPRE1_Msk CAN_RI0R_STID_Pos CAN_F11R2_FB29 USB_COUNT1_RX_0_NUM_BLOCK_0_3 CAN_F5R2_FB14 AFIO_EXTICR4_EXTI13_PG_Msk CAN_F6R2_FB30_Pos EXTI_EMR_MR13 USB_ADDR3_TX_ADDR3_TX_Pos CAN_F2R2_FB26 AFIO_EXTICR3_EXTI11_PC_Msk USB_COUNT7_RX_0_NUM_BLOCK_0_0 CAN_F4R1_FB21_Pos ADC_SQR1_SQ16_4 CAN_RI1R_IDE_Pos _RCC_H_ CAN_RDL1R_DATA3 CAN_F9R1_FB2_Msk SDIO_MASK_RXFIFOHFIE_Pos USB_COUNT3_RX_NUM_BLOCK_1 USB_COUNT0_TX_COUNT0_TX_Msk
+syn keyword CTagsDefinedName EXTI_RTSR_TR8_Msk CAN_F7R2_FB19 AFIO_EXTICR3_EXTI10_PF CAN_F9R2_FB26_Msk CAN_F7R2_FB25_Pos ADC_SMPR2_SMP7_Msk CAN_F13R1_FB26_Pos CAN_F6R2_FB8_Msk AFIO_EXTICR3_EXTI10_PB_Msk CAN_F9R1_FB11_Msk USB_CNTR_LP_MODE_Pos PWR_CR_DBP_Msk CAN_F0R2_FB8_Msk AFIO_MAPR_SWJ_CFG_DISABLE DBGMCU_IDCODE_REV_ID_Msk SPI_CR2_RXNEIE_Msk USART_CR1_PCE CAN_F3R1_FB3_Msk AFIO_EXTICR4_EXTI15_PG_Pos ADC_JSQR_JSQ1_4 CAN_F7R2_FB17_Msk CAN_F9R2_FB23_Msk FLASH_OBR_USER_Msk CAN_F13R2_FB26_Pos ADC_CR1_DUALMOD_3
+syn keyword CTagsDefinedName SDIO_RESP1_CARDSTATUS1 FLASH_USER_nUSER_Pos USART_CR1_WAKE_Pos CAN_TDL2R_DATA0_Pos CAN_F3R2_FB23_Msk FLASH_CR_PER_Pos GPIO_CRL_MODE4_Msk CAN_F0R1_FB19 ADC_JOFR3_JOFFSET3 ADC_SQR2_SQ7_Pos USB_COUNT5_TX_1_COUNT5_TX_1 I2C_CR2_DMAEN_Pos RTC_CRH_OWIE_Pos USB_EP4R_STAT_TX AFIO_EXTICR4_EXTI14_PG __SYSTEM_STM32F10X_H I2C_SR1_RXNE_Pos DMA_ISR_TEIF1 SDIO_STA_DTIMEOUT RCC_CR_HSICAL CAN_F13R1_FB26_Msk DBGMCU_IDCODE_REV_ID_7 CAN_F11R2_FB8_Msk FLASH_WRP0_nWRP0_Msk FLASH_CR_MER_Pos
+syn keyword CTagsDefinedName USART_CR2_STOP_0 ADC_JSQR_JSQ4_0 CAN_F2R1_FB30_Pos CAN_F10R1_FB26 CAN_F3R2_FB28_Pos GPIO_BRR_BR15 CAN_F2R1_FB23 RCC_CSR_RMVF CAN_TDH2R_DATA6_Pos TIM_EGR_UG_Pos TIM_CCER_CC1NE_Msk USART_CR1_TE DBGMCU_IDCODE_REV_ID_2 ADC_JSQR_JL_Msk CAN_TSR_TXOK1_Pos USB_CNTR_ESOFM_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos CAN_F12R2_FB8_Pos RCC_CIR_LSIRDYIE_Pos CAN_F12R1_FB21_Msk CAN_F7R2_FB11_Pos CAN_F3R1_FB24 CAN_F8R2_FB24 SDIO_CLKCR_CLKDIV USB_COUNT0_RX_NUM_BLOCK_1 CAN_TDT0R_TIME_Pos
+syn keyword CTagsDefinedName CAN_TSR_LOW2_Pos AFIO_EXTICR3_EXTI11_PB ADC_SQR2_SQ11_Pos CAN_F5R2_FB2_Msk CAN_F1R2_FB3_Msk CAN_F8R1_FB14_Msk RCC_CR_HSICAL_Pos CAN_F5R2_FB7_Pos CAN_F4R1_FB8 AFIO_MAPR_TIM3_REMAP NVIC_RAM_VECTOR_ADDRESS USART_CR1_UE_Msk DMA1_Channel6_BASE CAN_RF1R_FULL1 USB_EP1R_DTOG_TX_Pos CAN_F0R1_FB8_Msk CAN_F6R1_FB4_Pos ADC_SQR2_SQ10 GPIO_CRH_CNF12 __CM3_REV CAN_FA1R_FACT7 SDIO_MASK_RXFIFOFIE_Msk USB_COUNT3_RX_NUM_BLOCK_2 CAN_F2R1_FB26_Msk FLASH_DATA1_nDATA1_Msk CAN_TSR_ABRQ1_Pos
+syn keyword CTagsDefinedName TIM_DCR_DBL_Msk USB_EP_T_FIELD WWDG_CFR_W_6 CAN_F4R2_FB13_Pos I2C_SR1_AF CAN_F0R2_FB22 EXTI_PR_PR3_Msk CAN_F7R1_FB13_Pos EXTI_FTSR_TR13_Msk SDIO_STA_RXDAVL_Pos RCC_APB2RSTR_IOPCRST CAN_F10R2_FB11_Pos USB_COUNT2_RX_NUM_BLOCK_Pos CAN_TI1R_STID_Pos AFIO_MAPR_USART3_REMAP_NOREMAP EXTI_RTSR_TR15_Pos GPIO_CRH_MODE9_Msk ADC_SMPR2_SMP5_1 RCC_APB1RSTR_BKPRST_Pos SPI_I2SCFGR_I2SMOD_Msk TIM_EGR_COMG_Msk __STM32F103xB_H GPIO_BSRR_BS6_Pos EXTI_SWIER_SWIER1 CAN_F1R2_FB13
+syn keyword CTagsDefinedName SDIO_RESP4_CARDSTATUS4 USB_EP2R_STAT_TX_Pos PIN_9 RCC_APB1ENR_TIM3EN_Pos CAN_F5R2_FB12 TIM_CCER_CC3E CAN_RI0R_STID_Msk CAN_F10R1_FB15 CAN_F4R2_FB9 CAN_F10R2_FB27_Msk SDIO_STA_TXDAVL CAN_F3R2_FB26 TIM_SR_TIF CAN_F12R2_FB28_Pos CAN_F3R1_FB16_Msk EXTI_PR_PIF0 CAN_F11R1_FB14_Msk CAN_RDL0R_DATA1 I2C_OAR1_ADD6_Pos CAN_F4R2_FB9_Msk AFIO_EVCR_PORT_PE_Msk RCC_CFGR_HPRE_DIV4 RCC_CFGR_PLLMULL15_Pos GPIO_IDR_IDR8 CAN_F12R1_FB0_Pos USB_EP5R_CTR_TX ADC_SQR2_SQ9_3 SDIO_ICR_CMDSENTC_Msk
+syn keyword CTagsDefinedName I2C_OAR1_ADD4_Msk USB_COUNT7_RX_BLSIZE USB_EP4R_DTOG_RX_Pos CAN_F1R2_FB15_Msk EXTI_RTSR_TR8 AFIO_EXTICR2_EXTI4_PB_Msk AFIO_EVCR_PIN_PX11_Msk TIM_DIER_COMIE CAN_RDT0R_FMI RCC_CFGR_SW_PLL EXTI_FTSR_FT8 CAN_IER_TMEIE_Msk CAN_F10R2_FB12 CAN_F12R2_FB22_Pos CAN_F9R2_FB0_Msk SDIO_MASK_STBITERRIE_Msk I2C_OAR1_ADD5_Msk GPIO_CRH_MODE14_0 ADC_SR_JSTRT_Msk CAN_TSR_ABRQ1_Msk CAN_F8R1_FB5_Pos CAN_F10R1_FB14 RCC_CSR_WWDGRSTF_Pos DMA_IFCR_CGIF3 RCC_CIR_LSIRDYC GPIO_IDR_IDR10 CAN_F13R2_FB14_Pos
+syn keyword CTagsDefinedName GPIO_CRL_CNF6_0 RCC_APB1RSTR_I2C1RST_Msk EXTI_RTSR_RT16 USB_COUNT5_RX_1_NUM_BLOCK_1_0 CAN_F0R2_FB14_Pos SPI_CR1_DFF_Pos SDIO_MASK_TXFIFOFIE_Msk TIM_SMCR_MSM_Msk CAN_F8R1_FB4_Pos CAN_TSR_LOW CAN_F6R1_FB26 RCC_CFGR_PLLMULL14_Msk RCC_CR_CSSON_Pos CAN_F1R1_FB12 AFIO_EXTICR1_EXTI3_PB_Pos CAN_RI1R_RTR_Pos I2C2_IRQ_PRIORITY CAN_F1R1_FB19_Pos CAN_TSR_TME2_Msk USB_COUNT3_RX_1_BLSIZE_1 CAN_F4R2_FB18_Msk SPI_RXCRCR_RXCRC_Msk AFIO_EXTICR1_EXTI1_PG GPIO_LCKR_LCK3_Msk USB_FNR_RXDM_Pos
+syn keyword CTagsDefinedName RCC_CSR_LSION_Msk DBGMCU_CR_TRACE_IOEN CRC_IDR_IDR DBGMCU_CR_TRACE_MODE_0 USB_EP2R_DTOG_TX CAN_F10R1_FB13_Msk SDIO_STA_RXFIFOF_Msk TIM_DIER_UDE_Msk USB_COUNT2_RX_1_NUM_BLOCK_1 CAN_F6R2_FB20_Pos CAN_F13R2_FB23_Msk DBGMCU_CR_DBG_SLEEP PIN_OPT_AF0 ADC_JSQR_JSQ3_Pos USB_COUNT3_RX_0_NUM_BLOCK_0 EXTI_EMR_MR11_Pos CAN_F8R1_FB8_Pos CAN_F3R1_FB6_Msk CAN_F7R2_FB23_Pos I2C_OAR1_ADDMODE SPI_CR1_CRCEN_Pos CAN_F13R2_FB0 USART1_IRQ_PRIORITY ADC_CR1_SCAN CAN_FA1R_FACT6 CAN_F12R1_FB24_Msk
+syn keyword CTagsDefinedName CAN_TDL0R_DATA2_Msk ADC_SQR3_SQ5_0 EXTI_RTSR_TR17 CAN_F2R2_FB6 CAN_F6R1_FB10_Pos CAN_F6R1_FB20_Pos DBGMCU_CR_DBG_CAN1_STOP_Pos RTC_CRH_ALRIE_Pos EXTI_FTSR_TR12_Msk EXTI_FTSR_TR2_Msk FLASH_KEY1_Msk TIM_CCER_CC3NE_Pos EXTI_PR_PR4_Pos USB_COUNT7_RX_NUM_BLOCK_Msk AFIO_EXTICR2_EXTI5_PA CAN_F6R1_FB29_Msk CAN_F5R2_FB27_Pos CAN_F8R2_FB17 FLASH_ACR_LATENCY_Pos CAN_F2R1_FB11_Msk CAN_F9R2_FB5_Pos CAN_F7R1_FB17_Msk BKP_CSR_CTE_Pos ADC_CR1_AWDIE_Msk USB_BTABLE_BTABLE_Msk
+syn keyword CTagsDefinedName USB_EP4R_STAT_TX_Pos SPI_CR1_DFF_Msk CAN_F11R2_FB12_Pos CAN_F5R1_FB15_Pos I2C_CR1_ENGC EXTI_SWIER_SWIER11_Msk ADC_SMPR1_SMP17_2 CAN_F12R2_FB10 CAN_RDH0R_DATA4 TIM_SR_UIF_Msk FLASH_OBR_USER RCC_CR_CSSON CAN_F9R2_FB10_Pos CAN_F6R2_FB3_Pos CAN_F2R2_FB22_Msk SPI5_IRQ_PRIORITY AFIO_EXTICR3_EXTI8_PC_Msk CAN_F12R2_FB30_Msk CAN_F6R1_FB17_Msk CAN_MSR_TXM_Pos GPIO_CRL_CNF1 TIM_CR2_OIS3N_Pos GPIO_CRL_CNF4_1 SDIO_ICR_CEATAENDC_Pos TIM_SR_CC3OF_Msk ADC_SMPR2_SMP4_2 RCC_CR_HSEBYP_Msk
+syn keyword CTagsDefinedName CAN_F10R2_FB27 CAN_F4R2_FB14_Msk AFIO_EXTICR4_EXTI14_PE CAN_F0R2_FB4_Msk CAN_IER_SLKIE CAN_BTR_SJW GPIO_CRL_CNF1_Pos I2C_SR1_SB CAN_F13R2_FB6_Msk DMA_CMAR_MA_Pos CAN_MCR_ABOM_Pos GPIO_BRR_BR11_Pos PWR_CSR_PVDO_Msk USART_SR_FE_Msk ADC_CR1_JAUTO_Msk BKP_DR4_D CAN_RDT0R_TIME_Msk CAN_TSR_TERR0_Pos SDIO_MASK_RXFIFOHFIE ADC_CR1_AWDCH_Msk CAN_FS1R_FSC7_Msk SPI_CRCPR_CRCPOLY CAN_F3R1_FB0_Msk CAN_F10R1_FB14_Msk RCC_CFGR_PLLMULL9_Pos GPIO_CRH_MODE12 SDIO_DCTRL_RWSTOP I2C_SR1_BERR
+syn keyword CTagsDefinedName SDIO_MASK_CMDRENDIE_Pos SDIO_RESP4_CARDSTATUS4_Msk CAN_F5R1_FB18_Pos RCC_CFGR_MCOSEL_1 CAN_F13R2_FB25_Msk RCC_APB2ENR_USART1EN_Pos USB_CNTR_SUSPM_Msk CAN_F6R2_FB1_Pos CAN_F5R1_FB30 GPIO_BSRR_BS4_Msk DMA_CCR_PL_0 TIM_EGR_TG_Pos CAN_F11R2_FB28_Pos USB_ADDR3_TX_ADDR3_TX_Msk CAN_F0R1_FB26_Msk AFIO_EXTICR4_EXTI15_PB_Pos CAN_F0R1_FB16_Msk ADC_SQR2_SQ11_4 CAN_F5R1_FB0 CAN_IER_FFIE0_Pos USB_DADDR_ADD_Msk CAN_F0R2_FB31 ADC_SMPR2_SMP9_Msk EXTI_EMR_MR16_Msk CAN_F1R2_FB7_Pos
+syn keyword CTagsDefinedName ADC_SMPR2_SMP6_Pos I2C_CCR_CCR_Pos CAN_BTR_TS2_Pos AFIO_MAPR_I2C1_REMAP EXTI_EMR_MR15_Pos TIM_SR_CC4IF AFIO_EXTICR2_EXTI7_PE CAN_F1R2_FB21 CAN_F4R1_FB14_Pos CAN_F11R2_FB22_Msk CAN_F3R2_FB21_Pos USB_COUNT6_RX_0_NUM_BLOCK_0_3 CAN_TI1R_RTR RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_TIM1RST_Msk PWM_CHANNEL_1 CAN_F11R1_FB24_Pos RTC_PRLL_PRL_Pos CAN_F4R1_FB6 CAN_F5R2_FB27_Msk IS_TIM_CC2_INSTANCE CAN_F11R1_FB27_Msk GPIO_IDR_IDR7_Msk CAN_F5R1_FB31 CAN_F0R2_FB27_Msk USB_EP7R_STAT_TX_Pos
+syn keyword CTagsDefinedName CAN_F0R1_FB20_Pos SDIO_STA_DCRCFAIL_Pos RTC_PRLL_PRL AFIO_EVCR_PORT_PA RCC_HSE_MIN DBGMCU_IDCODE_REV_ID_1 GPIO_CRL_MODE4 TIM_DIER_CC2IE_Pos EXTI_FTSR_TR8_Msk CAN_FM1R_FBM8_Pos RCC_CIR_PLLRDYC_Msk AFIO_EVCR_PIN_PX10_Msk I2C_OAR1_ADD0_Msk I2C_OAR1_ADD3 CAN_F7R1_FB7_Pos CAN_F8R1_FB16_Msk FLASH_USER_USER USB_COUNT0_TX_COUNT0_TX CAN_TDT1R_TIME_Pos EXTI_SWIER_SWIER2 USART_CR2_LINEN_Pos CAN_F2R1_FB10_Msk CAN_F1R1_FB9_Msk CAN_F10R2_FB13_Pos ADC_SQR1_SQ16_3 CAN_F13R1_FB23_Msk
+syn keyword CTagsDefinedName CAN_F7R2_FB31_Pos USB_EP_ISOCHRONOUS DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT CAN_F10R1_FB11 USB_EP5R_EP_KIND CAN_F3R2_FB12_Pos CAN_BTR_TS2_0 CAN_F0R1_FB29_Msk CAN_FFA1R_FFA11_Msk EXTI_IMR_IM USB_EP_CTR_RX CAN_F12R1_FB31_Msk SDIO_STA_SDIOIT_Msk SPI_SR_CHSIDE_Msk ADC_SMPR2_SMP8_0 USB_EP2R_EP_TYPE_Msk IWDG_SR_RVU CAN_F8R1_FB29_Msk AFIO_MAPR_I2C1_REMAP_Msk DMA_IFCR_CHTIF6_Msk CAN_F9R2_FB22_Pos USB_COUNT5_RX_COUNT5_RX_Msk CAN_RF1R_FULL1_Pos DMA_ISR_TCIF4 CAN_F0R2_FB27_Pos
+syn keyword CTagsDefinedName AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos CAN_F10R1_FB23_Pos I2C_SR1_TXE_Pos USB_ISTR_EP_ID_Msk CAN_F9R2_FB11_Msk TIM_SR_CC4IF_Pos IS_TIM_DMA_INSTANCE CAN_F9R2_FB13_Pos RCC_BDCR_LSEON_Pos WWDG_CFR_WDGTB_0 CAN_F13R2_FB30 CAN_F9R2_FB27 ADC_SMPR2_SMP9_1 AFIO_MAPR_USART3_REMAP_0 GPIO_CRH_CNF15_1 CAN_F13R1_FB11 EXTI1_IRQ_PRIORITY GPIO_BSRR_BR9 DBGMCU_CR_DBG_STOP CAN_F7R2_FB20_Msk SDIO_RESP0_CARDSTATUS0 USART_DR_DR EXTI_PR_PIF15 FLASH_USER_nUSER_Msk EXTI_IMR_IM13 PWR_CR_PVDE_Pos
+syn keyword CTagsDefinedName EXTI_FTSR_TR5 CAN_F3R2_FB8 TIM_DIER_TDE_Pos CAN_F11R1_FB1_Msk ADC_SQR3_SQ6_0 CAN_F2R1_FB10 SDIO_STA_CMDREND CAN_TDT1R_TGT_Msk TIM_CCMR1_IC1PSC_0 USB_EP1R_STAT_TX_Pos USB CAN_F2R1_FB2 USART1_BASE SDIO_DCTRL_DMAEN_Pos DMA_ISR_GIF3 CAN_F9R2_FB8_Pos CAN_MSR_RX_Pos EXTI_FTSR_TR11_Msk WWDG_CR_T_2 SDIO_ICR_CMDSENTC_Pos CAN_F6R1_FB25_Pos USART_CR1_PEIE_Msk CAN_F5R1_FB15 EXTI_SWIER_SWIER14 USB_EP1R_STAT_RX_0 CAN_F11R2_FB26_Msk ADC_SMPR2_SMP9_2 USB_EP1R_CTR_TX CAN_F11R2_FB5_Msk
+syn keyword CTagsDefinedName GPIO_BSRR_BR13_Msk CAN_F5R2_FB19_Pos CAN_F0R2_FB30_Msk CAN_F5R1_FB0_Msk CAN_F8R1_FB13 ADC_CR2_DMA TIM_CCMR2_IC4PSC_1 TIM_CR2_CCPC CAN_F3R1_FB24_Pos CAN_F11R1_FB6_Pos CRC_DR_DR_Msk __MPU_PRESENT GPIO_BRR_BR10 CAN_F4R1_FB20_Msk CAN_F12R2_FB21 CAN_F7R1_FB6 TIM1_UP_TIM10_IRQHandler CAN_F2R2_FB12_Pos EXTI_EMR_MR3_Msk USB_EP2R_STAT_RX_0 CAN_F2R2_FB13_Pos CAN_F9R1_FB12_Pos ADC1 RCC_CR_PLLRDY_Pos TIM_DCR_DBL_2 EXTI_EMR_MR7_Pos SDIO_ICR_CTIMEOUTC_Pos USB_ADDR0_TX_ADDR0_TX RCC_CFGR_MCO_0
+syn keyword CTagsDefinedName DMA_ISR_HTIF3_Msk USB_EP5R_STAT_TX CAN_F10R1_FB2 AFIO_EXTICR2_EXTI6_PF_Msk AFIO_EXTICR3_EXTI10_PC_Msk CAN_F7R2_FB4_Pos CAN_F12R1_FB28 CAN_F13R1_FB15_Pos CAN_F8R2_FB9_Msk CAN_F2R2_FB20_Pos CAN_F7R1_FB28_Pos CAN_TSR_ABRQ0 USB_EP_TX_DIS CAN_F13R1_FB8_Msk PIN_ALL SDIO_POWER_PWRCTRL TIM_CR2_OIS1N AFIO_EVCR_PIN_PX10 PWR_CSR_WUF_Msk CAN_F10R2_FB21_Msk CAN_F6R2_FB4 CAN_F12R2_FB6_Pos USB_DADDR_ADD3_Pos AFIO_EXTICR4_EXTI13_PD_Msk CAN_F7R2_FB7_Msk CAN_F9R1_FB13_Pos CAN_F6R1_FB7_Msk
+syn keyword CTagsDefinedName AFIO_EVCR_PIN_PX13_Pos CAN_F12R2_FB20 CAN_F12R1_FB4_Msk ADC_SR_JEOS SPI_SR_CHSIDE_Pos DBGMCU_CR_DBG_TIM2_STOP_Pos ADC_CR1_JAUTO_Pos TIM_CR2_MMS_1 USB_EP7R_EA_Msk ADC_SQR3_SQ5 ADC_JSQR_JSQ1_Pos USB_EP1R_CTR_TX_Msk CAN_FM1R_FBM2 CAN_F1R2_FB30_Msk EXTI_SWIER_SWIER17_Pos CAN_F8R2_FB4_Msk CAN_F11R1_FB28_Msk CAN_RF1R_FULL1_Msk SDIO_STA_RXACT_Pos ADC_SQR2_SQ10_2 AFIO_EXTICR1_EXTI0_PD_Pos CAN_F13R2_FB6_Pos SDIO_MASK_TXDAVLIE_Msk DMA_IFCR_CTEIF3 GPIO_BSRR_BR2_Msk CAN_F6R2_FB26_Msk
+syn keyword CTagsDefinedName CAN1_BASE SDIO_STA_CMDSENT_Msk ADC_SQR3_SQ2_4 CAN_F4R2_FB6_Pos EXTI_RTSR_RT2 TIM_CCMR2_OC4CE_Msk CAN_F11R2_FB24_Msk CAN_F9R2_FB26_Pos CAN_F11R1_FB12_Msk EXTI_EMR_MR0_Pos FLASH_OBR_IWDG_SW_Pos IS_TIM_COUNTER_MODE_SELECT_INSTANCE USB_EP6R_CTR_TX_Msk CAN_F1R2_FB26_Msk RCC_CFGR_PLLMULL10 WWDG_CR_T_1 EXTI_EMR_EM3 CAN_F8R2_FB12_Pos EXTI_RTSR_RT11 AFIO_EVCR_PIN_PX6_Msk SPI_CR1_SSM_Msk CAN_F1R2_FB15_Pos USB_COUNT0_RX_1_NUM_BLOCK_1 CAN_F12R2_FB28_Msk CAN_F7R1_FB29
+syn keyword CTagsDefinedName USB_COUNT7_RX_BLSIZE_Pos CAN_F10R1_FB7 CAN_F2R2_FB7_Pos CAN_F13R1_FB24_Msk EXTI_IMR_MR11_Pos CAN_RDT0R_TIME CAN_F5R2_FB14_Msk IS_TIM_REPETITION_COUNTER_INSTANCE EXTI_FTSR_TR18_Msk CAN_F2R1_FB24 ADC_HTR_HT_Pos USB_EP4R_STAT_TX_0 CAN_F3R2_FB17_Pos CAN_F6R2_FB16_Msk USB_COUNT4_TX_COUNT4_TX_Pos CAN_F8R2_FB9_Pos TIM_SR_COMIF_Msk RCC_CFGR_ADCPRE_DIV8 USB_COUNT7_RX_NUM_BLOCK_0 USB_DADDR_ADD4_Msk GPIO_CRL_MODE7_1 I2C_SR2_MSL_Msk CAN_F0R1_FB11_Pos EXTI_SWIER_SWIER8 CAN_F0R2_FB11
+syn keyword CTagsDefinedName CAN_F10R1_FB29_Msk CAN_F10R1_FB4_Msk TIM_CR2_OIS3_Msk IS_SMBUS_ALL_INSTANCE GPIO_BSRR_BR0_Msk CAN_IER_FMPIE1_Msk CAN_F11R1_FB16_Pos CAN_F3R1_FB22_Pos CAN_RI0R_EXID FLASH_CR_EOPIE SPI_CR1_SPE_Msk EXTI_EMR_EM1 DMA_IFCR_CTCIF6 AFIO_EXTICR3_EXTI10_PD_Msk ADC_SMPR1_SMP13 CAN_TDH0R_DATA6_Msk AFIO_EXTICR1_EXTI3_Msk RCC_CFGR_PLLMULL15_Msk CAN_F13R1_FB18 EXTI_PR_PIF18 FLASH_DATA1_DATA1_Pos CAN_F3R2_FB12_Msk GPIO_CRH_MODE15_Msk CAN_F13R2_FB29 CAN_F7R1_FB10_Pos CAN_F11R1_FB1 CAN_F8R1_FB4
+syn keyword CTagsDefinedName AFIO_MAPR_USART1_REMAP_Pos CAN_FM1R_FBM4_Msk CAN_F4R1_FB13_Msk GPIO_CRL_CNF7 GPIO_ODR_ODR12 TIM_CR1_CKD_0 CAN_MCR_INRQ_Msk SDIO_STA_TXFIFOE_Msk TIM_CCER_CC2NE_Pos GPIO_ODR_ODR0_Msk EXTI_FTSR_TR6_Msk RCC_APB2ENR_ADC1EN GPIO_BRR_BR4 CAN_F5R2_FB12_Pos RCC_BDCR_LSEBYP ADC_CR2_CONT_Pos SDIO CAN_F2R2_FB21_Msk CAN_F8R1_FB28_Pos CAN_F5R2_FB10_Msk CAN_F7R2_FB25_Msk AFIO_MAPR_CAN_REMAP_REMAP2_Pos EXTI_RTSR_TR9_Msk CAN_F5R2_FB1 USB_COUNT4_RX_NUM_BLOCK_4 CAN_F11R1_FB12 CAN_F13R1_FB27_Pos
+syn keyword CTagsDefinedName CAN_F6R1_FB1 CAN_MSR_TXM_Msk FLASH_CR_OPTPG_Pos EXTI_EMR_EM2 CAN_F1R1_FB7_Pos GPIO_CRL_CNF_Pos EXTI_FTSR_TR15_Pos ADC_CR1_AWDCH_4 GPIO_CRL_MODE0_Pos CAN_IER_FFIE1 PWR_CR_PLS_LEV2 RCC_CFGR_PPRE1_DIV4 CAN_F7R1_FB25_Msk USB_FNR_FN_Pos CAN_F12R1_FB23 USART_CR1_M_Msk AFIO_EVCR_PIN_PX12 CAN_F12R1_FB9_Pos USB_COUNT0_TX_COUNT0_TX_Pos CAN_FS1R_FSC3_Msk CAN_F3R1_FB7_Msk CAN_F0R2_FB17_Msk RCC_CIR_LSIRDYF_Msk CAN_F1R2_FB23_Msk GPIO_IDR_IDR6_Pos EXTI_FTSR_FT15 CAN_F3R1_FB24_Msk
+syn keyword CTagsDefinedName ADC_SQR1_SQ15_3 CAN_F13R1_FB5 RCC_CFGR_PLLMULL5_Pos RCC_CR_HSITRIM DMA_CCR_PL_Msk CAN_F11R1_FB2_Pos ADC_SMPR1_SMP16_1 PIN_OPT_AF9 I2C_OAR1_ADDMODE_Msk CAN_ESR_LEC_0 TIM_CR1_OPM RCC_CFGR_PPRE1_DIV16 RCC_CFGR_HPRE_DIV_16 USART_GTPR_PSC_1 USB_EP2R_SETUP_Msk AFIO_EXTICR3_EXTI8_PF_Pos ADC1_IRQHandler CAN_F2R2_FB17_Pos FLASH_WRP1_nWRP1_Pos CAN_RDH0R_DATA6_Pos AFIO_EXTICR3_EXTI11_PB_Msk CAN_FS1R_FSC11 CAN_F11R2_FB7_Pos SPI_CR2_SSOE_Pos GPIO_CRL_CNF7_1 USB_EP0R_EA
+syn keyword CTagsDefinedName DBGMCU_CR_DBG_TIM3_STOP_Msk CAN_F6R1_FB1_Msk RTC_DIVL_RTC_DIV ADC_JSQR_JSQ2_1 CAN_F13R1_FB3 CAN_F13R2_FB4 CAN_F10R2_FB18_Msk CAN_F5R2_FB4 DBGMCU_CR_DBG_TIM3_STOP CAN_F9R2_FB16_Msk CAN_F4R2_FB1 CAN_F4R2_FB23_Msk USB_COUNT4_RX_COUNT4_RX TIM_RCR_REP GPIO_BSRR_BR7_Pos GPIO_CRH_CNF15 EXTI_SWIER_SWIER8_Pos CAN_F10R2_FB28 CAN_F3R2_FB6_Pos CAN_F1R2_FB21_Msk DMA_IFCR_CTCIF7_Msk CAN_F7R1_FB28 ADC_SQR2_SQ7_0 CAN_RF0R_RFOM0 GPIO_CRH_CNF10_1 CAN_F5R2_FB7 EXTI_SWIER_SWI4
+syn keyword CTagsDefinedName SDIO_CLKCR_HWFC_EN_Pos CAN_F0R1_FB10_Msk CAN_F1R2_FB2_Pos CAN_F1R1_FB0_Pos USB_DADDR_EF_Msk ADC_JSQR_JSQ2_2 CAN_F10R2_FB25_Msk USB_EP1R_STAT_TX_Msk CAN_TDT0R_DLC GPIO_BRR_BR5_Pos CAN_F0R2_FB12 EXTI_RTSR_TR16_Msk FLASH_WRP3_nWRP3 IS_UART_DMA_INSTANCE USB_COUNT1_RX_1_NUM_BLOCK_1 USB_COUNT6_RX_0_COUNT6_RX_0 USB_COUNT5_RX_BLSIZE USART_CR3_CTSE_Msk USB_EP2R_EP_KIND_Pos EXTI_EMR_MR12_Pos CAN_F8R1_FB3_Pos ADC_JSQR_JSQ1_2 CAN_F10R2_FB27_Pos EXTI_EMR_EM10 EXTI_SWIER_SWIER7
+syn keyword CTagsDefinedName SDIO_ICR_CMDRENDC_Msk I2C_SR2_GENCALL_Pos CAN_F6R1_FB7 CAN_IER_EWGIE AFIO_MAPR_TIM1_REMAP_Pos DMA_IFCR_CTCIF1_Pos ADC_JSQR_JSQ1_Msk CAN_F0R2_FB2 I2C_CR1_ENARP_Msk TIM_CR1_OPM_Msk USB_ADDR6_RX_ADDR6_RX_Pos CAN_F2R1_FB29_Msk EXTI_EMR_MR3_Pos EXTI_PR_PIF3 FLASH_CR_ERRIE_Pos CAN_F10R1_FB17_Msk CAN_F7R1_FB0 CAN_MCR_TXFP USB_EP3R_STAT_RX_Msk CAN_F2R2_FB4_Pos CAN_F4R2_FB16_Pos CAN_TDH2R_DATA5 EXTI3_IRQ_PRIORITY USB_EP0R_CTR_TX_Msk USB_EP7R_STAT_TX_0 AFIO_EXTICR1_EXTI1_PB_Msk
+syn keyword CTagsDefinedName CAN_F5R1_FB17_Pos DMA_ISR_GIF6 TIM_CCR1_CCR1 ADC_CR2_RSTCAL_Msk CAN_FA1R_FACT11_Msk RCC_CFGR_HPRE_DIV_512 EXTI_IMR_MR8 ADC_CR1_EOSIE_Pos CAN_F8R2_FB5_Pos CAN_FA1R_FACT2 GPIO_BRR_BR1 CAN_F5R1_FB10_Pos RCC_APB1ENR_I2C1EN_Pos CAN_F8R2_FB24_Msk ADC_JSQR_JSQ1 FLASH_OBR_RDPRT_Pos CAN_F7R1_FB3 GPIO_CRL_CNF AFIO_EXTICR4_EXTI14_PB CAN_F10R1_FB30_Pos USB_COUNT7_RX_COUNT7_RX USB_CNTR_FSUSP_Msk CAN_F12R2_FB19_Pos RCC_CSR_SFTRSTF FLASH_OBR_RDPRT_Msk AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk
+syn keyword CTagsDefinedName USB_COUNT6_RX_1_NUM_BLOCK_1 AFIO_EVCR_PORT_PC_Pos USB_COUNT4_RX_BLSIZE_Pos USB_EP6R_CTR_RX_Pos USB_EP6R_STAT_TX AFIO_MAPR_TIM1_REMAP_NOREMAP CAN_F4R1_FB29_Pos FLASH_OBR_RDPRT GPIO_LCKR_LCK12 CAN_F1R1_FB23_Msk USART_CR2_LBDIE CAN_F10R1_FB14_Pos WWDG_CFR_WDGTB CAN_F13R2_FB23 TIM_CR2_MMS_0 __Vendor_SysTickConfig EXTI_EMR_MR15 DMA_CCR_PSIZE_0 GPIO_CRH_MODE14 CAN_F12R1_FB11 CAN_RI1R_EXID_Msk GPIO_LCKR_LCK5_Pos CAN_FS1R_FSC_Pos WWDG_CR_WDGA_Pos CAN_F9R2_FB7_Pos CAN_F6R2_FB5
+syn keyword CTagsDefinedName DBGMCU_BASE GPIO_IDR_IDR0_Msk CAN_F5R2_FB17 CAN_F6R2_FB30_Msk EXTI_SWIER_SWIER1_Msk ADC_SR_JEOC DMA_ISR_GIF3_Msk RCC_CSR_PORRSTF_Pos AFIO_EXTICR3_EXTI10_Pos CAN_F11R1_FB16_Msk ADC_JSQR_JSQ4_4 CAN_F7R2_FB15 CAN_F13R1_FB13 CAN_F11R1_FB3_Pos CAN_F5R2_FB31_Msk RCC_APB1ENR_USART2EN_Msk USB_COUNT0_RX_0_NUM_BLOCK_0_1 CAN_FMR_CAN2SB_Pos CAN_F1R2_FB11_Msk CAN_F13R1_FB16 CAN_F1R2_FB29 USART_CR2_STOP_1 CAN_F0R1_FB0_Pos I2C2 I2C_SR2_SMBDEFAULT_Pos AFIO_EXTICR1_EXTI0_Msk CAN_F4R1_FB17_Pos
+syn keyword CTagsDefinedName DMA_ISR_GIF4 DMA1_BASE CAN_F7R2_FB28_Pos TIM_CCMR1_OC1M_Msk CAN_F2R2_FB27_Pos USB_EP5R_CTR_RX_Msk USB_EP4R_CTR_RX_Msk I2C_OAR1_ADD9_Pos CAN_F2R2_FB20 GPIO_IDR_IDR3_Pos SDIO_CLKCR_CLKEN CAN_F0R1_FB27_Msk USART_CR1_RXNEIE CAN_F6R2_FB27 CAN_F11R2_FB29_Pos RCC_APB1ENR_I2C2EN_Pos SDIO_CLKCR_CLKDIV_Pos AFIO_EXTICR1_EXTI3_PD CAN_F2R1_FB5_Pos CAN_F1R2_FB17_Pos CAN_F13R2_FB11_Msk EXTI_IMR_MR0_Msk ADC_JOFR4_JOFFSET4 CAN_BTR_TS2_1 ADC_JOFR3_JOFFSET3_Msk USB_ISTR_EP_ID USB_CNTR_RESETM_Pos
+syn keyword CTagsDefinedName USB_EP4R_CTR_TX_Msk CAN_F9R2_FB27_Pos CAN_F5R2_FB18 CAN_F11R1_FB5 CAN_F1R2_FB12 CAN_F5R1_FB1 CAN_F5R1_FB5_Msk CAN_F10R2_FB15_Pos CAN_F11R1_FB11 CAN_F7R2_FB1 AFIO_EXTICR4_EXTI14_PB_Pos CAN_MSR_WKUI SDIO_STA_CTIMEOUT RCC_CFGR_PLLMULL_3 USB_COUNT3_RX_1_NUM_BLOCK_1_0 AFIO_EVCR_PORT_PE_Pos CAN_F6R2_FB15_Msk USB_COUNT2_RX_0_NUM_BLOCK_0_2 USB_EP3R_DTOG_RX AFIO_MAPR_TIM2_REMAP_Pos AFIO_EVCR_PIN_PX14_Pos SDIO_STA_RXDAVL CAN_F1R1_FB12_Pos GPIO_BRR_BR14_Msk CAN_F8R2_FB27_Msk
+syn keyword CTagsDefinedName CAN_F4R2_FB1_Msk CAN_FA1R_FACT2_Pos GPIO_CRH_MODE10_Msk EXTI_IMR_MR7_Pos AFIO_EXTICR3_EXTI10_PE FLASH_CR_MER_Msk AFIO_EXTICR3_EXTI8_PD CAN_FA1R_FACT3 CAN_F0R2_FB13 CAN_F8R2_FB13_Msk FLASH_AR_FAR_Pos RCC_CIR_HSERDYF_Msk RTC_CRL_RTOFF I2C_SR2_GENCALL TIM_CCER_CC3E_Msk AFIO_EVCR_PIN_PX5 GPIO_LCKR_LCK8_Pos CAN_F2R2_FB29 WWDG_CR_WDGA_Msk CAN_F1R1_FB4_Pos CAN_IER_BOFIE_Pos GPIOC_BASE CAN_F2R2_FB9_Msk ADC_SQR2_SQ9_Pos USB_EP2R_SETUP CAN_F0R2_FB0_Pos AFIO_EVCR_PIN_PX10_Pos
+syn keyword CTagsDefinedName CAN_F13R1_FB17 USB_EP1R_EA_Msk USB_COUNT2_RX_1_COUNT2_RX_1 SDIO_CMD_WAITINT_Pos CAN_F13R2_FB22_Pos ADC2_BASE AFIO_EXTICR2_EXTI6_PD_Pos TIM_CCMR2_OC4M_Pos WWDG_CR_T6 BKP_CR_TPAL_Msk FLASH_KEY2 ADC_SQR1_SQ13_1 CAN_F12R2_FB13_Msk TIM_CCMR1_IC2F RCC_APB1RSTR_CAN1RST FLASH_SR_BSY_Pos CAN_F4R2_FB8_Pos CAN_F10R2_FB18 I2C_CR2_DMAEN_Msk SPI_CR1_BIDIOE CAN_F5R2_FB24_Msk USB_COUNT2_TX_0_COUNT2_TX_0 SDIO_ICR_CCRCFAILC_Pos ADC_JSQR_JSQ2_Msk AFIO_MAPR_TIM1_REMAP_Msk CAN_F0R1_FB31_Pos
+syn keyword CTagsDefinedName DMA_IFCR_CHTIF4_Msk FLASH_WRPR_WRP_Msk SDIO_STA_RXFIFOE ADC_SQR2_SQ11_3 CAN_F0R1_FB3_Msk ADC_SMPR1_SMP14_Pos USB_DADDR_ADD4_Pos RCC_CIR_HSERDYF CAN_TSR_LOW1_Pos GPIO_CRL_MODE3_0 USB_EP7R_STAT_RX_Pos CAN_F4R2_FB15_Msk CAN_F13R2_FB2 CAN_F5R2_FB9_Pos USB_EP2R_STAT_TX_1 PIN_12 USART_CR2_CPHA_Pos CAN_F10R1_FB7_Pos CAN_F5R1_FB26_Msk TIM_CCMR2_IC4F CAN_F10R2_FB19_Pos CAN_F10R2_FB7 CAN_F7R2_FB13_Msk USB_ISTR_WKUP CAN_F9R2_FB29 EXTI_EMR_MR8 GPIO_CRL_CNF1_Msk ADC_SQR1_L_Pos
+syn keyword CTagsDefinedName FLASH_WRP2_nWRP2_Msk SDIO_CLKCR_BYPASS FLASH_USER_USER_Pos CAN_F2R2_FB19_Pos CAN_F13R1_FB27_Msk CAN_F4R2_FB14_Pos GPIO_BSRR_BS13_Pos GPIO_ODR_ODR7_Pos DBGMCU_IDCODE_REV_ID TIM1_BRK_TIM9_IRQn CAN_F5R2_FB26 I2C_SR2_SMBDEFAULT USB_ADDR5_RX_ADDR5_RX_Pos CAN_FM1R_FBM13_Pos CAN_F9R2_FB18_Pos CAN_F0R2_FB30_Pos SDIO_MASK_TXACTIE_Msk TIM_BDTR_MOE_Pos CAN_F11R2_FB29_Msk BKP_DR8_D CAN_IER_WKUIE_Msk ADC_CR1_AWDEN PIN_OPT_AF11 SDIO_MASK_RXFIFOFIE_Pos CAN_F1R2_FB5_Msk CAN_F6R1_FB19_Msk
+syn keyword CTagsDefinedName ADC_SQR1_SQ14_4 DMA_CCR_MEM2MEM I2C_CR2_ITEVTEN_Pos ADC_SQR1_SQ16_Msk RCC_CIR_PLLRDYIE_Pos CAN_F11R2_FB14 AFIO_MAPR_USART3_REMAP_FULLREMAP CAN_F11R2_FB30_Pos FLASH_USER_nUSER USB_COUNT6_RX_0_NUM_BLOCK_0_4 EXTI_SWIER_SWIER13 CAN_F3R1_FB28_Msk GPIO_LCKR_LCK11 ADC_JSQR_JSQ4_3 CAN_F5R1_FB14_Pos CAN_F3R2_FB17_Msk USB_EP4R_EP_KIND_Pos CAN_F12R2_FB14_Pos CAN_F2R1_FB9 USB_EP7R_STAT_TX USB_BASE RCC_CIR_HSERDYF_Pos CAN_F13R2_FB20_Pos CAN_RDT0R_DLC_Pos SDIO_STA_TXFIFOE CAN_F10R2_FB14_Pos
+syn keyword CTagsDefinedName CAN_F1R2_FB4 TIM_SMCR_TS_Pos TIM_CCMR2_CC3S_Pos CAN_F0R2_FB10_Msk CAN_F12R1_FB15_Msk SDIO_MASK_TXFIFOEIE_Pos CAN_FM1R_FBM3_Pos TIM_CR1_URS CAN_F12R1_FB21 TIM_CR2_MMS_Pos CAN_FM1R_FBM6_Pos DMA_IFCR_CGIF7_Pos RTC_DIVH_RTC_DIV_Msk CAN_FM1R_FBM_Msk TIM_SR_CC1OF_Pos CAN_FS1R_FSC_Msk CAN_F11R1_FB28_Pos GPIO_ODR_ODR14 SDIO_DCTRL_DBLOCKSIZE_3 AFIO_EXTICR2_EXTI4 CAN_F4R1_FB25_Pos SDIO_STA_TXFIFOHE_Pos GPIO_CRL_CNF3_1 TIM_SR_CC3OF TIM_CCMR2_CC3S CAN_F13R1_FB9_Pos I2C_CR1_PE_Msk
+syn keyword CTagsDefinedName RCC_APB1RSTR_BKPRST TIM_DCR_DBL_Pos CAN_F8R1_FB11_Pos CAN_F6R1_FB9_Msk CAN_F3R2_FB24_Msk I2C_SR1_SMBALERT_Pos CAN_F13R2_FB3_Pos CAN_F9R1_FB7_Pos USB_CNTR_FSUSP CAN_TDH1R_DATA5_Pos CAN_F8R1_FB7 TIM_RCR_REP_Msk CAN_TI1R_EXID USB_COUNT3_RX_0_NUM_BLOCK_0_1 CAN_F12R1_FB18_Msk CAN_F5R2_FB20_Msk SDIO_MASK_RXFIFOEIE_Pos CAN_F3R1_FB15_Pos TIM_SMCR_ETPS_1 RCC_APB2ENR_TIM1EN_Pos CAN_F13R1_FB12_Msk CAN_F13R2_FB16_Pos CAN_F11R2_FB30_Msk CAN_F2R2_FB8_Pos AFIO_EXTICR3_EXTI9_PB_Pos
+syn keyword CTagsDefinedName CAN_F0R2_FB11_Msk CAN_F5R2_FB1_Msk CAN_F7R2_FB28 I2C_OAR1_ADD4_Pos I2C_SR2_BUSY USB_COUNT1_TX_COUNT1_TX ADC_JDR2_JDATA CAN_F13R1_FB12_Pos RCC_CSR_LSIRDY_Pos CAN_F1R1_FB7_Msk TIM_CCMR1_OC1CE USB_COUNT1_RX_NUM_BLOCK_1 CAN_F1R1_FB0_Msk USB_EP6R_EP_TYPE_Msk RCC_CSR_IWDGRSTF_Msk SDIO_MASK_RXOVERRIE_Pos CAN_F7R1_FB9_Pos CAN_F7R2_FB6_Pos CAN_F1R2_FB3 SDIO_ICR_RXOVERRC USB_COUNT5_RX_0_BLSIZE_0 RCC_CFGR_PLLXTPRE_HSE_DIV2 SDIO_CMD_CMDINDEX WWDG_CFR_WDGTB1 ADC_CR1_JEOSIE_Msk CAN_F6R1_FB23
+syn keyword CTagsDefinedName CAN_MCR_RFLM_Pos AFIO_EXTICR3_EXTI11_Msk AFIO_EXTICR3_EXTI11_PA GPIO_CRH_CNF12_1 CAN_F8R1_FB24 CAN_F9R1_FB2 CAN_F7R1_FB0_Pos CAN_F1R1_FB18_Pos RCC_APB2RSTR_IOPCRST_Msk USB_EP4R_EP_TYPE CAN_F1R2_FB8_Pos CAN_F11R2_FB23 CAN_F6R1_FB18 WWDG_CR_T4 CAN_F9R2_FB5 ADC_SMPR1_SMP10_1 EXTI_PR_PIF9 IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE USART_SR_CTS CAN_FA1R_FACT12_Msk CAN_F12R1_FB18_Pos CAN_RDH0R_DATA7_Msk RCC_CFGR_PLLMULL7_Pos CAN_F4R1_FB2_Pos CAN_RDH0R_DATA6_Msk CAN_F13R1_FB28_Pos
+syn keyword CTagsDefinedName CAN_F3R1_FB22_Msk TIM_DIER_COMDE_Msk AFIO_EVCR_PORT_2 SDIO_STA_TXFIFOHE GPIO_IDR_IDR13_Msk SDIO_MASK_DCRCFAILIE_Pos CAN_F11R1_FB9 CAN_F12R1_FB7_Pos GPIO_CRH_MODE12_Pos USB_EP2R_DTOG_TX_Pos GPIO_ODR_ODR5 USB_EP3R_STAT_RX CAN_F2R1_FB1_Pos TIM_SMCR_ETF_Msk USB_COUNT1_RX_NUM_BLOCK_2 GPIO_CRL_MODE_Pos SDIO_ICR_DTIMEOUTC CAN_F3R2_FB5_Pos EXTI_IMR_MR18 CAN_F6R2_FB1_Msk DMA_ISR_GIF2 RCC_CFGR_SWS_0 AFIO_MAPR_TIM3_REMAP_0 CAN_MCR_AWUM_Msk CAN_F1R2_FB6_Msk CAN_F11R2_FB14_Msk CAN_F4R2_FB28
+syn keyword CTagsDefinedName USB_EP5R_EA_Msk CAN_TI0R_TXRQ AFIO_EXTICR4_EXTI15 CAN_F13R2_FB17_Msk ADC_SMPR2_SMP5_0 CAN_F4R2_FB25 GPIO_CRL_CNF6 ADC_SQR3_SQ5_4 EXTI_IMR_IM10 USART_CR2_LBDL_Msk CAN_F8R1_FB19_Msk USB_EP_DTOG_TX_Msk CAN_F5R2_FB25_Msk CAN_F8R2_FB18 SPI_CR2_RXDMAEN_Pos EXTI_EMR_MR7_Msk USB_COUNT2_RX_NUM_BLOCK_Msk AFIO_EXTICR3_EXTI10_PE_Msk DMA_ISR_TEIF2_Pos WWDG_CFR_W_2 CAN_F6R1_FB2_Pos CAN_F1R2_FB28_Pos CAN_F10R2_FB19 CAN_BTR_SJW_1 CAN_F13R1_FB26 CAN_F4R2_FB9_Pos AFIO_EXTICR3_EXTI9_PG_Msk
+syn keyword CTagsDefinedName SPI_SR_MODF DBGMCU_IDCODE_REV_ID_4 RCC_CFGR_PLLMULL12_Msk CAN_F3R1_FB12_Pos EXTI_IMR_MR2 GPIO_BSRR_BR1 CAN_BTR_SILM_Pos USB_EP_CTR_TX_Pos USB_EP4R_CTR_RX CAN_F4R1_FB5_Msk AFIO_EVCR_PIN_PX15 CAN_F0R1_FB1_Pos GPIO_CRL_MODE7_0 CAN_IER_SLKIE_Pos CAN_ESR_LEC I2C_SR1_TIMEOUT_Pos I2C_CR2_DMAEN CAN_F2R1_FB27 EXTI_RTSR_TR9 CAN_F4R1_FB6_Pos TIM_DIER_CC1DE_Msk USB_EP2R_EP_TYPE_Pos USB_EP3R_EA USB_EP4R_STAT_RX_0 CAN_F4R1_FB3 TIM_CCMR2_CC4S_1 EXTI_EMR_MR14_Pos TIM_SMCR_TS_Msk CAN_ESR_TEC
+syn keyword CTagsDefinedName CAN_F7R1_FB14_Pos USB_COUNT2_RX_0_NUM_BLOCK_0 CAN_F2R1_FB21 EXTI_EMR_MR4_Msk CAN_F1R1_FB28_Msk AFIO_EXTICR4_EXTI13_PC RCC_CFGR_PLLMULL_1 CAN_F2R2_FB13_Msk FLASH_WRP0_nWRP0 CAN_F2R1_FB0 CAN_MCR_ABOM_Msk CAN_F5R1_FB16_Pos TIM_CCER_CC1NE CAN_TDH1R_DATA5_Msk GPIO_BSRR_BR4 CAN_F0R1_FB6 CAN_FM1R_FBM9_Msk SDIO_STA_TXFIFOF ADC_SR_JSTRT_Pos CAN_F7R2_FB17 USB_EP2R_DTOG_TX_Msk CAN_F9R2_FB29_Msk AFIO_EXTICR2_EXTI4_PF CAN_F7R1_FB4_Pos CAN_F8R1_FB15_Msk USB_EP_TX_VALID CAN_F0R2_FB3_Pos
+syn keyword CTagsDefinedName CAN_F9R1_FB26 DMA_CPAR_PA_Pos CAN_F5R2_FB16_Pos TIM_CCER_CC4E_Msk RTC_CRL_RSF_Pos RCC_CFGR_PLLXTPRE_Msk PIN_OPT_OUTPUT_OPENDRAIN CAN_F8R2_FB10_Pos GPIO_CRH_MODE11_0 USB_COUNT0_RX_BLSIZE CAN_F0R1_FB10 USART_CR3_RTSE_Pos USB_EP0R_STAT_TX_1 RCC_CFGR_SW_0 CAN_F0R1_FB9_Msk USB_COUNT3_RX_BLSIZE_Msk USB_COUNT2_RX_1_BLSIZE_1 CAN_TSR_LOW_Pos CAN_F2R2_FB22_Pos CAN_F4R1_FB24_Pos CAN_F7R2_FB0_Pos ADC_SMPR2_SMP0_0 CAN_F8R1_FB26_Msk CAN_BTR_TS1 CAN_FS1R_FSC6_Pos CAN_F6R2_FB20_Msk
+syn keyword CTagsDefinedName CAN_F3R2_FB2_Msk CAN_F4R1_FB16_Msk CAN_F12R2_FB11_Msk CAN_F11R2_FB17_Pos CAN_F8R2_FB22 CAN_F9R1_FB25_Msk USB_EP5R_DTOG_TX_Pos GPIO_BSRR_BS8 USB_CNTR_SUSPM_Pos DMA_ISR_GIF1_Pos ADC_SQR2_SQ11_2 CAN_RI1R_IDE CAN_F11R1_FB26 USB_ISTR_SOF_Pos USB_ADDR4_RX_ADDR4_RX_Msk CAN_F11R2_FB6 CAN_F8R2_FB12 SPI_CR1_SPE GPIO_LCKR_LCK13 CAN_F13R2_FB7_Pos RCC_CFGR_PLLMULL7 ADC_SQR3_SQ3 USB_EP_TYPE_MASK_Msk AFIO_EXTICR4_EXTI15_PG_Msk CAN_F6R1_FB3_Msk CAN_TDL1R_DATA0_Pos ADC_SQR3_SQ3_4
+syn keyword CTagsDefinedName CAN_F0R2_FB1_Pos USB_BTABLE_BTABLE CAN_F7R2_FB4_Msk __STM32F1XX_H TIM_SMCR_SMS_Pos CAN_F0R1_FB20_Msk AFIO_EXTICR2_EXTI6_PD CAN_TSR_ALST1 AFIO_MAPR_TIM1_REMAP CAN_F7R2_FB31 CAN_IER_WKUIE CAN_F9R2_FB23_Pos IS_UART_LIN_INSTANCE ADC_JSQR_JSQ2_0 CAN_F10R1_FB29_Pos CAN_F13R2_FB12_Pos I2C_SR1_ADDR_Pos RCC_CFGR_ADCPRE_DIV6 USB_COUNT4_RX_0_NUM_BLOCK_0 CAN_F0R2_FB14_Msk CAN_F7R2_FB11_Msk CAN_TDH0R_DATA7 RCC_CFGR_PLLMULL12_Pos CAN_F13R1_FB16_Pos CAN_F5R1_FB27_Msk I2C_CCR_FS
+syn keyword CTagsDefinedName DMA_IFCR_CTEIF4_Pos ADC_SMPR1_SMP11_Msk RCC_CFGR_PPRE2_1 RCC_APB1RSTR_USART3RST_Msk AFIO_EXTICR1_EXTI2_PB EXTI4_IRQ_PRIORITY DMA_IFCR_CTCIF7_Pos CAN_F4R2_FB0_Msk CAN_F7R2_FB14_Pos RTC_CRH_SECIE_Msk USART_CR1_UE CAN_F5R1_FB8 WWDG_CR_T_0 SDIO_CMD_WAITPEND_Msk AFIO_EXTICR3_EXTI8_PC_Pos EXTI_RTSR_RT18 EXTI_SWIER_SWIER17 CAN_F6R2_FB3_Msk GPIO_CRL_CNF5_0 EXTI_EMR_EM12 CAN_F0R2_FB29_Msk RCC_CFGR_HPRE_DIV_4 USB_LP_IRQHandler I2C_CR2_ITERREN_Pos CAN_FFA1R_FFA10_Pos CAN_F0R2_FB9_Msk
+syn keyword CTagsDefinedName ADC_SQR2_SQ9_4 USB_COUNT6_RX_0_NUM_BLOCK_0_2 USB_EP0R_CTR_TX GPIO_CRH_MODE14_Msk CAN_F13R1_FB0_Pos CAN_F11R2_FB11 CAN_F9R2_FB23 USART_SR_NE_Pos CAN_F10R1_FB28_Msk CAN_F10R1_FB16_Msk GPIO_BRR_BR2 CAN_F3R1_FB2_Msk RCC_APB2ENR_TIM1EN SDIO_DCTRL_DTEN_Msk USB_EP5R_SETUP_Msk TIM_BDTR_BKP_Pos EXTI_RTSR_TR8_Pos TIM_SMCR_ETF_Pos USART_GTPR_PSC_Pos CAN_F13R1_FB17_Msk BKP_DR10_D CAN_RI1R_STID_Msk CAN_F10R2_FB1_Msk AFIO_EVCR_PIN_PX15_Msk TIM_DCR_DBA CRC_IDR_IDR_Msk CAN_FS1R_FSC6
+syn keyword CTagsDefinedName USART_SR_RXNE_Pos CAN_F8R2_FB26_Pos SDIO_MASK_SDIOITIE USB_EP4R_EP_TYPE_0 GPIO_CRL_MODE1_Pos CAN_F10R2_FB12_Pos BKP_DR4_D_Msk CAN_F0R2_FB0 EXTI_FTSR_TR3 CAN_F13R2_FB5_Msk CAN_FFA1R_FFA3_Msk USB_EP6R_EP_KIND_Pos CAN_F10R1_FB25 SPI_CR2_ERRIE_Pos CAN_F0R1_FB25 CAN_F7R2_FB5_Msk CAN_TSR_TERR2 EXTI_RTSR_TR3 CAN_F7R2_FB23 ADC_SR_STRT DMA_CCR_PSIZE_Msk DMA_IFCR_CHTIF2_Msk SPI_CR2_TXDMAEN SDIO_DCTRL_DMAEN RCC_APB2ENR_ADC2EN_Msk CAN_F2R2_FB11 AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos
+syn keyword CTagsDefinedName CAN_F8R1_FB13_Pos RCC_APB1ENR_USART2EN_Pos RCC_CSR_IWDGRSTF AFIO_EXTICR1_EXTI1_Msk CAN_F3R1_FB14_Msk FLASH_WRP2_WRP2 USB_EP2R_EP_TYPE_1 CAN_F12R1_FB30 FLASH_CR_OPTWRE_Pos CAN_F12R1_FB22_Msk USB_EP6R_STAT_RX_Pos USB_COUNT6_RX_1_NUM_BLOCK_1_2 SDIO_ICR_CEATAENDC PIN_OPT_AF12 CAN_F1R1_FB24 CAN_F1R1_FB23 EXTI_PR_PR1_Msk DMA_CPAR_PA TIM_SR_CC2OF CAN_F7R2_FB7_Pos CAN_F7R2_FB15_Msk CAN_IER_ERRIE_Pos GPIO_IDR_IDR14_Msk SDIO_CLKCR_CLKEN_Msk SDIO_ICR_DCRCFAILC_Pos CAN_F1R1_FB2_Pos
+syn keyword CTagsDefinedName CAN_F1R1_FB5_Pos DMA_ISR_TCIF6_Msk TIM_BDTR_LOCK_0 USB_EP1R_EP_KIND USB_COUNT5_TX_COUNT5_TX_Msk CAN_F6R1_FB30 CRC_DR_DR CAN_F7R2_FB18_Msk AFIO_EXTICR4_EXTI15_PD_Msk CAN_F4R1_FB13 ADC_JDR3_JDATA_Pos CAN_F12R2_FB27_Msk USB_COUNT1_RX_1_NUM_BLOCK_1_3 CAN_F10R1_FB5_Pos AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos IS_TIM_BREAK_INSTANCE FLASH_CR_OPTER_Pos CAN_F6R2_FB10_Pos CAN_FM1R_FBM5_Msk RCC_APB1ENR_USBEN_Msk USB_EP_DTOG_TX_Pos TIM_CR2_MMS_2 DMA_ISR_TCIF1 CAN_F3R1_FB3 AFIO_EVCR_PIN_2
+syn keyword CTagsDefinedName CAN_F2R2_FB5 CAN_F6R2_FB26_Pos CAN_F13R2_FB28_Pos I2C_OAR1_ADD5 DBGMCU_CR_DBG_CAN1_STOP GPIO_ODR_ODR6_Pos CAN_F9R1_FB1 DMA1_Channel3_BASE AFIO_EXTICR2_EXTI7 CAN_F13R2_FB10 CAN_FFA1R_FFA2_Pos FLASH_CR_EOPIE_Msk CAN_RDL1R_DATA1_Pos CAN_F5R2_FB27 ADC_JOFR4_JOFFSET4_Msk CAN_F3R2_FB9_Msk CAN_F0R2_FB31_Msk TIM3_BASE TIM_CCMR1_CC1S_0 CAN_F4R2_FB22 ADC_DR_ADC2DATA_Msk CAN_FFA1R_FFA12_Msk CAN_F3R2_FB9_Pos I2C_SR1_OVR_Msk RCC_BDCR_LSERDY_Pos FLASH_ACR_LATENCY_2 OTG_FS_WKUP_IRQHandler
+syn keyword CTagsDefinedName CAN_F5R1_FB4_Msk EXTI_PR_PR1_Pos GPIO_IDR_IDR12_Msk CAN_F4R1_FB26_Msk CAN_F2R1_FB8_Msk AFIO_EXTICR3_EXTI9_PD VECT_TAB_OFFSET FLASH_DATA0_nDATA0 EXTI_SWIER_SWIER6 CAN_F10R2_FB21 CAN_ESR_EPVF_Msk CAN_F4R1_FB28 RCC_CFGR_MCO CAN_F9R2_FB3_Pos CAN_F6R2_FB16 AFIO_EXTICR4_EXTI15_PF_Pos CAN_F9R2_FB3 RCC_CR_HSEON TIM_SMCR_ECE TIM_CCMR1_IC1F_3 TIM_BDTR_DTG_5 CAN_F3R1_FB21 DBGMCU_CR_DBG_TIM4_STOP_Pos ADC_CR1_DISCNUM_Msk TIM_BDTR_DTG_6 CAN_BTR_SJW_0 CAN_RDT0R_DLC ADC_CR1_JEOSIE_Pos
+syn keyword CTagsDefinedName CAN_FA1R_FACT12 CAN_IER_BOFIE_Msk CAN_F8R2_FB1_Pos TIM_EGR_COMG USB_EP3R_DTOG_RX_Pos USB_EP1R_EA EXTI_RTSR_RT14 I2C_CR1_PEC_Msk GPIO_BSRR_BS4 USB_COUNT3_RX_0_COUNT3_RX_0 USB_COUNT5_RX_1_NUM_BLOCK_1_1 USB_EP3R_EP_TYPE_Pos EXTI_RTSR_RT6 GPIO_CRH_CNF14 SDIO_MASK_SDIOITIE_Msk CAN_F4R1_FB30_Pos AFIO_EXTICR1_EXTI2_PD_Pos ADC_SQR1_SQ16_Pos TIM_BDTR_DTG_1 RCC_APB2ENR_USART1EN CAN_F0R1_FB8 DMA_IFCR_CHTIF5 SDIO_MASK_RXDAVLIE_Msk SDIO_MASK_STBITERRIE USART_CR3_IREN CAN_F12R2_FB31
+syn keyword CTagsDefinedName CAN_TDL2R_DATA3_Msk TIM_CCMR1_OC2M USB_ISTR_ESOF_Msk ADC_SMPR2_SMP0 SPI_CR1_RXONLY_Pos CAN_F10R1_FB3_Pos AFIO_EXTICR2_EXTI5_PC CAN_F7R1_FB26_Pos DMA_IFCR_CGIF7_Msk CAN_F12R1_FB9 AFIO_EXTICR3_EXTI8_PD_Msk CAN_F3R2_FB22_Pos CAN_F0R2_FB13_Msk EXTI_PR_PR7_Msk TIM_BDTR_OSSR USB_COUNT4_RX_1_NUM_BLOCK_1_4 CAN_F3R1_FB31 USB_EP_TX_NAK CAN_F7R2_FB13 CAN_TSR_LOW0_Pos RTC_CRH_ALRIE_Msk CAN_F5R2_FB6_Msk AFIO_EXTICR2_EXTI5_Pos AFIO_EXTICR3_EXTI8_Pos GPIO_ODR_ODR8_Msk CAN_F10R2_FB28_Msk
+syn keyword CTagsDefinedName CAN_TDL1R_DATA2_Pos CAN_TSR_TXOK2_Msk GPIO_LCKR_LCK13_Msk DMA_IFCR_CGIF4_Pos PWR_CR_PDDS_Msk SPI_CR1_BR_Pos SDIO_DCTRL_DMAEN_Msk TIM_CCR3_CCR3_Msk USB_COUNT6_TX_1_COUNT6_TX_1 CAN_F2R1_FB24_Msk ADC_SR_EOS_Pos USB_EPADDR_FIELD_Pos CAN_F0R1_FB17 CAN_FM1R_FBM11 CAN_TI1R_RTR_Pos AFIO_EXTICR4_EXTI15_PC CAN_FA1R_FACT4 GPIO_CRL_MODE5_Pos CAN_F5R1_FB22 USB_COUNT2_RX_1_NUM_BLOCK_1_0 CAN_MCR_RFLM USB_EP6R_STAT_TX_Msk FLASH TIM_SMCR_ETPS_Msk AFIO_EXTICR4_EXTI13_PA FLASH_ACR_PRFTBE_Msk
+syn keyword CTagsDefinedName CAN_F6R2_FB8_Pos CAN_F8R1_FB6_Pos IWDG_KR_KEY CAN_BTR_TS1_Msk CAN_F0R2_FB7_Msk CAN_RDL1R_DATA2 IS_I2C_ALL_INSTANCE RCC_BDCR_RTCEN AFIO_MAPR_CAN_REMAP CAN_F5R1_FB30_Msk CAN_F2R1_FB17_Pos CAN_F9R2_FB13 EXTI_SWIER_SWI6 CAN_F0R1_FB17_Pos CAN_F10R1_FB2_Msk CAN_F13R2_FB31_Pos AFIO_MAPR_SWJ_CFG_JTAGDISABLE USB_COUNT4_RX_0_NUM_BLOCK_0_2 CAN_F13R2_FB27_Msk CAN_BTR_LBKM_Msk CAN_F6R2_FB8 GPIO_IDR_IDR1_Pos CAN_F10R1_FB17_Pos RCC_APB1ENR_PWREN_Pos ADC_SMPR1_SMP12_2 USB_EP_BULK
+syn keyword CTagsDefinedName EXTI_IMR_MR17_Msk RCC_APB2RSTR_IOPDRST_Pos ADC_JOFR2_JOFFSET2_Msk AFIO_MAPR_TIM1_REMAP_PARTIALREMAP CAN_FFA1R_FFA11 FLASH_OPTKEY1 USB_COUNT7_RX_0_NUM_BLOCK_0_2 CAN_F0R1_FB31 DMA_ISR_TCIF2_Msk CAN_MSR_RXM_Msk ADC_SQR3_SQ4 ADC_SQR3_SQ1_Msk TIM_CR2_MMS CAN_F13R2_FB21_Pos GPIO_ODR_ODR0 CAN_RDL1R_DATA3_Msk DMA_CCR_PSIZE_1 GPIO_BRR_BR7 EXTI_FTSR_FT7 CAN_F6R2_FB13_Pos CAN_RF1R_RFOM1 EXTI_EMR_MR1_Msk TIM_SR_CC4OF_Pos GPIO_CRH_MODE12_Msk USB_COUNT6_TX_COUNT6_TX AFIO_EXTICR1_EXTI0_PG_Msk
+syn keyword CTagsDefinedName CAN_F3R2_FB17 CAN_FS1R_FSC8 GPIO_ODR_ODR15_Pos I2C_DR_DR_Pos SDIO_STA_TXFIFOE_Pos RTC_BKP_NUMBER SDIO_CMD_WAITRESP_Pos CAN_F5R2_FB19_Msk CAN_TI1R_RTR_Msk SPI_CR1_RXONLY SDIO_DCTRL_RWSTOP_Msk GPIO_BSRR_BR0_Pos CAN_F10R1_FB9_Msk TIM_CCMR2_IC4PSC_Msk AFIO_EXTICR3_EXTI9_PB_Msk POSITION_VAL CAN_F9R2_FB5_Msk ADC_SMPR2_SMP0_2 CAN_FS1R_FSC1_Pos ADC_SMPR1_SMP10_2 CAN_F6R2_FB21 CAN_F7R2_FB22_Pos I2C_TRISE_TRISE ADC_SMPR2_SMP6 CAN_F0R1_FB5 CAN_F5R2_FB28_Pos CAN_F13R1_FB29_Msk
+syn keyword CTagsDefinedName CAN_F10R2_FB30 CAN_F8R2_FB19 CAN_F9R2_FB4_Msk CAN_F6R1_FB31_Pos AFIO_MAPR_SWJ_CFG_Msk USB_COUNT4_RX_NUM_BLOCK_2 USB_EP3R_CTR_TX_Pos CAN_F0R2_FB25 CAN_F4R1_FB31_Pos USB_DADDR_ADD5_Msk CAN_F12R2_FB8_Msk CAN_F12R1_FB16_Msk GPIO_CRH_MODE10_1 CAN_F8R1_FB29_Pos EXTI_RTSR_TR17_Msk AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk CAN_F2R2_FB12_Msk CAN_F9R2_FB12_Pos CAN_F6R2_FB12_Pos EXTI_PR_PR13_Msk CAN_F9R1_FB8_Msk GPIO_CRH_CNF8_Pos CAN_F13R2_FB29_Pos CAN_F1R1_FB5 CAN_F12R2_FB11_Pos CAN_F5R2_FB15
+syn keyword CTagsDefinedName AHBPERIPH_BASE GPIO_CRH_MODE8_0 BKP_DR3_D_Msk CAN_F13R1_FB6_Msk TIM_BDTR_AOE_Pos CAN_F11R2_FB9_Msk EXTI_PR_PIF14 GPIO_CRL_CNF5 TIM_DMAR_DMAB ADC_DR_DATA_Pos ADC_SQR3_SQ3_0 USART_CR2_LBCL_Pos DMA_ISR_GIF7 ADC_MULTIMODE_SUPPORT CAN_F10R2_FB22 CAN_F13R2_FB26_Msk ADC_SQR3_SQ1_4 CAN_F11R1_FB7_Pos GPIO_BSRR_BS8_Pos TIM_CR1_OPM_Pos AFIO_EVCR_PIN_PX9_Pos CAN_F13R1_FB17_Pos USB_CNTR_RESETM_Msk CAN_F7R1_FB24_Msk EXTI_EMR_MR2 CAN_F4R2_FB6 CAN_F0R2_FB16 CAN_F8R1_FB12_Msk EXTI_PR_PR2_Pos
+syn keyword CTagsDefinedName CAN_F13R2_FB9_Pos CAN_F6R2_FB3 I2C_CR2_ITERREN_Msk ADC_SQR2_SQ9_2 CAN_BTR_BRP_Pos RCC_APB2ENR_ADC2EN I2C_OAR1_ADD7_Pos AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ADC_CR2_JEXTSEL_2 EXTI_EMR_EM18 BKP_CSR_TIF_Pos GPIO_BSRR_BS9_Pos IWDG_SR_PVU USB_EP1R_EP_TYPE_1 CAN_IER_FOVIE1_Pos AFIO_EXTICR1_EXTI2_PE_Pos ADC_CR2_JEXTSEL_1 CAN_F12R2_FB27 GPIO_CRH_CNF11 ADC_SQR3_SQ4_1 RCC_CIR_LSIRDYF_Pos AFIO_EXTICR1_EXTI0_PG_Pos CAN_F6R1_FB13_Pos AFIO_EXTICR4_EXTI14_PB_Msk USB_EP7R_SETUP_Msk PWR_CR_PLS_2V2
+syn keyword CTagsDefinedName IWDG_PR_PR_0 TIM_CCR1_CCR1_Msk CAN_F12R1_FB18 CAN_F9R1_FB20_Msk CAN_F11R2_FB31 EXTI_PR_PR18_Pos CAN_F12R2_FB3_Pos RCC_CFGR_PLLMULL USB_EP1R_DTOG_TX SPI_CR1_BR AFIO_EXTICR3_EXTI8_PF_Msk CAN_F2R1_FB26 DMA_ISR_TCIF5_Msk STM32F1 EXTI_FTSR_FT1 USB_ISTR_CTR CAN_F4R1_FB16 USB_COUNT6_RX_0_NUM_BLOCK_0 CAN_F12R2_FB31_Msk USART_CR2_CPHA_Msk ADC_SMPR2_SMP4_Msk AFIO_EXTICR2_EXTI7_PD ADC_SQR1_L_2 DBGMCU_CR_TRACE_MODE_Pos GPIO_LCKR_LCK13_Pos WWDG_CR_T2 USART_CR3_NACK_Pos
+syn keyword CTagsDefinedName USB_COUNT7_TX_0_COUNT7_TX_0 DBGMCU_IDCODE_REV_ID_5 CAN_F1R2_FB31_Pos CAN_F13R1_FB19 CAN_F4R1_FB8_Pos GPIO_CRL_MODE7_Pos CAN_F4R2_FB22_Pos CAN_F5R2_FB31 RCC_BDCR_RTCSEL SDIO_CMD_ENCMDCOMPL TIM_DIER_CC4DE ADC_SQR2_SQ12_0 CAN_F4R2_FB3_Pos DMA_ISR_HTIF7_Msk CRC CAN_F2R1_FB29_Pos CAN_TSR_LOW2 PIN_OPT_AF3 EXTI_EMR_EM4 CAN_F7R2_FB3 CAN_TI0R_STID_Pos USART_CR3_EIE_Msk CAN_F9R1_FB21 CAN_FM1R_FBM11_Msk RCC_AHBENR_FLITFEN_Pos CAN_F0R2_FB24_Pos SDIO_MASK_TXUNDERRIE_Msk CAN_F7R2_FB26
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PF_Msk RCC_CFGR_HPRE_DIV128 CAN_F3R2_FB25_Msk CAN_F9R2_FB11 EXTI_PR_PR5_Pos CAN_F0R1_FB14_Msk ADC_SQR2_SQ10_4 SDIO_STA_DATAEND CAN_IER_TMEIE_Pos EXTI_IMR_IM7 ADC_SMPR1_SMP16_0 CAN_F12R2_FB16 AFIO_EXTICR2_EXTI7_PA GPIO_ODR_ODR4_Pos ADC_CR1_DISCNUM CAN_F7R1_FB16 USB_COUNT2_RX_1_NUM_BLOCK_1_4 USART_GTPR_PSC_3 AFIO_EXTICR4_EXTI12_PG_Msk TIM_DIER_CC3IE_Msk USB_COUNT0_RX_NUM_BLOCK_Msk BKP_RTCCR_CAL_Msk CAN_F4R2_FB7_Msk CAN_TDL0R_DATA3_Pos
+syn keyword CTagsDefinedName USB_COUNT4_RX_1_NUM_BLOCK_1_0 CAN_F11R2_FB0_Msk TIM_DIER_CC1IE EXTI_EMR_EM6 DMA_CCR_TEIE USB_EP7R_CTR_TX_Pos EXTI_FTSR_FT4 SDIO_CLKCR_CLKEN_Pos CAN_F6R1_FB3 AFIO_EXTICR2_EXTI4_PG_Msk CAN_F5R1_FB24 GPIO_IDR_IDR12 EXTI_SWIER_SWI1 CAN_TSR_TERR0_Msk GPIO_BRR_BR0_Pos CAN_F7R2_FB16 CAN_F2R1_FB20 SPI_CR1_SSM CAN_FA1R_FACT2_Msk CAN_FS1R_FSC13_Msk CAN_F3R1_FB17_Pos CAN_TI2R_IDE_Msk TIM_BDTR_DTG_0 FLASH_CR_STRT_Pos DMA_IFCR_CGIF2_Msk WWDG_CFR_W_5 USART_SR_PE_Msk CAN_MCR_SLEEP_Pos
+syn keyword CTagsDefinedName DMA1_Channel2_BASE RTC_ALRH_RTC_ALR_Msk CAN_F1R2_FB23 CAN_F4R2_FB11_Msk GPIO_BRR_BR8_Pos USB_EP3R_CTR_RX_Pos EXTI_RTSR_TR0_Msk ADC_JSQR_JL_Pos CAN_F9R2_FB4 CAN_F10R2_FB5 CAN_F12R2_FB7_Pos CAN_F4R1_FB26 CAN_TDL1R_DATA1 AFIO_EXTICR2_EXTI7_PG_Msk DMA_CCR_MSIZE_1 AFIO_MAPR_USART2_REMAP_Pos ADC_SQR3_SQ3_Pos DMA_ISR_TCIF7 RCC_APB2RSTR_IOPARST_Pos USB_EP2R_STAT_TX CAN_F5R1_FB3_Msk CAN_F11R2_FB2_Msk I2C_OAR1_ADD3_Msk EXTI_PR_PR12_Msk CAN_F0R1_FB16_Pos USB_COUNT1_RX_COUNT1_RX_Pos
+syn keyword CTagsDefinedName USB_COUNT1_RX_1_NUM_BLOCK_1_1 CAN_F3R2_FB16_Msk ADC_SQR1_SQ16_2 CAN_RF1R_FMP1 RCC_APB1RSTR_SPI2RST_Msk ADC_SMPR1_SMP13_Pos RCC_APB2RSTR_IOPARST I2C_OAR1_ADD9 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_EXTICR4_EXTI15_PE_Pos CAN_F12R2_FB20_Msk DMA_ISR_TCIF5 EXTI_FTSR_FT9 CAN_F7R1_FB24_Pos CAN_F3R2_FB31_Msk SDIO_ICR_SDIOITC_Pos EXTI_RTSR_TR5_Msk AFIO_EVCR_PIN_PX7_Msk AFIO_EXTICR4_EXTI14_PF_Msk DMA_IFCR_CHTIF2 TIM_CCMR2_OC4M_Msk CAN_FS1R_FSC8_Pos RCC_CSR_PORRSTF I2C_SR1_RXNE_Msk
+syn keyword CTagsDefinedName RDP_KEY CAN_F2R1_FB25_Pos USB_COUNT0_RX_0_NUM_BLOCK_0 EXTI_SWIER_SWIER7_Pos CAN_FFA1R_FFA2 CAN_F4R2_FB8_Msk CAN_F7R2_FB9_Msk USB_EP2R_CTR_TX GPIO_ODR_ODR2 AFIO_MAPR_TIM1_REMAP_FULLREMAP GPIO_BSRR_BR1_Msk GPIO_CRH_CNF12_Msk DMA_CCR_PL SPI_CR2_ERRIE USB_EP0R_EP_TYPE_0 IS_TIM_INSTANCE CAN_F3R1_FB9 CAN_F9R2_FB21_Msk CAN_F8R1_FB8 FLASH_WRP2_nWRP2_Pos CAN_F3R1_FB13_Msk USB_COUNT6_TX_COUNT6_TX_Msk ADC_CR1_AWDCH_0 USB_EP0R_CTR_RX_Msk CAN_F9R2_FB28_Msk CAN_F11R2_FB1_Msk CAN_F11R1_FB22
+syn keyword CTagsDefinedName FLASH_OPTKEYR_OPTKEYR_Msk GPIO_CRL_CNF_Msk CAN_F0R1_FB14_Pos GPIO_BSRR_BR15_Msk CAN_F8R2_FB7_Pos RCC_CR_HSION_Msk USB_COUNT5_TX_COUNT5_TX_Pos CAN_F0R1_FB15_Pos TIM_CCMR2_IC3PSC CAN_F12R1_FB31 CAN_F13R2_FB31 USB_ISTR_DIR CAN_F10R2_FB14_Msk CAN_F13R1_FB31 CAN_ESR_EWGF AFIO_EXTICR3_EXTI10_PF_Msk CAN_F12R1_FB3_Msk USB_EP4R_SETUP TIM_CCMR1_OC2M_Pos PWR_CSR_PVDO_Pos EXTI_IMR_MR2_Msk ADC_SMPR1_SMP14_1 CAN_F6R1_FB30_Msk CAN_F10R1_FB4 CAN_F11R1_FB29 CAN_TDH1R_DATA4_Pos FLASH_KEYR_FKEYR
+syn keyword CTagsDefinedName I2C_CR1_POS TIM_CCMR1_IC2PSC_0 TIM_CCMR1_IC2PSC_Msk USB_EP7R_SETUP_Pos ADC_SMPR1_SMP16_Msk CAN_F10R1_FB19_Msk DMA_IFCR_CGIF5 CAN_F9R1_FB2_Pos TIM_CCMR1_OC2PE_Pos CAN_F4R2_FB30_Pos EXTI_RTSR_TR3_Pos USB_EP1R_SETUP CAN_F8R2_FB29 GPIO_ODR_ODR5_Msk EXTI_FTSR_TR17_Msk AFIO_EXTICR3_EXTI10 USART_GTPR_PSC_4 BKP_CR_TPAL CAN_RDT1R_FMI_Pos RCC_CFGR_PLLMULL13_Pos DMA_ISR_GIF2_Pos CAN_F4R1_FB26_Pos USB_EP7R_STAT_TX_Msk CAN_F13R2_FB7 AFIO_EXTICR2_EXTI6_PB GPIO_CRH_MODE15_0 CAN_F4R1_FB15_Pos
+syn keyword CTagsDefinedName SDIO_STA_TXDAVL_Pos USB_CNTR_PDWN_Msk CAN_F10R1_FB28 USB_ADDR6_RX_ADDR6_RX FLASH_CR_ERRIE_Msk GPIO_IDR_IDR3 TIM_CCMR2_OC3M_1 GPIO_CRL_MODE3_1 I2C_SR1_ADD10 CAN_F4R2_FB0 CAN_RF0R_FULL0 RCC_CFGR_PLLMULL3_Pos CAN_F4R2_FB24 CAN_F4R1_FB29_Msk CAN_F7R2_FB18_Pos FLASH_WRP0_nWRP0_Pos EXTI_PR_PR11_Msk TIM_CCMR1_OC2FE_Msk USART_CR2_LINEN_Msk CAN_F0R1_FB26 ADC_SQR3_SQ4_3 CAN_F10R1_FB1_Msk GPIO_CRL_CNF1_1 USB_COUNT6_RX_BLSIZE USB_COUNT0_TX_1_COUNT0_TX_1 DMA_ISR_TEIF5 DMA_ISR_HTIF3
+syn keyword CTagsDefinedName AFIO_EXTICR1_EXTI3_Pos ADC_CR1_DISCNUM_2 CAN_F8R2_FB21_Pos GPIO_ODR_ODR13_Msk CAN_F12R1_FB1 CAN_F6R2_FB18 USB_EP4R_DTOG_TX USB_COUNT2_RX_NUM_BLOCK_1 CAN_TI1R_TXRQ_Pos CAN_FS1R_FSC5_Msk EXTI_IMR_MR6 EXTI_FTSR_TR10_Msk GPIO_CRL_MODE3_Pos FLASH_SR_EOP_Msk CAN_F11R2_FB1_Pos TIM_CR2_OIS4_Msk USB_COUNT1_RX_0_COUNT1_RX_0 SDIO_STA_CCRCFAIL_Pos CAN_F5R1_FB25_Pos USART_CR2_CPOL CAN_BTR_TS1_Pos CAN_F0R2_FB19_Pos CAN_F10R1_FB3_Msk GPIO_CRH_CNF9_0 USB_COUNT4_TX_COUNT4_TX_Msk
+syn keyword CTagsDefinedName AFIO_EXTICR4_EXTI15_PF CAN_F7R1_FB17 GPIO_BRR_BR12 RCC_CSR_LSION_Pos ADC_DR_DATA_Msk CAN_F11R2_FB18_Msk CAN_F1R2_FB1_Pos SDIO_RESP3_CARDSTATUS3 PIN_OPT_NONE USB_EP7R_EA_Pos EXTI_PR_PIF1 EXTI_RTSR_TR6_Msk FLASH_WRP1_WRP1 CAN_F5R2_FB8 DMA_ISR_TEIF3_Msk USB_EP2R_EA_Pos CAN_F10R1_FB6 CAN_F5R2_FB20 CAN_F5R2_FB15_Pos GPIO_BSRR_BR6_Pos SDIO_MASK_DATAENDIE_Msk CAN_F5R1_FB7 I2C_CR1_SMBUS_Pos ADC_SMPR2_SMP2_0 CAN_F4R2_FB11_Pos GPIO_BSRR_BR13_Pos CAN_F10R2_FB30_Msk GPIO_BRR_BR11
+syn keyword CTagsDefinedName PWR_CR_LPDS_Msk AFIO_EVCR_EVOE_Pos TIM_EGR_BG_Msk CAN_F11R1_FB27_Pos CAN_F3R1_FB6_Pos USART2 CAN_F1R1_FB14 GPIO_BSRR_BS2_Pos ADC_SMPR1_SMP15_Pos ADC_CR2_SWSTART_Msk CAN_F10R1_FB18 USART_SR_TC CAN_F6R1_FB5 CAN_F7R1_FB20 IWDG_SR_PVU_Pos CAN_F7R2_FB10_Pos CAN_FFA1R_FFA6_Pos AFIO_EVCR_PIN_PX2 SDIO_DCTRL_DTDIR_Pos TIM_DIER_UIE_Msk AFIO_EXTICR3_EXTI10_PD CAN_F5R1_FB18 ADC_SMPR1_SMP12_1 FLASH_AR_FAR_Msk SPI_CR1_BR_0 AFIO_EVCR_PORT_Pos USB_EP1R_STAT_TX_1 AFIO_EXTICR2_EXTI7_PG
+syn keyword CTagsDefinedName USB_EP_DTOG_RX_Msk CAN_F6R1_FB24 GPIO_BRR_BR4_Msk EXTI_SWIER_SWIER15 ADC_SQR3_SQ5_3 AFIO_EXTICR3_EXTI9_PE CAN_F2R2_FB9 USART_CR2_CPOL_Msk GPIO_BSRR_BR10_Pos CAN_TSR_TME1_Msk I2C_SR1_ADDR ADC_SQR2_SQ9_0 CAN_F6R2_FB26 CAN_F2R2_FB23 TIM_CCMR1_OC2FE_Pos TIM1_UP_TIM16_IRQn AFIO_MAPR_SWJ_CFG_Pos CAN_F3R1_FB30 CAN_F7R1_FB29_Msk DMA_IFCR_CTCIF5 USB_EP_DTOG_RX_Pos EXTI_SWIER_SWIER15_Msk ADC_SMPR1_SMP14_0 GPIO_LCKR_LCK11_Pos USB_COUNT0_RX_1_NUM_BLOCK_1_1 TIM_CCMR2_OC4PE_Msk
+syn keyword CTagsDefinedName CAN_F6R1_FB3_Pos SDIO_MASK_TXFIFOHEIE_Pos TIM_CCMR2_OC4M_1 USB_FNR_RXDM_Msk CAN_F4R2_FB16_Msk CAN_F9R2_FB24_Pos USB_COUNT3_RX_COUNT3_RX ADC_SQR1_SQ13 CAN_F4R1_FB9_Pos RCC_CFGR_PPRE2_DIV1 BKP_DR2_D_Pos CAN_F7R1_FB28_Msk SDIO_STA_CEATAEND_Pos RCC_CSR_RMVF_Msk GPIO_LCKR_LCK6_Msk CAN_F2R2_FB27 CAN_F5R2_FB18_Msk AFIO_EXTICR3_EXTI9_PF_Pos CAN_ESR_LEC_Msk USB_EP3R_DTOG_TX_Pos RCC_CFGR_PLLMULL16_Pos CAN_F11R2_FB1 TIM_EGR_CC3G GPIO_BSRR_BR5_Pos TIM_CCER_CC3NE DBGMCU_IDCODE_DEV_ID
+syn keyword CTagsDefinedName USB_COUNT3_RX_1_NUM_BLOCK_1_3 SDIO_MASK_CCRCFAILIE_Msk GPIO_BSRR_BR6 IS_TIM_32B_COUNTER_INSTANCE pwm_start RCC_CFGR_PLLMULL11 USB_COUNT3_RX_0_NUM_BLOCK_0_2 GPIO_CRL_CNF5_Pos PWR_CR_PLS_Msk CAN_F9R1_FB14_Msk CAN_F8R2_FB0 CAN_F9R2_FB0 EXTI_IMR_MR13_Pos AFIO_EXTICR2_EXTI4_PF_Pos CAN_F4R2_FB4 USB_EP3R_STAT_TX_Msk CAN_F2R1_FB29 EXTI_PR_PR16_Pos CAN_TSR_TXOK1_Msk CAN_F6R2_FB19 CAN_TSR_TERR2_Pos PIN_OPT_IRQ_EDGE_FALL I2C_CR2_LAST CAN_F13R2_FB13_Pos EXTI_IMR_MR5_Msk CAN_F4R2_FB19
+syn keyword CTagsDefinedName CAN_F10R1_FB20_Pos TIM4_IRQ_PRIORITY CAN_F2R2_FB31 DMA_ISR_TEIF6_Pos RCC_APB2RSTR_SPI1RST_Pos EXTI_PR_PR17_Msk TIM_CCMR1_IC1PSC RCC_CFGR_SW_HSI CAN_F10R1_FB30_Msk CAN_F11R2_FB23_Msk CAN_F4R2_FB10_Msk EXTI_RTSR_TR7_Msk DMA_ISR_HTIF1_Msk TIM_DIER_UDE DMA_IFCR_CTEIF1 CAN_F13R1_FB22 DBGMCU_CR_TRACE_MODE_Msk RCC_BDCR_BDRST_Pos GPIO_IDR_IDR9 CAN_F3R2_FB1_Pos GPIO_LCKR_LCK8 ADC_SQR3_SQ1_Pos EXTI_PR_PIF13 USART_CR3_IREN_Pos CAN_F2R1_FB11_Pos USB_EPRX_DTOG2 EXTI_SWIER_SWIER16_Pos
+syn keyword CTagsDefinedName CAN_F8R1_FB30_Pos TIM_CR1_CMS_1 AFIO_EXTICR4_EXTI12_PE CAN_F6R1_FB15 RCC_CFGR_PLLMULL4_Pos CAN_F8R2_FB14_Pos CAN_F12R2_FB9 CAN_F1R2_FB12_Pos FLASH_CR_PER_Msk I2C_CR1_STOP_Msk GPIO_BSRR_BS9_Msk GPIO_CRH_CNF9_Pos SDIO_RESP3_CARDSTATUS3_Msk CAN_F8R1_FB14_Pos ADC_SQR1_SQ15_4 ADC_SMPR2_SMP9_Pos CAN_F8R1_FB31 FLASH_CR_OPTWRE_Msk USB_EP5R_CTR_TX_Msk RCC_CFGR_PLLMULL9 CAN_F4R2_FB5_Pos CAN_F11R1_FB13 CAN_F11R2_FB19_Pos CAN_FM1R_FBM4_Pos SPI_CR2_RXDMAEN SDIO_DTIMER_DATATIME
+syn keyword CTagsDefinedName RCC_CFGR_PPRE1_2 CAN_TSR_TME1 ADC_CR2_EXTTRIG_Msk AFIO_EXTICR3_EXTI11_PD RCC_CFGR_ADCPRE CAN_F13R2_FB30_Msk USB_ISTR_SUSP EXTI_EMR_MR13_Pos USB_COUNT0_RX_NUM_BLOCK_0 CAN_F1R1_FB31 CAN_F7R1_FB18 CAN_F1R1_FB16_Pos USB_EP4R_EP_TYPE_Msk WWDG_CR_T_Msk CAN_F8R2_FB4 CAN_F9R2_FB30 PWR_CR_DBP CAN_F6R2_FB9_Msk CAN_RDL0R_DATA2_Pos RCC_CFGR_MCOSEL USB_COUNT2_RX_1_NUM_BLOCK_1_1 CAN_F1R1_FB31_Pos TIM_CCER_CC3NE_Msk BKP_DR10_D_Msk AFIO_EXTICR2_EXTI4_PA CAN_F3R1_FB10_Msk CAN_F10R2_FB15_Msk
+syn keyword CTagsDefinedName GPIO_ODR_ODR3_Pos GPIO_BSRR_BS1_Pos CAN_F2R2_FB1 TIM_CCMR1_OC2PE EXTI_RTSR_RT9 CAN_F10R2_FB31 CAN_F0R2_FB1 CAN_F6R2_FB13_Msk CAN_F0R2_FB29 TIM_CCER_CC4E CAN_F11R2_FB31_Pos EXTI_FTSR_TR16_Pos EXTI_IMR_MR3_Msk CAN_F5R1_FB24_Pos CAN_F8R2_FB25_Pos I2C_CR2_FREQ_5 GPIO_ODR_ODR8_Pos AFIO_EXTICR1_EXTI2_Msk USB_ADDR4_RX_ADDR4_RX_Pos RCC_HSE_MAX CAN_F3R2_FB22 RTC_ALRH_RTC_ALR_Pos IS_TIM_CC4_INSTANCE DBGMCU_IDCODE_REV_ID_11 CAN_F8R2_FB23_Pos EXTI_PR_PR10
+syn keyword CTagsDefinedName DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos GPIO_CRL_MODE1_0 EXTI_RTSR_RT17 GPIO_BSRR_BS3_Msk USB_COUNT4_RX_1_NUM_BLOCK_1_2 CAN_F6R2_FB17_Pos ADC_CR2_TSVREFE CAN_F5R2_FB22 CAN_FA1R_FACT11_Pos BKP TIM_DIER_CC4IE_Msk ADC_CR2_JEXTTRIG DMA_ISR_GIF3_Pos RCC_CIR_HSERDYIE_Pos FLASH_SR_PGERR_Pos CAN_F6R1_FB20 RCC_CFGR_ADCPRE_DIV4 RCC_APB2RSTR_USART1RST AFIO_MAPR_USART2_REMAP_Msk SDIO_CMD_CPSMEN EXTI_PR_PIF7 USB_ADDR7_TX_ADDR7_TX_Msk EXTI_EMR_MR9_Msk CAN_F10R1_FB5 RTC_CRH_SECIE_Pos
+syn keyword CTagsDefinedName CAN_F11R1_FB21_Msk CAN_FA1R_FACT3_Msk CAN_FFA1R_FFA7_Pos CAN_F11R2_FB26 GPIO_CRH_CNF15_Pos CAN_F5R1_FB29_Msk SDIO_DCTRL_RWMOD_Msk IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE USB_EP6R_CTR_RX CAN_F9R1_FB16_Pos GPIO_BSRR_BS14_Msk CAN_F6R2_FB28_Msk AFIO_EXTICR2_EXTI7_PC MBED_CMSIS_NVIC_H SDIO_RESP0_CARDSTATUS0_Pos RCC_AHBENR_SRAMEN RCC_CFGR_SWS_HSI CAN_F4R1_FB22_Msk I2C_OAR1_ADD2 GPIO_BSRR_BS0_Pos USB_LP_IRQn CAN_F1R2_FB11 SDIO_ICR_DBCKENDC_Msk ADC_SQR2_SQ7 DMA_CCR_HTIE CAN_F0R1_FB7_Msk
+syn keyword CTagsDefinedName GPIOD_BASE CAN_F12R1_FB16_Pos USB_EP0R_DTOG_TX_Pos CAN_IER_FOVIE1_Msk EXTI_PR_PIF12 CRC_BASE CAN_TDT2R_TGT RCC_CIR_HSIRDYC AFIO_EXTICR1_EXTI2_PE CAN_IER_FOVIE1 TIM_DCR_DBL_3 CAN_BTR_TS2_Msk GPIO_BSRR_BR8 GPIO_ODR_ODR15_Msk RTC_CRH_OWIE_Msk CAN_F1R1_FB30_Msk CAN_RI1R_EXID_Pos TIM_CR2_CCDS_Msk CAN_F5R2_FB21 AFIO_EXTICR1_EXTI2_PA TIM_SMCR_ETPS CAN_F10R2_FB9_Msk TIM_CCMR2_IC4F_0 PWR_CR_LPDS DBGMCU_CR_TRACE_MODE USART3 TIM_CCMR2_IC4F_Pos AFIO_EXTICR4_EXTI12_PB CAN_F3R2_FB2_Pos
+syn keyword CTagsDefinedName EXTI_IMR_IM14 BKP_RTCCR_CCO_Msk FLASH_WRPR_WRP CAN_F4R2_FB2_Pos CAN_TSR_TERR0 AFIO_MAPR_TIM2_REMAP_0 CAN_F13R1_FB20_Msk ADC_SMPR2_SMP7_2 CAN_TI0R_STID CAN_F8R1_FB1_Pos USB_DADDR_ADD2 I2C_CR2_FREQ RTC CAN_TDT0R_TGT_Msk CAN_F7R2_FB30 FLASH_OBR_OPTERR_Msk GPIO_CRH_CNF8 ADC_SMPR2_SMP1 CAN_F13R1_FB30_Msk FLASH_AR_FAR CAN_RDL1R_DATA0 AFIO_EXTICR2_EXTI7_PF_Pos USART_BRR_DIV_Fraction DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk USB_ISTR_ERR_Msk USB_COUNT7_RX_0_NUM_BLOCK_0_3 I2C_SR2_PEC_Msk
+syn keyword CTagsDefinedName SDIO_CLKCR_WIDBUS_Pos EXTI_IMR_MR4_Pos CAN_F9R1_FB31_Msk RCC_APB1ENR_SPI2EN_Pos CAN_F0R1_FB30 CAN_F8R2_FB30_Msk ADC_SMPR2_SMP0_1 RCC_APB2ENR_TIM1EN_Msk USB_COUNT6_RX_0_NUM_BLOCK_0_1 USART_CR2_CLKEN_Msk GPIOA USB_COUNT1_RX_1_NUM_BLOCK_1_4 CAN_F0R1_FB16 CAN_F1R2_FB31_Msk I2C_SR2_TRA_Msk CAN_F4R1_FB24 ADC_SMPR2_SMP4_1 CAN_TDT0R_DLC_Msk CAN_F5R1_FB20_Msk I2C_OAR1_ADD1 USB_COUNT3_RX_NUM_BLOCK EXTI_IMR_MR18_Msk USB_COUNT4_TX_1_COUNT4_TX_1 CAN_F0R2_FB6 CAN_F6R2_FB11_Pos
+syn keyword CTagsDefinedName USB_EP7R_CTR_TX_Msk CAN_RI1R_STID_Pos RCC_CSR_LSIRDY DBGMCU_IDCODE_REV_ID_6 FLASH_SR_EOP AFIO_MAPR_SWJ_CFG_RESET GPIO_CRH_CNF14_Msk CAN_F1R2_FB11_Pos USB_COUNT2_RX_0_NUM_BLOCK_0_3 DBGMCU_IDCODE_DEV_ID_Pos USB_PMAADDR CAN_F4R2_FB27_Pos CAN_F7R2_FB1_Msk EXTI_FTSR_TR4_Msk EXTI_FTSR_TR16_Msk AFIO_EVCR_PORT_Msk AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk CAN_F2R1_FB7_Msk RDP_KEY_Pos CAN_F1R2_FB14 SDIO_DCTRL_DBLOCKSIZE_2 TIM_SMCR_MSM RCC_APB1RSTR_SPI2RST_Pos CAN_F0R2_FB3_Msk I2C_OAR1_ADD5_Pos
+syn keyword CTagsDefinedName CAN_F4R2_FB21 TIM_DIER_COMIE_Pos CAN_F4R2_FB26_Msk SYSCFG_EXTI_PD_MASK CAN_F1R1_FB14_Msk AFIO_EXTICR4_EXTI15_PG EXTI_PR_PR10_Msk WWDG_CFR_W_Msk TIM_CCMR2_OC4PE_Pos USB_EP_RX_NAK CAN_BTR_TS1_1 GPIO_IDR_IDR14 CAN_F3R2_FB11_Msk USB_FNR_RXDP_Msk USART_SR_CTS_Msk EXTI_FTSR_TR14_Pos TIM_CCMR2_CC3S_Msk TIM_DIER_TDE_Msk BKP_DR1_D RCC_AHBENR_SRAMEN_Pos AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 EXTI_PR_PR18_Msk ADC_SQR2_SQ7_4 SDIO_MASK_CMDSENTIE_Msk AFIO_EXTICR3_EXTI8_PB_Pos GPIO_BRR_BR9_Pos
+syn keyword CTagsDefinedName USB_COUNT1_TX_COUNT1_TX_Msk RCC_CIR_PLLRDYIE_Msk GPIO_ODR_ODR11 CAN_F3R1_FB2_Pos CAN_RDH1R_DATA6_Msk CAN_F10R2_FB5_Msk SPI_CR1_CRCEN TIM_CR2_CCPC_Msk CAN_F3R2_FB20_Pos CAN_F7R2_FB27 CAN_TDT0R_TIME CAN_F8R2_FB7_Msk CAN_F6R2_FB4_Pos SDIO_FIFOCNT_FIFOCOUNT_Msk RCC_BDCR_RTCSEL_0 CAN_F5R2_FB31_Pos CAN_F4R1_FB31_Msk CAN_F11R1_FB24 CAN_F4R2_FB10_Pos IS_USB_ALL_INSTANCE CAN_F12R1_FB13_Pos CAN_F13R1_FB0_Msk AFIO_EXTICR2_EXTI4_PC CAN_F8R2_FB19_Pos AFIO_EXTICR1_EXTI0_PE_Msk
+syn keyword CTagsDefinedName TIM_BDTR_BKE_Pos USB_EP1R_DTOG_RX_Msk CAN_F12R2_FB19 CAN_F6R2_FB11 CAN_F12R2_FB16_Pos CAN_TDH1R_DATA6_Pos TIM_ARR_ARR_Msk RCC_CFGR_PPRE2 TIM_DIER_CC3DE_Msk CAN_F10R1_FB25_Msk PWR_CR_PLS_2V9 TIM_CCER_CC3E_Pos ADC_CR1_DUALMOD_Msk AFIO_EXTICR1_EXTI0_PA CAN_F13R1_FB6 DMA_ISR_TEIF2 CAN_RF0R_FOVR0_Msk CAN_F3R1_FB8_Pos AFIO_EXTICR2_EXTI5_PG_Msk CAN_F8R1_FB28_Msk FLASH_OBR_nRST_STOP CAN_F6R1_FB9_Pos CAN_F9R2_FB0_Pos TIM_CCMR1_OC2M_Msk CAN_F7R1_FB11_Pos FLASH_OBR_nRST_STDBY_Msk
+syn keyword CTagsDefinedName GPIO_CRL_MODE5_1 I2C_OAR1_ADD8_9 CAN_F3R1_FB18_Pos AFIO_EXTICR1_EXTI3_PA FLASH_CR_PG CAN_F9R1_FB5_Pos WWDG_CFR_W2 CAN_F8R1_FB23_Msk DMA_ISR_TCIF7_Msk CAN_IER_LECIE_Pos CAN_F12R2_FB0_Pos IWDG_BASE RCC_BDCR_LSEBYP_Pos DMA_IFCR_CTEIF6 CAN_F10R2_FB20_Pos IS_TIM_ENCODER_INTERFACE_INSTANCE RCC_CFGR_PLLMUL USB_COUNT2_TX_1_COUNT2_TX_1 TIM_CCER_CC2NE_Msk CAN_F10R2_FB5_Pos CAN_F10R2_FB6_Msk CAN_F1R1_FB19 CAN_TSR_TME_Msk USB_COUNT4_RX_0_BLSIZE_0 TIM_CR1_CKD_1 CAN_F12R2_FB27_Pos
+syn keyword CTagsDefinedName TIM_CR2_OIS2_Pos CAN_F2R1_FB23_Pos USART2_BASE RCC_CFGR_SW_Msk CAN_F11R1_FB31 GPIO_LCKR_LCK3 USB_EP2R_EP_TYPE RCC_APB2ENR_SPI1EN CAN_F3R2_FB10_Pos ADC_SMPR1_SMP10_0 CAN_F10R2_FB26_Msk AFIO_EVCR_PIN_PX11_Pos AFIO_EXTICR4_EXTI14_PG_Msk EXTI_PR_PR4_Msk SDIO_CMD_NIEN USB_COUNT3_RX_0_BLSIZE_0 ADC_CR2_TSVREFE_Msk CAN_TI2R_TXRQ_Msk DMA_ISR_GIF7_Msk PIN_15 GPIO_LCKR_LCK0_Pos SDIO_DCTRL_DTMODE_Pos CAN_F0R2_FB21_Msk I2C_OAR1_ADD6_Msk SDIO_ICR_STBITERRC_Pos CAN_MCR_DBF_Msk USART_CR3_CTSE
+syn keyword CTagsDefinedName ADC_CR1_JEOCIE CAN_TSR_TME2_Pos DMA_ISR_TEIF4 CAN_F11R1_FB30_Msk USB_EP4R_EP_TYPE_1 CAN_F2R1_FB16 DBGMCU_CR_DBG_CAN1_STOP_Msk CAN_F1R2_FB16_Msk GPIO_CRL_CNF5_1 PWM_CHANNEL_3 USART_SR_LBD_Msk CAN_F9R2_FB19_Pos TIM_BDTR_DTG_Pos AFIO_EXTICR2_EXTI4_PD TIM_CCER_CC1NE_Pos ADC_SQR2_SQ11_1 CAN_F12R1_FB12_Pos AFIO_EVCR_PORT_PC_Msk CAN_FM1R_FBM6 CAN_F1R1_FB16_Msk CAN_TDT1R_DLC_Msk ADC_SQR2_SQ10_Msk I2C_CR1_ENPEC ADC_CR1_DUALMOD_2 EXTI_PR_PR13 PIN_OPT_AF15 TIM_CCER_CC3P_Pos
+syn keyword CTagsDefinedName ADC_CR2_DMA_Pos AFIO_EXTICR4_EXTI15_PA CAN_F4R2_FB19_Pos CAN_F8R2_FB13_Pos AFIO_EXTICR1_EXTI0 CAN_F3R1_FB5 GPIO_IDR_IDR4_Msk USB_EP3R_SETUP FLASH_OBR_nRST_STOP_Msk CAN_F6R1_FB10 EXTI_SWIER_SWI9 AFIO_EXTICR1_EXTI0_PF FLASH_WRP3_WRP3 CAN_FM1R_FBM2_Msk ADC_SMPR2_SMP9 CAN_F4R2_FB26_Pos TIM_CR1_CEN CAN_F5R2_FB28_Msk RCC_CFGR_PLLXTPRE CAN_F8R1_FB30_Msk CAN_FS1R_FSC AFIO_EXTICR1_EXTI2_PB_Msk USB_COUNT6_TX_COUNT6_TX_Pos AFIO_EVCR_PORT_PB_Msk CAN_F6R1_FB15_Pos EXTI_RTSR_TR13 I2C_CCR_CCR
+syn keyword CTagsDefinedName DMA_IFCR_CTEIF7_Msk USART_CR3_CTSIE EXTI_RTSR_TR13_Msk RCC_CFGR_PLLMULL16 ADC_JSQR_JSQ3_0 CAN_F9R2_FB2_Pos ADC_SMPR1_SMP11_2 CAN_F10R1_FB6_Pos GPIO_LCKR_LCK1 ADC_SQR1_SQ15_Msk USB_EP5R EXTI_IMR_MR18_Pos SDIO_MASK_CEATAENDIE_Pos ADC_SQR1_SQ16 AFIO_EXTICR4_EXTI12_Pos CAN_FFA1R_FFA12_Pos RCC_CR_HSIRDY_Msk DMA_ISR_GIF4_Msk FLASH_CR_STRT CAN_F5R1_FB11_Msk SDIO_STA_STBITERR_Pos CAN_F8R1_FB30 CAN_F7R1_FB1_Msk RTC_DIVL_RTC_DIV_Msk CAN_F0R1_FB22_Pos CAN_TDL0R_DATA3 ADC_SQR1_SQ15_2 TIM3
+syn keyword CTagsDefinedName CAN_F8R2_FB22_Pos CAN_F13R1_FB20 CAN_F4R1_FB24_Msk EXTI_IMR_IM5 CAN_F6R2_FB23_Msk TIM_SMCR_ETF_0 DMA_ISR_HTIF4_Msk GPIO_BSRR_BR14_Msk GPIO_BSRR_BR12_Msk CAN_F0R2_FB5 SDIO_STA_RXOVERR_Pos RCC_CFGR_HPRE USB_ISTR_DIR_Msk CAN_F1R1_FB22_Pos GPIO_BRR_BR5 GPIO_BSRR_BS11_Pos GPIO_CRH_CNF11_0 CAN_F4R1_FB5_Pos CAN_F9R1_FB23 CAN_F0R1_FB17_Msk CAN_FS1R_FSC7_Pos RCC_CFGR_HPRE_DIV256 EXTI_IMR_MR12_Msk GPIO_BRR_BR15_Msk SPI_CR1_CPHA_Pos CAN_F8R1_FB17_Pos CAN_TDH1R_DATA5
+syn keyword CTagsDefinedName DBGMCU_IDCODE_REV_ID_12 CAN_F12R1_FB8 CAN_TDL2R_DATA1 CAN_F11R2_FB30 TIM_CCER_CC2NP_Msk CAN_F10R1_FB0_Msk CAN_F6R2_FB5_Pos CAN_IER_BOFIE CAN_F10R1_FB21_Pos CAN_F2R1_FB16_Msk ADC_SMPR2_SMP7_1 CAN_ESR_EWGF_Msk SDIO_CMD_ENCMDCOMPL_Pos EXTI_SWIER_SWI13 DMA_IFCR_CTCIF4 GPIO_CRH_MODE9_0 CAN_F11R2_FB2 PIN_OPT_IRQ_EDGE_BOTH USART_CR1_RWU_Msk SPI1 ADC_SQR1_L CAN_F9R1_FB6_Pos ADC_SQR1_SQ15_0 USB_COUNT7_RX_NUM_BLOCK_Pos CAN_F11R1_FB27 ADC_SMPR1_SMP11_Pos USB_EP_SETUP GPIO_LCKR_LCK0_Msk
+syn keyword CTagsDefinedName TIM_CCER_CC1P_Msk TIM_EGR_CC4G_Msk ADC_CR1_JDISCEN_Pos CAN_F5R1_FB5 SPI_SR_TXE_Pos EXTI_PR_PR15 ADC12_COMMON AFIO_EXTICR4_EXTI12_PF SDIO_STA_CTIMEOUT_Msk EXTI_EMR_MR9 CAN_F12R2_FB17_Msk ADC_JDR1_JDATA_Msk USB_FNR_FN_Msk CAN_F1R2_FB19_Pos I2C_OAR1_ADD2_Pos ADC_SR_JEOS_Pos I2C_SR2_SMBHOST_Pos IWDG_PR_PR_Msk PWR_CR_PLS_2V3 AFIO_EXTICR2_EXTI4_PE_Msk RTC_CNTL_RTC_CNT_Pos DMA_IFCR_CTEIF2_Pos ADC_SMPR1_SMP11_0 WWDG_CFR_W_0 AFIO_EXTICR3_EXTI8_PG_Pos BKP_RTCCR_ASOE_Msk CAN_F4R1_FB27_Msk
+syn keyword CTagsDefinedName CAN_F5R1_FB27 CAN_F12R1_FB8_Msk TIM_EGR_UG SDIO_STA_TXACT CAN_F9R2_FB6_Msk CAN_F9R2_FB2 EXTI_EMR_MR18_Msk CAN_F3R1_FB30_Msk CAN_MSR_SAMP I2C_CR2_ITBUFEN_Pos EXTI_SWIER_SWIER15_Pos EXTI_FTSR_TR6 PWR_CR_PLS_Pos WWDG_CFR_WDGTB_Pos CAN_F10R1_FB9 PIN_OPT_RESISTOR_PULLUP CAN_F1R2_FB8 CAN_F11R2_FB24_Pos DMA_IFCR_CHTIF5_Pos RCC_CFGR_ADCPRE_DIV2 USART_CR3_HDSEL_Pos DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos CAN_F9R2_FB10_Msk DMA_IFCR_CTCIF1 IWDG_KR_KEY_Pos ADC_JSQR_JSQ2 CAN_F9R2_FB24_Msk
+syn keyword CTagsDefinedName GPIO_BSRR_BR2 USB_COUNT4_RX_0_NUM_BLOCK_0_3 CAN_F13R1_FB21_Msk SDIO_MASK_TXACTIE PWR DBGMCU_CR_DBG_STOP_Msk USB_EP7R_DTOG_RX CAN_RDL1R_DATA3_Pos CAN_F3R2_FB0 CAN_F1R2_FB30 TIM_CCMR2_IC3F_3 RCC_CFGR_HPRE_2 ADC_JDR4_JDATA_Pos TIM_CCMR1_OC1PE_Pos USB_COUNT0_RX_1_NUM_BLOCK_1_3 CAN_F11R2_FB12 ADC_SMPR2_SMP3_2 USB_COUNT4_RX_BLSIZE_Msk TIM1_TRG_COM_TIM17_IRQn RCC_CFGR_HPRE_DIV_256 CAN_F3R2_FB3_Msk CAN_F5R1_FB20 USART_GTPR_GT_Msk USB_EP5R_STAT_TX_1 CAN_F13R2_FB19_Msk CAN_F10R2_FB17_Pos
+syn keyword CTagsDefinedName DMA_IFCR_CHTIF3_Pos EXTI_EMR_EM11 CAN_TI0R_EXID CAN_F11R2_FB3_Msk DMA_CCR_TEIE_Msk SPI_CR1_BR_2 ADC_SMPR2_SMP0_Pos CAN_F7R2_FB5_Pos CAN_F1R2_FB6 GPIO_LCKR_LCK10_Pos AFIO_EXTICR3_EXTI9_Pos GPIO_CRL_MODE5 TIM_CCER_CC1P_Pos CAN_F2R2_FB12 CAN_F12R2_FB2 AFIO_EXTICR2_EXTI6_PC_Msk CAN_F12R2_FB1_Msk CAN_F9R2_FB16 AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk CAN_FM1R_FBM1 RCC_CFGR_MCOSEL_HSE TIM1_TRG_COM_TIM11_IRQn ADC_SQR3_SQ5_2 GPIO_BRR_BR6 CAN_F8R1_FB17_Msk USB_EP6R_EP_TYPE_1
+syn keyword CTagsDefinedName AFIO_EXTICR2_EXTI5_PG USB_CNTR_PDWN_Pos AFIO_EXTICR3_EXTI11_PG_Msk FLASH_CR_OPTWRE RCC_CR_PLLON I2C_CR2_FREQ_0 AFIO_MAPR_TIM2_REMAP_1 USB_EP5R_CTR_RX CAN_F13R2_FB24_Pos CAN_F1R1_FB27_Msk RTC_ALRL_RTC_ALR_Pos CAN_F13R1_FB2 CAN_F10R1_FB31_Msk CAN_ESR_REC FLASH_OBR_IWDG_SW_Msk AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk CAN_MCR_NART_Pos USB_EP3R_STAT_TX_1 CAN_F5R2_FB24_Pos TIM_DIER_BIE_Msk USART_CR1_TCIE_Msk _TIMER_H_ AFIO_EVCR_PORT_PB PIN_6 CAN_F2R1_FB21_Pos AFIO_EXTICR4_EXTI14_PD_Msk
+syn keyword CTagsDefinedName AFIO_MAPR_USART3_REMAP_PARTIALREMAP CAN_F8R1_FB11 CAN_F8R2_FB18_Pos EXTI_RTSR_TR18 ADC_SMPR2_SMP4 GPIO_BSRR_BS15_Pos EXTI_SWIER_SWI8 EXTI_PR_PR7_Pos EXTI_SWIER_SWIER3 CAN_F1R1_FB4 CAN_F6R1_FB27_Msk RTC_CRL_OWF_Msk CAN_RDH0R_DATA4_Pos FLASH_WRP1_nWRP1 USART_CR1_IDLEIE_Msk CAN_F13R2_FB23_Pos CAN_F5R1_FB28 USB_EP_KIND_Msk RCC_APB1RSTR_WWDGRST_Msk CAN_F13R1_FB2_Pos DMA_ISR_TCIF4_Pos RCC_CR_HSIRDY CAN_IER_WKUIE_Pos CAN_RF0R_FMP0_Pos ADC_CR1_DISCNUM_1 RCC_CR_HSEON_Msk
+syn keyword CTagsDefinedName CAN_RI0R_EXID_Msk EXTI_FTSR_TR15 SDIO_MASK_RXOVERRIE_Msk AFIO_EXTICR2_EXTI7_PF USB_EP7R_STAT_RX_Msk GPIO_CRH_MODE11_Pos USB_EP7R_EP_TYPE_Msk USART_CR2_LBCL CAN_F0R2_FB28 DMA_CCR_EN_Pos CAN_F3R2_FB0_Msk CAN_TDT0R_TIME_Msk CAN_F11R1_FB3_Msk EXTI_EMR_MR2_Pos ADC_JDR2_JDATA_Pos CAN_F6R2_FB9_Pos SDIO_ICR_DCRCFAILC_Msk EXTI_SWIER_SWIER11_Pos EXTI_EMR_MR14_Msk AFIO_EXTICR4_EXTI15_PE_Msk USB_COUNT5_RX_NUM_BLOCK_Pos CAN_F10R1_FB26_Pos DBGMCU_CR_DBG_TIM2_STOP CAN_F1R2_FB29_Msk
+syn keyword CTagsDefinedName CAN_F9R1_FB13_Msk RCC_CR_HSIRDY_Pos USB_EP_RX_VALID CAN_F6R2_FB7_Pos GPIO_BSRR_BS7 TIM_CNT_CNT USB_EP5R_STAT_RX_0 FLASH_ACR_LATENCY_1 EXTI_IMR_MR0 CAN_F5R1_FB1_Pos CAN_F4R2_FB26 CAN_F5R1_FB15_Msk CAN_F1R1_FB22 CAN_F5R1_FB10_Msk CAN_F7R2_FB13_Pos DBGMCU_CR_DBG_TIM2_STOP_Msk EXTI_IMR_MR16_Msk RTC_DIVL_RTC_DIV_Pos RCC_CFGR_MCO_SYSCLK CAN_F9R1_FB15_Msk RCC_CFGR_MCOSEL_2 CAN_F7R2_FB14_Msk CAN_F6R1_FB1_Pos SDIO_STA_DCRCFAIL CAN_F0R1_FB5_Msk ADC_SQR2_SQ9_1 CAN_TSR_TERR1
+syn keyword CTagsDefinedName SPI_CR1_LSBFIRST CAN_TDH1R_DATA4 CAN_F5R2_FB3_Pos CAN_F7R1_FB29_Pos CAN_FM1R_FBM1_Msk GPIO_IDR_IDR15_Pos CAN_F7R2_FB14 USB_COUNT2_RX_NUM_BLOCK CAN_F8R2_FB23 TIM_CR1_DIR_Msk GPIO_CRH_MODE14_1 CAN_F7R1_FB6_Msk CAN_F11R1_FB23_Pos CAN_F13R2_FB12_Msk SPI_SR_MODF_Pos EXTI_EMR_MR6 CAN_F13R2_FB16 RCC_CIR_HSERDYC_Msk CAN_F9R2_FB29_Pos ADC_SR_JSTRT CAN_F1R2_FB23_Pos SPI_CR1_BR_1 CAN_F7R2_FB6_Msk CAN_F6R2_FB17 CAN_F10R1_FB8_Pos CAN_F6R1_FB2 RCC_AHBENR_FLITFEN_Msk CAN_FA1R_FACT13_Msk
+syn keyword CTagsDefinedName USB_EP5R_STAT_RX_Msk RCC_APB2RSTR_TIM1RST_Pos CAN_F5R1_FB28_Pos I2C_CR1_ENARP_Pos USB_EP_SETUP_Msk CAN_F0R1_FB7_Pos CAN_F1R2_FB20 GPIO_IDR_IDR13 DMA_ISR_TEIF1_Msk I2C_SR1_ARLO AFIO_EXTICR4_EXTI12_PB_Msk PIN_OPT_AF5 TIM_CR1_ARPE_Msk PWM_CHANNEL_2 CAN_F5R1_FB23_Msk SPI_SR_CRCERR_Pos CAN_F10R1_FB16_Pos USB_COUNT1_RX_1_NUM_BLOCK_1_0 RCC_CFGR_PLLMULL6 CAN_TI2R_IDE CAN_F11R2_FB3 CAN_F9R2_FB28_Pos CAN_FM1R_FBM0_Msk GPIO_CRL_CNF4_Pos CAN_ESR_BOFF_Msk RCC_APB2RSTR_USART1RST_Pos
+syn keyword CTagsDefinedName ADC_JDR2_JDATA_Msk SDIO_MASK_CCRCFAILIE_Pos BKP_DR8_D_Msk TIM_CR2_OIS2N_Msk CAN_F9R1_FB18 SDIO_STA_CMDACT_Pos USART_GTPR_GT_Pos CAN_F8R2_FB16 PWR_CR_PVDE_Msk USART_CR3_IRLP_Pos SDIO_POWER_PWRCTRL_Pos GPIOD GPIO_ODR_ODR7 RCC_CIR_LSERDYF USB_DADDR_ADD_Pos RCC_CFGR_PLLMULL10_Pos CAN_RDH1R_DATA4_Pos GPIO_BRR_BR0_Msk ADC_SR_STRT_Pos AFIO_EXTICR2_EXTI6_PE_Pos CAN_F2R1_FB3 CAN_F6R1_FB22_Pos CAN_F10R2_FB4_Pos CAN_F12R1_FB31_Pos CAN_F8R2_FB26_Msk CAN_F12R2_FB2_Msk CAN_F10R2_FB11
+syn keyword CTagsDefinedName USB_COUNT1_RX_NUM_BLOCK ADC_CR2_EXTTRIG CAN_F6R2_FB22_Pos AFIO_MAPR_CAN_REMAP_0
+