|
|
123ef70487
|
Changed Memory to Peripheral
The "Memory" name is too restrictive given that the bus itself
implement that trait.
|
2022-05-08 21:00:51 +02:00 |
|
|
|
1b9c73c432
|
Tested and fixed all instructions
! something might still be bugged since the test program is failing,
although not in an obvious manner
|
2022-04-07 15:32:28 +02:00 |
|
|
|
051cfe6611
|
Finished implementing instructions
+ added all legal instructions
|
2022-02-21 21:17:11 +01:00 |
|
|
|
012992c4ad
|
Got first CPU instructions working
+ added interface
+ added CPU, Bus, and memory implementations
+ implemented a few CPU instructions
|
2022-02-15 22:24:58 +01:00 |
|
|
|
8cc0019dca
|
Initial commit
|
2022-02-01 19:38:27 +01:00 |
|
