Steins7/stm32f1xx_HBL
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Use TC instead of TXE

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Transfer Complete is preferable to TX Empty when using a DMA since we could be
polling the bit between transfers. TXE would be 1 but the DMA would be
transfering another at the same time. TC takes the DMA into account
This commit is contained in:
Steins7 2023-09-24 18:35:36 +02:00
parent dbfba20520
commit 0628c4c07c
1 changed files with 1 additions and 1 deletions
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2
drv/usart.c
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@ -107,7 +107,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
if (buffer->buffers) { if (buffer->buffers) {
//if the tx register is empty, there is no need to go through the dma //if the tx register is empty, there is no need to go through the dma
if (regs->SR.TXE) { if (regs->SR.TC) {
reg_write(regs->DR, USART_DR_DR, byte); reg_write(regs->DR, USART_DR_DR, byte);
//enable IRQ, disable DMA //enable IRQ, disable DMA
reg_reset(regs->CR3, USART_CR3_DMAT); reg_reset(regs->CR3, USART_CR3_DMAT);