Define tim module's registers
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6d95bce6df
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93f1b5a992
455
drv/tim_regs.h
Normal file
455
drv/tim_regs.h
Normal file
@ -0,0 +1,455 @@
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/** @file tim_regs.h
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* Module defining the TIMers registers.
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*
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* Mainly made to be used by the tim module. It is recommanded to go through
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* the functions provided by that module instead of directly using the registers
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* defined here.
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*/
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#ifndef _TIM_REGS_H_
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#define _TIM_REGS_H_
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//--includes--------------------------------------------------------------------
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#include "stdint.h"
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//--type definitions------------------------------------------------------------
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#define TIM1_BASE_ADDRESS 0x40012C00
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#define TIM2_BASE_ADDRESS 0x40000000
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#define TIM3_BASE_ADDRESS 0x40000400
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#define TIM4_BASE_ADDRESS 0x40000800
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union TIM_CR1 {
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struct {
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uint32_t CEN:1;
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uint32_t UDIS:1;
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uint32_t URS:1;
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uint32_t OPM:1;
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uint32_t DIR:1;
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uint32_t CMS:2;
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uint32_t ARPE:1;
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uint32_t CKD:2;
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uint32_t reserved1:22;
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};
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uint32_t word;
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};
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union TIM_CR2 {
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struct {
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uint32_t reserved1:3;
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uint32_t CCDS:1;
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uint32_t MMS:3;
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uint32_t TI1S:1;
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uint32_t reserved2:24;
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};
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uint32_t word;
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};
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union TIM_ADV_CR2 {
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struct {
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uint32_t CCPC:1;
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uint32_t reserved1:1;
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uint32_t CCUS:1;
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uint32_t CCDS:1;
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uint32_t MMS:3;
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uint32_t TI1S:1;
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uint32_t OI1S:1;
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uint32_t OIS1N:1;
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uint32_t OIS2:1;
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uint32_t OIS2N:1;
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uint32_t OIS3:1;
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uint32_t OIS3N:1;
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uint32_t OIS4:1;
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uint32_t reserved2:17;
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};
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uint32_t word;
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};
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union TIM_SMCR {
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struct {
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uint32_t SMS:3;
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uint32_t reserved1:1;
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uint32_t TS:3;
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uint32_t MSM:1;
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uint32_t ETF:4;
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uint32_t ETPS:2;
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uint32_t ECE:1;
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uint32_t ETP:1;
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uint32_t reserved2:16;
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};
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uint32_t word;
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};
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union TIM_DIER {
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struct {
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uint32_t UIE:1;
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uint32_t CC1IE:1;
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uint32_t CC2IE:1;
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uint32_t CC3IE:1;
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uint32_t CC4IE:1;
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uint32_t reserved1:1;
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uint32_t TIE:1;
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uint32_t reserved2:1;
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uint32_t UDE:1;
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uint32_t CC1DE:1;
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uint32_t CC2DE:1;
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uint32_t CC3DE:1;
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uint32_t CC4DE:1;
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uint32_t COMDE:1;
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uint32_t TDE:1;
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uint32_t reserved3:17;
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};
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uint32_t word;
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};
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union TIM_ADV_DIER {
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struct {
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uint32_t UIE:1;
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uint32_t CC1IE:1;
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uint32_t CC2IE:1;
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uint32_t CC3IE:1;
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uint32_t CC4IE:1;
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uint32_t COMIE:1;
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uint32_t TIE:1;
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uint32_t BIE:1;
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uint32_t UDE:1;
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uint32_t CC1DE:1;
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uint32_t CC2DE:1;
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uint32_t CC3DE:1;
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uint32_t CC4DE:1;
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uint32_t COMDE:1;
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uint32_t TDE:1;
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uint32_t reserved1:17;
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};
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uint32_t word;
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};
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union TIM_SR {
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struct {
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uint32_t UIF:1;
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uint32_t CC1IF:1;
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uint32_t CC2IF:1;
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uint32_t CC3IF:1;
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uint32_t CC4IF:1;
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uint32_t reserved1:1;
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uint32_t TIF:1;
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uint32_t reserved2:2;
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uint32_t CC1OF:1;
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uint32_t CC2OF:1;
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uint32_t CC3OF:1;
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uint32_t CC4OF:1;
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uint32_t reserved3:19;
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};
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uint32_t word;
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};
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union TIM_ADV_SR {
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struct {
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uint32_t UIF:1;
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uint32_t CC1IF:1;
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uint32_t CC2IF:1;
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uint32_t CC3IF:1;
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uint32_t CC4IF:1;
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uint32_t COMIF:1;
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uint32_t TIF:1;
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uint32_t BIF:1;
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uint32_t reserved1:1;
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uint32_t CC1OF:1;
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uint32_t CC2OF:1;
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uint32_t CC3OF:1;
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uint32_t CC4OF:1;
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uint32_t reserved2:19;
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};
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uint32_t word;
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};
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union TIM_EGR {
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struct {
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uint32_t UG:1;
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uint32_t CC1G:1;
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uint32_t CC2G:1;
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uint32_t CC3G:1;
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uint32_t CC4G:1;
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uint32_t reserved1:1;
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uint32_t TG:1;
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uint32_t reserved2:25;
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};
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uint32_t word;
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};
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union TIM_ADV_EGR {
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struct {
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uint32_t UG:1;
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uint32_t CC1G:1;
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uint32_t CC2G:1;
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uint32_t CC3G:1;
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uint32_t CC4G:1;
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uint32_t COMG:1;
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uint32_t TG:1;
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uint32_t BG:1;
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uint32_t reserved1:24;
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};
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uint32_t word;
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};
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union TIM_CCMR1_INPUT {
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struct {
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uint32_t CC1S:2;
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uint32_t OC1FE:1;
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uint32_t OC1PE:1;
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uint32_t OC1M:3;
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uint32_t OC1CE:1;
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uint32_t CC2S:2;
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uint32_t OC2FE:1;
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uint32_t OC2PE:1;
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uint32_t OC2M:3;
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uint32_t OC2CE:1;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCMR1_OUTPUT {
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struct {
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uint32_t CC1S:2;
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uint32_t IC1PSC:2;
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uint32_t IC1F:4;
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uint32_t CC2S:2;
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uint32_t IC2PSC:2;
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uint32_t IC2F:4;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCMR1 {
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union TIM_CCMR1_INPUT input;
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union TIM_CCMR1_OUTPUT output;
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};
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union TIM_CCMR2_INPUT {
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struct {
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uint32_t CC3S:2;
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uint32_t OC3FE:1;
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uint32_t OC3PE:1;
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uint32_t OC3M:3;
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uint32_t OC3CE:1;
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uint32_t CC4S:2;
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uint32_t OC4FE:1;
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uint32_t OC4PE:1;
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uint32_t OC4M:3;
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uint32_t OC4CE:1;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCMR2_OUTPUT {
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struct {
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uint32_t CC3S:2;
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uint32_t IC3PSC:2;
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uint32_t IC3F:4;
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uint32_t CC4S:2;
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uint32_t IC4PSC:2;
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uint32_t IC4F:4;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCMR2 {
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union TIM_CCMR2_INPUT input;
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union TIM_CCMR2_OUTPUT output;
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};
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union TIM_CCER {
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struct {
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uint32_t CC1E:1;
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uint32_t CC1P:1;
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uint32_t reserved1:2;
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uint32_t CC2E:1;
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uint32_t CC2P:1;
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uint32_t reserved2:2;
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uint32_t CC3E:1;
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uint32_t CC3P:1;
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uint32_t reserved3:2;
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uint32_t CC4E:1;
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uint32_t CC4P:1;
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uint32_t reserved4:18;
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};
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uint32_t word;
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};
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union TIM_ADV_CCER {
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struct {
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uint32_t CC1E:1;
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uint32_t CC1P:1;
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uint32_t CC1NE:1;
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uint32_t CC1NP:1;
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uint32_t CC2E:1;
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uint32_t CC2P:1;
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uint32_t CC2NE:1;
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uint32_t CC2NP:1;
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uint32_t CC3E:1;
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uint32_t CC3P:1;
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uint32_t CC3NE:1;
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uint32_t CC3NP:1;
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uint32_t CC4E:1;
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uint32_t CC4P:1;
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uint32_t CC4NE:1;
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uint32_t CC4NP:1;
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uint32_t reserved1:18;
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};
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uint32_t word;
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};
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union TIM_CNT {
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struct {
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uint32_t CNT:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_PSC {
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struct {
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uint32_t PSC:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_ARR {
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struct {
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uint32_t ARR:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_ADV_RCR {
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struct {
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uint32_t REP:8;
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uint32_t reserved1:24;
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};
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uint32_t word;
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};
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union TIM_CCR1 {
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struct {
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uint32_t CCR1:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCR2 {
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struct {
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uint32_t CCR2:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCR3 {
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struct {
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uint32_t CCR3:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_CCR4 {
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struct {
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uint32_t CCR4:16;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_ADV_BDTR {
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struct {
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uint32_t DT:8;
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uint32_t LOCK:2;
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uint32_t OSSI:1;
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uint32_t OSSR:1;
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uint32_t BKE:1;
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uint32_t BKP:1;
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uint32_t AOE:1;
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uint32_t MOE:1;
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uint32_t reserved1:16;
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};
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uint32_t word;
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};
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union TIM_DCR {
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struct {
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uint32_t DBA:5;
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uint32_t reserved1:3;
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uint32_t MBL:5;
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uint32_t reserved2:19;
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};
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uint32_t word;
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};
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union TIM_DMAR {
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struct {
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uint32_t DMAB;
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};
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uint32_t word;
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};
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struct TIM {
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union TIM_CR1 cr1;
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union TIM_CR2 cr2;
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union TIM_SMCR smcr;
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union TIM_DIER dier;
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union TIM_SR sr;
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union TIM_EGR egr;
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union TIM_CCMR1 ccmr1;
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union TIM_CCMR2 ccmr2;
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union TIM_CCER ccer;
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union TIM_CNT cnt;
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union TIM_PSC psc;
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union TIM_ARR arr;
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uint32_t reserved1;
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union TIM_CCR1 ccr1;
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union TIM_CCR2 ccr2;
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union TIM_CCR3 ccr3;
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union TIM_CCR4 ccr4;
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uint32_t reserved2;
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union TIM_DCR dcr;
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union TIM_DMAR dmar;
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};
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struct TIM_ADV {
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union TIM_CR1 cr1;
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union TIM_ADV_CR2 cr2;
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union TIM_SMCR smcr;
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union TIM_ADV_DIER dier;
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union TIM_ADV_SR sr;
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union TIM_ADV_EGR egr;
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union TIM_CCMR1 ccmr1;
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union TIM_CCMR2 ccmr2;
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union TIM_ADV_CCER ccer;
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union TIM_CNT cnt;
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union TIM_PSC psc;
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union TIM_ARR arr;
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union TIM_ADV_RCR rcr;
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union TIM_CCR1 ccr1;
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union TIM_CCR2 ccr2;
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union TIM_CCR3 ccr3;
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union TIM_CCR4 ccr4;
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union TIM_ADV_BDTR bdtr;
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union TIM_DCR dcr;
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union TIM_DMAR dmar;
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};
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//--functions-------------------------------------------------------------------
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#endif //_TIM_REGS_H_
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