3 Commits

Author	SHA1	Message	Date
Steins7	e1097048a6	RAM initialisation fixed in 086f915	2023-09-24 22:04:38 +02:00
Steins7	0628c4c07c	Use TC instead of TXE ... Transfer Complete is preferable to TX Empty when using a DMA since we could be polling the bit between transfers. TXE would be 1 but the DMA would be transfering another at the same time. TC takes the DMA into account	2023-09-24 18:35:36 +02:00
Steins7	a7099d5dfd	Rename drivers folder to drv	2023-09-21 20:42:16 +02:00