Steins7/stm32f1xx_HBL
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rework #4

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Steins7 merged 88 commits from rework into dev 2024-04-20 18:20:23 +00:00
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Showing only changes of commit 0628c4c07c - Show all commits

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drv/usart.c
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@ -107,7 +107,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
if (buffer->buffers) {
//if the tx register is empty, there is no need to go through the dma
if (regs->SR.TXE) {
if (regs->SR.TC) {
reg_write(regs->DR, USART_DR_DR, byte);
//enable IRQ, disable DMA
reg_reset(regs->CR3, USART_CR3_DMAT);