drivers/rcc.c

@@ -14,6 +14,7 @@
 
 //--local definitions-----------------------------------------------------------
 
+#define AHB_MASK  0x00000557
 #define APB1_MASK 0x3afec9ff
 #define APB2_MASK 0x0038fffd
 
@@ -56,6 +57,16 @@ void rcc_configure(enum RccPreset preset)
 	regs->APB2ENR = apb2_enr;
 }
 
+void rcc_enable_ahb(enum RccAhb mask)
+{
+	regs->AHBENR.word |= mask & AHB_MASK;
+}
+
+void rcc_disable_ahb(enum RccAhb mask)
+{
+	regs->AHBENR.word &= !(mask & AHB_MASK);
+}
+
 void rcc_enable_apb1(enum RccApb1 mask)
 {
 	regs->APB1ENR.word |= mask & APB1_MASK;

drivers/rcc.h

@@ -23,6 +23,20 @@ enum RccPreset {
 	RCC_PRESET_SPEED,   //highest clocks, uses 8MHz HSE if available
 };
 
+/**
+ * Available peripherals on the AHB bus. Note that some of these peripherals
+ * may not be availables on all chips
+ */
+enum RccAhb {
+	RCC_AHB_DMA1  = (0x1 <<  0),
+	RCC_AHB_DMA2  = (0x1 <<  1),
+	RCC_AHB_SRAM  = (0x1 <<  2),
+	RCC_AHB_FLITF = (0x1 <<  4),
+	RCC_AHB_CRC   = (0x1 <<  6),
+	RCC_AHB_FSMC  = (0x1 <<  8),
+	RCC_AHB_SDIO  = (0x1 << 10),
+};
+
 /**
  * Available peripherals on the APB1 bus. Note that some of these peripherals
  * may not be availables on all chips
@@ -89,6 +103,16 @@ enum RccApb2 {
  */
 void rcc_configure(enum RccPreset preset);
 
+/**
+ * Enables peripherals on the AHB bus
+ */
+void rcc_enable_ahb(enum RccAhb mask);
+
+/**
+ * Disables peripherals on the AHB bus
+ */
+void rcc_disable_ahb(enum RccAhb mask);
+
 /**
  * Enables peripherals on the APB1 bus
  */