Steins7/stm32f1xx_HBL
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rework #4

Merged
Steins7 merged 88 commits from rework into dev 2024-04-20 18:20:23 +00:00
Conversation 0 Commits 88 Files Changed 91 +20 -16
2 changed files with 20 additions and 16 deletions
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Showing only changes of commit 9f2b337abf - Show all commits

30
drivers/dma.c
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@ -28,14 +28,16 @@ static void configure_dma(volatile struct DMA* dma, enum DmaChannel channel,
static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS; static volatile struct DMA* const dma1 = (struct DMA*)DMA1_BASE_ADDRESS;
static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS; static volatile struct DMA* const dma2 = (struct DMA*)DMA2_BASE_ADDRESS;
static DmaCallback dma1_callbacks[7]; static DmaCallback dma1_callbacks[7];
static void* dma1_cb_params[7];
static DmaCallback dma2_callbacks[5]; static DmaCallback dma2_callbacks[5];
static void* dma2_cb_params[5];
//--public functions------------------------------------------------------------ //--public functions------------------------------------------------------------
void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
enum DmaConfig config_mask, void* periph, void* mem, enum DmaConfig config_mask, void* periph, void* mem,
uint16_t size, DmaCallback callback) uint16_t size, DmaCallback callback, void* cb_param)
{ {
//reset peripheral first, to ensure proper configuration //reset peripheral first, to ensure proper configuration
dma_reset(dma, channel); dma_reset(dma, channel);
@ -46,6 +48,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
configure_dma(dma1, channel, config_mask, periph, mem, size); configure_dma(dma1, channel, config_mask, periph, mem, size);
if (callback) { if (callback) {
dma1_callbacks[channel] = callback; dma1_callbacks[channel] = callback;
dma1_cb_params[channel] = cb_param;
nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel); nvic_enable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
} }
break; break;
@ -54,6 +57,7 @@ void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
configure_dma(dma2, channel, config_mask, periph, mem, size); configure_dma(dma2, channel, config_mask, periph, mem, size);
if (callback) { if (callback) {
dma2_callbacks[channel] = callback; dma2_callbacks[channel] = callback;
dma2_cb_params[channel] = cb_param;
nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel); nvic_enable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
} }
break; break;
@ -206,7 +210,7 @@ void hdr_dma1_channel1(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF1); reg_set(dma1->IFCR, DMA_IFCR_CGIF1);
dma1_callbacks[0](src); dma1_callbacks[0](src, dma1_cb_params[0]);
} }
void hdr_dma1_channel2(void) void hdr_dma1_channel2(void)
@ -216,7 +220,7 @@ void hdr_dma1_channel2(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF2); reg_set(dma1->IFCR, DMA_IFCR_CGIF2);
dma1_callbacks[1](src); dma1_callbacks[1](src, dma1_cb_params[1]);
} }
void hdr_dma1_channel3(void) void hdr_dma1_channel3(void)
@ -226,7 +230,7 @@ void hdr_dma1_channel3(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF3); reg_set(dma1->IFCR, DMA_IFCR_CGIF3);
dma1_callbacks[2](src); dma1_callbacks[2](src, dma1_cb_params[2]);
} }
void hdr_dma1_channel4(void) void hdr_dma1_channel4(void)
@ -236,7 +240,7 @@ void hdr_dma1_channel4(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF4); reg_set(dma1->IFCR, DMA_IFCR_CGIF4);
dma1_callbacks[3](src); dma1_callbacks[3](src, dma1_cb_params[3]);
} }
void hdr_dma1_channel5(void) void hdr_dma1_channel5(void)
@ -246,7 +250,7 @@ void hdr_dma1_channel5(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF5); reg_set(dma1->IFCR, DMA_IFCR_CGIF5);
dma1_callbacks[4](src); dma1_callbacks[4](src, dma1_cb_params[4]);
} }
void hdr_dma1_channel6(void) void hdr_dma1_channel6(void)
@ -256,7 +260,7 @@ void hdr_dma1_channel6(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF6); reg_set(dma1->IFCR, DMA_IFCR_CGIF6);
dma1_callbacks[5](src); dma1_callbacks[5](src, dma1_cb_params[5]);
} }
void hdr_dma1_channel7(void) void hdr_dma1_channel7(void)
@ -266,7 +270,7 @@ void hdr_dma1_channel7(void)
enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF7); reg_set(dma1->IFCR, DMA_IFCR_CGIF7);
dma1_callbacks[6](src); dma1_callbacks[6](src, dma1_cb_params[6]);
} }
void hdr_dma2_channel1(void) void hdr_dma2_channel1(void)
@ -276,7 +280,7 @@ void hdr_dma2_channel1(void)
enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF1); reg_set(dma2->IFCR, DMA_IFCR_CGIF1);
dma1_callbacks[0](src); dma2_callbacks[0](src, dma2_cb_params[0]);
} }
void hdr_dma2_channel2(void) void hdr_dma2_channel2(void)
@ -286,7 +290,7 @@ void hdr_dma2_channel2(void)
enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF2); reg_set(dma2->IFCR, DMA_IFCR_CGIF2);
dma2_callbacks[1](src); dma2_callbacks[1](src, dma2_cb_params[1]);
} }
void hdr_dma2_channel3(void) void hdr_dma2_channel3(void)
@ -296,7 +300,7 @@ void hdr_dma2_channel3(void)
enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF3); reg_set(dma2->IFCR, DMA_IFCR_CGIF3);
dma2_callbacks[2](src); dma2_callbacks[2](src, dma2_cb_params[2]);
} }
void hdr_dma2_channel4_5(void) void hdr_dma2_channel4_5(void)
@ -306,13 +310,13 @@ void hdr_dma2_channel4_5(void)
enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7;
if (src != 0) { if (src != 0) {
reg_set(dma2->IFCR, DMA_IFCR_CGIF4); reg_set(dma2->IFCR, DMA_IFCR_CGIF4);
dma1_callbacks[3](src); dma1_callbacks[3](src, dma2_cb_params[3]);
} }
src = (dma2->IFCR.word >> 17) & 0x7; src = (dma2->IFCR.word >> 17) & 0x7;
if (src != 0) { if (src != 0) {
reg_set(dma2->IFCR, DMA_IFCR_CGIF5); reg_set(dma2->IFCR, DMA_IFCR_CGIF5);
dma1_callbacks[4](src); dma1_callbacks[4](src, dma2_cb_params[4]);
} }
} }

6
drivers/dma.h
View File

@ -75,18 +75,18 @@ enum DmaIRQSource {
DMA_IQR_SOURCE_ERROR = (0x2 << 3), DMA_IQR_SOURCE_ERROR = (0x2 << 3),
}; };
typedef void (*DmaCallback)(enum DmaIRQSource); typedef void (*DmaCallback)(enum DmaIRQSource, void* param);
//--functions------------------------------------------------------------------- //--functions-------------------------------------------------------------------
void dma_configure(enum DmaPeriph dma, enum DmaChannel channel, void dma_configure(enum DmaPeriph dma, enum DmaChannel channel,
enum DmaConfig config_mask, void* periph, void* mem, enum DmaConfig config_mask, void* periph, void* mem,
uint16_t size, DmaCallback callback); uint16_t size, DmaCallback callback, void* cb_param);
void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel, void dma_configure_mem2mem(enum DmaPeriph dma, enum DmaChannel channel,
enum DmaConfigM2M config_mask, const void* src, void* dest, enum DmaConfigM2M config_mask, const void* src, void* dest,
uint16_t size, DmaCallback callback); uint16_t size, DmaCallback callback, void* cb_param);
void dma_reset(enum DmaPeriph dma, enum DmaChannel channel); void dma_reset(enum DmaPeriph dma, enum DmaChannel channel);