rework #4
@ -57,44 +57,26 @@ void rcc_configure(enum RccPreset preset)
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regs->APB2ENR = apb2_enr;
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regs->APB2ENR = apb2_enr;
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}
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}
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void rcc_enable_ahb(enum RccAhb mask)
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void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask)
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{
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{
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regs->AHBENR.word |= mask & AHB_MASK;
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regs->AHBENR.word |= ahb_mask & AHB_MASK;
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regs->APB1ENR.word |= apb1_mask & APB1_MASK;
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regs->APB2ENR.word |= apb2_mask & APB2_MASK;
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}
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}
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void rcc_disable_ahb(enum RccAhb mask)
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void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask)
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{
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{
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regs->AHBENR.word &= !(mask & AHB_MASK);
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regs->AHBENR.word &= !(ahb_mask & AHB_MASK);
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regs->APB1ENR.word &= !(apb1_mask & APB1_MASK);
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regs->APB2ENR.word &= !(apb2_mask & APB2_MASK);
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}
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}
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void rcc_enable_apb1(enum RccApb1 mask)
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void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask)
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{
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{
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regs->APB1ENR.word |= mask & APB1_MASK;
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regs->APB1RSTR.word &= !(apb1_mask & APB1_MASK);
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}
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regs->APB2RSTR.word &= !(apb2_mask & APB2_MASK);
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void rcc_disable_apb1(enum RccApb1 mask)
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{
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regs->APB1ENR.word &= !(mask & APB1_MASK);
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}
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void rcc_reset_apb1(enum RccApb1 mask)
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{
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regs->APB1RSTR.word &= !(mask & APB1_MASK);
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}
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void rcc_enable_apb2(enum RccApb2 mask)
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{
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regs->APB2ENR.word |= mask & APB2_MASK;
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}
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void rcc_disable_apb2(enum RccApb2 mask)
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{
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regs->APB2ENR.word &= !(mask & APB2_MASK);
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}
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void rcc_reset_apb2(enum RccApb2 mask)
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{
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regs->APB2RSTR.word &= !(mask & APB2_MASK);
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}
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}
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@ -28,6 +28,7 @@ enum RccPreset {
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* may not be availables on all chips
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* may not be availables on all chips
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*/
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*/
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enum RccAhb {
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enum RccAhb {
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RCC_AHB_NONE = 0,
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RCC_AHB_DMA1 = (0x1 << 0),
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RCC_AHB_DMA1 = (0x1 << 0),
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RCC_AHB_DMA2 = (0x1 << 1),
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RCC_AHB_DMA2 = (0x1 << 1),
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RCC_AHB_SRAM = (0x1 << 2),
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RCC_AHB_SRAM = (0x1 << 2),
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@ -42,6 +43,7 @@ enum RccAhb {
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* may not be availables on all chips
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* may not be availables on all chips
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*/
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*/
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enum RccApb1 {
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enum RccApb1 {
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RCC_APB1_NONE = 0,
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RCC_APB1_TIM2 = (0x1 << 0),
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RCC_APB1_TIM2 = (0x1 << 0),
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RCC_APB1_TIM3 = (0x1 << 1),
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RCC_APB1_TIM3 = (0x1 << 1),
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RCC_APB1_TIM4 = (0x1 << 2),
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RCC_APB1_TIM4 = (0x1 << 2),
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@ -72,6 +74,7 @@ enum RccApb1 {
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* may not be available on all chips
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* may not be available on all chips
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*/
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*/
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enum RccApb2 {
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enum RccApb2 {
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RCC_APB2_NONE = 0,
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RCC_APB2_AFOI = (0x1 << 0),
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RCC_APB2_AFOI = (0x1 << 0),
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RCC_APB2_IOPA = (0x1 << 2),
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RCC_APB2_IOPA = (0x1 << 2),
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RCC_APB2_IOPB = (0x1 << 3),
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RCC_APB2_IOPB = (0x1 << 3),
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@ -104,44 +107,27 @@ enum RccApb2 {
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void rcc_configure(enum RccPreset preset);
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void rcc_configure(enum RccPreset preset);
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/**
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/**
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* Enables peripherals on the AHB bus
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* Enables peripherals on the different buses. The enums values can used as
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* masks to enable multiple peripherals at the same time. Invalid values will be
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* ignored.
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*/
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*/
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void rcc_enable_ahb(enum RccAhb mask);
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void rcc_enable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask);
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/**
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/**
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* Disables peripherals on the AHB bus
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* Disables peripherals on the different buses. The enums values can used as
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* masks to disable multiple peripherals at the same time. Invalid values will
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* be ignored.
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*/
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*/
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void rcc_disable_ahb(enum RccAhb mask);
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void rcc_disable(enum RccAhb ahb_mask, enum RccApb1 apb1_mask,
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enum RccApb2 apb2_mask);
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/**
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/**
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* Enables peripherals on the APB1 bus
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* Resets peripherals on the different buses. The enums values can used as
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* masks to reset multiple peripherals at the same time. Invalid values will
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* be ignored.
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*/
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*/
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void rcc_enable_apb1(enum RccApb1 mask);
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void rcc_reset(enum RccApb1 apb1_mask, enum RccApb2 apb2_mask);
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/**
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* Disables peripherals on the APB1 bus
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*/
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void rcc_disable_apb1(enum RccApb1 mask);
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/**
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* Resets peripherals on the APB1 bus
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*/
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void rcc_reset_apb1(enum RccApb1 mask);
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/**
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* Enables peripherals on the APB2 bus
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*/
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void rcc_enable_apb2(enum RccApb2 mask);
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/**
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* Disables peripherals on the APB2 bus
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*/
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void rcc_disable_apb2(enum RccApb2 mask);
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/**
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* Resets peripherals on the APB2 bus
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*/
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void rcc_reset_apb2(enum RccApb2 mask);
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#endif //_RCC_H_
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#endif //_RCC_H_
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Reference in New Issue
Block a user