Steins7/stm32f1xx_HBL
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task #5

Merged
Steins7 merged 35 commits from task into dev 2024-08-04 18:30:16 +00:00
Conversation 0 Commits 35 Files Changed 34 +140 -654
16 changed files with 140 additions and 654 deletions
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Showing only changes of commit 5e4d87474a - Show all commits

16
drv/afio_regs.h
View File

@ -19,7 +19,7 @@
#define AFIO_BASE_ADDRESS 0x40010000 #define AFIO_BASE_ADDRESS 0x40010000
union EVCR { union EVCR {
struct __attribute__((packed)) { struct {
uint32_t PIN:4; uint32_t PIN:4;
uint32_t PORT:3; uint32_t PORT:3;
uint32_t EVOE:1; uint32_t EVOE:1;
@ -29,7 +29,7 @@ union EVCR {
}; };
union MAPR { union MAPR {
struct __attribute__((packed)) { struct {
uint32_t SPI1_REMAP:1; uint32_t SPI1_REMAP:1;
uint32_t I2C1_REMAP:1; uint32_t I2C1_REMAP:1;
uint32_t USART1_REMAP:1; uint32_t USART1_REMAP:1;
@ -54,7 +54,7 @@ union MAPR {
}; };
union EXTICR1 { union EXTICR1 {
struct __attribute__((packed)) { struct {
uint32_t EXTI0:4; uint32_t EXTI0:4;
uint32_t EXTI1:4; uint32_t EXTI1:4;
uint32_t EXTI2:4; uint32_t EXTI2:4;
@ -65,7 +65,7 @@ union EXTICR1 {
}; };
union EXTICR2 { union EXTICR2 {
struct __attribute__((packed)) { struct {
uint32_t EXTI4:4; uint32_t EXTI4:4;
uint32_t EXTI5:4; uint32_t EXTI5:4;
uint32_t EXTI6:4; uint32_t EXTI6:4;
@ -76,7 +76,7 @@ union EXTICR2 {
}; };
union EXTICR3 { union EXTICR3 {
struct __attribute__((packed)) { struct {
uint32_t EXTI8:4; uint32_t EXTI8:4;
uint32_t EXTI9:4; uint32_t EXTI9:4;
uint32_t EXTI10:4; uint32_t EXTI10:4;
@ -87,7 +87,7 @@ union EXTICR3 {
}; };
union EXTICR4 { union EXTICR4 {
struct __attribute__((packed)) { struct {
uint32_t EXTI12:4; uint32_t EXTI12:4;
uint32_t EXTI13:4; uint32_t EXTI13:4;
uint32_t EXTI14:4; uint32_t EXTI14:4;
@ -98,7 +98,7 @@ union EXTICR4 {
}; };
union MAPR2 { union MAPR2 {
struct __attribute__((packed)) { struct {
uint32_t reserved1:5; uint32_t reserved1:5;
uint32_t TIM9_REMAP:1; uint32_t TIM9_REMAP:1;
uint32_t TIM10_REMAP:1; uint32_t TIM10_REMAP:1;
@ -111,7 +111,7 @@ union MAPR2 {
uint32_t word; uint32_t word;
}; };
struct __attribute__((packed)) AFIO { struct AFIO {
union EVCR EVCR; union EVCR EVCR;
union MAPR MAPR; union MAPR MAPR;
union EXTICR1 EXTICR1; union EXTICR1 EXTICR1;

32
drv/dma.c
View File

@ -121,13 +121,13 @@ void dma_stop(enum DmaPeriph dma, enum DmaChannel channel)
{ {
switch (dma) { switch (dma) {
case DMA_PERIPH_1: case DMA_PERIPH_1:
reg_reset(dma1->CHANNELS[channel].CCR, DMA_CCR_EN); dma1->CHANNELS[channel].CCR.EN = 0;
if (dma1_callbacks[channel]) { if (dma1_callbacks[channel]) {
nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel); nvic_disable(NVIC_IRQ_DMA1_CHANNEL1 + channel);
} }
break; break;
case DMA_PERIPH_2: case DMA_PERIPH_2:
reg_reset(dma2->CHANNELS[channel].CCR, DMA_CCR_EN); dma2->CHANNELS[channel].CCR.EN;
if (dma2_callbacks[channel]) { if (dma2_callbacks[channel]) {
nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel); nvic_disable(NVIC_IRQ_DMA2_CHANNEL1 + channel);
} }
@ -207,11 +207,11 @@ static void start_dma(volatile struct DMA* dma, enum DmaChannel channel,
volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel]; volatile struct DMA_CHANNEL* regs = &dma->CHANNELS[channel];
//registers should already be configured, apply transfer config //registers should already be configured, apply transfer config
reg_write(regs->CNDTR, DMA_CNDTR_NDT, size); regs->CNDTR.NDT = size;
regs->CMAR = (uint32_t)mem; regs->CMAR = (uint32_t)mem;
//only start transfer when everything is configured //only start transfer when everything is configured
reg_set(regs->CCR, DMA_CCR_EN); regs->CCR.EN = 1;
} }
//--ISRs------------------------------------------------------------------------ //--ISRs------------------------------------------------------------------------
@ -221,7 +221,7 @@ void hdr_dma1_channel1(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL1); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL1);
enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 1) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF1); dma1->IFCR.CGIF1 = 1;
dma1_callbacks[0](src, dma1_cb_params[0]); dma1_callbacks[0](src, dma1_cb_params[0]);
} }
@ -231,7 +231,7 @@ void hdr_dma1_channel2(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL2); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL2);
enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 5) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF2); dma1->IFCR.CGIF2 = 1;
dma1_callbacks[1](src, dma1_cb_params[1]); dma1_callbacks[1](src, dma1_cb_params[1]);
} }
@ -241,7 +241,7 @@ void hdr_dma1_channel3(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL3); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL3);
enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 9) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF3); dma1->IFCR.CGIF3 = 1;
dma1_callbacks[2](src, dma1_cb_params[2]); dma1_callbacks[2](src, dma1_cb_params[2]);
} }
@ -251,7 +251,7 @@ void hdr_dma1_channel4(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL4); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL4);
enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 13) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF4); dma1->IFCR.CGIF4 = 1;
dma1_callbacks[3](src, dma1_cb_params[3]); dma1_callbacks[3](src, dma1_cb_params[3]);
} }
@ -261,7 +261,7 @@ void hdr_dma1_channel5(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL5); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL5);
enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 17) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF5); dma1->IFCR.CGIF5 = 1;
dma1_callbacks[4](src, dma1_cb_params[4]); dma1_callbacks[4](src, dma1_cb_params[4]);
} }
@ -271,7 +271,7 @@ void hdr_dma1_channel6(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL6); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL6);
enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 21) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF6); dma1->IFCR.CGIF6 = 1;
dma1_callbacks[5](src, dma1_cb_params[5]); dma1_callbacks[5](src, dma1_cb_params[5]);
} }
@ -281,7 +281,7 @@ void hdr_dma1_channel7(void)
nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL7); nvic_clear_pending(NVIC_IRQ_DMA1_CHANNEL7);
enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7; enum DmaIRQSource src = (dma1->IFCR.word >> 25) & 0x7;
reg_set(dma1->IFCR, DMA_IFCR_CGIF7); dma1->IFCR.CGIF7 = 1;
dma1_callbacks[6](src, dma1_cb_params[6]); dma1_callbacks[6](src, dma1_cb_params[6]);
} }
@ -291,7 +291,7 @@ void hdr_dma2_channel1(void)
nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL1); nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL1);
enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 1) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF1); dma2->IFCR.CGIF1 = 1;
dma2_callbacks[0](src, dma2_cb_params[0]); dma2_callbacks[0](src, dma2_cb_params[0]);
} }
@ -301,7 +301,7 @@ void hdr_dma2_channel2(void)
nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL2); nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL2);
enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 5) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF2); dma2->IFCR.CGIF2 = 1;
dma2_callbacks[1](src, dma2_cb_params[1]); dma2_callbacks[1](src, dma2_cb_params[1]);
} }
@ -311,7 +311,7 @@ void hdr_dma2_channel3(void)
nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL3); nvic_clear_pending(NVIC_IRQ_DMA2_CHANNEL3);
enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 9) & 0x7;
reg_set(dma2->IFCR, DMA_IFCR_CGIF3); dma2->IFCR.CGIF3 = 1;
dma2_callbacks[2](src, dma2_cb_params[2]); dma2_callbacks[2](src, dma2_cb_params[2]);
} }
@ -322,13 +322,13 @@ void hdr_dma2_channel4_5(void)
enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7; enum DmaIRQSource src = (dma2->IFCR.word >> 13) & 0x7;
if (src != 0) { if (src != 0) {
reg_set(dma2->IFCR, DMA_IFCR_CGIF4); dma2->IFCR.CGIF4 = 1;
dma1_callbacks[3](src, dma2_cb_params[3]); dma1_callbacks[3](src, dma2_cb_params[3]);
} }
src = (dma2->IFCR.word >> 17) & 0x7; src = (dma2->IFCR.word >> 17) & 0x7;
if (src != 0) { if (src != 0) {
reg_set(dma2->IFCR, DMA_IFCR_CGIF5); dma2->IFCR.CGIF5 = 1;
dma1_callbacks[4](src, dma2_cb_params[4]); dma1_callbacks[4](src, dma2_cb_params[4]);
} }
} }

91
drv/dma_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include "stdint.h" #include "stdint.h"
@ -22,7 +20,7 @@
#define DMA2_BASE_ADDRESS 0x40020400 #define DMA2_BASE_ADDRESS 0x40020400
union DMA_ISR { union DMA_ISR {
struct __attribute__((packed)) { struct {
uint32_t GIF1:1; uint32_t GIF1:1;
uint32_t TCIF1:1; uint32_t TCIF1:1;
uint32_t HTIF1:1; uint32_t HTIF1:1;
@ -56,38 +54,8 @@ union DMA_ISR {
uint32_t word; uint32_t word;
}; };
#define DMA_ISR_GIF1 reg_def( 0, 1)
#define DMA_ISR_TCIF1 reg_def( 1, 1)
#define DMA_ISR_HTIF1 reg_def( 2, 1)
#define DMA_ISR_TEIF1 reg_def( 3, 1)
#define DMA_ISR_GIF2 reg_def( 4, 1)
#define DMA_ISR_TCIF2 reg_def( 5, 1)
#define DMA_ISR_HTIF2 reg_def( 6, 1)
#define DMA_ISR_TEIF2 reg_def( 7, 1)
#define DMA_ISR_GIF3 reg_def( 8, 1)
#define DMA_ISR_TCIF3 reg_def( 9, 1)
#define DMA_ISR_HTIF3 reg_def(10, 1)
#define DMA_ISR_TEIF3 reg_def(11, 1)
#define DMA_ISR_GIF4 reg_def(12, 1)
#define DMA_ISR_TCIF4 reg_def(13, 1)
#define DMA_ISR_HTIF4 reg_def(14, 1)
#define DMA_ISR_TEIF4 reg_def(15, 1)
#define DMA_ISR_GIF5 reg_def(16, 1)
#define DMA_ISR_TCIF5 reg_def(17, 1)
#define DMA_ISR_HTIF5 reg_def(18, 1)
#define DMA_ISR_TEIF5 reg_def(19, 1)
#define DMA_ISR_GIF6 reg_def(20, 1)
#define DMA_ISR_TCIF6 reg_def(21, 1)
#define DMA_ISR_HTIF6 reg_def(22, 1)
#define DMA_ISR_TEIF6 reg_def(23, 1)
#define DMA_ISR_GIF7 reg_def(24, 1)
#define DMA_ISR_TCIF7 reg_def(25, 1)
#define DMA_ISR_HTIF7 reg_def(26, 1)
#define DMA_ISR_TEIF7 reg_def(27, 1)
#define DMA_ISR_reserved1 reg_def(28, 4)
union DMA_IFCR { union DMA_IFCR {
struct __attribute__((packed)) { struct {
uint32_t CGIF1:1; uint32_t CGIF1:1;
uint32_t CTCIF1:1; uint32_t CTCIF1:1;
uint32_t CHTIF1:1; uint32_t CHTIF1:1;
@ -121,38 +89,8 @@ union DMA_IFCR {
uint32_t word; uint32_t word;
}; };
#define DMA_IFCR_CGIF1 reg_def( 0, 1)
#define DMA_IFCR_CTCIF1 reg_def( 1, 1)
#define DMA_IFCR_CHTIF1 reg_def( 2, 1)
#define DMA_IFCR_CTEIF1 reg_def( 3, 1)
#define DMA_IFCR_CGIF2 reg_def( 4, 1)
#define DMA_IFCR_CTCIF2 reg_def( 5, 1)
#define DMA_IFCR_CHTIF2 reg_def( 6, 1)
#define DMA_IFCR_CTEIF2 reg_def( 7, 1)
#define DMA_IFCR_CGIF3 reg_def( 8, 1)
#define DMA_IFCR_CTCIF3 reg_def( 9, 1)
#define DMA_IFCR_CHTIF3 reg_def(10, 1)
#define DMA_IFCR_CTEIF3 reg_def(11, 1)
#define DMA_IFCR_CGIF4 reg_def(12, 1)
#define DMA_IFCR_CTCIF4 reg_def(13, 1)
#define DMA_IFCR_CHTIF4 reg_def(14, 1)
#define DMA_IFCR_CTEIF4 reg_def(15, 1)
#define DMA_IFCR_CGIF5 reg_def(16, 1)
#define DMA_IFCR_CTCIF5 reg_def(17, 1)
#define DMA_IFCR_CHTIF5 reg_def(18, 1)
#define DMA_IFCR_CTEIF5 reg_def(19, 1)
#define DMA_IFCR_CGIF6 reg_def(20, 1)
#define DMA_IFCR_CTCIF6 reg_def(21, 1)
#define DMA_IFCR_CHTIF6 reg_def(22, 1)
#define DMA_IFCR_CTEIF6 reg_def(23, 1)
#define DMA_IFCR_CGIF7 reg_def(24, 1)
#define DMA_IFCR_CTCIF7 reg_def(25, 1)
#define DMA_IFCR_CHTIF7 reg_def(26, 1)
#define DMA_IFCR_CTEIF7 reg_def(27, 1)
#define DMA_IFCR_reserved1 reg_def(28, 4)
union DMA_CCR { union DMA_CCR {
struct __attribute__((packed)) { struct {
uint32_t EN:1; uint32_t EN:1;
uint32_t TCIE:1; uint32_t TCIE:1;
uint32_t HTIE:1; uint32_t HTIE:1;
@ -170,32 +108,15 @@ union DMA_CCR {
uint32_t word; uint32_t word;
}; };
#define DMA_CCR_EN reg_def( 0, 1)
#define DMA_CCR_TCIE reg_def( 1, 1)
#define DMA_CCR_HTIE reg_def( 2, 1)
#define DMA_CCR_TEIE reg_def( 3, 1)
#define DMA_CCR_DIR reg_def( 4, 1)
#define DMA_CCR_CIRC reg_def( 5, 1)
#define DMA_CCR_PINC reg_def( 6, 1)
#define DMA_CCR_MINC reg_def( 7, 1)
#define DMA_CCR_PSIZE reg_def( 8, 2)
#define DMA_CCR_MSIZE reg_def(10, 2)
#define DMA_CCR_PL reg_def(12, 2)
#define DMA_CCR_MEM2MEM reg_def(14, 1)
#define DMA_CCR_reserved1 reg_def(15, 17)
union DMA_CNDTR { union DMA_CNDTR {
struct __attribute__((packed)) { struct {
uint32_t NDT:16; uint32_t NDT:16;
uint32_t reserved1:16; uint32_t reserved1:16;
}; };
uint32_t word; uint32_t word;
}; };
#define DMA_CNDTR_NDT reg_def( 0, 16) struct DMA_CHANNEL {
#define DMA_CNDTR_reserved1 reg_def(16, 16)
struct __attribute__((packed)) DMA_CHANNEL {
union DMA_CCR CCR; union DMA_CCR CCR;
union DMA_CNDTR CNDTR; union DMA_CNDTR CNDTR;
uint32_t CPAR; uint32_t CPAR;
@ -203,7 +124,7 @@ struct __attribute__((packed)) DMA_CHANNEL {
uint32_t reserved1; uint32_t reserved1;
}; };
struct __attribute__((packed)) DMA { struct DMA {
union DMA_ISR ISR; union DMA_ISR ISR;
union DMA_IFCR IFCR; union DMA_IFCR IFCR;
struct DMA_CHANNEL CHANNELS[7]; struct DMA_CHANNEL CHANNELS[7];

16
drv/exti.c
View File

@ -193,35 +193,35 @@ void exti_reset_peripheral(void)
void hdr_exti0(void) void hdr_exti0(void)
{ {
nvic_clear_pending(NVIC_IRQ_EXTI0); nvic_clear_pending(NVIC_IRQ_EXTI0);
reg_set(regs->PR, EXTI_PR_PR0); regs->PR.PR0 = 1;
callbacks[0](); callbacks[0]();
} }
void hdr_exti1(void) void hdr_exti1(void)
{ {
nvic_clear_pending(NVIC_IRQ_EXTI1); nvic_clear_pending(NVIC_IRQ_EXTI1);
reg_set(regs->PR, EXTI_PR_PR1); regs->PR.PR1 = 1;
callbacks[1](); callbacks[1]();
} }
void hdr_exti2(void) void hdr_exti2(void)
{ {
nvic_clear_pending(NVIC_IRQ_EXTI2); nvic_clear_pending(NVIC_IRQ_EXTI2);
reg_set(regs->PR, EXTI_PR_PR2); regs->PR.PR2 = 1;
callbacks[2](); callbacks[2]();
} }
void hdr_exti3(void) void hdr_exti3(void)
{ {
nvic_clear_pending(NVIC_IRQ_EXTI3); nvic_clear_pending(NVIC_IRQ_EXTI3);
reg_set(regs->PR, EXTI_PR_PR3); regs->PR.PR3 = 1;
callbacks[3](); callbacks[3]();
} }
void hdr_exti4(void) void hdr_exti4(void)
{ {
nvic_clear_pending(NVIC_IRQ_EXTI4); nvic_clear_pending(NVIC_IRQ_EXTI4);
reg_set(regs->PR, EXTI_PR_PR4); regs->PR.PR4 = 1;
callbacks[4](); callbacks[4]();
} }
@ -250,21 +250,21 @@ void hdr_exti15_10(void)
void hdr_pvd(void) void hdr_pvd(void)
{ {
nvic_clear_pending(NVIC_IRQ_PVD); nvic_clear_pending(NVIC_IRQ_PVD);
reg_set(regs->PR, EXTI_PR_PR16); regs->PR.PR16 = 1;
callbacks[16](); callbacks[16]();
} }
void hdr_rtc_alarm(void) void hdr_rtc_alarm(void)
{ {
nvic_clear_pending(NVIC_IRQ_RTC_ALARM); nvic_clear_pending(NVIC_IRQ_RTC_ALARM);
reg_set(regs->PR, EXTI_PR_PR17); regs->PR.PR17 = 1;
callbacks[17](); callbacks[17]();
} }
void hdr_usb_wakeup(void) void hdr_usb_wakeup(void)
{ {
nvic_clear_pending(NVIC_IRQ_USB_WAKEUP); nvic_clear_pending(NVIC_IRQ_USB_WAKEUP);
reg_set(regs->PR, EXTI_PR_PR18); regs->PR.PR18 = 1;
callbacks[18](); callbacks[18]();
} }

142
drv/exti_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include "stdint.h" #include "stdint.h"
@ -21,7 +19,7 @@
#define EXTI_BASE_ADDRESS 0x40010400 #define EXTI_BASE_ADDRESS 0x40010400
union EXTI_IMR { union EXTI_IMR {
struct __attribute__((packed)) { struct {
uint32_t MR0:1; uint32_t MR0:1;
uint32_t MR1:1; uint32_t MR1:1;
uint32_t MR2:1; uint32_t MR2:1;
@ -46,29 +44,8 @@ union EXTI_IMR {
uint32_t word; uint32_t word;
}; };
#define EXTI_IMR_MR0 reg_def( 0, 1)
#define EXTI_IMR_MR1 reg_def( 1, 1)
#define EXTI_IMR_MR2 reg_def( 2, 1)
#define EXTI_IMR_MR3 reg_def( 3, 1)
#define EXTI_IMR_MR4 reg_def( 4, 1)
#define EXTI_IMR_MR5 reg_def( 5, 1)
#define EXTI_IMR_MR6 reg_def( 6, 1)
#define EXTI_IMR_MR7 reg_def( 7, 1)
#define EXTI_IMR_MR8 reg_def( 8, 1)
#define EXTI_IMR_MR9 reg_def( 9, 1)
#define EXTI_IMR_MR10 reg_def(10, 1)
#define EXTI_IMR_MR11 reg_def(11, 1)
#define EXTI_IMR_MR12 reg_def(12, 1)
#define EXTI_IMR_MR13 reg_def(13, 1)
#define EXTI_IMR_MR14 reg_def(14, 1)
#define EXTI_IMR_MR15 reg_def(15, 1)
#define EXTI_IMR_MR16 reg_def(16, 1)
#define EXTI_IMR_MR17 reg_def(17, 1)
#define EXTI_IMR_MR18 reg_def(18, 1)
#define EXTI_IMR_reserved1 reg_def(19, 13)
union EXTI_EMR { union EXTI_EMR {
struct __attribute__((packed)) { struct {
uint32_t MR0:1; uint32_t MR0:1;
uint32_t MR1:1; uint32_t MR1:1;
uint32_t MR2:1; uint32_t MR2:1;
@ -93,29 +70,8 @@ union EXTI_EMR {
uint32_t word; uint32_t word;
}; };
#define EXTI_EMR_MR0 reg_def( 0, 1)
#define EXTI_EMR_MR1 reg_def( 1, 1)
#define EXTI_EMR_MR2 reg_def( 2, 1)
#define EXTI_EMR_MR3 reg_def( 3, 1)
#define EXTI_EMR_MR4 reg_def( 4, 1)
#define EXTI_EMR_MR5 reg_def( 5, 1)
#define EXTI_EMR_MR6 reg_def( 6, 1)
#define EXTI_EMR_MR7 reg_def( 7, 1)
#define EXTI_EMR_MR8 reg_def( 8, 1)
#define EXTI_EMR_MR9 reg_def( 9, 1)
#define EXTI_EMR_MR10 reg_def(10, 1)
#define EXTI_EMR_MR11 reg_def(11, 1)
#define EXTI_EMR_MR12 reg_def(12, 1)
#define EXTI_EMR_MR13 reg_def(13, 1)
#define EXTI_EMR_MR14 reg_def(14, 1)
#define EXTI_EMR_MR15 reg_def(15, 1)
#define EXTI_EMR_MR16 reg_def(16, 1)
#define EXTI_EMR_MR17 reg_def(17, 1)
#define EXTI_EMR_MR18 reg_def(18, 1)
#define EXTI_EMR_reserved1 reg_def(19, 13)
union EXTI_RTSR { union EXTI_RTSR {
struct __attribute__((packed)) { struct {
uint32_t TR0:1; uint32_t TR0:1;
uint32_t TR1:1; uint32_t TR1:1;
uint32_t TR2:1; uint32_t TR2:1;
@ -140,29 +96,8 @@ union EXTI_RTSR {
uint32_t word; uint32_t word;
}; };
#define EXTI_RTSR_TR0 reg_def( 0, 1)
#define EXTI_RTSR_TR1 reg_def( 1, 1)
#define EXTI_RTSR_TR2 reg_def( 2, 1)
#define EXTI_RTSR_TR3 reg_def( 3, 1)
#define EXTI_RTSR_TR4 reg_def( 4, 1)
#define EXTI_RTSR_TR5 reg_def( 5, 1)
#define EXTI_RTSR_TR6 reg_def( 6, 1)
#define EXTI_RTSR_TR7 reg_def( 7, 1)
#define EXTI_RTSR_TR8 reg_def( 8, 1)
#define EXTI_RTSR_TR9 reg_def( 9, 1)
#define EXTI_RTSR_TR10 reg_def(10, 1)
#define EXTI_RTSR_TR11 reg_def(11, 1)
#define EXTI_RTSR_TR12 reg_def(12, 1)
#define EXTI_RTSR_TR13 reg_def(13, 1)
#define EXTI_RTSR_TR14 reg_def(14, 1)
#define EXTI_RTSR_TR15 reg_def(15, 1)
#define EXTI_RTSR_TR16 reg_def(16, 1)
#define EXTI_RTSR_TR17 reg_def(17, 1)
#define EXTI_RTSR_TR18 reg_def(18, 1)
#define EXTI_RTSR_reserved1 reg_def(19, 13)
union EXTI_FTSR { union EXTI_FTSR {
struct __attribute__((packed)) { struct {
uint32_t TR0:1; uint32_t TR0:1;
uint32_t TR1:1; uint32_t TR1:1;
uint32_t TR2:1; uint32_t TR2:1;
@ -187,29 +122,8 @@ union EXTI_FTSR {
uint32_t word; uint32_t word;
}; };
#define EXTI_FTSR_TR0 reg_def( 0, 1)
#define EXTI_FTSR_TR1 reg_def( 1, 1)
#define EXTI_FTSR_TR2 reg_def( 2, 1)
#define EXTI_FTSR_TR3 reg_def( 3, 1)
#define EXTI_FTSR_TR4 reg_def( 4, 1)
#define EXTI_FTSR_TR5 reg_def( 5, 1)
#define EXTI_FTSR_TR6 reg_def( 6, 1)
#define EXTI_FTSR_TR7 reg_def( 7, 1)
#define EXTI_FTSR_TR8 reg_def( 8, 1)
#define EXTI_FTSR_TR9 reg_def( 9, 1)
#define EXTI_FTSR_TR10 reg_def(10, 1)
#define EXTI_FTSR_TR11 reg_def(11, 1)
#define EXTI_FTSR_TR12 reg_def(12, 1)
#define EXTI_FTSR_TR13 reg_def(13, 1)
#define EXTI_FTSR_TR14 reg_def(14, 1)
#define EXTI_FTSR_TR15 reg_def(15, 1)
#define EXTI_FTSR_TR16 reg_def(16, 1)
#define EXTI_FTSR_TR17 reg_def(17, 1)
#define EXTI_FTSR_TR18 reg_def(18, 1)
#define EXTI_FTSR_reserved1 reg_def(19, 13)
union EXTI_SWIER { union EXTI_SWIER {
struct __attribute__((packed)) { struct {
uint32_t SWIER0:1; uint32_t SWIER0:1;
uint32_t SWIER1:1; uint32_t SWIER1:1;
uint32_t SWIER2:1; uint32_t SWIER2:1;
@ -234,29 +148,8 @@ union EXTI_SWIER {
uint32_t word; uint32_t word;
}; };
#define EXTI_SWIER_SWIER0 reg_def( 0, 1)
#define EXTI_SWIER_SWIER1 reg_def( 1, 1)
#define EXTI_SWIER_SWIER2 reg_def( 2, 1)
#define EXTI_SWIER_SWIER3 reg_def( 3, 1)
#define EXTI_SWIER_SWIER4 reg_def( 4, 1)
#define EXTI_SWIER_SWIER5 reg_def( 5, 1)
#define EXTI_SWIER_SWIER6 reg_def( 6, 1)
#define EXTI_SWIER_SWIER7 reg_def( 7, 1)
#define EXTI_SWIER_SWIER8 reg_def( 8, 1)
#define EXTI_SWIER_SWIER9 reg_def( 9, 1)
#define EXTI_SWIER_SWIER10 reg_def(10, 1)
#define EXTI_SWIER_SWIER11 reg_def(11, 1)
#define EXTI_SWIER_SWIER12 reg_def(12, 1)
#define EXTI_SWIER_SWIER13 reg_def(13, 1)
#define EXTI_SWIER_SWIER14 reg_def(14, 1)
#define EXTI_SWIER_SWIER15 reg_def(15, 1)
#define EXTI_SWIER_SWIER16 reg_def(16, 1)
#define EXTI_SWIER_SWIER17 reg_def(17, 1)
#define EXTI_SWIER_SWIER18 reg_def(18, 1)
#define EXTI_SWIER_reserved1 reg_def(19, 13)
union EXTI_PR { union EXTI_PR {
struct __attribute__((packed)) { struct {
uint32_t PR0:1; uint32_t PR0:1;
uint32_t PR1:1; uint32_t PR1:1;
uint32_t PR2:1; uint32_t PR2:1;
@ -281,28 +174,7 @@ union EXTI_PR {
uint32_t word; uint32_t word;
}; };
#define EXTI_PR_PR0 reg_def( 0, 1) struct EXTI {
#define EXTI_PR_PR1 reg_def( 1, 1)
#define EXTI_PR_PR2 reg_def( 2, 1)
#define EXTI_PR_PR3 reg_def( 3, 1)
#define EXTI_PR_PR4 reg_def( 4, 1)
#define EXTI_PR_PR5 reg_def( 5, 1)
#define EXTI_PR_PR6 reg_def( 6, 1)
#define EXTI_PR_PR7 reg_def( 7, 1)
#define EXTI_PR_PR8 reg_def( 8, 1)
#define EXTI_PR_PR9 reg_def( 9, 1)
#define EXTI_PR_PR10 reg_def(10, 1)
#define EXTI_PR_PR11 reg_def(11, 1)
#define EXTI_PR_PR12 reg_def(12, 1)
#define EXTI_PR_PR13 reg_def(13, 1)
#define EXTI_PR_PR14 reg_def(14, 1)
#define EXTI_PR_PR15 reg_def(15, 1)
#define EXTI_PR_PR16 reg_def(16, 1)
#define EXTI_PR_PR17 reg_def(17, 1)
#define EXTI_PR_PR18 reg_def(18, 1)
#define EXTI_PR_reserved1 reg_def(19, 13)
struct __attribute__((packed)) EXTI {
union EXTI_IMR IMR; union EXTI_IMR IMR;
union EXTI_EMR EMR; union EXTI_EMR EMR;
union EXTI_RTSR RTSR; union EXTI_RTSR RTSR;

8
drv/flash.c
View File

@ -34,15 +34,13 @@ void flash_configure(enum FlashPreset preset)
//apply new configuration //apply new configuration
switch (preset) { switch (preset) {
case FLASH_PRESET_LOW_CLOCK_SPEED: case FLASH_PRESET_LOW_CLOCK_SPEED:
reg_set(regs->ACR, FLASH_ACR_HLFCYA); //half cycle for power saving regs->ACR.HLFCYA = 1; //half cycle for power saving
break; break;
case FLASH_PRESET_MEDIUM_CLOCK_SPEED: case FLASH_PRESET_MEDIUM_CLOCK_SPEED:
reg_reset(regs->ACR, FLASH_ACR_LATENCY); regs->ACR.LATENCY = 0x1;
reg_write(regs->ACR, FLASH_ACR_LATENCY, 0x1);
break; break;
case FLASH_PRESET_HIGH_CLOCK_SPEED: case FLASH_PRESET_HIGH_CLOCK_SPEED:
reg_reset(regs->ACR, FLASH_ACR_LATENCY); regs->ACR.LATENCY = 0x2;
reg_write(regs->ACR, FLASH_ACR_LATENCY, 0x2);
break; break;
default: default:
break; break;

26
drv/flash_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include "stdint.h" #include "stdint.h"
@ -21,7 +19,7 @@
#define FLASH_BASE_ADDRESS 0x40022000 #define FLASH_BASE_ADDRESS 0x40022000
union FLASH_ACR { union FLASH_ACR {
struct __attribute__((packed)) { struct {
uint32_t LATENCY:3; uint32_t LATENCY:3;
uint32_t HLFCYA:1; uint32_t HLFCYA:1;
uint32_t PRFTBE:1; uint32_t PRFTBE:1;
@ -31,62 +29,56 @@ union FLASH_ACR {
uint32_t word; uint32_t word;
}; };
#define FLASH_ACR_LATENCY reg_def(0, 3)
#define FLASH_ACR_HLFCYA reg_def(3, 1)
#define FLASH_ACR_PRFTBE reg_def(4, 1)
#define FLASH_ACR_PRFTBS reg_def(5, 1)
#define FLASH_ACR_reserved1 reg_def(6, 26)
union FLASH_KEYR { union FLASH_KEYR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_OPTKEYR { union FLASH_OPTKEYR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_SR { union FLASH_SR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_CR { union FLASH_CR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_AR { union FLASH_AR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_OBR { union FLASH_OBR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
union FLASH_WRPR { union FLASH_WRPR {
struct __attribute__((packed)) { struct {
uint32_t reserved1; //TODO uint32_t reserved1; //TODO
}; };
uint32_t word; uint32_t word;
}; };
struct __attribute__((packed)) FLASH { struct FLASH {
union FLASH_ACR ACR; union FLASH_ACR ACR;
union FLASH_KEYR KEYR; union FLASH_KEYR KEYR;
union FLASH_OPTKEYR OPTKEYR; union FLASH_OPTKEYR OPTKEYR;

18
drv/gpio_regs.h
View File

@ -19,7 +19,7 @@
#define GPIO_BASE_ADDRESS 0x40010800 #define GPIO_BASE_ADDRESS 0x40010800
union GPIO_CRL { union GPIO_CRL {
struct __attribute__((packed)) { struct {
uint32_t MODE0:2; uint32_t MODE0:2;
uint32_t CNF0:2; uint32_t CNF0:2;
uint32_t MODE1:2; uint32_t MODE1:2;
@ -41,7 +41,7 @@ union GPIO_CRL {
}; };
union GPIO_CRH { union GPIO_CRH {
struct __attribute__((packed)) { struct {
uint32_t MODE8:2; uint32_t MODE8:2;
uint32_t CNF8:2; uint32_t CNF8:2;
uint32_t MODE9:2; uint32_t MODE9:2;
@ -63,7 +63,7 @@ union GPIO_CRH {
}; };
union GPIO_IDR { union GPIO_IDR {
struct __attribute__((packed)) { struct {
uint32_t IDR0:1; uint32_t IDR0:1;
uint32_t IDR1:1; uint32_t IDR1:1;
uint32_t IDR2:1; uint32_t IDR2:1;
@ -86,7 +86,7 @@ union GPIO_IDR {
}; };
union GPIO_ODR { union GPIO_ODR {
struct __attribute__((packed)) { struct {
uint32_t ODR0:1; uint32_t ODR0:1;
uint32_t ODR1:1; uint32_t ODR1:1;
uint32_t ODR2:1; uint32_t ODR2:1;
@ -109,7 +109,7 @@ union GPIO_ODR {
}; };
union GPIO_BSRR { union GPIO_BSRR {
struct __attribute__((packed)) { struct {
uint32_t BS0:1; uint32_t BS0:1;
uint32_t BS1:1; uint32_t BS1:1;
uint32_t BS2:1; uint32_t BS2:1;
@ -147,7 +147,7 @@ union GPIO_BSRR {
}; };
union GPIO_BRR { union GPIO_BRR {
struct __attribute__((packed)) { struct {
uint32_t BR0:1; uint32_t BR0:1;
uint32_t BR1:1; uint32_t BR1:1;
uint32_t BR2:1; uint32_t BR2:1;
@ -170,7 +170,7 @@ union GPIO_BRR {
}; };
union GPIO_LCKK { union GPIO_LCKK {
struct __attribute__((packed)) { struct {
uint32_t LCK0:1; uint32_t LCK0:1;
uint32_t LCK1:1; uint32_t LCK1:1;
uint32_t LCK2:1; uint32_t LCK2:1;
@ -193,7 +193,7 @@ union GPIO_LCKK {
uint32_t word; uint32_t word;
}; };
struct __attribute__((packed)) GPIO_PORT { struct GPIO_PORT {
union GPIO_CRL CRL; union GPIO_CRL CRL;
union GPIO_CRH CRH; union GPIO_CRH CRH;
union GPIO_IDR IDR; union GPIO_IDR IDR;
@ -204,7 +204,7 @@ struct __attribute__((packed)) GPIO_PORT {
uint32_t reserved1[249]; uint32_t reserved1[249];
}; };
struct __attribute__((packed)) GPIO { struct GPIO {
struct GPIO_PORT PORTS[7]; struct GPIO_PORT PORTS[7];
}; };

4
drv/nvic_regs.h
View File

@ -19,7 +19,7 @@
#define NVIC1_BASE_ADDRESS 0xE000E100 #define NVIC1_BASE_ADDRESS 0xE000E100
#define NVIC2_BASE_ADDRESS 0xE000EF00 #define NVIC2_BASE_ADDRESS 0xE000EF00
struct __attribute__((packed)) NVIC1 { struct NVIC1 {
uint32_t ISERX[3]; uint32_t ISERX[3];
uint32_t ICERX[3]; uint32_t ICERX[3];
uint32_t ISPRX[3]; uint32_t ISPRX[3];
@ -28,7 +28,7 @@ struct __attribute__((packed)) NVIC1 {
uint32_t IPRX[20]; uint32_t IPRX[20];
}; };
struct __attribute__((packed)) NVIC2 { struct NVIC2 {
uint32_t INTID; uint32_t INTID;
}; };

42
drv/rcc.c
View File

@ -113,26 +113,26 @@ void rcc_get_clocks(struct RccClocks* clocks)
static void apply_default_preset(void) static void apply_default_preset(void)
{ {
//ensures HSI is enabled //ensures HSI is enabled
reg_set(regs->CR, RCC_CR_HSION); regs->CR.HSION = 1;
while (regs->CR.HSIRDY != 0x1); while (regs->CR.HSIRDY != 0x1);
//set HSI as main clock source and disable prescalers //set HSI as main clock source and disable prescalers
regs->CFGR.word &= ~0x077fff3; regs->CFGR.word &= ~0x077fff3;
//disable all options //disable all options
reg_reset(regs->CR, RCC_CR_HSITRIM); regs->CR.HSITRIM = 0;
reg_write(regs->CR, RCC_CR_HSITRIM, 0x10); regs->CR.HSITRIM = 0x10;
reg_reset(regs->CR, RCC_CR_HSEON); regs->CR.HSEON = 0;
reg_reset(regs->CR, RCC_CR_HSEBYP); regs->CR.HSEBYP = 0;
reg_reset(regs->CR, RCC_CR_CCSON); regs->CR.CCSON = 0;
reg_reset(regs->CR, RCC_CR_PLLON); regs->CR.PLLON = 0;
//disable all interrupts //disable all interrupts
reg_reset(regs->CIR, RCC_CIR_LSIRDYIE); regs->CIR.LSIRDYIE = 0;
reg_reset(regs->CIR, RCC_CIR_LSERDYIE); regs->CIR.LSERDYIE = 0;
reg_reset(regs->CIR, RCC_CIR_HSIRDYIE); regs->CIR.HSIRDYIE = 0;
reg_reset(regs->CIR, RCC_CIR_HSERDYIE); regs->CIR.HSERDYIE = 0;
reg_reset(regs->CIR, RCC_CIR_PLLRDYIE); regs->CIR.PLLRDYIE = 0;
//reconfigure flash //reconfigure flash
flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED); flash_configure(FLASH_PRESET_LOW_CLOCK_SPEED);
@ -149,35 +149,35 @@ static void apply_speed_preset(void)
apply_default_preset(); apply_default_preset();
//try enabling HSE, fallback to HSI if HSE fails //try enabling HSE, fallback to HSI if HSE fails
reg_set(regs->CR, RCC_CR_HSEON); regs->CR.HSEON = 1;
for (uint32_t i=0; i<1000; ++i) { for (uint32_t i=0; i<1000; ++i) {
__asm__("nop"); __asm__("nop");
} }
if (regs->CR.HSERDY == 0x1) { if (regs->CR.HSERDY == 0x1) {
reg_set(regs->CFGR, RCC_CFGR_PLLSCR); regs->CFGR.PLLSCR = 1;
} else { } else {
reg_reset(regs->CR, RCC_CR_HSEON); regs->CR.HSEON = 0;
} }
//configure PLL, fallback to HSI if PLL fails //configure PLL, fallback to HSI if PLL fails
reg_write(regs->CFGR, RCC_CFGR_PLLMUL, 0x7); //PLL x9 regs->CFGR.PLLMUL = 0x7; //PLL x9
reg_set(regs->CR, RCC_CR_PLLON); regs->CR.PLLON = 1;
for (uint32_t i=0; i<1000; ++i) { for (uint32_t i=0; i<1000; ++i) {
__asm__("nop"); __asm__("nop");
} }
if (regs->CR.PLLRDY != 0x1) { if (regs->CR.PLLRDY != 0x1) {
reg_reset(regs->CR, RCC_CR_PLLON); regs->CR.PLLON = 0;
return; //clock low enough, no need for prescalers return; //clock low enough, no need for prescalers
} }
//configure prescalers //configure prescalers
reg_write(regs->CFGR, RCC_CFGR_PPRE1, 0x4); // /2 regs->CFGR.PPRE1 = 0x4; // /2
reg_write(regs->CFGR, RCC_CFGR_ADCPRE, 0x2); // /6 regs->CFGR.ADCPRE = 0x2; // /6
//reconfigure flash //reconfigure flash
flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED); flash_configure(FLASH_PRESET_HIGH_CLOCK_SPEED);
//switch to PLL output //switch to PLL output
reg_write(regs->CFGR, RCC_CFGR_SW, 0x2); regs->CFGR.SW = 0x2;
} }

213
drv/rcc_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include "stdint.h" #include "stdint.h"
@ -21,7 +19,7 @@
#define RCC_BASE_ADDRESS 0x40021000 #define RCC_BASE_ADDRESS 0x40021000
union RCC_CR { union RCC_CR {
struct __attribute__((packed)) { struct {
uint32_t HSION:1; uint32_t HSION:1;
uint32_t HSIRDY:1; uint32_t HSIRDY:1;
uint32_t reserved1:1; uint32_t reserved1:1;
@ -39,22 +37,8 @@ union RCC_CR {
uint32_t word; uint32_t word;
}; };
#define RCC_CR_HSION reg_def( 0, 1)
#define RCC_CR_HSIRDY reg_def( 1, 1)
#define RCC_CR_reserved1 reg_def( 2, 1)
#define RCC_CR_HSITRIM reg_def( 3, 5)
#define RCC_CR_HSICAL reg_def( 8, 8)
#define RCC_CR_HSEON reg_def(16, 1)
#define RCC_CR_HSERDY reg_def(17, 1)
#define RCC_CR_HSEBYP reg_def(18, 1)
#define RCC_CR_CCSON reg_def(19, 1)
#define RCC_CR_reserved2 reg_def(20, 4)
#define RCC_CR_PLLON reg_def(24, 1)
#define RCC_CR_PLLRDY reg_def(25, 1)
#define RCC_CR_reserved3 reg_def(26, 6)
union RCC_CFGR { union RCC_CFGR {
struct __attribute__((packed)) { struct {
uint32_t SW:2; uint32_t SW:2;
uint32_t SWS:2; uint32_t SWS:2;
uint32_t HPRE:4; uint32_t HPRE:4;
@ -72,22 +56,8 @@ union RCC_CFGR {
uint32_t word; uint32_t word;
}; };
#define RCC_CFGR_SW reg_def( 0, 2)
#define RCC_CFGR_SWS reg_def( 2, 2)
#define RCC_CFGR_HPRE reg_def( 4, 4)
#define RCC_CFGR_PPRE1 reg_def( 8, 3)
#define RCC_CFGR_PPRE2 reg_def(11, 3)
#define RCC_CFGR_ADCPRE reg_def(14, 2)
#define RCC_CFGR_PLLSCR reg_def(16, 1)
#define RCC_CFGR_PLLXTPRE reg_def(17, 1)
#define RCC_CFGR_PLLMUL reg_def(18, 4)
#define RCC_CFGR_USBPRE reg_def(22, 1)
#define RCC_CFGR_reserved1 reg_def(23, 1)
#define RCC_CFGR_MCO reg_def(24, 3)
#define RCC_CFGR_reserved2 reg_def(27, 5)
union RCC_CIR { union RCC_CIR {
struct __attribute__((packed)) { struct {
uint32_t LSIRDYF:1; uint32_t LSIRDYF:1;
uint32_t LSERDYF:1; uint32_t LSERDYF:1;
uint32_t HSIRDYF:1; uint32_t HSIRDYF:1;
@ -113,30 +83,8 @@ union RCC_CIR {
uint32_t word; uint32_t word;
}; };
#define RCC_CIR_LSIRDYF reg_def( 0, 1)
#define RCC_CIR_LSERDYF reg_def( 1, 1)
#define RCC_CIR_HSIRDYF reg_def( 2, 1)
#define RCC_CIR_HSERDYF reg_def( 3, 1)
#define RCC_CIR_PLLRDYF reg_def( 4, 1)
#define RCC_CIR_reserved1 reg_def( 5, 2)
#define RCC_CIR_CSSF reg_def( 7, 1)
#define RCC_CIR_LSIRDYIE reg_def( 8, 1)
#define RCC_CIR_LSERDYIE reg_def( 9, 1)
#define RCC_CIR_HSIRDYIE reg_def(10, 1)
#define RCC_CIR_HSERDYIE reg_def(11, 1)
#define RCC_CIR_PLLRDYIE reg_def(12, 1)
#define RCC_CIR_RSE2 reg_def(13, 3)
#define RCC_CIR_LSIRDYC reg_def(16, 1)
#define RCC_CIR_LSERDYC reg_def(17, 1)
#define RCC_CIR_HSIRDYC reg_def(18, 1)
#define RCC_CIR_HSERDYC reg_def(19, 1)
#define RCC_CIR_PLLRDYC reg_def(20, 1)
#define RCC_CIR_reserved3 reg_def(21, 2)
#define RCC_CIR_CSSC reg_def(23, 1)
#define RCC_CIR_reserved4 reg_def(24, 8)
union RCC_APB2RSTR { union RCC_APB2RSTR {
struct __attribute__((packed)) { struct {
uint32_t AFIORST:1; uint32_t AFIORST:1;
uint32_t reserved1:1; uint32_t reserved1:1;
uint32_t IOPARST:1; uint32_t IOPARST:1;
@ -162,30 +110,8 @@ union RCC_APB2RSTR {
uint32_t word; uint32_t word;
}; };
#define RCC_APB2RSTR_AFIORST reg_def( 0, 1)
#define RCC_APB2RSTR_reserved1 reg_def( 1, 1)
#define RCC_APB2RSTR_IOPARST reg_def( 2, 1)
#define RCC_APB2RSTR_IOPBRST reg_def( 3, 1)
#define RCC_APB2RSTR_IOPCRST reg_def( 4, 1)
#define RCC_APB2RSTR_IOPDRST reg_def( 5, 1)
#define RCC_APB2RSTR_IOPERST reg_def( 6, 1)
#define RCC_APB2RSTR_IOPFRST reg_def( 7, 1)
#define RCC_APB2RSTR_IOPGRST reg_def( 8, 1)
#define RCC_APB2RSTR_ADC1RST reg_def( 9, 1)
#define RCC_APB2RSTR_ACD2RST reg_def(10, 1)
#define RCC_APB2RSTR_TIM1RST reg_def(11, 1)
#define RCC_APB2RSTR_SPI1RST reg_def(12, 1)
#define RCC_APB2RSTR_TIM8RST reg_def(13, 1)
#define RCC_APB2RSTR_USART1RST reg_def(14, 1)
#define RCC_APB2RSTR_ADC3RST reg_def(15, 1)
#define RCC_APB2RSTR_reserved2 reg_def(16, 3)
#define RCC_APB2RSTR_TIM9RST reg_def(19, 1)
#define RCC_APB2RSTR_TIM10RST reg_def(20, 1)
#define RCC_APB2RSTR_TIM11RST reg_def(21, 1)
#define RCC_APB2RSTR_reserved3 reg_def(22, 10)
union RCC_APB1RSTR { union RCC_APB1RSTR {
struct __attribute__((packed)) { struct {
uint32_t TIM2RST:1; uint32_t TIM2RST:1;
uint32_t TIM3RST:1; uint32_t TIM3RST:1;
uint32_t TIM4RST:1; uint32_t TIM4RST:1;
@ -219,38 +145,8 @@ union RCC_APB1RSTR {
uint32_t word; uint32_t word;
}; };
#define RCC_APB1RSTR_TIM2RST reg_def( 0, 1)
#define RCC_APB1RSTR_TIM3RST reg_def( 1, 1)
#define RCC_APB1RSTR_TIM4RST reg_def( 2, 1)
#define RCC_APB1RSTR_TIM5RST reg_def( 3, 1)
#define RCC_APB1RSTR_TIM6RST reg_def( 4, 1)
#define RCC_APB1RSTR_TIM7RST reg_def( 5, 1)
#define RCC_APB1RSTR_TIM12RST reg_def( 6, 1)
#define RCC_APB1RSTR_TIM13RST reg_def( 7, 1)
#define RCC_APB1RSTR_TIM14RST reg_def( 8, 1)
#define RCC_APB1RSTR_reserved1 reg_def( 9, 2)
#define RCC_APB1RSTR_WWDGRST reg_def(11, 1)
#define RCC_APB1RSTR_reserved2 reg_def(12, 2)
#define RCC_APB1RSTR_SPI2RST reg_def(14, 1)
#define RCC_APB1RSTR_SPI3RST reg_def(15, 1)
#define RCC_APB1RSTR_reserved3 reg_def(16, 1)
#define RCC_APB1RSTR_USART2RST reg_def(17, 1)
#define RCC_APB1RSTR_USART3RST reg_def(18, 1)
#define RCC_APB1RSTR_UART4RST reg_def(19, 1)
#define RCC_APB1RSTR_UART5RST reg_def(20, 1)
#define RCC_APB1RSTR_I2C12RST reg_def(21, 1)
#define RCC_APB1RSTR_I2C2RST reg_def(22, 1)
#define RCC_APB1RSTR_USB2RST reg_def(23, 1)
#define RCC_APB1RSTR_reserved4 reg_def(24, 1)
#define RCC_APB1RSTR_CANRST reg_def(25, 1)
#define RCC_APB1RSTR_reserved5 reg_def(26, 1)
#define RCC_APB1RSTR_BKPRST reg_def(27, 1)
#define RCC_APB1RSTR_PWRRST reg_def(28, 1)
#define RCC_APB1RSTR_DACRST reg_def(29, 1)
#define RCC_APB1RSTR_reserved6 reg_def(30, 2)
union RCC_AHBENR { union RCC_AHBENR {
struct __attribute__((packed)) { struct {
uint32_t DMA1EN:1; uint32_t DMA1EN:1;
uint32_t DMA2EN:1; uint32_t DMA2EN:1;
uint32_t SRAMEN:1; uint32_t SRAMEN:1;
@ -267,21 +163,8 @@ union RCC_AHBENR {
uint32_t word; uint32_t word;
}; };
#define RCC_AHBENR_DMA1EN reg_def( 0, 1)
#define RCC_AHBENR_DMA2EN reg_def( 1, 1)
#define RCC_AHBENR_SRAMEN reg_def( 2, 1)
#define RCC_AHBENR_reserved1 reg_def( 3, 1)
#define RCC_AHBENR_FLITFEN reg_def( 4, 1)
#define RCC_AHBENR_reserved2 reg_def( 5, 1)
#define RCC_AHBENR_CRCEN reg_def( 6, 1)
#define RCC_AHBENR_reserved3 reg_def( 7, 1)
#define RCC_AHBENR_FSMCEN reg_def( 8, 1)
#define RCC_AHBENR_reserved4 reg_def( 9, 1)
#define RCC_AHBENR_SDIOEN reg_def(10, 1)
#define RCC_AHBENR_reserved5 reg_def(11, 21)
union RCC_APB2ENR { union RCC_APB2ENR {
struct __attribute__((packed)) { struct {
uint32_t AFIOEN:1; uint32_t AFIOEN:1;
uint32_t reserved1:1; uint32_t reserved1:1;
uint32_t IOPAEN:1; uint32_t IOPAEN:1;
@ -307,30 +190,8 @@ union RCC_APB2ENR {
uint32_t word; uint32_t word;
}; };
#define RCC_APB2ENR_AFIOEN reg_def( 0, 1)
#define RCC_APB2ENR_reserved1 reg_def( 1, 1)
#define RCC_APB2ENR_IOPAEN reg_def( 2, 1)
#define RCC_APB2ENR_IOPBEN reg_def( 3, 1)
#define RCC_APB2ENR_IOPCEN reg_def( 4, 1)
#define RCC_APB2ENR_IOPDEN reg_def( 5, 1)
#define RCC_APB2ENR_IOPEEN reg_def( 6, 1)
#define RCC_APB2ENR_IOPFEN reg_def( 7, 1)
#define RCC_APB2ENR_IOPGEN reg_def( 8, 1)
#define RCC_APB2ENR_ADC1EN reg_def( 9, 1)
#define RCC_APB2ENR_ACD2EN reg_def(10, 1)
#define RCC_APB2ENR_TIM1EN reg_def(11, 1)
#define RCC_APB2ENR_SPI1EN reg_def(12, 1)
#define RCC_APB2ENR_TIM8EN reg_def(13, 1)
#define RCC_APB2ENR_USART1EN reg_def(14, 1)
#define RCC_APB2ENR_ADC3EN reg_def(15, 1)
#define RCC_APB2ENR_reserved2 reg_def(16, 3)
#define RCC_APB2ENR_TIM9EN reg_def(19, 1)
#define RCC_APB2ENR_TIM10EN reg_def(20, 1)
#define RCC_APB2ENR_TIM11EN reg_def(21, 1)
#define RCC_APB2ENR_reserved3 reg_def(22, 10)
union RCC_APB1ENR { union RCC_APB1ENR {
struct __attribute__((packed)) { struct {
uint32_t TIM2EN:1; uint32_t TIM2EN:1;
uint32_t TIM3EN:1; uint32_t TIM3EN:1;
uint32_t TIM4EN:1; uint32_t TIM4EN:1;
@ -364,38 +225,8 @@ union RCC_APB1ENR {
uint32_t word; uint32_t word;
}; };
#define RCC_APB1ENR_TIM2EN reg_def( 0, 1)
#define RCC_APB1ENR_TIM3EN reg_def( 1, 1)
#define RCC_APB1ENR_TIM4EN reg_def( 2, 1)
#define RCC_APB1ENR_TIM5EN reg_def( 3, 1)
#define RCC_APB1ENR_TIM6EN reg_def( 4, 1)
#define RCC_APB1ENR_TIM7EN reg_def( 5, 1)
#define RCC_APB1ENR_TIM12EN reg_def( 6, 1)
#define RCC_APB1ENR_TIM13EN reg_def( 7, 1)
#define RCC_APB1ENR_TIM14EN reg_def( 8, 1)
#define RCC_APB1ENR_reserved1 reg_def( 9, 2)
#define RCC_APB1ENR_WWDGEN reg_def(11, 1)
#define RCC_APB1ENR_reserved reg_def(12, 2)
#define RCC_APB1ENR_SPI2EN reg_def(14, 1)
#define RCC_APB1ENR_SPI3EN reg_def(15, 1)
#define RCC_APB1ENR_reserved2 reg_def(16, 1)
#define RCC_APB1ENR_USART2EN reg_def(17, 1)
#define RCC_APB1ENR_USART3EN reg_def(18, 1)
#define RCC_APB1ENR_UART4EN reg_def(19, 1)
#define RCC_APB1ENR_UART5EN reg_def(20, 1)
#define RCC_APB1ENR_I2C12EN reg_def(21, 1)
#define RCC_APB1ENR_I2C2EN reg_def(22, 1)
#define RCC_APB1ENR_USB2EN reg_def(23, 1)
#define RCC_APB1ENR_reserved3 reg_def(24, 1)
#define RCC_APB1ENR_CANEN reg_def(25, 1)
#define RCC_APB1ENR_reserved4 reg_def(26, 1)
#define RCC_APB1ENR_BKPEN reg_def(27, 1)
#define RCC_APB1ENR_PWREN reg_def(28, 1)
#define RCC_APB1ENR_DACEN reg_def(29, 1)
#define RCC_APB1ENR_reserved5 reg_def(30, 2)
union RCC_BDCR { union RCC_BDCR {
struct __attribute__((packed)) { struct {
uint32_t LSEON:1; uint32_t LSEON:1;
uint32_t LSERDY:1; uint32_t LSERDY:1;
uint32_t LSEBYP:1; uint32_t LSEBYP:1;
@ -409,18 +240,8 @@ union RCC_BDCR {
uint32_t word; uint32_t word;
}; };
#define RCC_BDCR_LSEON reg_def( 0, 1)
#define RCC_BDCR_LSERDY reg_def( 1, 1)
#define RCC_BDCR_LSEBYP reg_def( 2, 1)
#define RCC_BDCR_reserved1 reg_def( 3, 5)
#define RCC_BDCR_RTCSEL reg_def( 8, 2)
#define RCC_BDCR_reserved2 reg_def(10, 5)
#define RCC_BDCR_RTCEN reg_def(15, 1)
#define RCC_BDCR_BDRST reg_def(16, 1)
#define RCC_BDCR_reserved3 reg_def(17, 15)
union RCC_CSR { union RCC_CSR {
struct __attribute__((packed)) { struct {
uint32_t LSION:1; uint32_t LSION:1;
uint32_t LSIRDY:1; uint32_t LSIRDY:1;
uint32_t reserved1:22; uint32_t reserved1:22;
@ -436,19 +257,7 @@ union RCC_CSR {
uint32_t word; uint32_t word;
}; };
#define RCC_CSR_LSION reg_def( 0, 1) struct RCC {
#define RCC_CSR_LSIRDY reg_def( 1, 1)
#define RCC_CSR_reserved1 reg_def( 2, 22)
#define RCC_CSR_RMVF reg_def(24, 1)
#define RCC_CSR_reserved2 reg_def(25, 1)
#define RCC_CSR_PINRSTF reg_def(26, 1)
#define RCC_CSR_PORRSTF reg_def(27, 1)
#define RCC_CSR_SFTRSTF reg_def(28, 1)
#define RCC_CSR_IWDGRSTF reg_def(29, 1)
#define RCC_CSR_WWDGRSTF reg_def(30, 1)
#define RCC_CSR_LPWRSTF reg_def(31, 1)
struct __attribute__((packed)) RCC {
union RCC_CR CR; union RCC_CR CR;
union RCC_CFGR CFGR; union RCC_CFGR CFGR;
union RCC_CIR CIR; union RCC_CIR CIR;

15
drv/reg.h
View File

@ -1,15 +0,0 @@
#define reg_def(pos, size) pos, (((0x1 << size) - 1) << pos)
#define reg_set(reg, field) _reg_set(reg, field)
#define _reg_set(reg, pos, mask) do { reg.word |= mask; } while (false)
#define reg_reset(reg, field) _reg_reset(reg, field)
#define _reg_reset(reg, pos, mask) do { reg.word &= ~mask; } while (false)
#define reg_write(reg, field, value) _reg_write(reg, field, (value))
#define _reg_write(reg, pos, mask, value) \
do { \
reg.word |= value << pos; \
} while (false) \

22
drv/stk.c
View File

@ -43,10 +43,10 @@ uint32_t stk_configure(uint32_t period_us, StkCallback cb)
//period is still too small //period is still too small
return 1; return 1;
} }
reg_set(regs->CTRL, STK_CTRL_CLKSOURCE); regs->CTRL.CLKSOURCE = 1;
} }
reg_write(regs->LOAD, STK_LOAD_RELOAD, reload); regs->LOAD.RELOAD = reload;
reg_set(regs->CTRL, STK_CTRL_TICKINT); regs->CTRL.TICKINT = 1;
callback = cb; callback = cb;
@ -55,23 +55,23 @@ uint32_t stk_configure(uint32_t period_us, StkCallback cb)
void stk_reset(void) void stk_reset(void)
{ {
reg_reset(regs->CTRL, STK_CTRL_ENABLE); regs->CTRL.ENABLE = 0;
reg_reset(regs->CTRL, STK_CTRL_TICKINT); regs->CTRL.TICKINT = 0;
reg_reset(regs->CTRL, STK_CTRL_CLKSOURCE); regs->CTRL.CLKSOURCE = 0;
reg_reset(regs->CTRL, STK_CTRL_COUNTFLAG); regs->CTRL.COUNTFLAG = 0;
reg_write(regs->LOAD, STK_LOAD_RELOAD, 0); regs->LOAD.RELOAD = 0;
reg_write(regs->VAL, STK_VAL_CURRENT, 0); regs->VAL.CURRENT = 0;
} }
void stk_start(void) void stk_start(void)
{ {
reg_set(regs->CTRL, STK_CTRL_ENABLE); regs->CTRL.ENABLE = 1;
} }
void stk_stop(void) void stk_stop(void)
{ {
reg_reset(regs->CTRL, STK_CTRL_ENABLE); regs->CTRL.ENABLE = 0;
} }
uint32_t stk_read_us(void) uint32_t stk_read_us(void)

30
drv/stk_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include <stdint.h> #include <stdint.h>
@ -21,7 +19,7 @@
#define STK_BASE_ADDRESS 0xE000E010 #define STK_BASE_ADDRESS 0xE000E010
union STK_CTRL { union STK_CTRL {
struct __attribute__((packed)) { struct {
uint32_t ENABLE:1; uint32_t ENABLE:1;
uint32_t TICKINT:1; uint32_t TICKINT:1;
uint32_t CLKSOURCE:1; uint32_t CLKSOURCE:1;
@ -32,37 +30,24 @@ union STK_CTRL {
uint32_t word; uint32_t word;
}; };
#define STK_CTRL_ENABLE reg_def( 0, 1)
#define STK_CTRL_TICKINT reg_def( 1, 1)
#define STK_CTRL_CLKSOURCE reg_def( 2, 1)
#define STK_CTRL_reserved reg_def( 3, 13)
#define STK_CTRL_COUNTFLAG reg_def(16, 1)
#define STK_CTRL_reserved2 reg_def(17, 15)
union STK_LOAD { union STK_LOAD {
struct __attribute__((packed)) { struct {
uint32_t RELOAD:24; uint32_t RELOAD:24;
uint32_t reserved1:8; uint32_t reserved1:8;
}; };
uint32_t word; uint32_t word;
}; };
#define STK_LOAD_RELOAD reg_def( 0, 24)
#define STK_LOAD_reserved1 reg_def(24, 8)
union STK_VAL { union STK_VAL {
struct __attribute__((packed)) { struct {
uint32_t CURRENT:24; uint32_t CURRENT:24;
uint32_t reserved1:8; uint32_t reserved1:8;
}; };
uint32_t word; uint32_t word;
}; };
#define STK_VAL_CURRENT reg_def( 0, 24)
#define STK_VAL_reserved1 reg_def(24, 8)
union STK_CALIB { union STK_CALIB {
struct __attribute__((packed)) { struct {
uint32_t TENMS:24; uint32_t TENMS:24;
uint32_t reserved1:6; uint32_t reserved1:6;
uint32_t SKEW:1; uint32_t SKEW:1;
@ -71,12 +56,7 @@ union STK_CALIB {
uint32_t word; uint32_t word;
}; };
#define STK_CALIB_RELOAD reg_def( 0, 24) struct STK {
#define STK_CALIB_reserved1 reg_def(24, 6)
#define STK_CALIB_SKEW reg_def(30, 1)
#define STK_CALIB_NOREF reg_def(31, 1)
struct __attribute__((packed)) STK {
union STK_CTRL CTRL; union STK_CTRL CTRL;
union STK_LOAD LOAD; union STK_LOAD LOAD;
union STK_VAL VAL; union STK_VAL VAL;

38
drv/usart.c
View File

@ -9,7 +9,6 @@
#include "usart.h" #include "usart.h"
#include "usart_regs.h" #include "usart_regs.h"
#include "reg.h"
#include "rcc.h" #include "rcc.h"
#include "dma.h" #include "dma.h"
@ -132,7 +131,7 @@ uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
//only write data if the tx register it empty, give up otherwise //only write data if the tx register it empty, give up otherwise
if (usarts[periph]->SR.TXE) { if (usarts[periph]->SR.TXE) {
reg_write(usarts[periph]->DR, USART_DR_DR, byte); usarts[periph]->DR.DR = byte;
return 0; return 0;
} else { } else {
return 1; return 1;
@ -145,7 +144,7 @@ const struct DmaParam* usart_configure_rx_dma(enum UsartPeriph periph)
return nullptr; return nullptr;
} }
reg_set(usarts[periph]->CR3, USART_CR3_DMAR); usarts[periph]->CR3.DMAR = 1;
return &usarts_rx_param[periph]; return &usarts_rx_param[periph];
} }
@ -155,7 +154,7 @@ const struct DmaParam* usart_configure_tx_dma(enum UsartPeriph periph)
return nullptr; return nullptr;
} }
reg_set(usarts[periph]->CR3, USART_CR3_DMAT); usarts[periph]->CR3.DMAT = 1;
return &usarts_tx_param[periph]; return &usarts_tx_param[periph];
} }
@ -176,19 +175,19 @@ static void configure_usart(volatile struct USART* regs,
case USART_CONFIG_8E1: case USART_CONFIG_8E1:
case USART_CONFIG_7E2: case USART_CONFIG_7E2:
case USART_CONFIG_8E2: case USART_CONFIG_8E2:
reg_set(regs->CR1, USART_CR1_PCE); regs->CR1.PCE = 1;
reg_reset(regs->CR1, USART_CR1_PS); regs->CR1.PS = 0;
break; break;
case USART_CONFIG_7O1: case USART_CONFIG_7O1:
case USART_CONFIG_7O2: case USART_CONFIG_7O2:
case USART_CONFIG_8O1: case USART_CONFIG_8O1:
case USART_CONFIG_8O2: case USART_CONFIG_8O2:
reg_set(regs->CR1, USART_CR1_PCE); regs->CR1.PCE = 1;
reg_set(regs->CR1, USART_CR1_PS); regs->CR1.PS = 1;
break; break;
case USART_CONFIG_8N1: case USART_CONFIG_8N1:
case USART_CONFIG_8N2: case USART_CONFIG_8N2:
reg_reset(regs->CR1, USART_CR1_PCE); regs->CR1.PCE = 0;
break; break;
default: default:
break; break;
@ -203,13 +202,13 @@ static void configure_usart(volatile struct USART* regs,
case USART_CONFIG_7O2: case USART_CONFIG_7O2:
case USART_CONFIG_8N1: case USART_CONFIG_8N1:
case USART_CONFIG_8N2: case USART_CONFIG_8N2:
reg_reset(regs->CR1, USART_CR1_M); regs->CR1.M = 0;
break; break;
case USART_CONFIG_8E2: case USART_CONFIG_8E2:
case USART_CONFIG_8E1: case USART_CONFIG_8E1:
case USART_CONFIG_8O1: case USART_CONFIG_8O1:
case USART_CONFIG_8O2: case USART_CONFIG_8O2:
reg_set(regs->CR1, USART_CR1_M); regs->CR1.M = 1;
break; break;
default: default:
break; break;
@ -223,24 +222,23 @@ static void configure_usart(volatile struct USART* regs,
case USART_CONFIG_8N1: case USART_CONFIG_8N1:
case USART_CONFIG_8E1: case USART_CONFIG_8E1:
case USART_CONFIG_8O1: case USART_CONFIG_8O1:
reg_reset(regs->CR2, USART_CR2_STOP); regs->CR2.STOP = 0;
break; break;
case USART_CONFIG_7E2: case USART_CONFIG_7E2:
case USART_CONFIG_7O2: case USART_CONFIG_7O2:
case USART_CONFIG_8N2: case USART_CONFIG_8N2:
case USART_CONFIG_8E2: case USART_CONFIG_8E2:
case USART_CONFIG_8O2: case USART_CONFIG_8O2:
reg_reset(regs->CR2, USART_CR2_STOP); regs->CR2.STOP = 2;
reg_write(regs->CR2, USART_CR2_STOP, 2);
break; break;
default: default:
break; break;
} }
//enable Rx/Tx //enable Rx/Tx
reg_set(regs->CR1, USART_CR1_TE); regs->CR1.TE = 1;
reg_set(regs->CR1, USART_CR1_RE); regs->CR1.RE = 1;
reg_set(regs->CR1, USART_CR1_UE); regs->CR1.UE = 1;
} }
/** /**
@ -255,9 +253,7 @@ static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
uint32_t factor = clock / baudrate; uint32_t factor = clock / baudrate;
volatile uint32_t divider = factor - (mantissa * 16); volatile uint32_t divider = factor - (mantissa * 16);
reg_reset(regs->BRR, USART_BRR_DIV_Mantissa); regs->BRR.DIV_Mantissa = mantissa & 0xFFF;
reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF); regs->BRR.DIV_Fraction = divider & 0xF;
reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
} }

81
drv/usart_regs.h
View File

@ -11,8 +11,6 @@
//--includes-------------------------------------------------------------------- //--includes--------------------------------------------------------------------
#include "reg.h"
#include "stdint.h" #include "stdint.h"
@ -23,7 +21,7 @@
#define USART3_BASE_ADDRESS 0x40004800 #define USART3_BASE_ADDRESS 0x40004800
union USART_SR { union USART_SR {
struct __attribute__((packed)) { struct {
uint32_t PE:1; uint32_t PE:1;
uint32_t FE:1; uint32_t FE:1;
uint32_t NE:1; uint32_t NE:1;
@ -39,31 +37,16 @@ union USART_SR {
uint32_t word; uint32_t word;
}; };
#define USART_SR_PE reg_def( 0, 1)
#define USART_SR_FE reg_def( 1, 1)
#define USART_SR_NE reg_def( 2, 1)
#define USART_SR_ORE reg_def( 3, 1)
#define USART_SR_IDLE reg_def( 4, 1)
#define USART_SR_RXNE reg_def( 5, 1)
#define USART_SR_TC reg_def( 6, 1)
#define USART_SR_TXE reg_def( 7, 1)
#define USART_SR_LBD reg_def( 8, 1)
#define USART_SR_CTS reg_def( 9, 1)
#define USART_SR_reserved1 reg_def(10, 22)
union USART_DR { union USART_DR {
struct __attribute__((packed)) { struct {
uint32_t DR:9; uint32_t DR:9;
uint32_t reserved1:23; uint32_t reserved1:23;
}; };
uint32_t word; uint32_t word;
}; };
#define USART_DR_DR reg_def( 0, 9)
#define USART_DR_reserved1 reg_def( 9, 23)
union USART_BRR { union USART_BRR {
struct __attribute__((packed)) { struct {
uint32_t DIV_Fraction:4; uint32_t DIV_Fraction:4;
uint32_t DIV_Mantissa:12; uint32_t DIV_Mantissa:12;
uint32_t reserved1:16; uint32_t reserved1:16;
@ -71,12 +54,8 @@ union USART_BRR {
uint32_t word; uint32_t word;
}; };
#define USART_BRR_DIV_Fraction reg_def( 0, 4)
#define USART_BRR_DIV_Mantissa reg_def( 4, 12)
#define USART_BRR_reserved1 reg_def(16, 16)
union USART_CR1 { union USART_CR1 {
struct __attribute__((packed)) { struct {
uint32_t SBK:1; uint32_t SBK:1;
uint32_t RWU:1; uint32_t RWU:1;
uint32_t RE:1; uint32_t RE:1;
@ -96,24 +75,8 @@ union USART_CR1 {
uint32_t word; uint32_t word;
}; };
#define USART_CR1_SBK reg_def( 0, 1)
#define USART_CR1_RWU reg_def( 1, 1)
#define USART_CR1_RE reg_def( 2, 1)
#define USART_CR1_TE reg_def( 3, 1)
#define USART_CR1_IDLEIE reg_def( 4, 1)
#define USART_CR1_RXNEIE reg_def( 5, 1)
#define USART_CR1_TCIE reg_def( 6, 1)
#define USART_CR1_TXEIE reg_def( 7, 1)
#define USART_CR1_PEI reg_def( 8, 1)
#define USART_CR1_PS reg_def( 9, 1)
#define USART_CR1_PCE reg_def(10, 1)
#define USART_CR1_WAKE reg_def(11, 1)
#define USART_CR1_M reg_def(12, 1)
#define USART_CR1_UE reg_def(13, 1)
#define USART_CR1_reserved1 reg_def(14, 18)
union USART_CR2 { union USART_CR2 {
struct __attribute__((packed)) { struct {
uint32_t ADD:4; uint32_t ADD:4;
uint32_t reserved1:1; uint32_t reserved1:1;
uint32_t LBDL:1; uint32_t LBDL:1;
@ -130,21 +93,8 @@ union USART_CR2 {
uint32_t word; uint32_t word;
}; };
#define USART_CR2_ADD reg_def( 0, 4)
#define USART_CR2_reserved1 reg_def( 4, 1)
#define USART_CR2_LBDL reg_def( 5, 1)
#define USART_CR2_LBDIE reg_def( 6, 1)
#define USART_CR2_reserved2 reg_def( 7, 1)
#define USART_CR2_LBCL reg_def( 8, 1)
#define USART_CR2_CPHA reg_def( 9, 1)
#define USART_CR2_CPOL reg_def(10, 1)
#define USART_CR2_CLKEN reg_def(11, 1)
#define USART_CR2_STOP reg_def(12, 2)
#define USART_CR2_LINEN reg_def(14, 1)
#define USART_CR2_reserved3 reg_def(15, 17)
union USART_CR3 { union USART_CR3 {
struct __attribute__((packed)) { struct {
uint32_t EIE:1; uint32_t EIE:1;
uint32_t IREN:1; uint32_t IREN:1;
uint32_t IRLP:1; uint32_t IRLP:1;
@ -161,21 +111,8 @@ union USART_CR3 {
uint32_t word; uint32_t word;
}; };
#define USART_CR3_EIE reg_def( 0, 1)
#define USART_CR3_IREN reg_def( 1, 1)
#define USART_CR3_IRLP reg_def( 2, 1)
#define USART_CR3_HDSEL reg_def( 3, 1)
#define USART_CR3_NACK reg_def( 4, 1)
#define USART_CR3_SCEN reg_def( 5, 1)
#define USART_CR3_DMAR reg_def( 6, 1)
#define USART_CR3_DMAT reg_def( 7, 1)
#define USART_CR3_RTSE reg_def( 8, 1)
#define USART_CR3_CTSE reg_def( 9, 1)
#define USART_CR3_CTSIE reg_def(10, 1)
#define USART_CR3_reserved3 reg_def(11, 21)
union USART_GTPR { union USART_GTPR {
struct __attribute__((packed)) { struct {
uint32_t PSC:8; uint32_t PSC:8;
uint32_t GT:8; uint32_t GT:8;
uint32_t reserved1:16; uint32_t reserved1:16;
@ -183,10 +120,6 @@ union USART_GTPR {
uint32_t word; uint32_t word;
}; };
#define USART_GTPR_PSC reg_def( 0, 8)
#define USART_GTPR_GT reg_def( 8, 8)
#define USART_GTPR_reserved1 reg_def(16, 16)
struct USART { struct USART {
union USART_SR SR; union USART_SR SR;
union USART_DR DR; union USART_DR DR;