task #5

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Steins7 merged 35 commits from task into dev 2024-08-04 18:30:16 +00:00
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Implementation of the task module, a proto-os capable of running multiple tasks concurrently, with cooperative scheduling, stack-less tasks, internal timing management and power management. This implementation includes :

  • the task module itself, responsible for the tasks and the power management
  • the stk module responsible for configuring the systick of the cortex M3
  • the scb module responsible for managing the cortex m3 and in this case its sleep state
  • the pwr module responsible for managing the sleep state of the microcontroller except the cortex M3, and configuring access to the backup domain for the bkp module
  • the bkp module responsible for configuring the RTC

Remaining work on this implementation include calibrating the RTC when using the LSI wich will be done later since it would require the use of timers for which the driver is yet to be created

Implementation of the task module, a proto-os capable of running multiple tasks concurrently, with cooperative scheduling, stack-less tasks, internal timing management and power management. This implementation includes : - the task module itself, responsible for the tasks and the power management - the stk module responsible for configuring the systick of the cortex M3 - the scb module responsible for managing the cortex m3 and in this case its sleep state - the pwr module responsible for managing the sleep state of the microcontroller except the cortex M3, and configuring access to the backup domain for the bkp module - the bkp module responsible for configuring the RTC Remaining work on this implementation include calibrating the RTC when using the LSI wich will be done later since it would require the use of timers for which the driver is yet to be created
Steins7 added 35 commits 2024-08-04 18:29:48 +00:00
For now, most code is temporary to validate that the system can work as
envisionned. Optimisations and cleaning will be done shortly
This function used to return the raw current value, but that exposes the
prescaling used internaly
In the end, priorities are only usefull in preemptive systems. Here, it would
only garentee the execution order, which we don't care about most of the time
A while back, macros had to be put in place to avoid letting the
compiler directly use the bitfields. This was necessary because the
compiler used strb instruction which only write bytes. On the AHB bus,
byte writes are transformed into word writes by repeating the byte,
which caused mayhem in the registers. After a lot of research, turns out
the packed attribute stops the compiler from does optimal (word) writes
and isn't needed anyway. Removing them fixes the issue
FUnctions need a cleanup and some details need be ironned, like the
clock management since the whole backup domain must be reset to
configure them
RCC's BCDR register has been moved to the BKP module since it is part of
the backup circuit and thus also aboeys some restrictions access-wise
The target's debug would sometime get stuck while in low-power, making
it difficult to resume communications, even after hardware resets. Some
peripherals were also kept running when halted. This config should fix
these issues
The "specific" lines configuration would not work due to index error in
the callback configuration. While fixing the error, simplifying the API
by moving the afio calls to the calling context seemed a cleaner way to
do things
Since the alarm must be set each time it is to be used, a separated
function is a better fit
Using the system's reset avoids the debug getting stuck when the chip
enters low power. Hopefully this works all the time
Steins7 merged commit 6d95bce6df into dev 2024-08-04 18:30:16 +00:00
Steins7 deleted branch task 2024-08-04 18:30:16 +00:00
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Reference: Steins7/stm32f1xx_HBL#5
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