349 lines
8.8 KiB
C
349 lines
8.8 KiB
C
/** @file usart.c
|
|
* Module handling Universal Synchronous/Asynchronous Receiver/Transmitter
|
|
*
|
|
* The module provides functions to configure the usarts and read/write from/to
|
|
* it
|
|
*/
|
|
|
|
//--includes--------------------------------------------------------------------
|
|
|
|
#include "usart.h"
|
|
#include "nvic.h"
|
|
#include "usart_regs.h"
|
|
#include "reg.h"
|
|
|
|
#include "rcc.h"
|
|
#include "dma.h"
|
|
#include "dma_mbuf.h"
|
|
#include "dma_cbuf.h"
|
|
|
|
#include "stddef.h"
|
|
|
|
|
|
//--local definitions-----------------------------------------------------------
|
|
|
|
static void configure_usart(volatile struct USART* regs,
|
|
enum UsartConfig config);
|
|
static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
|
|
uint32_t baudrate);
|
|
|
|
|
|
//--local variables-------------------------------------------------------------
|
|
|
|
static volatile struct USART* const usart1 = (struct USART*)USART1_BASE_ADDRESS;
|
|
static volatile struct USART* const usart2 = (struct USART*)USART2_BASE_ADDRESS;
|
|
static volatile struct USART* const usart3 = (struct USART*)USART3_BASE_ADDRESS;
|
|
|
|
static volatile struct DmaCircBuffer usart1_rx_buffer;
|
|
static volatile struct DmaMultiBuffer usart1_tx_buffer;
|
|
static volatile struct DmaCircBuffer usart2_rx_buffer;
|
|
static volatile struct DmaMultiBuffer usart2_tx_buffer;
|
|
static volatile struct DmaCircBuffer usart3_rx_buffer;
|
|
static volatile struct DmaMultiBuffer usart3_tx_buffer;
|
|
|
|
|
|
//--public functions------------------------------------------------------------
|
|
|
|
void usart_configure(enum UsartPeriph periph, enum UsartConfig config,
|
|
uint32_t baudrate)
|
|
{
|
|
struct RccClocks clocks;
|
|
rcc_get_clocks(&clocks);
|
|
|
|
switch (periph) {
|
|
case USART_PERIPH_1:
|
|
rcc_enable(RCC_AHB_NONE, RCC_APB1_NONE, RCC_APB2_USART);
|
|
configure_baudrate(usart1, clocks.apb2_freq, baudrate);
|
|
configure_usart(usart1, config);
|
|
#warning "fix zeroed variables init"
|
|
usart1_tx_buffer.buffers = NULL;
|
|
usart1_rx_buffer.buffer = NULL;
|
|
break;
|
|
case USART_PERIPH_2:
|
|
rcc_enable(RCC_AHB_NONE, RCC_APB1_USART2, RCC_APB2_NONE);
|
|
configure_baudrate(usart2, clocks.apb1_freq, baudrate);
|
|
configure_usart(usart2, config);
|
|
usart2_tx_buffer.buffers = NULL;
|
|
usart2_rx_buffer.buffer = NULL;
|
|
break;
|
|
case USART_PERIPH_3:
|
|
rcc_enable(RCC_AHB_NONE, RCC_APB1_USART3, RCC_APB2_NONE);
|
|
configure_baudrate(usart3, clocks.apb1_freq, baudrate);
|
|
configure_usart(usart3, config);
|
|
usart3_tx_buffer.buffers = NULL;
|
|
usart3_rx_buffer.buffer = NULL;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
uint32_t usart_write_byte(enum UsartPeriph periph, uint8_t byte)
|
|
{
|
|
volatile struct USART* regs;
|
|
volatile struct DmaMultiBuffer* buffer;
|
|
enum NvicIrq irq;
|
|
|
|
switch (periph) {
|
|
case USART_PERIPH_1:
|
|
regs = usart1;
|
|
buffer = &usart1_tx_buffer;
|
|
irq = NVIC_IRQ_USART1;
|
|
break;
|
|
case USART_PERIPH_2:
|
|
regs = usart2;
|
|
buffer = &usart2_tx_buffer;
|
|
irq = NVIC_IRQ_USART2;
|
|
break;
|
|
case USART_PERIPH_3:
|
|
regs = usart3;
|
|
buffer = &usart3_tx_buffer;
|
|
irq = NVIC_IRQ_USART3;
|
|
break;
|
|
default:
|
|
return 1;
|
|
break;
|
|
}
|
|
|
|
if (buffer->buffers) {
|
|
//if the tx register is empty, there is no need to go through the dma
|
|
if (regs->SR.TXE) {
|
|
reg_write(regs->DR, USART_DR_DR, byte);
|
|
//enable IRQ, disable DMA
|
|
reg_reset(regs->CR3, USART_CR3_DMAT);
|
|
reg_set(regs->CR1, USART_CR1_TXEIE);
|
|
nvic_enable(irq);
|
|
return 0;
|
|
} else {
|
|
return dma_mbuf_write_byte(buffer, byte);
|
|
}
|
|
} else {
|
|
//only write data if the tx register it empty, give up otherwise
|
|
if (regs->SR.TXE) {
|
|
reg_write(regs->DR, USART_DR_DR, byte);
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
uint32_t usart_read_byte(enum UsartPeriph periph, uint8_t* byte)
|
|
{
|
|
volatile struct USART* regs;
|
|
volatile struct DmaCircBuffer* buffer;
|
|
|
|
switch (periph) {
|
|
case USART_PERIPH_1:
|
|
regs = usart1;
|
|
buffer = &usart1_rx_buffer;
|
|
break;
|
|
case USART_PERIPH_2:
|
|
regs = usart2;
|
|
buffer = &usart2_rx_buffer;
|
|
break;
|
|
case USART_PERIPH_3:
|
|
regs = usart3;
|
|
buffer = &usart3_rx_buffer;
|
|
break;
|
|
default:
|
|
return 1;
|
|
break;
|
|
}
|
|
|
|
if (buffer->buffer) {
|
|
return dma_cbuf_read_byte(buffer, byte);
|
|
} else {
|
|
if (regs->SR.RXNE) {
|
|
*byte = regs->DR.DR;
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
void usart_set_tx_buffer(enum UsartPeriph periph, uint8_t** buffers,
|
|
uint16_t buffer_size, uint8_t buffer_nb, enum DmaConfig priority)
|
|
{
|
|
switch (periph) {
|
|
case USART_PERIPH_1:
|
|
dma_mbuf_configure(&usart1_tx_buffer, (void**)buffers, &usart1->DR,
|
|
buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_4,
|
|
priority);
|
|
break;
|
|
case USART_PERIPH_2:
|
|
dma_mbuf_configure(&usart2_tx_buffer, (void**)buffers, &usart2->DR,
|
|
buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_7,
|
|
priority);
|
|
break;
|
|
case USART_PERIPH_3:
|
|
dma_mbuf_configure(&usart3_tx_buffer, (void**)buffers, &usart3->DR,
|
|
buffer_size, buffer_nb, DMA_PERIPH_1, DMA_CHANNEL_2,
|
|
priority);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void usart_set_rx_buffer(enum UsartPeriph periph, uint8_t* buffer,
|
|
uint16_t size, enum DmaConfig priority)
|
|
{
|
|
switch (periph) {
|
|
case USART_PERIPH_1:
|
|
dma_cbuf_configure(&usart1_rx_buffer, buffer, (void*)&usart1->DR,
|
|
size, DMA_PERIPH_1, DMA_CHANNEL_5, priority);
|
|
reg_set(usart1->CR3, USART_CR3_DMAR);
|
|
break;
|
|
case USART_PERIPH_2:
|
|
dma_cbuf_configure(&usart2_rx_buffer, buffer, (void*)&usart2->DR,
|
|
size, DMA_PERIPH_1, DMA_CHANNEL_6, priority);
|
|
reg_set(usart2->CR3, USART_CR3_DMAR);
|
|
break;
|
|
|
|
case USART_PERIPH_3:
|
|
dma_cbuf_configure(&usart3_rx_buffer, buffer, (void*)&usart3->DR,
|
|
size, DMA_PERIPH_1, DMA_CHANNEL_3, priority);
|
|
reg_set(usart3->CR3, USART_CR3_DMAR);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
//--local functions-------------------------------------------------------------
|
|
|
|
/**
|
|
* Apply the given configuration to the given registers. Generic version of
|
|
* usart_configure()
|
|
*/
|
|
static void configure_usart(volatile struct USART* regs,
|
|
enum UsartConfig config)
|
|
{
|
|
//configure parity
|
|
switch (config)
|
|
{
|
|
case USART_CONFIG_7E1:
|
|
case USART_CONFIG_8E1:
|
|
case USART_CONFIG_7E2:
|
|
case USART_CONFIG_8E2:
|
|
reg_set(regs->CR1, USART_CR1_PCE);
|
|
reg_reset(regs->CR1, USART_CR1_PS);
|
|
break;
|
|
case USART_CONFIG_7O1:
|
|
case USART_CONFIG_7O2:
|
|
case USART_CONFIG_8O1:
|
|
case USART_CONFIG_8O2:
|
|
reg_set(regs->CR1, USART_CR1_PCE);
|
|
reg_set(regs->CR1, USART_CR1_PS);
|
|
break;
|
|
case USART_CONFIG_8N1:
|
|
case USART_CONFIG_8N2:
|
|
reg_reset(regs->CR1, USART_CR1_PCE);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
//configure bit number
|
|
switch (config)
|
|
{
|
|
case USART_CONFIG_7E1:
|
|
case USART_CONFIG_7E2:
|
|
case USART_CONFIG_7O1:
|
|
case USART_CONFIG_7O2:
|
|
case USART_CONFIG_8N1:
|
|
case USART_CONFIG_8N2:
|
|
reg_reset(regs->CR1, USART_CR1_M);
|
|
break;
|
|
case USART_CONFIG_8E2:
|
|
case USART_CONFIG_8E1:
|
|
case USART_CONFIG_8O1:
|
|
case USART_CONFIG_8O2:
|
|
reg_set(regs->CR1, USART_CR1_M);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
//configure stop bits
|
|
switch (config)
|
|
{
|
|
case USART_CONFIG_7E1:
|
|
case USART_CONFIG_7O1:
|
|
case USART_CONFIG_8N1:
|
|
case USART_CONFIG_8E1:
|
|
case USART_CONFIG_8O1:
|
|
reg_reset(regs->CR2, USART_CR2_STOP);
|
|
break;
|
|
case USART_CONFIG_7E2:
|
|
case USART_CONFIG_7O2:
|
|
case USART_CONFIG_8N2:
|
|
case USART_CONFIG_8E2:
|
|
case USART_CONFIG_8O2:
|
|
reg_reset(regs->CR2, USART_CR2_STOP);
|
|
reg_write(regs->CR2, USART_CR2_STOP, 2);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
//enable Rx/Tx
|
|
reg_set(regs->CR1, USART_CR1_TE);
|
|
reg_set(regs->CR1, USART_CR1_RE);
|
|
reg_set(regs->CR1, USART_CR1_UE);
|
|
}
|
|
|
|
/**
|
|
* Configure the given registers with the given baudrate. Baudrate is dependant
|
|
* on the peripheric's clock and may not be exact due to precision errors (see
|
|
* table 192 in documentation)
|
|
*/
|
|
static void configure_baudrate(volatile struct USART* regs, uint32_t clock,
|
|
uint32_t baudrate)
|
|
{
|
|
uint32_t mantissa = clock / (baudrate * 16);
|
|
uint32_t factor = clock / baudrate;
|
|
volatile uint32_t divider = factor - (mantissa * 16);
|
|
|
|
reg_reset(regs->BRR, USART_BRR_DIV_Mantissa);
|
|
reg_write(regs->BRR, USART_BRR_DIV_Mantissa, mantissa & 0xFFF);
|
|
reg_reset(regs->BRR, USART_BRR_DIV_Fraction);
|
|
reg_write(regs->BRR, USART_BRR_DIV_Fraction, divider & 0xF);
|
|
}
|
|
|
|
|
|
//--ISRs------------------------------------------------------------------------
|
|
|
|
void hdr_usart1(void)
|
|
{
|
|
//disable the interrupt. It will be reenabled on a write if needed
|
|
nvic_clear_pending(NVIC_IRQ_USART1);
|
|
nvic_disable(NVIC_IRQ_USART1);
|
|
reg_reset(usart1->CR1, USART_CR1_TXEIE);
|
|
reg_set(usart1->CR3, USART_CR3_DMAT);
|
|
|
|
dma_mbuf_refresh(&usart1_tx_buffer);
|
|
}
|
|
|
|
void hdr_usart2(void)
|
|
{
|
|
//disable the interrupt. It will be reenabled on a write if needed
|
|
nvic_clear_pending(NVIC_IRQ_USART2);
|
|
nvic_disable(NVIC_IRQ_USART2);
|
|
reg_reset(usart2->CR1, USART_CR1_TXEIE);
|
|
reg_set(usart2->CR3, USART_CR3_DMAT);
|
|
|
|
dma_mbuf_refresh(&usart2_tx_buffer);
|
|
}
|
|
|
|
void hdr_usart3(void)
|
|
{
|
|
//disable the interrupt. It will be reenabled on a write if needed
|
|
nvic_clear_pending(NVIC_IRQ_USART3);
|
|
nvic_disable(NVIC_IRQ_USART3);
|
|
reg_reset(usart3->CR1, USART_CR1_TXEIE);
|
|
reg_set(usart3->CR3, USART_CR3_DMAT);
|
|
|
|
dma_mbuf_refresh(&usart3_tx_buffer);
|
|
}
|
|
|