Commit Graph

37 Commits

Author SHA1 Message Date
6ab59f1545 Add timer clocks to rcc's clock frequencies 2024-08-30 22:23:24 +02:00
edb59d7e6b Validate basic use case for tim 2 to 4
tim 2, 3 and 4 work as expected in continuous upcounting with IRQ. tim 1
doesn't seem to work at all (no IRQ), though the issue as not be found
yet
2024-08-28 23:11:18 +02:00
d7da7618e3 Define tim's first API iteration
This API is subject to changes and lacks DMA management
2024-08-28 22:06:20 +02:00
3cbc836fe5 Setup tim's module backbone 2024-08-07 21:37:44 +02:00
93f1b5a992 Define tim module's registers 2024-08-04 23:18:38 +02:00
bc4bab4704 Fix include issue in afio module 2024-08-04 20:17:52 +02:00
24e412446d Implement bkp's rtc alarm configuration
Since the alarm must be set each time it is to be used, a separated
function is a better fit
2024-08-04 20:12:28 +02:00
7ab6622908 Rework exti module to use a simpler API
The "specific" lines configuration would not work due to index error in
the callback configuration. While fixing the error, simplifying the API
by moving the afio calls to the calling context seemed a cleaner way to
do things
2024-08-04 19:38:24 +02:00
947df53ecb Add missing file documentation 2024-07-27 22:19:29 +02:00
80c027370b Document BKP module 2024-07-27 22:13:46 +02:00
b1d25561b4 Temporarily fix warning 2024-07-27 21:57:53 +02:00
507f1e6863 Move rtc control to new BKP module
RCC's BCDR register has been moved to the BKP module since it is part of
the backup circuit and thus also aboeys some restrictions access-wise
2024-07-27 20:11:51 +02:00
3e3d4d2bff Implement RTC module's basic functionnalities
FUnctions need a cleanup and some details need be ironned, like the
clock management since the whole backup domain must be reset to
configure them
2024-07-27 16:41:36 +02:00
b37eb1dd6e Add RTC configuration to RCC module 2024-07-27 14:17:58 +02:00
0b483c535b Ensure PWR is enabled before configuration 2024-07-27 14:15:55 +02:00
a02bcecaec Implement RTC module's registers 2024-07-16 22:21:05 +02:00
699569ec99 Add LSI configuration function to RCC 2024-07-16 21:50:01 +02:00
3e97d4fe7e Implement sleep modes 2024-07-14 19:17:20 +02:00
5c89df4324 Fix typo in PWR registers 2024-07-13 21:35:42 +02:00
1741d47546 Implement SCB module 2024-07-13 21:35:22 +02:00
97dad53621 Define SCB module's registers 2024-07-13 21:14:44 +02:00
9681755168 Define PWR module's registers 2024-07-13 13:19:17 +02:00
5e4d87474a Fix major reg bitfield issue
A while back, macros had to be put in place to avoid letting the
compiler directly use the bitfields. This was necessary because the
compiler used strb instruction which only write bytes. On the AHB bus,
byte writes are transformed into word writes by repeating the byte,
which caused mayhem in the registers. After a lot of research, turns out
the packed attribute stops the compiler from does optimal (word) writes
and isn't needed anyway. Removing them fixes the issue
2024-07-10 23:16:49 +02:00
34fb4dac76 Make stk_read function usable
This function used to return the raw current value, but that exposes the
prescaling used internaly
2024-04-30 20:17:58 +02:00
7e69bfd89c Document systick module 2024-04-28 22:11:37 +02:00
ddd05da6eb Implement systick module 2024-04-28 22:04:10 +02:00
7ba9063d02 Define systick's registers 2024-04-28 19:43:37 +02:00
4eec301d17 Optimize USART driver's code size
Using tables reduces code size while also improving lisibility. That is a
win-win
2024-04-06 22:56:28 +02:00
c6da4e11d8 Document USART driver 2024-04-06 22:19:19 +02:00
85e7ad5ef1 Document DMA driver 2024-04-06 17:26:56 +02:00
fd33003e26 Rework DMA buffer to work properly
DMA buffers now work reliably with USART. The DMA api has changed to make it
more efficient code-size-wise. This may, however, complicate things when
implementating powersaving features
2024-04-06 16:29:45 +02:00
ccf36ac400 Simplify dma buffers and adjust usart
The dma buffer should be services that are used on top of peripherals. As such,
the usart driver should'nt directly use them, this is up to the user. The
multi-buffer has also been simplified since I was not satisfied with the
previous implementation
2024-04-03 22:03:15 +02:00
e1097048a6 RAM initialisation fixed in 086f915 2023-09-24 22:04:38 +02:00
cc54ca7ca8 Improve mbuf fix
Byte index is now stored on 2 bytes. Macros have been made cleaner
2023-09-24 21:59:29 +02:00
0628c4c07c Use TC instead of TXE
Transfer Complete is preferable to TX Empty when using a DMA since we could be
polling the bit between transfers. TXE would be 1 but the DMA would be
transfering another at the same time. TC takes the DMA into account
2023-09-24 18:35:36 +02:00
dbfba20520 Temporary fix for mbuf's byte index
Each buffer should use its own byte index since the value would otherwise be
overwritten when writing to other buffers
2023-09-24 18:33:20 +02:00
a7099d5dfd Rename drivers folder to drv 2023-09-21 20:42:16 +02:00