tim #6

Merged
Steins7 merged 16 commits from tim into dev 2024-11-03 12:07:39 +00:00

16 Commits

Author SHA1 Message Date
70e6cd2d19 Replace wfi by wfe for faster wakeup time 2024-11-03 13:01:12 +01:00
3303bf6435 Document RTC calibration functions 2024-11-03 13:00:46 +01:00
ec9f5f85fb Remove debug statement left in the code 2024-10-21 17:13:03 +02:00
bd15878cb5 Add missing variable name to dma's function 2024-10-21 17:07:02 +02:00
5ddcf4b15e Fix dual LF at the end of debug lines 2024-10-21 17:05:49 +02:00
05e3397d95 Implement rtc's LSI calibration 2024-10-21 17:05:26 +02:00
ae9cdc3582 Fix majors bugs in tim module 2024-10-21 17:04:45 +02:00
a0dadf166d Fix rcc's timer frequency being 10x too low 2024-10-21 17:03:03 +02:00
a1028b29b8 Fix bkp regs missing a field 2024-10-21 17:02:16 +02:00
449ec77f9f Implement backup domain's data registers access 2024-09-01 22:43:14 +02:00
92085aabb0 Fix rtc prescaler computation 2024-09-01 19:32:38 +02:00
6ab59f1545 Add timer clocks to rcc's clock frequencies 2024-08-30 22:23:24 +02:00
edb59d7e6b Validate basic use case for tim 2 to 4
tim 2, 3 and 4 work as expected in continuous upcounting with IRQ. tim 1
doesn't seem to work at all (no IRQ), though the issue as not be found
yet
2024-08-28 23:11:18 +02:00
d7da7618e3 Define tim's first API iteration
This API is subject to changes and lacks DMA management
2024-08-28 22:06:20 +02:00
3cbc836fe5 Setup tim's module backbone 2024-08-07 21:37:44 +02:00
93f1b5a992 Define tim module's registers 2024-08-04 23:18:38 +02:00