daf5920814
Merge pull request 'tim' ( #6 ) from tim into dev
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Reviewed-on: https://git.steins7.ovh/Steins7/stm32f1xx_HBL/pulls/6
2024-11-03 12:07:39 +00:00
70e6cd2d19
Replace wfi by wfe for faster wakeup time
2024-11-03 13:01:12 +01:00
3303bf6435
Document RTC calibration functions
2024-11-03 13:00:46 +01:00
ec9f5f85fb
Remove debug statement left in the code
2024-10-21 17:13:03 +02:00
bd15878cb5
Add missing variable name to dma's function
2024-10-21 17:07:02 +02:00
5ddcf4b15e
Fix dual LF at the end of debug lines
2024-10-21 17:05:49 +02:00
05e3397d95
Implement rtc's LSI calibration
2024-10-21 17:05:26 +02:00
ae9cdc3582
Fix majors bugs in tim module
2024-10-21 17:04:45 +02:00
a0dadf166d
Fix rcc's timer frequency being 10x too low
2024-10-21 17:03:03 +02:00
a1028b29b8
Fix bkp regs missing a field
2024-10-21 17:02:16 +02:00
449ec77f9f
Implement backup domain's data registers access
2024-09-01 22:43:14 +02:00
92085aabb0
Fix rtc prescaler computation
2024-09-01 19:32:38 +02:00
6ab59f1545
Add timer clocks to rcc's clock frequencies
2024-08-30 22:23:24 +02:00
edb59d7e6b
Validate basic use case for tim 2 to 4
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tim 2, 3 and 4 work as expected in continuous upcounting with IRQ. tim 1
doesn't seem to work at all (no IRQ), though the issue as not be found
yet
2024-08-28 23:11:18 +02:00
d7da7618e3
Define tim's first API iteration
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This API is subject to changes and lacks DMA management
2024-08-28 22:06:20 +02:00
3cbc836fe5
Setup tim's module backbone
2024-08-07 21:37:44 +02:00
93f1b5a992
Define tim module's registers
2024-08-04 23:18:38 +02:00
6d95bce6df
Merge pull request 'task' ( #5 ) from task into dev
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Reviewed-on: https://git.steins7.ovh/Steins7/stm32f1xx_HBL/pulls/5
2024-08-04 18:30:15 +00:00
ebc7ad4235
Fix compilation warning in task module
2024-08-04 20:18:45 +02:00
bc4bab4704
Fix include issue in afio module
2024-08-04 20:17:52 +02:00
a4ca0d30c3
Force the use of system's reset in openocd
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Using the system's reset avoids the debug getting stuck when the chip
enters low power. Hopefully this works all the time
2024-08-04 20:14:34 +02:00
89c81b8c42
Integrate the RTC to the task module
2024-08-04 20:14:24 +02:00
24e412446d
Implement bkp's rtc alarm configuration
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Since the alarm must be set each time it is to be used, a separated
function is a better fit
2024-08-04 20:12:28 +02:00
7ab6622908
Rework exti module to use a simpler API
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The "specific" lines configuration would not work due to index error in
the callback configuration. While fixing the error, simplifying the API
by moving the afio calls to the calling context seemed a cleaner way to
do things
2024-08-04 19:38:24 +02:00
ba9bc57a49
Add openocd configuration
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The target's debug would sometime get stuck while in low-power, making
it difficult to resume communications, even after hardware resets. Some
peripherals were also kept running when halted. This config should fix
these issues
2024-08-04 15:52:24 +02:00
947df53ecb
Add missing file documentation
2024-07-27 22:19:29 +02:00
80c027370b
Document BKP module
2024-07-27 22:13:46 +02:00
b1d25561b4
Temporarily fix warning
2024-07-27 21:57:53 +02:00
507f1e6863
Move rtc control to new BKP module
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RCC's BCDR register has been moved to the BKP module since it is part of
the backup circuit and thus also aboeys some restrictions access-wise
2024-07-27 20:11:51 +02:00
3e3d4d2bff
Implement RTC module's basic functionnalities
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FUnctions need a cleanup and some details need be ironned, like the
clock management since the whole backup domain must be reset to
configure them
2024-07-27 16:41:36 +02:00
b37eb1dd6e
Add RTC configuration to RCC module
2024-07-27 14:17:58 +02:00
0b483c535b
Ensure PWR is enabled before configuration
2024-07-27 14:15:55 +02:00
a02bcecaec
Implement RTC module's registers
2024-07-16 22:21:05 +02:00
699569ec99
Add LSI configuration function to RCC
2024-07-16 21:50:01 +02:00
3e97d4fe7e
Implement sleep modes
2024-07-14 19:17:20 +02:00
5c89df4324
Fix typo in PWR registers
2024-07-13 21:35:42 +02:00
1741d47546
Implement SCB module
2024-07-13 21:35:22 +02:00
97dad53621
Define SCB module's registers
2024-07-13 21:14:44 +02:00
9681755168
Define PWR module's registers
2024-07-13 13:19:17 +02:00
5e4d87474a
Fix major reg bitfield issue
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A while back, macros had to be put in place to avoid letting the
compiler directly use the bitfields. This was necessary because the
compiler used strb instruction which only write bytes. On the AHB bus,
byte writes are transformed into word writes by repeating the byte,
which caused mayhem in the registers. After a lot of research, turns out
the packed attribute stops the compiler from does optimal (word) writes
and isn't needed anyway. Removing them fixes the issue
2024-07-10 23:16:49 +02:00
d5c70a3a04
Document the task module
2024-07-10 21:54:23 +02:00
93b383be49
Add API to access task's system time
2024-07-09 22:07:35 +02:00
dd1756221d
Fix typo in task macros
2024-07-09 21:46:15 +02:00
173e16eb2e
Add back task features in a simplified way
2024-07-09 11:53:05 +02:00
b7951f2211
Simplify task module
2024-07-06 22:43:50 +02:00
7cb33f65a5
Create new delay module
2024-05-14 15:03:18 +02:00
c09d2cda67
Remove priority parameter from tasks
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In the end, priorities are only usefull in preemptive systems. Here, it would
only garentee the execution order, which we don't care about most of the time
2024-05-14 14:53:51 +02:00
34fb4dac76
Make stk_read function usable
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This function used to return the raw current value, but that exposes the
prescaling used internaly
2024-04-30 20:17:58 +02:00
432310a52d
Implement task module
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For now, most code is temporary to validate that the system can work as
envisionned. Optimisations and cleaning will be done shortly
2024-04-30 20:15:58 +02:00
7e69bfd89c
Document systick module
2024-04-28 22:11:37 +02:00
